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ac: add cpdma_prefetch_writes_memory to ac_gpu_info
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_SI_SCHED,
149 DBG_GISEL,
150 DBG_W32_GE,
151 DBG_W32_PS,
152 DBG_W32_CS,
153 DBG_W64_GE,
154 DBG_W64_PS,
155 DBG_W64_CS,
156
157 /* Shader compiler options (with no effect on the shader cache): */
158 DBG_CHECK_IR,
159 DBG_MONOLITHIC_SHADERS,
160 DBG_NO_OPT_VARIANT,
161
162 /* Information logging options: */
163 DBG_INFO,
164 DBG_TEX,
165 DBG_COMPUTE,
166 DBG_VM,
167
168 /* Driver options: */
169 DBG_FORCE_DMA,
170 DBG_NO_ASYNC_DMA,
171 DBG_NO_WC,
172 DBG_CHECK_VM,
173 DBG_RESERVE_VMID,
174 DBG_ZERO_VRAM,
175
176 /* 3D engine options: */
177 DBG_NO_GFX,
178 DBG_ALWAYS_PD,
179 DBG_PD,
180 DBG_NO_PD,
181 DBG_SWITCH_ON_EOP,
182 DBG_NO_OUT_OF_ORDER,
183 DBG_NO_DPBB,
184 DBG_NO_DFSM,
185 DBG_DPBB,
186 DBG_DFSM,
187 DBG_NO_HYPERZ,
188 DBG_NO_RB_PLUS,
189 DBG_NO_2D_TILING,
190 DBG_NO_TILING,
191 DBG_NO_DCC,
192 DBG_NO_DCC_CLEAR,
193 DBG_NO_DCC_FB,
194 DBG_NO_DCC_MSAA,
195 DBG_NO_FMASK,
196
197 /* Tests: */
198 DBG_TEST_DMA,
199 DBG_TEST_VMFAULT_CP,
200 DBG_TEST_VMFAULT_SDMA,
201 DBG_TEST_VMFAULT_SHADER,
202 DBG_TEST_DMA_PERF,
203 DBG_TEST_GDS,
204 DBG_TEST_GDS_MM,
205 DBG_TEST_GDS_OA_MM,
206 };
207
208 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
209 #define DBG(name) (1ull << DBG_##name)
210
211 enum si_cache_policy {
212 L2_BYPASS,
213 L2_STREAM, /* same as SLC=1 */
214 L2_LRU, /* same as SLC=0 */
215 };
216
217 enum si_coherency {
218 SI_COHERENCY_NONE, /* no cache flushes needed */
219 SI_COHERENCY_SHADER,
220 SI_COHERENCY_CB_META,
221 SI_COHERENCY_CP,
222 };
223
224 struct si_compute;
225 struct si_shader_context;
226 struct hash_table;
227 struct u_suballocator;
228
229 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
230 * at the moment.
231 */
232 struct si_resource {
233 struct threaded_resource b;
234
235 /* Winsys objects. */
236 struct pb_buffer *buf;
237 uint64_t gpu_address;
238 /* Memory usage if the buffer placement is optimal. */
239 uint64_t vram_usage;
240 uint64_t gart_usage;
241
242 /* Resource properties. */
243 uint64_t bo_size;
244 unsigned bo_alignment;
245 enum radeon_bo_domain domains;
246 enum radeon_bo_flag flags;
247 unsigned bind_history;
248 int max_forced_staging_uploads;
249
250 /* The buffer range which is initialized (with a write transfer,
251 * streamout, DMA, or as a random access target). The rest of
252 * the buffer is considered invalid and can be mapped unsynchronized.
253 *
254 * This allows unsychronized mapping of a buffer range which hasn't
255 * been used yet. It's for applications which forget to use
256 * the unsynchronized map flag and expect the driver to figure it out.
257 */
258 struct util_range valid_buffer_range;
259
260 /* For buffers only. This indicates that a write operation has been
261 * performed by TC L2, but the cache hasn't been flushed.
262 * Any hw block which doesn't use or bypasses TC L2 should check this
263 * flag and flush the cache before using the buffer.
264 *
265 * For example, TC L2 must be flushed if a buffer which has been
266 * modified by a shader store instruction is about to be used as
267 * an index buffer. The reason is that VGT DMA index fetching doesn't
268 * use TC L2.
269 */
270 bool TC_L2_dirty;
271
272 /* Whether this resource is referenced by bindless handles. */
273 bool texture_handle_allocated;
274 bool image_handle_allocated;
275
276 /* Whether the resource has been exported via resource_get_handle. */
277 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
278 };
279
280 struct si_transfer {
281 struct threaded_transfer b;
282 struct si_resource *staging;
283 unsigned offset;
284 };
285
286 struct si_texture {
287 struct si_resource buffer;
288
289 struct radeon_surf surface;
290 uint64_t size;
291 struct si_texture *flushed_depth_texture;
292
293 /* One texture allocation can contain these buffers:
294 * - image (pixel data)
295 * - FMASK buffer (MSAA compression)
296 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
297 * - HTILE buffer (Z/S compression and fast Z/S clear)
298 * - DCC buffer (color compression and new fast color clear)
299 * - displayable DCC buffer (if the DCC buffer is not displayable)
300 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
301 */
302 uint64_t fmask_offset;
303 uint64_t cmask_offset;
304 uint64_t cmask_base_address_reg;
305 struct si_resource *cmask_buffer;
306 uint64_t dcc_offset; /* 0 = disabled */
307 uint64_t display_dcc_offset;
308 uint64_t dcc_retile_map_offset;
309 unsigned cb_color_info; /* fast clear enable bit */
310 unsigned color_clear_value[2];
311 unsigned last_msaa_resolve_target_micro_mode;
312 unsigned num_level0_transfers;
313
314 /* Depth buffer compression and fast clear. */
315 uint64_t htile_offset;
316 float depth_clear_value;
317 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
318 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
319 enum pipe_format db_render_format:16;
320 uint8_t stencil_clear_value;
321 bool tc_compatible_htile:1;
322 bool htile_stencil_disabled:1;
323 bool depth_cleared:1; /* if it was cleared at least once */
324 bool stencil_cleared:1; /* if it was cleared at least once */
325 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
326 bool is_depth:1;
327 bool db_compatible:1;
328 bool can_sample_z:1;
329 bool can_sample_s:1;
330
331 /* We need to track DCC dirtiness, because st/dri usually calls
332 * flush_resource twice per frame (not a bug) and we don't wanna
333 * decompress DCC twice. Also, the dirty tracking must be done even
334 * if DCC isn't used, because it's required by the DCC usage analysis
335 * for a possible future enablement.
336 */
337 bool separate_dcc_dirty:1;
338 /* Statistics gathering for the DCC enablement heuristic. */
339 bool dcc_gather_statistics:1;
340 /* Counter that should be non-zero if the texture is bound to a
341 * framebuffer.
342 */
343 unsigned framebuffers_bound;
344 /* Whether the texture is a displayable back buffer and needs DCC
345 * decompression, which is expensive. Therefore, it's enabled only
346 * if statistics suggest that it will pay off and it's allocated
347 * separately. It can't be bound as a sampler by apps. Limited to
348 * target == 2D and last_level == 0. If enabled, dcc_offset contains
349 * the absolute GPUVM address, not the relative one.
350 */
351 struct si_resource *dcc_separate_buffer;
352 /* When DCC is temporarily disabled, the separate buffer is here. */
353 struct si_resource *last_dcc_separate_buffer;
354 /* Estimate of how much this color buffer is written to in units of
355 * full-screen draws: ps_invocations / (width * height)
356 * Shader kills, late Z, and blending with trivial discards make it
357 * inaccurate (we need to count CB updates, not PS invocations).
358 */
359 unsigned ps_draw_ratio;
360 /* The number of clears since the last DCC usage analysis. */
361 unsigned num_slow_clears;
362 };
363
364 struct si_surface {
365 struct pipe_surface base;
366
367 /* These can vary with block-compressed textures. */
368 uint16_t width0;
369 uint16_t height0;
370
371 bool color_initialized:1;
372 bool depth_initialized:1;
373
374 /* Misc. color flags. */
375 bool color_is_int8:1;
376 bool color_is_int10:1;
377 bool dcc_incompatible:1;
378
379 /* Color registers. */
380 unsigned cb_color_info;
381 unsigned cb_color_view;
382 unsigned cb_color_attrib;
383 unsigned cb_color_attrib2; /* GFX9 and later */
384 unsigned cb_color_attrib3; /* GFX10 and later */
385 unsigned cb_dcc_control; /* GFX8 and later */
386 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
387 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
388 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
389 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
390
391 /* DB registers. */
392 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
393 uint64_t db_stencil_base;
394 uint64_t db_htile_data_base;
395 unsigned db_depth_info;
396 unsigned db_z_info;
397 unsigned db_z_info2; /* GFX9 only */
398 unsigned db_depth_view;
399 unsigned db_depth_size;
400 unsigned db_depth_slice;
401 unsigned db_stencil_info;
402 unsigned db_stencil_info2; /* GFX9 only */
403 unsigned db_htile_surface;
404 };
405
406 struct si_mmio_counter {
407 unsigned busy;
408 unsigned idle;
409 };
410
411 union si_mmio_counters {
412 struct {
413 /* For global GPU load including SDMA. */
414 struct si_mmio_counter gpu;
415
416 /* GRBM_STATUS */
417 struct si_mmio_counter spi;
418 struct si_mmio_counter gui;
419 struct si_mmio_counter ta;
420 struct si_mmio_counter gds;
421 struct si_mmio_counter vgt;
422 struct si_mmio_counter ia;
423 struct si_mmio_counter sx;
424 struct si_mmio_counter wd;
425 struct si_mmio_counter bci;
426 struct si_mmio_counter sc;
427 struct si_mmio_counter pa;
428 struct si_mmio_counter db;
429 struct si_mmio_counter cp;
430 struct si_mmio_counter cb;
431
432 /* SRBM_STATUS2 */
433 struct si_mmio_counter sdma;
434
435 /* CP_STAT */
436 struct si_mmio_counter pfp;
437 struct si_mmio_counter meq;
438 struct si_mmio_counter me;
439 struct si_mmio_counter surf_sync;
440 struct si_mmio_counter cp_dma;
441 struct si_mmio_counter scratch_ram;
442 } named;
443 unsigned array[0];
444 };
445
446 struct si_memory_object {
447 struct pipe_memory_object b;
448 struct pb_buffer *buf;
449 uint32_t stride;
450 };
451
452 /* Saved CS data for debugging features. */
453 struct radeon_saved_cs {
454 uint32_t *ib;
455 unsigned num_dw;
456
457 struct radeon_bo_list_item *bo_list;
458 unsigned bo_count;
459 };
460
461 struct si_screen {
462 struct pipe_screen b;
463 struct radeon_winsys *ws;
464 struct disk_cache *disk_shader_cache;
465
466 struct radeon_info info;
467 uint64_t debug_flags;
468 char renderer_string[183];
469
470 void (*make_texture_descriptor)(
471 struct si_screen *screen,
472 struct si_texture *tex,
473 bool sampler,
474 enum pipe_texture_target target,
475 enum pipe_format pipe_format,
476 const unsigned char state_swizzle[4],
477 unsigned first_level, unsigned last_level,
478 unsigned first_layer, unsigned last_layer,
479 unsigned width, unsigned height, unsigned depth,
480 uint32_t *state,
481 uint32_t *fmask_state);
482
483 unsigned pa_sc_raster_config;
484 unsigned pa_sc_raster_config_1;
485 unsigned se_tile_repeat;
486 unsigned gs_table_depth;
487 unsigned tess_offchip_block_dw_size;
488 unsigned tess_offchip_ring_size;
489 unsigned tess_factor_ring_size;
490 unsigned vgt_hs_offchip_param;
491 unsigned eqaa_force_coverage_samples;
492 unsigned eqaa_force_z_samples;
493 unsigned eqaa_force_color_samples;
494 bool has_draw_indirect_multi;
495 bool has_out_of_order_rast;
496 bool assume_no_z_fights;
497 bool commutative_blend_add;
498 bool has_gfx9_scissor_bug;
499 bool has_msaa_sample_loc_bug;
500 bool has_ls_vgpr_init_bug;
501 bool dpbb_allowed;
502 bool dfsm_allowed;
503 bool llvm_has_working_vgpr_indexing;
504 bool use_ngg;
505 bool use_ngg_streamout;
506
507 struct {
508 #define OPT_BOOL(name, dflt, description) bool name:1;
509 #include "si_debug_options.h"
510 } options;
511
512 /* Whether shaders are monolithic (1-part) or separate (3-part). */
513 bool use_monolithic_shaders;
514 bool record_llvm_ir;
515 bool rbplus_allowed; /* if RB+ is allowed */
516 bool dcc_msaa_allowed;
517
518 struct slab_parent_pool pool_transfers;
519
520 /* Texture filter settings. */
521 int force_aniso; /* -1 = disabled */
522
523 /* Auxiliary context. Mainly used to initialize resources.
524 * It must be locked prior to using and flushed before unlocking. */
525 struct pipe_context *aux_context;
526 mtx_t aux_context_lock;
527
528 /* This must be in the screen, because UE4 uses one context for
529 * compilation and another one for rendering.
530 */
531 unsigned num_compilations;
532 /* Along with ST_DEBUG=precompile, this should show if applications
533 * are loading shaders on demand. This is a monotonic counter.
534 */
535 unsigned num_shaders_created;
536 unsigned num_shader_cache_hits;
537
538 /* GPU load thread. */
539 mtx_t gpu_load_mutex;
540 thrd_t gpu_load_thread;
541 union si_mmio_counters mmio_counters;
542 volatile unsigned gpu_load_stop_thread; /* bool */
543
544 /* Performance counters. */
545 struct si_perfcounters *perfcounters;
546
547 /* If pipe_screen wants to recompute and re-emit the framebuffer,
548 * sampler, and image states of all contexts, it should atomically
549 * increment this.
550 *
551 * Each context will compare this with its own last known value of
552 * the counter before drawing and re-emit the states accordingly.
553 */
554 unsigned dirty_tex_counter;
555 unsigned dirty_buf_counter;
556
557 /* Atomically increment this counter when an existing texture's
558 * metadata is enabled or disabled in a way that requires changing
559 * contexts' compressed texture binding masks.
560 */
561 unsigned compressed_colortex_counter;
562
563 struct {
564 /* Context flags to set so that all writes from earlier jobs
565 * in the CP are seen by L2 clients.
566 */
567 unsigned cp_to_L2;
568
569 /* Context flags to set so that all writes from earlier jobs
570 * that end in L2 are seen by CP.
571 */
572 unsigned L2_to_cp;
573 } barrier_flags;
574
575 mtx_t shader_parts_mutex;
576 struct si_shader_part *vs_prologs;
577 struct si_shader_part *tcs_epilogs;
578 struct si_shader_part *gs_prologs;
579 struct si_shader_part *ps_prologs;
580 struct si_shader_part *ps_epilogs;
581
582 /* Shader cache in memory.
583 *
584 * Design & limitations:
585 * - The shader cache is per screen (= per process), never saved to
586 * disk, and skips redundant shader compilations from TGSI to bytecode.
587 * - It can only be used with one-variant-per-shader support, in which
588 * case only the main (typically middle) part of shaders is cached.
589 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
590 * variants of VS and TES are cached, so LS and ES aren't.
591 * - GS and CS aren't cached, but it's certainly possible to cache
592 * those as well.
593 */
594 mtx_t shader_cache_mutex;
595 struct hash_table *shader_cache;
596
597 /* Shader compiler queue for multithreaded compilation. */
598 struct util_queue shader_compiler_queue;
599 /* Use at most 3 normal compiler threads on quadcore and better.
600 * Hyperthreaded CPUs report the number of threads, but we want
601 * the number of cores. We only need this many threads for shader-db. */
602 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
603
604 struct util_queue shader_compiler_queue_low_priority;
605 /* Use at most 2 low priority threads on quadcore and better.
606 * We want to minimize the impact on multithreaded Mesa. */
607 struct ac_llvm_compiler compiler_lowp[10];
608
609 unsigned compute_wave_size;
610 unsigned ps_wave_size;
611 unsigned ge_wave_size;
612 };
613
614 struct si_blend_color {
615 struct pipe_blend_color state;
616 bool any_nonzeros;
617 };
618
619 struct si_sampler_view {
620 struct pipe_sampler_view base;
621 /* [0..7] = image descriptor
622 * [4..7] = buffer descriptor */
623 uint32_t state[8];
624 uint32_t fmask_state[8];
625 const struct legacy_surf_level *base_level_info;
626 ubyte base_level;
627 ubyte block_width;
628 bool is_stencil_sampler;
629 bool is_integer;
630 bool dcc_incompatible;
631 };
632
633 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
634
635 struct si_sampler_state {
636 #ifndef NDEBUG
637 unsigned magic;
638 #endif
639 uint32_t val[4];
640 uint32_t integer_val[4];
641 uint32_t upgraded_depth_val[4];
642 };
643
644 struct si_cs_shader_state {
645 struct si_compute *program;
646 struct si_compute *emitted_program;
647 unsigned offset;
648 bool initialized;
649 bool uses_scratch;
650 };
651
652 struct si_samplers {
653 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
654 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
655
656 /* The i-th bit is set if that element is enabled (non-NULL resource). */
657 unsigned enabled_mask;
658 uint32_t needs_depth_decompress_mask;
659 uint32_t needs_color_decompress_mask;
660 };
661
662 struct si_images {
663 struct pipe_image_view views[SI_NUM_IMAGES];
664 uint32_t needs_color_decompress_mask;
665 unsigned enabled_mask;
666 };
667
668 struct si_framebuffer {
669 struct pipe_framebuffer_state state;
670 unsigned colorbuf_enabled_4bit;
671 unsigned spi_shader_col_format;
672 unsigned spi_shader_col_format_alpha;
673 unsigned spi_shader_col_format_blend;
674 unsigned spi_shader_col_format_blend_alpha;
675 ubyte nr_samples:5; /* at most 16xAA */
676 ubyte log_samples:3; /* at most 4 = 16xAA */
677 ubyte nr_color_samples; /* at most 8xAA */
678 ubyte compressed_cb_mask;
679 ubyte uncompressed_cb_mask;
680 ubyte color_is_int8;
681 ubyte color_is_int10;
682 ubyte dirty_cbufs;
683 ubyte dcc_overwrite_combiner_watermark;
684 ubyte min_bytes_per_pixel;
685 bool dirty_zsbuf;
686 bool any_dst_linear;
687 bool CB_has_shader_readable_metadata;
688 bool DB_has_shader_readable_metadata;
689 bool all_DCC_pipe_aligned;
690 };
691
692 enum si_quant_mode {
693 /* This is the list we want to support. */
694 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
695 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
696 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
697 };
698
699 struct si_signed_scissor {
700 int minx;
701 int miny;
702 int maxx;
703 int maxy;
704 enum si_quant_mode quant_mode;
705 };
706
707 struct si_viewports {
708 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
709 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
710 bool y_inverted;
711 };
712
713 struct si_clip_state {
714 struct pipe_clip_state state;
715 bool any_nonzeros;
716 };
717
718 struct si_streamout_target {
719 struct pipe_stream_output_target b;
720
721 /* The buffer where BUFFER_FILLED_SIZE is stored. */
722 struct si_resource *buf_filled_size;
723 unsigned buf_filled_size_offset;
724 bool buf_filled_size_valid;
725
726 unsigned stride_in_dw;
727 };
728
729 struct si_streamout {
730 bool begin_emitted;
731
732 unsigned enabled_mask;
733 unsigned num_targets;
734 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
735
736 unsigned append_bitmask;
737 bool suspended;
738
739 /* External state which comes from the vertex shader,
740 * it must be set explicitly when binding a shader. */
741 uint16_t *stride_in_dw;
742 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
743
744 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
745 unsigned hw_enabled_mask;
746
747 /* The state of VGT_STRMOUT_(CONFIG|EN). */
748 bool streamout_enabled;
749 bool prims_gen_query_enabled;
750 int num_prims_gen_queries;
751 };
752
753 /* A shader state consists of the shader selector, which is a constant state
754 * object shared by multiple contexts and shouldn't be modified, and
755 * the current shader variant selected for this context.
756 */
757 struct si_shader_ctx_state {
758 struct si_shader_selector *cso;
759 struct si_shader *current;
760 };
761
762 #define SI_NUM_VGT_PARAM_KEY_BITS 12
763 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
764
765 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
766 * Some fields are set by state-change calls, most are set by draw_vbo.
767 */
768 union si_vgt_param_key {
769 struct {
770 #ifdef PIPE_ARCH_LITTLE_ENDIAN
771 unsigned prim:4;
772 unsigned uses_instancing:1;
773 unsigned multi_instances_smaller_than_primgroup:1;
774 unsigned primitive_restart:1;
775 unsigned count_from_stream_output:1;
776 unsigned line_stipple_enabled:1;
777 unsigned uses_tess:1;
778 unsigned tess_uses_prim_id:1;
779 unsigned uses_gs:1;
780 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
781 #else /* PIPE_ARCH_BIG_ENDIAN */
782 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
783 unsigned uses_gs:1;
784 unsigned tess_uses_prim_id:1;
785 unsigned uses_tess:1;
786 unsigned line_stipple_enabled:1;
787 unsigned count_from_stream_output:1;
788 unsigned primitive_restart:1;
789 unsigned multi_instances_smaller_than_primgroup:1;
790 unsigned uses_instancing:1;
791 unsigned prim:4;
792 #endif
793 } u;
794 uint32_t index;
795 };
796
797 #define SI_NUM_VGT_STAGES_KEY_BITS 4
798 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
799
800 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
801 * Some fields are set by state-change calls, most are set by draw_vbo.
802 */
803 union si_vgt_stages_key {
804 struct {
805 #ifdef PIPE_ARCH_LITTLE_ENDIAN
806 unsigned tess:1;
807 unsigned gs:1;
808 unsigned ngg:1; /* gfx10+ */
809 unsigned streamout:1; /* only used with NGG */
810 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
811 #else /* PIPE_ARCH_BIG_ENDIAN */
812 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
813 unsigned streamout:1;
814 unsigned ngg:1;
815 unsigned gs:1;
816 unsigned tess:1;
817 #endif
818 } u;
819 uint32_t index;
820 };
821
822 struct si_texture_handle
823 {
824 unsigned desc_slot;
825 bool desc_dirty;
826 struct pipe_sampler_view *view;
827 struct si_sampler_state sstate;
828 };
829
830 struct si_image_handle
831 {
832 unsigned desc_slot;
833 bool desc_dirty;
834 struct pipe_image_view view;
835 };
836
837 struct si_saved_cs {
838 struct pipe_reference reference;
839 struct si_context *ctx;
840 struct radeon_saved_cs gfx;
841 struct radeon_saved_cs compute;
842 struct si_resource *trace_buf;
843 unsigned trace_id;
844
845 unsigned gfx_last_dw;
846 unsigned compute_last_dw;
847 bool flushed;
848 int64_t time_flush;
849 };
850
851 struct si_sdma_upload {
852 struct si_resource *dst;
853 struct si_resource *src;
854 unsigned src_offset;
855 unsigned dst_offset;
856 unsigned size;
857 };
858
859 struct si_context {
860 struct pipe_context b; /* base class */
861
862 enum radeon_family family;
863 enum chip_class chip_class;
864
865 struct radeon_winsys *ws;
866 struct radeon_winsys_ctx *ctx;
867 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
868 struct radeon_cmdbuf *dma_cs;
869 struct pipe_fence_handle *last_gfx_fence;
870 struct pipe_fence_handle *last_sdma_fence;
871 struct si_resource *eop_bug_scratch;
872 struct u_upload_mgr *cached_gtt_allocator;
873 struct threaded_context *tc;
874 struct u_suballocator *allocator_zeroed_memory;
875 struct slab_child_pool pool_transfers;
876 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
877 struct pipe_device_reset_callback device_reset_callback;
878 struct u_log_context *log;
879 void *query_result_shader;
880 void *sh_query_result_shader;
881
882 void (*emit_cache_flush)(struct si_context *ctx);
883
884 struct blitter_context *blitter;
885 void *noop_blend;
886 void *noop_dsa;
887 void *discard_rasterizer_state;
888 void *custom_dsa_flush;
889 void *custom_blend_resolve;
890 void *custom_blend_fmask_decompress;
891 void *custom_blend_eliminate_fastclear;
892 void *custom_blend_dcc_decompress;
893 void *vs_blit_pos;
894 void *vs_blit_pos_layered;
895 void *vs_blit_color;
896 void *vs_blit_color_layered;
897 void *vs_blit_texcoord;
898 void *cs_clear_buffer;
899 void *cs_copy_buffer;
900 void *cs_copy_image;
901 void *cs_copy_image_1d_array;
902 void *cs_clear_render_target;
903 void *cs_clear_render_target_1d_array;
904 void *cs_dcc_retile;
905 struct si_screen *screen;
906 struct pipe_debug_callback debug;
907 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
908 struct si_shader_ctx_state fixed_func_tcs_shader;
909 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
910 struct si_resource *wait_mem_scratch;
911 unsigned wait_mem_number;
912 uint16_t prefetch_L2_mask;
913
914 bool has_graphics;
915 bool gfx_flush_in_progress:1;
916 bool gfx_last_ib_is_busy:1;
917 bool compute_is_busy:1;
918
919 unsigned num_gfx_cs_flushes;
920 unsigned initial_gfx_cs_size;
921 unsigned last_dirty_tex_counter;
922 unsigned last_dirty_buf_counter;
923 unsigned last_compressed_colortex_counter;
924 unsigned last_num_draw_calls;
925 unsigned flags; /* flush flags */
926 /* Current unaccounted memory usage. */
927 uint64_t vram;
928 uint64_t gtt;
929
930 /* Compute-based primitive discard. */
931 unsigned prim_discard_vertex_count_threshold;
932 struct pb_buffer *gds;
933 struct pb_buffer *gds_oa;
934 struct radeon_cmdbuf *prim_discard_compute_cs;
935 unsigned compute_gds_offset;
936 struct si_shader *compute_ib_last_shader;
937 uint32_t compute_rewind_va;
938 unsigned compute_num_prims_in_batch;
939 bool preserve_prim_restart_gds_at_flush;
940 /* index_ring is divided into 2 halves for doublebuffering. */
941 struct si_resource *index_ring;
942 unsigned index_ring_base; /* offset of a per-IB portion */
943 unsigned index_ring_offset; /* offset within a per-IB portion */
944 unsigned index_ring_size_per_ib; /* max available size per IB */
945 bool prim_discard_compute_ib_initialized;
946 /* For tracking the last execution barrier - it can be either
947 * a WRITE_DATA packet or a fence. */
948 uint32_t *last_pkt3_write_data;
949 struct si_resource *barrier_buf;
950 unsigned barrier_buf_offset;
951 struct pipe_fence_handle *last_ib_barrier_fence;
952 struct si_resource *last_ib_barrier_buf;
953 unsigned last_ib_barrier_buf_offset;
954
955 /* Atoms (direct states). */
956 union si_state_atoms atoms;
957 unsigned dirty_atoms; /* mask */
958 /* PM4 states (precomputed immutable states) */
959 unsigned dirty_states;
960 union si_state queued;
961 union si_state emitted;
962
963 /* Atom declarations. */
964 struct si_framebuffer framebuffer;
965 unsigned sample_locs_num_samples;
966 uint16_t sample_mask;
967 unsigned last_cb_target_mask;
968 struct si_blend_color blend_color;
969 struct si_clip_state clip_state;
970 struct si_shader_data shader_pointers;
971 struct si_stencil_ref stencil_ref;
972 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
973 struct si_streamout streamout;
974 struct si_viewports viewports;
975 unsigned num_window_rectangles;
976 bool window_rectangles_include;
977 struct pipe_scissor_state window_rectangles[4];
978
979 /* Precomputed states. */
980 struct si_pm4_state *init_config;
981 struct si_pm4_state *init_config_gs_rings;
982 bool init_config_has_vgt_flush;
983 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
984
985 /* shaders */
986 struct si_shader_ctx_state ps_shader;
987 struct si_shader_ctx_state gs_shader;
988 struct si_shader_ctx_state vs_shader;
989 struct si_shader_ctx_state tcs_shader;
990 struct si_shader_ctx_state tes_shader;
991 struct si_shader_ctx_state cs_prim_discard_state;
992 struct si_cs_shader_state cs_shader_state;
993
994 /* shader information */
995 struct si_vertex_elements *vertex_elements;
996 unsigned sprite_coord_enable;
997 unsigned cs_max_waves_per_sh;
998 bool flatshade;
999 bool do_update_shaders;
1000
1001 /* vertex buffer descriptors */
1002 uint32_t *vb_descriptors_gpu_list;
1003 struct si_resource *vb_descriptors_buffer;
1004 unsigned vb_descriptors_offset;
1005
1006 /* shader descriptors */
1007 struct si_descriptors descriptors[SI_NUM_DESCS];
1008 unsigned descriptors_dirty;
1009 unsigned shader_pointers_dirty;
1010 unsigned shader_needs_decompress_mask;
1011 struct si_buffer_resources rw_buffers;
1012 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1013 struct si_samplers samplers[SI_NUM_SHADERS];
1014 struct si_images images[SI_NUM_SHADERS];
1015 bool bo_list_add_all_resident_resources;
1016 bool bo_list_add_all_gfx_resources;
1017 bool bo_list_add_all_compute_resources;
1018
1019 /* other shader resources */
1020 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1021 struct pipe_resource *esgs_ring;
1022 struct pipe_resource *gsvs_ring;
1023 struct pipe_resource *tess_rings;
1024 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1025 struct si_resource *border_color_buffer;
1026 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1027 unsigned border_color_count;
1028 unsigned num_vs_blit_sgprs;
1029 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1030 uint32_t cs_user_data[4];
1031
1032 /* Vertex and index buffers. */
1033 bool vertex_buffers_dirty;
1034 bool vertex_buffer_pointer_dirty;
1035 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1036 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1037
1038 /* MSAA config state. */
1039 int ps_iter_samples;
1040 bool ps_uses_fbfetch;
1041 bool smoothing_enabled;
1042
1043 /* DB render state. */
1044 unsigned ps_db_shader_control;
1045 unsigned dbcb_copy_sample;
1046 bool dbcb_depth_copy_enabled:1;
1047 bool dbcb_stencil_copy_enabled:1;
1048 bool db_flush_depth_inplace:1;
1049 bool db_flush_stencil_inplace:1;
1050 bool db_depth_clear:1;
1051 bool db_depth_disable_expclear:1;
1052 bool db_stencil_clear:1;
1053 bool db_stencil_disable_expclear:1;
1054 bool occlusion_queries_disabled:1;
1055 bool generate_mipmap_for_depth:1;
1056
1057 /* Emitted draw state. */
1058 bool gs_tri_strip_adj_fix:1;
1059 bool ls_vgpr_fix:1;
1060 bool prim_discard_cs_instancing:1;
1061 bool ngg:1;
1062 int last_index_size;
1063 int last_base_vertex;
1064 int last_start_instance;
1065 int last_instance_count;
1066 int last_drawid;
1067 int last_sh_base_reg;
1068 int last_primitive_restart_en;
1069 int last_restart_index;
1070 int last_prim;
1071 int last_multi_vgt_param;
1072 int last_rast_prim;
1073 int last_flatshade_first;
1074 int last_binning_enabled;
1075 unsigned last_sc_line_stipple;
1076 unsigned current_vs_state;
1077 unsigned last_vs_state;
1078 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1079
1080 /* Scratch buffer */
1081 struct si_resource *scratch_buffer;
1082 unsigned scratch_waves;
1083 unsigned spi_tmpring_size;
1084
1085 struct si_resource *compute_scratch_buffer;
1086
1087 /* Emitted derived tessellation state. */
1088 /* Local shader (VS), or HS if LS-HS are merged. */
1089 struct si_shader *last_ls;
1090 struct si_shader_selector *last_tcs;
1091 int last_num_tcs_input_cp;
1092 int last_tes_sh_base;
1093 bool last_tess_uses_primid;
1094 unsigned last_num_patches;
1095 int last_ls_hs_config;
1096
1097 /* Debug state. */
1098 bool is_debug;
1099 struct si_saved_cs *current_saved_cs;
1100 uint64_t dmesg_timestamp;
1101 unsigned apitrace_call_number;
1102
1103 /* Other state */
1104 bool need_check_render_feedback;
1105 bool decompression_enabled;
1106 bool dpbb_force_off;
1107 bool vs_writes_viewport_index;
1108 bool vs_disables_clipping_viewport;
1109
1110 /* Precomputed IA_MULTI_VGT_PARAM */
1111 union si_vgt_param_key ia_multi_vgt_param_key;
1112 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1113
1114 /* Bindless descriptors. */
1115 struct si_descriptors bindless_descriptors;
1116 struct util_idalloc bindless_used_slots;
1117 unsigned num_bindless_descriptors;
1118 bool bindless_descriptors_dirty;
1119 bool graphics_bindless_pointer_dirty;
1120 bool compute_bindless_pointer_dirty;
1121
1122 /* Allocated bindless handles */
1123 struct hash_table *tex_handles;
1124 struct hash_table *img_handles;
1125
1126 /* Resident bindless handles */
1127 struct util_dynarray resident_tex_handles;
1128 struct util_dynarray resident_img_handles;
1129
1130 /* Resident bindless handles which need decompression */
1131 struct util_dynarray resident_tex_needs_color_decompress;
1132 struct util_dynarray resident_img_needs_color_decompress;
1133 struct util_dynarray resident_tex_needs_depth_decompress;
1134
1135 /* Bindless state */
1136 bool uses_bindless_samplers;
1137 bool uses_bindless_images;
1138
1139 /* MSAA sample locations.
1140 * The first index is the sample index.
1141 * The second index is the coordinate: X, Y. */
1142 struct {
1143 float x1[1][2];
1144 float x2[2][2];
1145 float x4[4][2];
1146 float x8[8][2];
1147 float x16[16][2];
1148 } sample_positions;
1149 struct pipe_resource *sample_pos_buffer;
1150
1151 /* Misc stats. */
1152 unsigned num_draw_calls;
1153 unsigned num_decompress_calls;
1154 unsigned num_mrt_draw_calls;
1155 unsigned num_prim_restart_calls;
1156 unsigned num_spill_draw_calls;
1157 unsigned num_compute_calls;
1158 unsigned num_spill_compute_calls;
1159 unsigned num_dma_calls;
1160 unsigned num_cp_dma_calls;
1161 unsigned num_vs_flushes;
1162 unsigned num_ps_flushes;
1163 unsigned num_cs_flushes;
1164 unsigned num_cb_cache_flushes;
1165 unsigned num_db_cache_flushes;
1166 unsigned num_L2_invalidates;
1167 unsigned num_L2_writebacks;
1168 unsigned num_resident_handles;
1169 uint64_t num_alloc_tex_transfer_bytes;
1170 unsigned last_tex_ps_draw_ratio; /* for query */
1171 unsigned compute_num_verts_accepted;
1172 unsigned compute_num_verts_rejected;
1173 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1174 unsigned context_roll;
1175
1176 /* Queries. */
1177 /* Maintain the list of active queries for pausing between IBs. */
1178 int num_occlusion_queries;
1179 int num_perfect_occlusion_queries;
1180 int num_pipeline_stat_queries;
1181 struct list_head active_queries;
1182 unsigned num_cs_dw_queries_suspend;
1183
1184 /* Render condition. */
1185 struct pipe_query *render_cond;
1186 unsigned render_cond_mode;
1187 bool render_cond_invert;
1188 bool render_cond_force_off; /* for u_blitter */
1189
1190 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1191 bool sdma_uploads_in_progress;
1192 struct si_sdma_upload *sdma_uploads;
1193 unsigned num_sdma_uploads;
1194 unsigned max_sdma_uploads;
1195
1196 /* Shader-based queries. */
1197 struct list_head shader_query_buffers;
1198 unsigned num_active_shader_queries;
1199
1200 /* Statistics gathering for the DCC enablement heuristic. It can't be
1201 * in si_texture because si_texture can be shared by multiple
1202 * contexts. This is for back buffers only. We shouldn't get too many
1203 * of those.
1204 *
1205 * X11 DRI3 rotates among a finite set of back buffers. They should
1206 * all fit in this array. If they don't, separate DCC might never be
1207 * enabled by DCC stat gathering.
1208 */
1209 struct {
1210 struct si_texture *tex;
1211 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1212 struct pipe_query *ps_stats[3];
1213 /* If all slots are used and another slot is needed,
1214 * the least recently used slot is evicted based on this. */
1215 int64_t last_use_timestamp;
1216 bool query_active;
1217 } dcc_stats[5];
1218
1219 /* Copy one resource to another using async DMA. */
1220 void (*dma_copy)(struct pipe_context *ctx,
1221 struct pipe_resource *dst,
1222 unsigned dst_level,
1223 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1224 struct pipe_resource *src,
1225 unsigned src_level,
1226 const struct pipe_box *src_box);
1227
1228 struct si_tracked_regs tracked_regs;
1229 };
1230
1231 /* cik_sdma.c */
1232 void cik_init_sdma_functions(struct si_context *sctx);
1233
1234 /* si_blit.c */
1235 enum si_blitter_op /* bitmask */
1236 {
1237 SI_SAVE_TEXTURES = 1,
1238 SI_SAVE_FRAMEBUFFER = 2,
1239 SI_SAVE_FRAGMENT_STATE = 4,
1240 SI_DISABLE_RENDER_COND = 8,
1241 };
1242
1243 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1244 void si_blitter_end(struct si_context *sctx);
1245 void si_init_blit_functions(struct si_context *sctx);
1246 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1247 void si_resource_copy_region(struct pipe_context *ctx,
1248 struct pipe_resource *dst,
1249 unsigned dst_level,
1250 unsigned dstx, unsigned dsty, unsigned dstz,
1251 struct pipe_resource *src,
1252 unsigned src_level,
1253 const struct pipe_box *src_box);
1254 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1255
1256 /* si_buffer.c */
1257 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1258 struct pb_buffer *buf,
1259 enum radeon_bo_usage usage);
1260 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1261 struct si_resource *resource,
1262 unsigned usage);
1263 void si_init_resource_fields(struct si_screen *sscreen,
1264 struct si_resource *res,
1265 uint64_t size, unsigned alignment);
1266 bool si_alloc_resource(struct si_screen *sscreen,
1267 struct si_resource *res);
1268 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1269 unsigned flags, unsigned usage,
1270 unsigned size, unsigned alignment);
1271 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1272 unsigned flags, unsigned usage,
1273 unsigned size, unsigned alignment);
1274 void si_replace_buffer_storage(struct pipe_context *ctx,
1275 struct pipe_resource *dst,
1276 struct pipe_resource *src);
1277 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1278 void si_init_buffer_functions(struct si_context *sctx);
1279
1280 /* si_clear.c */
1281 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1282 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1283 bool vi_dcc_clear_level(struct si_context *sctx,
1284 struct si_texture *tex,
1285 unsigned level, unsigned clear_value);
1286 void si_init_clear_functions(struct si_context *sctx);
1287
1288 /* si_compute_blit.c */
1289 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1290 enum si_cache_policy cache_policy);
1291 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1292 uint64_t offset, uint64_t size, uint32_t *clear_value,
1293 uint32_t clear_value_size, enum si_coherency coher,
1294 bool force_cpdma);
1295 void si_copy_buffer(struct si_context *sctx,
1296 struct pipe_resource *dst, struct pipe_resource *src,
1297 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1298 void si_compute_copy_image(struct si_context *sctx,
1299 struct pipe_resource *dst,
1300 unsigned dst_level,
1301 struct pipe_resource *src,
1302 unsigned src_level,
1303 unsigned dstx, unsigned dsty, unsigned dstz,
1304 const struct pipe_box *src_box);
1305 void si_compute_clear_render_target(struct pipe_context *ctx,
1306 struct pipe_surface *dstsurf,
1307 const union pipe_color_union *color,
1308 unsigned dstx, unsigned dsty,
1309 unsigned width, unsigned height,
1310 bool render_condition_enabled);
1311 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1312 void si_init_compute_blit_functions(struct si_context *sctx);
1313
1314 /* si_cp_dma.c */
1315 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1316 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1317 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1318 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1319 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1320 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1321 SI_CPDMA_SKIP_SYNC_AFTER | \
1322 SI_CPDMA_SKIP_SYNC_BEFORE | \
1323 SI_CPDMA_SKIP_GFX_SYNC | \
1324 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1325
1326 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1327 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1328 struct pipe_resource *dst, uint64_t offset,
1329 uint64_t size, unsigned value, unsigned user_flags,
1330 enum si_coherency coher, enum si_cache_policy cache_policy);
1331 void si_cp_dma_copy_buffer(struct si_context *sctx,
1332 struct pipe_resource *dst, struct pipe_resource *src,
1333 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1334 unsigned user_flags, enum si_coherency coher,
1335 enum si_cache_policy cache_policy);
1336 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1337 uint64_t offset, unsigned size);
1338 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1339 void si_test_gds(struct si_context *sctx);
1340 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1341 unsigned offset, unsigned size, unsigned dst_sel,
1342 unsigned engine, const void *data);
1343 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1344 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1345 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1346
1347 /* si_debug.c */
1348 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1349 struct radeon_saved_cs *saved, bool get_buffer_list);
1350 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1351 void si_destroy_saved_cs(struct si_saved_cs *scs);
1352 void si_auto_log_cs(void *data, struct u_log_context *log);
1353 void si_log_hw_flush(struct si_context *sctx);
1354 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1355 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1356 void si_init_debug_functions(struct si_context *sctx);
1357 void si_check_vm_faults(struct si_context *sctx,
1358 struct radeon_saved_cs *saved, enum ring_type ring);
1359 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1360
1361 /* si_dma.c */
1362 void si_init_dma_functions(struct si_context *sctx);
1363
1364 /* si_dma_cs.c */
1365 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1366 uint64_t offset);
1367 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1368 uint64_t offset, uint64_t size, unsigned clear_value);
1369 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1370 struct si_resource *dst, struct si_resource *src);
1371 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1372 struct pipe_fence_handle **fence);
1373 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1374 uint64_t offset, uint64_t size, unsigned value);
1375
1376 /* si_fence.c */
1377 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1378 unsigned event, unsigned event_flags,
1379 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1380 struct si_resource *buf, uint64_t va,
1381 uint32_t new_fence, unsigned query_type);
1382 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1383 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1384 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1385 void si_init_fence_functions(struct si_context *ctx);
1386 void si_init_screen_fence_functions(struct si_screen *screen);
1387 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1388 struct tc_unflushed_batch_token *tc_token);
1389
1390 /* si_get.c */
1391 void si_init_screen_get_functions(struct si_screen *sscreen);
1392
1393 /* si_gfx_cs.c */
1394 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1395 struct pipe_fence_handle **fence);
1396 void si_allocate_gds(struct si_context *ctx);
1397 void si_begin_new_gfx_cs(struct si_context *ctx);
1398 void si_need_gfx_cs_space(struct si_context *ctx);
1399 void si_unref_sdma_uploads(struct si_context *sctx);
1400
1401 /* si_gpu_load.c */
1402 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1403 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1404 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1405 uint64_t begin);
1406
1407 /* si_compute.c */
1408 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1409 void si_init_compute_functions(struct si_context *sctx);
1410
1411 /* si_compute_prim_discard.c */
1412 enum si_prim_discard_outcome {
1413 SI_PRIM_DISCARD_ENABLED,
1414 SI_PRIM_DISCARD_DISABLED,
1415 SI_PRIM_DISCARD_DRAW_SPLIT,
1416 };
1417
1418 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1419 enum si_prim_discard_outcome
1420 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1421 const struct pipe_draw_info *info,
1422 bool primitive_restart);
1423 void si_compute_signal_gfx(struct si_context *sctx);
1424 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1425 const struct pipe_draw_info *info,
1426 unsigned index_size,
1427 unsigned base_vertex,
1428 uint64_t input_indexbuf_va,
1429 unsigned input_indexbuf_max_elements);
1430 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1431
1432 /* si_perfcounters.c */
1433 void si_init_perfcounters(struct si_screen *screen);
1434 void si_destroy_perfcounters(struct si_screen *screen);
1435
1436 /* si_pipe.c */
1437 bool si_check_device_reset(struct si_context *sctx);
1438
1439 /* si_query.c */
1440 void si_init_screen_query_functions(struct si_screen *sscreen);
1441 void si_init_query_functions(struct si_context *sctx);
1442 void si_suspend_queries(struct si_context *sctx);
1443 void si_resume_queries(struct si_context *sctx);
1444
1445 /* si_shaderlib_tgsi.c */
1446 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1447 unsigned num_layers);
1448 void *si_create_fixed_func_tcs(struct si_context *sctx);
1449 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1450 unsigned num_dwords_per_thread,
1451 bool dst_stream_cache_policy, bool is_copy);
1452 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1453 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1454 void *si_clear_render_target_shader(struct pipe_context *ctx);
1455 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1456 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1457 void *si_create_query_result_cs(struct si_context *sctx);
1458 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1459
1460 /* gfx10_query.c */
1461 void gfx10_init_query(struct si_context *sctx);
1462 void gfx10_destroy_query(struct si_context *sctx);
1463
1464 /* si_test_dma.c */
1465 void si_test_dma(struct si_screen *sscreen);
1466
1467 /* si_test_clearbuffer.c */
1468 void si_test_dma_perf(struct si_screen *sscreen);
1469
1470 /* si_uvd.c */
1471 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1472 const struct pipe_video_codec *templ);
1473
1474 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1475 const struct pipe_video_buffer *tmpl);
1476
1477 /* si_viewport.c */
1478 void si_update_vs_viewport_state(struct si_context *ctx);
1479 void si_init_viewport_functions(struct si_context *ctx);
1480
1481 /* si_texture.c */
1482 bool si_prepare_for_dma_blit(struct si_context *sctx,
1483 struct si_texture *dst,
1484 unsigned dst_level, unsigned dstx,
1485 unsigned dsty, unsigned dstz,
1486 struct si_texture *src,
1487 unsigned src_level,
1488 const struct pipe_box *src_box);
1489 void si_eliminate_fast_color_clear(struct si_context *sctx,
1490 struct si_texture *tex);
1491 void si_texture_discard_cmask(struct si_screen *sscreen,
1492 struct si_texture *tex);
1493 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1494 struct pipe_resource *texture);
1495 void si_print_texture_info(struct si_screen *sscreen,
1496 struct si_texture *tex, struct u_log_context *log);
1497 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1498 const struct pipe_resource *templ);
1499 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1500 enum pipe_format format1,
1501 enum pipe_format format2);
1502 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1503 unsigned level,
1504 enum pipe_format view_format);
1505 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1506 struct pipe_resource *tex,
1507 unsigned level,
1508 enum pipe_format view_format);
1509 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1510 struct pipe_resource *texture,
1511 const struct pipe_surface *templ,
1512 unsigned width0, unsigned height0,
1513 unsigned width, unsigned height);
1514 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1515 void vi_separate_dcc_try_enable(struct si_context *sctx,
1516 struct si_texture *tex);
1517 void vi_separate_dcc_start_query(struct si_context *sctx,
1518 struct si_texture *tex);
1519 void vi_separate_dcc_stop_query(struct si_context *sctx,
1520 struct si_texture *tex);
1521 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1522 struct si_texture *tex);
1523 bool si_texture_disable_dcc(struct si_context *sctx,
1524 struct si_texture *tex);
1525 void si_init_screen_texture_functions(struct si_screen *sscreen);
1526 void si_init_context_texture_functions(struct si_context *sctx);
1527
1528
1529 /*
1530 * common helpers
1531 */
1532
1533 static inline struct si_resource *si_resource(struct pipe_resource *r)
1534 {
1535 return (struct si_resource*)r;
1536 }
1537
1538 static inline void
1539 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1540 {
1541 pipe_resource_reference((struct pipe_resource **)ptr,
1542 (struct pipe_resource *)res);
1543 }
1544
1545 static inline void
1546 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1547 {
1548 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1549 }
1550
1551 static inline bool
1552 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1553 {
1554 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1555 }
1556
1557 static inline unsigned
1558 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1559 {
1560 if (stencil)
1561 return tex->surface.u.legacy.stencil_tiling_index[level];
1562 else
1563 return tex->surface.u.legacy.tiling_index[level];
1564 }
1565
1566 static inline unsigned
1567 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1568 {
1569 /* Don't count the needed CS space exactly and just use an upper bound.
1570 *
1571 * Also reserve space for stopping queries at the end of IB, because
1572 * the number of active queries is unlimited in theory.
1573 */
1574 return 2048 + sctx->num_cs_dw_queries_suspend;
1575 }
1576
1577 static inline void
1578 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1579 {
1580 if (r) {
1581 /* Add memory usage for need_gfx_cs_space */
1582 sctx->vram += si_resource(r)->vram_usage;
1583 sctx->gtt += si_resource(r)->gart_usage;
1584 }
1585 }
1586
1587 static inline void
1588 si_invalidate_draw_sh_constants(struct si_context *sctx)
1589 {
1590 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1591 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1592 }
1593
1594 static inline unsigned
1595 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1596 {
1597 return 1 << (atom - sctx->atoms.array);
1598 }
1599
1600 static inline void
1601 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1602 {
1603 unsigned bit = si_get_atom_bit(sctx, atom);
1604
1605 if (dirty)
1606 sctx->dirty_atoms |= bit;
1607 else
1608 sctx->dirty_atoms &= ~bit;
1609 }
1610
1611 static inline bool
1612 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1613 {
1614 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1615 }
1616
1617 static inline void
1618 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1619 {
1620 si_set_atom_dirty(sctx, atom, true);
1621 }
1622
1623 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1624 {
1625 if (sctx->gs_shader.cso)
1626 return &sctx->gs_shader;
1627 if (sctx->tes_shader.cso)
1628 return &sctx->tes_shader;
1629
1630 return &sctx->vs_shader;
1631 }
1632
1633 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1634 {
1635 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1636
1637 return vs->cso ? &vs->cso->info : NULL;
1638 }
1639
1640 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1641 {
1642 if (sctx->gs_shader.cso &&
1643 sctx->gs_shader.current &&
1644 !sctx->gs_shader.current->key.as_ngg)
1645 return sctx->gs_shader.cso->gs_copy_shader;
1646
1647 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1648 return vs->current ? vs->current : NULL;
1649 }
1650
1651 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1652 unsigned processor)
1653 {
1654 return sscreen->debug_flags & (1 << processor);
1655 }
1656
1657 static inline bool si_get_strmout_en(struct si_context *sctx)
1658 {
1659 return sctx->streamout.streamout_enabled ||
1660 sctx->streamout.prims_gen_query_enabled;
1661 }
1662
1663 static inline unsigned
1664 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1665 {
1666 unsigned alignment, tcc_cache_line_size;
1667
1668 /* If the upload size is less than the cache line size (e.g. 16, 32),
1669 * the whole thing will fit into a cache line if we align it to its size.
1670 * The idea is that multiple small uploads can share a cache line.
1671 * If the upload size is greater, align it to the cache line size.
1672 */
1673 alignment = util_next_power_of_two(upload_size);
1674 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1675 return MIN2(alignment, tcc_cache_line_size);
1676 }
1677
1678 static inline void
1679 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1680 {
1681 if (pipe_reference(&(*dst)->reference, &src->reference))
1682 si_destroy_saved_cs(*dst);
1683
1684 *dst = src;
1685 }
1686
1687 static inline void
1688 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1689 bool shaders_read_metadata, bool dcc_pipe_aligned)
1690 {
1691 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1692 SI_CONTEXT_INV_VCACHE;
1693
1694 if (sctx->chip_class >= GFX10) {
1695 if (shaders_read_metadata)
1696 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1697 } else if (sctx->chip_class == GFX9) {
1698 /* Single-sample color is coherent with shaders on GFX9, but
1699 * L2 metadata must be flushed if shaders read metadata.
1700 * (DCC, CMASK).
1701 */
1702 if (num_samples >= 2 ||
1703 (shaders_read_metadata && !dcc_pipe_aligned))
1704 sctx->flags |= SI_CONTEXT_INV_L2;
1705 else if (shaders_read_metadata)
1706 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1707 } else {
1708 /* GFX6-GFX8 */
1709 sctx->flags |= SI_CONTEXT_INV_L2;
1710 }
1711 }
1712
1713 static inline void
1714 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1715 bool include_stencil, bool shaders_read_metadata)
1716 {
1717 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1718 SI_CONTEXT_INV_VCACHE;
1719
1720 if (sctx->chip_class >= GFX10) {
1721 if (shaders_read_metadata)
1722 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1723 } else if (sctx->chip_class == GFX9) {
1724 /* Single-sample depth (not stencil) is coherent with shaders
1725 * on GFX9, but L2 metadata must be flushed if shaders read
1726 * metadata.
1727 */
1728 if (num_samples >= 2 || include_stencil)
1729 sctx->flags |= SI_CONTEXT_INV_L2;
1730 else if (shaders_read_metadata)
1731 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1732 } else {
1733 /* GFX6-GFX8 */
1734 sctx->flags |= SI_CONTEXT_INV_L2;
1735 }
1736 }
1737
1738 static inline bool
1739 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1740 {
1741 return (stencil_sampler && tex->can_sample_s) ||
1742 (!stencil_sampler && tex->can_sample_z);
1743 }
1744
1745 static inline bool
1746 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1747 {
1748 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1749 return false;
1750
1751 return tex->htile_offset && level == 0;
1752 }
1753
1754 static inline bool
1755 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1756 {
1757 assert(!tex->tc_compatible_htile || tex->htile_offset);
1758 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1759 }
1760
1761 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1762 {
1763 if (sctx->ps_uses_fbfetch)
1764 return sctx->framebuffer.nr_color_samples;
1765
1766 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1767 }
1768
1769 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1770 {
1771 if (sctx->queued.named.rasterizer->rasterizer_discard)
1772 return 0;
1773
1774 struct si_shader_selector *ps = sctx->ps_shader.cso;
1775 if (!ps)
1776 return 0;
1777
1778 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1779 sctx->queued.named.blend->cb_target_mask;
1780
1781 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1782 colormask &= ps->colors_written_4bit;
1783 else if (!ps->colors_written_4bit)
1784 colormask = 0; /* color0 writes all cbufs, but it's not written */
1785
1786 return colormask;
1787 }
1788
1789 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1790 (1 << PIPE_PRIM_LINE_LOOP) | \
1791 (1 << PIPE_PRIM_LINE_STRIP) | \
1792 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1793 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1794
1795 static inline bool util_prim_is_lines(unsigned prim)
1796 {
1797 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1798 }
1799
1800 static inline bool util_prim_is_points_or_lines(unsigned prim)
1801 {
1802 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1803 (1 << PIPE_PRIM_POINTS))) != 0;
1804 }
1805
1806 static inline bool util_rast_prim_is_triangles(unsigned prim)
1807 {
1808 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1809 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1810 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1811 (1 << PIPE_PRIM_QUADS) |
1812 (1 << PIPE_PRIM_QUAD_STRIP) |
1813 (1 << PIPE_PRIM_POLYGON) |
1814 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1815 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1816 }
1817
1818 /**
1819 * Return true if there is enough memory in VRAM and GTT for the buffers
1820 * added so far.
1821 *
1822 * \param vram VRAM memory size not added to the buffer list yet
1823 * \param gtt GTT memory size not added to the buffer list yet
1824 */
1825 static inline bool
1826 radeon_cs_memory_below_limit(struct si_screen *screen,
1827 struct radeon_cmdbuf *cs,
1828 uint64_t vram, uint64_t gtt)
1829 {
1830 vram += cs->used_vram;
1831 gtt += cs->used_gart;
1832
1833 /* Anything that goes above the VRAM size should go to GTT. */
1834 if (vram > screen->info.vram_size)
1835 gtt += vram - screen->info.vram_size;
1836
1837 /* Now we just need to check if we have enough GTT. */
1838 return gtt < screen->info.gart_size * 0.7;
1839 }
1840
1841 /**
1842 * Add a buffer to the buffer list for the given command stream (CS).
1843 *
1844 * All buffers used by a CS must be added to the list. This tells the kernel
1845 * driver which buffers are used by GPU commands. Other buffers can
1846 * be swapped out (not accessible) during execution.
1847 *
1848 * The buffer list becomes empty after every context flush and must be
1849 * rebuilt.
1850 */
1851 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1852 struct radeon_cmdbuf *cs,
1853 struct si_resource *bo,
1854 enum radeon_bo_usage usage,
1855 enum radeon_bo_priority priority)
1856 {
1857 assert(usage);
1858 sctx->ws->cs_add_buffer(
1859 cs, bo->buf,
1860 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1861 bo->domains, priority);
1862 }
1863
1864 /**
1865 * Same as above, but also checks memory usage and flushes the context
1866 * accordingly.
1867 *
1868 * When this SHOULD NOT be used:
1869 *
1870 * - if si_context_add_resource_size has been called for the buffer
1871 * followed by *_need_cs_space for checking the memory usage
1872 *
1873 * - if si_need_dma_space has been called for the buffer
1874 *
1875 * - when emitting state packets and draw packets (because preceding packets
1876 * can't be re-emitted at that point)
1877 *
1878 * - if shader resource "enabled_mask" is not up-to-date or there is
1879 * a different constraint disallowing a context flush
1880 */
1881 static inline void
1882 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1883 struct si_resource *bo,
1884 enum radeon_bo_usage usage,
1885 enum radeon_bo_priority priority,
1886 bool check_mem)
1887 {
1888 if (check_mem &&
1889 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1890 sctx->vram + bo->vram_usage,
1891 sctx->gtt + bo->gart_usage))
1892 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1893
1894 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1895 }
1896
1897 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1898 {
1899 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1900 }
1901
1902 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1903 enum pipe_shader_type shader_type,
1904 bool ngg, bool es)
1905 {
1906 if (shader_type == PIPE_SHADER_COMPUTE)
1907 return sscreen->compute_wave_size;
1908 else if (shader_type == PIPE_SHADER_FRAGMENT)
1909 return sscreen->ps_wave_size;
1910 else if ((shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1911 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1912 return 64;
1913 else
1914 return sscreen->ge_wave_size;
1915 }
1916
1917 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1918 {
1919 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1920 shader->key.as_ngg, shader->key.as_es);
1921 }
1922
1923 #define PRINT_ERR(fmt, args...) \
1924 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1925
1926 #endif