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radeonsi/gfx10: allocate GDS BOs for streamout
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_UNSAFE_MATH,
149 DBG_SI_SCHED,
150 DBG_GISEL,
151
152 /* Shader compiler options (with no effect on the shader cache): */
153 DBG_CHECK_IR,
154 DBG_MONOLITHIC_SHADERS,
155 DBG_NO_OPT_VARIANT,
156
157 /* Information logging options: */
158 DBG_INFO,
159 DBG_TEX,
160 DBG_COMPUTE,
161 DBG_VM,
162
163 /* Driver options: */
164 DBG_FORCE_DMA,
165 DBG_NO_ASYNC_DMA,
166 DBG_NO_WC,
167 DBG_CHECK_VM,
168 DBG_RESERVE_VMID,
169 DBG_ZERO_VRAM,
170
171 /* 3D engine options: */
172 DBG_ALWAYS_PD,
173 DBG_PD,
174 DBG_NO_PD,
175 DBG_SWITCH_ON_EOP,
176 DBG_NO_OUT_OF_ORDER,
177 DBG_NO_DPBB,
178 DBG_NO_DFSM,
179 DBG_DPBB,
180 DBG_DFSM,
181 DBG_NO_HYPERZ,
182 DBG_NO_RB_PLUS,
183 DBG_NO_2D_TILING,
184 DBG_NO_TILING,
185 DBG_NO_DCC,
186 DBG_NO_DCC_CLEAR,
187 DBG_NO_DCC_FB,
188 DBG_NO_DCC_MSAA,
189 DBG_NO_FMASK,
190
191 /* Tests: */
192 DBG_TEST_DMA,
193 DBG_TEST_VMFAULT_CP,
194 DBG_TEST_VMFAULT_SDMA,
195 DBG_TEST_VMFAULT_SHADER,
196 DBG_TEST_DMA_PERF,
197 DBG_TEST_GDS,
198 DBG_TEST_GDS_MM,
199 DBG_TEST_GDS_OA_MM,
200 };
201
202 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
203 #define DBG(name) (1ull << DBG_##name)
204
205 enum si_cache_policy {
206 L2_BYPASS,
207 L2_STREAM, /* same as SLC=1 */
208 L2_LRU, /* same as SLC=0 */
209 };
210
211 enum si_coherency {
212 SI_COHERENCY_NONE, /* no cache flushes needed */
213 SI_COHERENCY_SHADER,
214 SI_COHERENCY_CB_META,
215 SI_COHERENCY_CP,
216 };
217
218 struct si_compute;
219 struct si_shader_context;
220 struct hash_table;
221 struct u_suballocator;
222
223 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
224 * at the moment.
225 */
226 struct si_resource {
227 struct threaded_resource b;
228
229 /* Winsys objects. */
230 struct pb_buffer *buf;
231 uint64_t gpu_address;
232 /* Memory usage if the buffer placement is optimal. */
233 uint64_t vram_usage;
234 uint64_t gart_usage;
235
236 /* Resource properties. */
237 uint64_t bo_size;
238 unsigned bo_alignment;
239 enum radeon_bo_domain domains;
240 enum radeon_bo_flag flags;
241 unsigned bind_history;
242 int max_forced_staging_uploads;
243
244 /* The buffer range which is initialized (with a write transfer,
245 * streamout, DMA, or as a random access target). The rest of
246 * the buffer is considered invalid and can be mapped unsynchronized.
247 *
248 * This allows unsychronized mapping of a buffer range which hasn't
249 * been used yet. It's for applications which forget to use
250 * the unsynchronized map flag and expect the driver to figure it out.
251 */
252 struct util_range valid_buffer_range;
253
254 /* For buffers only. This indicates that a write operation has been
255 * performed by TC L2, but the cache hasn't been flushed.
256 * Any hw block which doesn't use or bypasses TC L2 should check this
257 * flag and flush the cache before using the buffer.
258 *
259 * For example, TC L2 must be flushed if a buffer which has been
260 * modified by a shader store instruction is about to be used as
261 * an index buffer. The reason is that VGT DMA index fetching doesn't
262 * use TC L2.
263 */
264 bool TC_L2_dirty;
265
266 /* Whether this resource is referenced by bindless handles. */
267 bool texture_handle_allocated;
268 bool image_handle_allocated;
269
270 /* Whether the resource has been exported via resource_get_handle. */
271 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
272 };
273
274 struct si_transfer {
275 struct threaded_transfer b;
276 struct si_resource *staging;
277 unsigned offset;
278 };
279
280 struct si_texture {
281 struct si_resource buffer;
282
283 struct radeon_surf surface;
284 uint64_t size;
285 struct si_texture *flushed_depth_texture;
286
287 /* One texture allocation can contain these buffers:
288 * - image (pixel data)
289 * - FMASK buffer (MSAA compression)
290 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
291 * - HTILE buffer (Z/S compression and fast Z/S clear)
292 * - DCC buffer (color compression and new fast color clear)
293 * - displayable DCC buffer (if the DCC buffer is not displayable)
294 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
295 */
296 uint64_t fmask_offset;
297 uint64_t cmask_offset;
298 uint64_t cmask_base_address_reg;
299 struct si_resource *cmask_buffer;
300 uint64_t dcc_offset; /* 0 = disabled */
301 uint64_t display_dcc_offset;
302 uint64_t dcc_retile_map_offset;
303 unsigned cb_color_info; /* fast clear enable bit */
304 unsigned color_clear_value[2];
305 unsigned last_msaa_resolve_target_micro_mode;
306 unsigned num_level0_transfers;
307
308 /* Depth buffer compression and fast clear. */
309 uint64_t htile_offset;
310 float depth_clear_value;
311 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
312 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
313 enum pipe_format db_render_format:16;
314 uint8_t stencil_clear_value;
315 bool tc_compatible_htile:1;
316 bool depth_cleared:1; /* if it was cleared at least once */
317 bool stencil_cleared:1; /* if it was cleared at least once */
318 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
319 bool is_depth:1;
320 bool db_compatible:1;
321 bool can_sample_z:1;
322 bool can_sample_s:1;
323
324 /* We need to track DCC dirtiness, because st/dri usually calls
325 * flush_resource twice per frame (not a bug) and we don't wanna
326 * decompress DCC twice. Also, the dirty tracking must be done even
327 * if DCC isn't used, because it's required by the DCC usage analysis
328 * for a possible future enablement.
329 */
330 bool separate_dcc_dirty:1;
331 /* Statistics gathering for the DCC enablement heuristic. */
332 bool dcc_gather_statistics:1;
333 /* Counter that should be non-zero if the texture is bound to a
334 * framebuffer.
335 */
336 unsigned framebuffers_bound;
337 /* Whether the texture is a displayable back buffer and needs DCC
338 * decompression, which is expensive. Therefore, it's enabled only
339 * if statistics suggest that it will pay off and it's allocated
340 * separately. It can't be bound as a sampler by apps. Limited to
341 * target == 2D and last_level == 0. If enabled, dcc_offset contains
342 * the absolute GPUVM address, not the relative one.
343 */
344 struct si_resource *dcc_separate_buffer;
345 /* When DCC is temporarily disabled, the separate buffer is here. */
346 struct si_resource *last_dcc_separate_buffer;
347 /* Estimate of how much this color buffer is written to in units of
348 * full-screen draws: ps_invocations / (width * height)
349 * Shader kills, late Z, and blending with trivial discards make it
350 * inaccurate (we need to count CB updates, not PS invocations).
351 */
352 unsigned ps_draw_ratio;
353 /* The number of clears since the last DCC usage analysis. */
354 unsigned num_slow_clears;
355 };
356
357 struct si_surface {
358 struct pipe_surface base;
359
360 /* These can vary with block-compressed textures. */
361 uint16_t width0;
362 uint16_t height0;
363
364 bool color_initialized:1;
365 bool depth_initialized:1;
366
367 /* Misc. color flags. */
368 bool color_is_int8:1;
369 bool color_is_int10:1;
370 bool dcc_incompatible:1;
371
372 /* Color registers. */
373 unsigned cb_color_info;
374 unsigned cb_color_view;
375 unsigned cb_color_attrib;
376 unsigned cb_color_attrib2; /* GFX9 and later */
377 unsigned cb_color_attrib3; /* GFX10 and later */
378 unsigned cb_dcc_control; /* GFX8 and later */
379 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
380 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
381 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
382 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
383
384 /* DB registers. */
385 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
386 uint64_t db_stencil_base;
387 uint64_t db_htile_data_base;
388 unsigned db_depth_info;
389 unsigned db_z_info;
390 unsigned db_z_info2; /* GFX9 only */
391 unsigned db_depth_view;
392 unsigned db_depth_size;
393 unsigned db_depth_slice;
394 unsigned db_stencil_info;
395 unsigned db_stencil_info2; /* GFX9 only */
396 unsigned db_htile_surface;
397 };
398
399 struct si_mmio_counter {
400 unsigned busy;
401 unsigned idle;
402 };
403
404 union si_mmio_counters {
405 struct {
406 /* For global GPU load including SDMA. */
407 struct si_mmio_counter gpu;
408
409 /* GRBM_STATUS */
410 struct si_mmio_counter spi;
411 struct si_mmio_counter gui;
412 struct si_mmio_counter ta;
413 struct si_mmio_counter gds;
414 struct si_mmio_counter vgt;
415 struct si_mmio_counter ia;
416 struct si_mmio_counter sx;
417 struct si_mmio_counter wd;
418 struct si_mmio_counter bci;
419 struct si_mmio_counter sc;
420 struct si_mmio_counter pa;
421 struct si_mmio_counter db;
422 struct si_mmio_counter cp;
423 struct si_mmio_counter cb;
424
425 /* SRBM_STATUS2 */
426 struct si_mmio_counter sdma;
427
428 /* CP_STAT */
429 struct si_mmio_counter pfp;
430 struct si_mmio_counter meq;
431 struct si_mmio_counter me;
432 struct si_mmio_counter surf_sync;
433 struct si_mmio_counter cp_dma;
434 struct si_mmio_counter scratch_ram;
435 } named;
436 unsigned array[0];
437 };
438
439 struct si_memory_object {
440 struct pipe_memory_object b;
441 struct pb_buffer *buf;
442 uint32_t stride;
443 };
444
445 /* Saved CS data for debugging features. */
446 struct radeon_saved_cs {
447 uint32_t *ib;
448 unsigned num_dw;
449
450 struct radeon_bo_list_item *bo_list;
451 unsigned bo_count;
452 };
453
454 struct si_screen {
455 struct pipe_screen b;
456 struct radeon_winsys *ws;
457 struct disk_cache *disk_shader_cache;
458
459 struct radeon_info info;
460 uint64_t debug_flags;
461 char renderer_string[183];
462
463 void (*make_texture_descriptor)(
464 struct si_screen *screen,
465 struct si_texture *tex,
466 bool sampler,
467 enum pipe_texture_target target,
468 enum pipe_format pipe_format,
469 const unsigned char state_swizzle[4],
470 unsigned first_level, unsigned last_level,
471 unsigned first_layer, unsigned last_layer,
472 unsigned width, unsigned height, unsigned depth,
473 uint32_t *state,
474 uint32_t *fmask_state);
475
476 unsigned pa_sc_raster_config;
477 unsigned pa_sc_raster_config_1;
478 unsigned se_tile_repeat;
479 unsigned gs_table_depth;
480 unsigned tess_offchip_block_dw_size;
481 unsigned tess_offchip_ring_size;
482 unsigned tess_factor_ring_size;
483 unsigned vgt_hs_offchip_param;
484 unsigned eqaa_force_coverage_samples;
485 unsigned eqaa_force_z_samples;
486 unsigned eqaa_force_color_samples;
487 bool has_clear_state;
488 bool has_distributed_tess;
489 bool has_draw_indirect_multi;
490 bool has_out_of_order_rast;
491 bool assume_no_z_fights;
492 bool commutative_blend_add;
493 bool has_gfx9_scissor_bug;
494 bool has_msaa_sample_loc_bug;
495 bool has_ls_vgpr_init_bug;
496 bool has_dcc_constant_encode;
497 bool dpbb_allowed;
498 bool dfsm_allowed;
499 bool llvm_has_working_vgpr_indexing;
500
501 struct {
502 #define OPT_BOOL(name, dflt, description) bool name:1;
503 #include "si_debug_options.h"
504 } options;
505
506 /* Whether shaders are monolithic (1-part) or separate (3-part). */
507 bool use_monolithic_shaders;
508 bool record_llvm_ir;
509 bool has_rbplus; /* if RB+ registers exist */
510 bool rbplus_allowed; /* if RB+ is allowed */
511 bool dcc_msaa_allowed;
512 bool cpdma_prefetch_writes_memory;
513
514 struct slab_parent_pool pool_transfers;
515
516 /* Texture filter settings. */
517 int force_aniso; /* -1 = disabled */
518
519 /* Auxiliary context. Mainly used to initialize resources.
520 * It must be locked prior to using and flushed before unlocking. */
521 struct pipe_context *aux_context;
522 mtx_t aux_context_lock;
523
524 /* This must be in the screen, because UE4 uses one context for
525 * compilation and another one for rendering.
526 */
527 unsigned num_compilations;
528 /* Along with ST_DEBUG=precompile, this should show if applications
529 * are loading shaders on demand. This is a monotonic counter.
530 */
531 unsigned num_shaders_created;
532 unsigned num_shader_cache_hits;
533
534 /* GPU load thread. */
535 mtx_t gpu_load_mutex;
536 thrd_t gpu_load_thread;
537 union si_mmio_counters mmio_counters;
538 volatile unsigned gpu_load_stop_thread; /* bool */
539
540 /* Performance counters. */
541 struct si_perfcounters *perfcounters;
542
543 /* If pipe_screen wants to recompute and re-emit the framebuffer,
544 * sampler, and image states of all contexts, it should atomically
545 * increment this.
546 *
547 * Each context will compare this with its own last known value of
548 * the counter before drawing and re-emit the states accordingly.
549 */
550 unsigned dirty_tex_counter;
551 unsigned dirty_buf_counter;
552
553 /* Atomically increment this counter when an existing texture's
554 * metadata is enabled or disabled in a way that requires changing
555 * contexts' compressed texture binding masks.
556 */
557 unsigned compressed_colortex_counter;
558
559 struct {
560 /* Context flags to set so that all writes from earlier jobs
561 * in the CP are seen by L2 clients.
562 */
563 unsigned cp_to_L2;
564
565 /* Context flags to set so that all writes from earlier jobs
566 * that end in L2 are seen by CP.
567 */
568 unsigned L2_to_cp;
569 } barrier_flags;
570
571 mtx_t shader_parts_mutex;
572 struct si_shader_part *vs_prologs;
573 struct si_shader_part *tcs_epilogs;
574 struct si_shader_part *gs_prologs;
575 struct si_shader_part *ps_prologs;
576 struct si_shader_part *ps_epilogs;
577
578 /* Shader cache in memory.
579 *
580 * Design & limitations:
581 * - The shader cache is per screen (= per process), never saved to
582 * disk, and skips redundant shader compilations from TGSI to bytecode.
583 * - It can only be used with one-variant-per-shader support, in which
584 * case only the main (typically middle) part of shaders is cached.
585 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
586 * variants of VS and TES are cached, so LS and ES aren't.
587 * - GS and CS aren't cached, but it's certainly possible to cache
588 * those as well.
589 */
590 mtx_t shader_cache_mutex;
591 struct hash_table *shader_cache;
592
593 /* Shader compiler queue for multithreaded compilation. */
594 struct util_queue shader_compiler_queue;
595 /* Use at most 3 normal compiler threads on quadcore and better.
596 * Hyperthreaded CPUs report the number of threads, but we want
597 * the number of cores. We only need this many threads for shader-db. */
598 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
599
600 struct util_queue shader_compiler_queue_low_priority;
601 /* Use at most 2 low priority threads on quadcore and better.
602 * We want to minimize the impact on multithreaded Mesa. */
603 struct ac_llvm_compiler compiler_lowp[10];
604 };
605
606 struct si_blend_color {
607 struct pipe_blend_color state;
608 bool any_nonzeros;
609 };
610
611 struct si_sampler_view {
612 struct pipe_sampler_view base;
613 /* [0..7] = image descriptor
614 * [4..7] = buffer descriptor */
615 uint32_t state[8];
616 uint32_t fmask_state[8];
617 const struct legacy_surf_level *base_level_info;
618 ubyte base_level;
619 ubyte block_width;
620 bool is_stencil_sampler;
621 bool is_integer;
622 bool dcc_incompatible;
623 };
624
625 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
626
627 struct si_sampler_state {
628 #ifndef NDEBUG
629 unsigned magic;
630 #endif
631 uint32_t val[4];
632 uint32_t integer_val[4];
633 uint32_t upgraded_depth_val[4];
634 };
635
636 struct si_cs_shader_state {
637 struct si_compute *program;
638 struct si_compute *emitted_program;
639 unsigned offset;
640 bool initialized;
641 bool uses_scratch;
642 };
643
644 struct si_samplers {
645 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
646 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
647
648 /* The i-th bit is set if that element is enabled (non-NULL resource). */
649 unsigned enabled_mask;
650 uint32_t needs_depth_decompress_mask;
651 uint32_t needs_color_decompress_mask;
652 };
653
654 struct si_images {
655 struct pipe_image_view views[SI_NUM_IMAGES];
656 uint32_t needs_color_decompress_mask;
657 unsigned enabled_mask;
658 };
659
660 struct si_framebuffer {
661 struct pipe_framebuffer_state state;
662 unsigned colorbuf_enabled_4bit;
663 unsigned spi_shader_col_format;
664 unsigned spi_shader_col_format_alpha;
665 unsigned spi_shader_col_format_blend;
666 unsigned spi_shader_col_format_blend_alpha;
667 ubyte nr_samples:5; /* at most 16xAA */
668 ubyte log_samples:3; /* at most 4 = 16xAA */
669 ubyte nr_color_samples; /* at most 8xAA */
670 ubyte compressed_cb_mask;
671 ubyte uncompressed_cb_mask;
672 ubyte color_is_int8;
673 ubyte color_is_int10;
674 ubyte dirty_cbufs;
675 ubyte dcc_overwrite_combiner_watermark;
676 bool dirty_zsbuf;
677 bool any_dst_linear;
678 bool CB_has_shader_readable_metadata;
679 bool DB_has_shader_readable_metadata;
680 bool all_DCC_pipe_aligned;
681 };
682
683 enum si_quant_mode {
684 /* This is the list we want to support. */
685 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
686 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
687 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
688 };
689
690 struct si_signed_scissor {
691 int minx;
692 int miny;
693 int maxx;
694 int maxy;
695 enum si_quant_mode quant_mode;
696 };
697
698 struct si_viewports {
699 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
700 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
701 bool y_inverted;
702 };
703
704 struct si_clip_state {
705 struct pipe_clip_state state;
706 bool any_nonzeros;
707 };
708
709 struct si_streamout_target {
710 struct pipe_stream_output_target b;
711
712 /* The buffer where BUFFER_FILLED_SIZE is stored. */
713 struct si_resource *buf_filled_size;
714 unsigned buf_filled_size_offset;
715 bool buf_filled_size_valid;
716
717 unsigned stride_in_dw;
718 };
719
720 struct si_streamout {
721 bool begin_emitted;
722
723 unsigned enabled_mask;
724 unsigned num_targets;
725 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
726
727 unsigned append_bitmask;
728 bool suspended;
729
730 /* External state which comes from the vertex shader,
731 * it must be set explicitly when binding a shader. */
732 uint16_t *stride_in_dw;
733 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
734
735 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
736 unsigned hw_enabled_mask;
737
738 /* The state of VGT_STRMOUT_(CONFIG|EN). */
739 bool streamout_enabled;
740 bool prims_gen_query_enabled;
741 int num_prims_gen_queries;
742 };
743
744 /* A shader state consists of the shader selector, which is a constant state
745 * object shared by multiple contexts and shouldn't be modified, and
746 * the current shader variant selected for this context.
747 */
748 struct si_shader_ctx_state {
749 struct si_shader_selector *cso;
750 struct si_shader *current;
751 };
752
753 #define SI_NUM_VGT_PARAM_KEY_BITS 12
754 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
755
756 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
757 * Some fields are set by state-change calls, most are set by draw_vbo.
758 */
759 union si_vgt_param_key {
760 struct {
761 #ifdef PIPE_ARCH_LITTLE_ENDIAN
762 unsigned prim:4;
763 unsigned uses_instancing:1;
764 unsigned multi_instances_smaller_than_primgroup:1;
765 unsigned primitive_restart:1;
766 unsigned count_from_stream_output:1;
767 unsigned line_stipple_enabled:1;
768 unsigned uses_tess:1;
769 unsigned tess_uses_prim_id:1;
770 unsigned uses_gs:1;
771 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
772 #else /* PIPE_ARCH_BIG_ENDIAN */
773 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
774 unsigned uses_gs:1;
775 unsigned tess_uses_prim_id:1;
776 unsigned uses_tess:1;
777 unsigned line_stipple_enabled:1;
778 unsigned count_from_stream_output:1;
779 unsigned primitive_restart:1;
780 unsigned multi_instances_smaller_than_primgroup:1;
781 unsigned uses_instancing:1;
782 unsigned prim:4;
783 #endif
784 } u;
785 uint32_t index;
786 };
787
788 #define SI_NUM_VGT_STAGES_KEY_BITS 4
789 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
790
791 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
792 * Some fields are set by state-change calls, most are set by draw_vbo.
793 */
794 union si_vgt_stages_key {
795 struct {
796 #ifdef PIPE_ARCH_LITTLE_ENDIAN
797 unsigned tess:1;
798 unsigned gs:1;
799 unsigned ngg:1; /* gfx10+ */
800 unsigned streamout:1; /* only used with NGG */
801 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
802 #else /* PIPE_ARCH_BIG_ENDIAN */
803 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
804 unsigned streamout:1;
805 unsigned ngg:1;
806 unsigned gs:1;
807 unsigned tess:1;
808 #endif
809 } u;
810 uint32_t index;
811 };
812
813 struct si_texture_handle
814 {
815 unsigned desc_slot;
816 bool desc_dirty;
817 struct pipe_sampler_view *view;
818 struct si_sampler_state sstate;
819 };
820
821 struct si_image_handle
822 {
823 unsigned desc_slot;
824 bool desc_dirty;
825 struct pipe_image_view view;
826 };
827
828 struct si_saved_cs {
829 struct pipe_reference reference;
830 struct si_context *ctx;
831 struct radeon_saved_cs gfx;
832 struct radeon_saved_cs compute;
833 struct si_resource *trace_buf;
834 unsigned trace_id;
835
836 unsigned gfx_last_dw;
837 unsigned compute_last_dw;
838 bool flushed;
839 int64_t time_flush;
840 };
841
842 struct si_sdma_upload {
843 struct si_resource *dst;
844 struct si_resource *src;
845 unsigned src_offset;
846 unsigned dst_offset;
847 unsigned size;
848 };
849
850 struct si_context {
851 struct pipe_context b; /* base class */
852
853 enum radeon_family family;
854 enum chip_class chip_class;
855
856 struct radeon_winsys *ws;
857 struct radeon_winsys_ctx *ctx;
858 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
859 struct radeon_cmdbuf *dma_cs;
860 struct pipe_fence_handle *last_gfx_fence;
861 struct pipe_fence_handle *last_sdma_fence;
862 struct si_resource *eop_bug_scratch;
863 struct u_upload_mgr *cached_gtt_allocator;
864 struct threaded_context *tc;
865 struct u_suballocator *allocator_zeroed_memory;
866 struct slab_child_pool pool_transfers;
867 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
868 struct pipe_device_reset_callback device_reset_callback;
869 struct u_log_context *log;
870 void *query_result_shader;
871 void *sh_query_result_shader;
872
873 void (*emit_cache_flush)(struct si_context *ctx);
874
875 struct blitter_context *blitter;
876 void *custom_dsa_flush;
877 void *custom_blend_resolve;
878 void *custom_blend_fmask_decompress;
879 void *custom_blend_eliminate_fastclear;
880 void *custom_blend_dcc_decompress;
881 void *vs_blit_pos;
882 void *vs_blit_pos_layered;
883 void *vs_blit_color;
884 void *vs_blit_color_layered;
885 void *vs_blit_texcoord;
886 void *cs_clear_buffer;
887 void *cs_copy_buffer;
888 void *cs_copy_image;
889 void *cs_copy_image_1d_array;
890 void *cs_clear_render_target;
891 void *cs_clear_render_target_1d_array;
892 void *cs_dcc_retile;
893 struct si_screen *screen;
894 struct pipe_debug_callback debug;
895 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
896 struct si_shader_ctx_state fixed_func_tcs_shader;
897 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
898 struct si_resource *wait_mem_scratch;
899 unsigned wait_mem_number;
900 uint16_t prefetch_L2_mask;
901
902 bool has_graphics;
903 bool gfx_flush_in_progress:1;
904 bool gfx_last_ib_is_busy:1;
905 bool compute_is_busy:1;
906
907 unsigned num_gfx_cs_flushes;
908 unsigned initial_gfx_cs_size;
909 unsigned last_dirty_tex_counter;
910 unsigned last_dirty_buf_counter;
911 unsigned last_compressed_colortex_counter;
912 unsigned last_num_draw_calls;
913 unsigned flags; /* flush flags */
914 /* Current unaccounted memory usage. */
915 uint64_t vram;
916 uint64_t gtt;
917
918 /* Compute-based primitive discard. */
919 unsigned prim_discard_vertex_count_threshold;
920 struct pb_buffer *gds;
921 struct pb_buffer *gds_oa;
922 struct radeon_cmdbuf *prim_discard_compute_cs;
923 unsigned compute_gds_offset;
924 struct si_shader *compute_ib_last_shader;
925 uint32_t compute_rewind_va;
926 unsigned compute_num_prims_in_batch;
927 bool preserve_prim_restart_gds_at_flush;
928 /* index_ring is divided into 2 halves for doublebuffering. */
929 struct si_resource *index_ring;
930 unsigned index_ring_base; /* offset of a per-IB portion */
931 unsigned index_ring_offset; /* offset within a per-IB portion */
932 unsigned index_ring_size_per_ib; /* max available size per IB */
933 bool prim_discard_compute_ib_initialized;
934 /* For tracking the last execution barrier - it can be either
935 * a WRITE_DATA packet or a fence. */
936 uint32_t *last_pkt3_write_data;
937 struct si_resource *barrier_buf;
938 unsigned barrier_buf_offset;
939 struct pipe_fence_handle *last_ib_barrier_fence;
940 struct si_resource *last_ib_barrier_buf;
941 unsigned last_ib_barrier_buf_offset;
942
943 /* Atoms (direct states). */
944 union si_state_atoms atoms;
945 unsigned dirty_atoms; /* mask */
946 /* PM4 states (precomputed immutable states) */
947 unsigned dirty_states;
948 union si_state queued;
949 union si_state emitted;
950
951 /* Atom declarations. */
952 struct si_framebuffer framebuffer;
953 unsigned sample_locs_num_samples;
954 uint16_t sample_mask;
955 unsigned last_cb_target_mask;
956 struct si_blend_color blend_color;
957 struct si_clip_state clip_state;
958 struct si_shader_data shader_pointers;
959 struct si_stencil_ref stencil_ref;
960 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
961 struct si_streamout streamout;
962 struct si_viewports viewports;
963 unsigned num_window_rectangles;
964 bool window_rectangles_include;
965 struct pipe_scissor_state window_rectangles[4];
966
967 /* Precomputed states. */
968 struct si_pm4_state *init_config;
969 struct si_pm4_state *init_config_gs_rings;
970 bool init_config_has_vgt_flush;
971 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
972
973 /* shaders */
974 struct si_shader_ctx_state ps_shader;
975 struct si_shader_ctx_state gs_shader;
976 struct si_shader_ctx_state vs_shader;
977 struct si_shader_ctx_state tcs_shader;
978 struct si_shader_ctx_state tes_shader;
979 struct si_shader_ctx_state cs_prim_discard_state;
980 struct si_cs_shader_state cs_shader_state;
981
982 /* shader information */
983 struct si_vertex_elements *vertex_elements;
984 unsigned sprite_coord_enable;
985 unsigned cs_max_waves_per_sh;
986 bool flatshade;
987 bool do_update_shaders;
988
989 /* vertex buffer descriptors */
990 uint32_t *vb_descriptors_gpu_list;
991 struct si_resource *vb_descriptors_buffer;
992 unsigned vb_descriptors_offset;
993
994 /* shader descriptors */
995 struct si_descriptors descriptors[SI_NUM_DESCS];
996 unsigned descriptors_dirty;
997 unsigned shader_pointers_dirty;
998 unsigned shader_needs_decompress_mask;
999 struct si_buffer_resources rw_buffers;
1000 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1001 struct si_samplers samplers[SI_NUM_SHADERS];
1002 struct si_images images[SI_NUM_SHADERS];
1003 bool bo_list_add_all_resident_resources;
1004 bool bo_list_add_all_gfx_resources;
1005 bool bo_list_add_all_compute_resources;
1006
1007 /* other shader resources */
1008 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1009 struct pipe_resource *esgs_ring;
1010 struct pipe_resource *gsvs_ring;
1011 struct pipe_resource *tess_rings;
1012 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1013 struct si_resource *border_color_buffer;
1014 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1015 unsigned border_color_count;
1016 unsigned num_vs_blit_sgprs;
1017 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1018 uint32_t cs_user_data[4];
1019
1020 /* Vertex and index buffers. */
1021 bool vertex_buffers_dirty;
1022 bool vertex_buffer_pointer_dirty;
1023 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1024 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1025
1026 /* MSAA config state. */
1027 int ps_iter_samples;
1028 bool ps_uses_fbfetch;
1029 bool smoothing_enabled;
1030
1031 /* DB render state. */
1032 unsigned ps_db_shader_control;
1033 unsigned dbcb_copy_sample;
1034 bool dbcb_depth_copy_enabled:1;
1035 bool dbcb_stencil_copy_enabled:1;
1036 bool db_flush_depth_inplace:1;
1037 bool db_flush_stencil_inplace:1;
1038 bool db_depth_clear:1;
1039 bool db_depth_disable_expclear:1;
1040 bool db_stencil_clear:1;
1041 bool db_stencil_disable_expclear:1;
1042 bool occlusion_queries_disabled:1;
1043 bool generate_mipmap_for_depth:1;
1044
1045 /* Emitted draw state. */
1046 bool gs_tri_strip_adj_fix:1;
1047 bool ls_vgpr_fix:1;
1048 bool prim_discard_cs_instancing:1;
1049 bool ngg:1;
1050 int last_index_size;
1051 int last_base_vertex;
1052 int last_start_instance;
1053 int last_instance_count;
1054 int last_drawid;
1055 int last_sh_base_reg;
1056 int last_primitive_restart_en;
1057 int last_restart_index;
1058 int last_prim;
1059 int last_multi_vgt_param;
1060 int last_rast_prim;
1061 unsigned last_sc_line_stipple;
1062 unsigned current_vs_state;
1063 unsigned last_vs_state;
1064 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1065
1066 /* Scratch buffer */
1067 struct si_resource *scratch_buffer;
1068 unsigned scratch_waves;
1069 unsigned spi_tmpring_size;
1070
1071 struct si_resource *compute_scratch_buffer;
1072
1073 /* Emitted derived tessellation state. */
1074 /* Local shader (VS), or HS if LS-HS are merged. */
1075 struct si_shader *last_ls;
1076 struct si_shader_selector *last_tcs;
1077 int last_num_tcs_input_cp;
1078 int last_tes_sh_base;
1079 bool last_tess_uses_primid;
1080 unsigned last_num_patches;
1081 int last_ls_hs_config;
1082
1083 /* Debug state. */
1084 bool is_debug;
1085 struct si_saved_cs *current_saved_cs;
1086 uint64_t dmesg_timestamp;
1087 unsigned apitrace_call_number;
1088
1089 /* Other state */
1090 bool need_check_render_feedback;
1091 bool decompression_enabled;
1092 bool dpbb_force_off;
1093 bool vs_writes_viewport_index;
1094 bool vs_disables_clipping_viewport;
1095
1096 /* Precomputed IA_MULTI_VGT_PARAM */
1097 union si_vgt_param_key ia_multi_vgt_param_key;
1098 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1099
1100 /* Bindless descriptors. */
1101 struct si_descriptors bindless_descriptors;
1102 struct util_idalloc bindless_used_slots;
1103 unsigned num_bindless_descriptors;
1104 bool bindless_descriptors_dirty;
1105 bool graphics_bindless_pointer_dirty;
1106 bool compute_bindless_pointer_dirty;
1107
1108 /* Allocated bindless handles */
1109 struct hash_table *tex_handles;
1110 struct hash_table *img_handles;
1111
1112 /* Resident bindless handles */
1113 struct util_dynarray resident_tex_handles;
1114 struct util_dynarray resident_img_handles;
1115
1116 /* Resident bindless handles which need decompression */
1117 struct util_dynarray resident_tex_needs_color_decompress;
1118 struct util_dynarray resident_img_needs_color_decompress;
1119 struct util_dynarray resident_tex_needs_depth_decompress;
1120
1121 /* Bindless state */
1122 bool uses_bindless_samplers;
1123 bool uses_bindless_images;
1124
1125 /* MSAA sample locations.
1126 * The first index is the sample index.
1127 * The second index is the coordinate: X, Y. */
1128 struct {
1129 float x1[1][2];
1130 float x2[2][2];
1131 float x4[4][2];
1132 float x8[8][2];
1133 float x16[16][2];
1134 } sample_positions;
1135 struct pipe_resource *sample_pos_buffer;
1136
1137 /* Misc stats. */
1138 unsigned num_draw_calls;
1139 unsigned num_decompress_calls;
1140 unsigned num_mrt_draw_calls;
1141 unsigned num_prim_restart_calls;
1142 unsigned num_spill_draw_calls;
1143 unsigned num_compute_calls;
1144 unsigned num_spill_compute_calls;
1145 unsigned num_dma_calls;
1146 unsigned num_cp_dma_calls;
1147 unsigned num_vs_flushes;
1148 unsigned num_ps_flushes;
1149 unsigned num_cs_flushes;
1150 unsigned num_cb_cache_flushes;
1151 unsigned num_db_cache_flushes;
1152 unsigned num_L2_invalidates;
1153 unsigned num_L2_writebacks;
1154 unsigned num_resident_handles;
1155 uint64_t num_alloc_tex_transfer_bytes;
1156 unsigned last_tex_ps_draw_ratio; /* for query */
1157 unsigned compute_num_verts_accepted;
1158 unsigned compute_num_verts_rejected;
1159 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1160 unsigned context_roll;
1161
1162 /* Queries. */
1163 /* Maintain the list of active queries for pausing between IBs. */
1164 int num_occlusion_queries;
1165 int num_perfect_occlusion_queries;
1166 int num_pipeline_stat_queries;
1167 struct list_head active_queries;
1168 unsigned num_cs_dw_queries_suspend;
1169
1170 /* Render condition. */
1171 struct pipe_query *render_cond;
1172 unsigned render_cond_mode;
1173 bool render_cond_invert;
1174 bool render_cond_force_off; /* for u_blitter */
1175
1176 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1177 bool sdma_uploads_in_progress;
1178 struct si_sdma_upload *sdma_uploads;
1179 unsigned num_sdma_uploads;
1180 unsigned max_sdma_uploads;
1181
1182 /* Shader-based queries. */
1183 struct list_head shader_query_buffers;
1184 unsigned num_active_shader_queries;
1185
1186 /* Statistics gathering for the DCC enablement heuristic. It can't be
1187 * in si_texture because si_texture can be shared by multiple
1188 * contexts. This is for back buffers only. We shouldn't get too many
1189 * of those.
1190 *
1191 * X11 DRI3 rotates among a finite set of back buffers. They should
1192 * all fit in this array. If they don't, separate DCC might never be
1193 * enabled by DCC stat gathering.
1194 */
1195 struct {
1196 struct si_texture *tex;
1197 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1198 struct pipe_query *ps_stats[3];
1199 /* If all slots are used and another slot is needed,
1200 * the least recently used slot is evicted based on this. */
1201 int64_t last_use_timestamp;
1202 bool query_active;
1203 } dcc_stats[5];
1204
1205 /* Copy one resource to another using async DMA. */
1206 void (*dma_copy)(struct pipe_context *ctx,
1207 struct pipe_resource *dst,
1208 unsigned dst_level,
1209 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1210 struct pipe_resource *src,
1211 unsigned src_level,
1212 const struct pipe_box *src_box);
1213
1214 struct si_tracked_regs tracked_regs;
1215 };
1216
1217 /* cik_sdma.c */
1218 void cik_init_sdma_functions(struct si_context *sctx);
1219
1220 /* si_blit.c */
1221 enum si_blitter_op /* bitmask */
1222 {
1223 SI_SAVE_TEXTURES = 1,
1224 SI_SAVE_FRAMEBUFFER = 2,
1225 SI_SAVE_FRAGMENT_STATE = 4,
1226 SI_DISABLE_RENDER_COND = 8,
1227 };
1228
1229 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1230 void si_blitter_end(struct si_context *sctx);
1231 void si_init_blit_functions(struct si_context *sctx);
1232 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1233 void si_resource_copy_region(struct pipe_context *ctx,
1234 struct pipe_resource *dst,
1235 unsigned dst_level,
1236 unsigned dstx, unsigned dsty, unsigned dstz,
1237 struct pipe_resource *src,
1238 unsigned src_level,
1239 const struct pipe_box *src_box);
1240 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1241
1242 /* si_buffer.c */
1243 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1244 struct pb_buffer *buf,
1245 enum radeon_bo_usage usage);
1246 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1247 struct si_resource *resource,
1248 unsigned usage);
1249 void si_init_resource_fields(struct si_screen *sscreen,
1250 struct si_resource *res,
1251 uint64_t size, unsigned alignment);
1252 bool si_alloc_resource(struct si_screen *sscreen,
1253 struct si_resource *res);
1254 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1255 unsigned flags, unsigned usage,
1256 unsigned size, unsigned alignment);
1257 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1258 unsigned flags, unsigned usage,
1259 unsigned size, unsigned alignment);
1260 void si_replace_buffer_storage(struct pipe_context *ctx,
1261 struct pipe_resource *dst,
1262 struct pipe_resource *src);
1263 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1264 void si_init_buffer_functions(struct si_context *sctx);
1265
1266 /* si_clear.c */
1267 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1268 bool vi_alpha_is_on_msb(enum pipe_format format);
1269 void vi_dcc_clear_level(struct si_context *sctx,
1270 struct si_texture *tex,
1271 unsigned level, unsigned clear_value);
1272 void si_init_clear_functions(struct si_context *sctx);
1273
1274 /* si_compute_blit.c */
1275 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1276 enum si_cache_policy cache_policy);
1277 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1278 uint64_t offset, uint64_t size, uint32_t *clear_value,
1279 uint32_t clear_value_size, enum si_coherency coher,
1280 bool force_cpdma);
1281 void si_copy_buffer(struct si_context *sctx,
1282 struct pipe_resource *dst, struct pipe_resource *src,
1283 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1284 void si_compute_copy_image(struct si_context *sctx,
1285 struct pipe_resource *dst,
1286 unsigned dst_level,
1287 struct pipe_resource *src,
1288 unsigned src_level,
1289 unsigned dstx, unsigned dsty, unsigned dstz,
1290 const struct pipe_box *src_box);
1291 void si_compute_clear_render_target(struct pipe_context *ctx,
1292 struct pipe_surface *dstsurf,
1293 const union pipe_color_union *color,
1294 unsigned dstx, unsigned dsty,
1295 unsigned width, unsigned height,
1296 bool render_condition_enabled);
1297 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1298 void si_init_compute_blit_functions(struct si_context *sctx);
1299
1300 /* si_cp_dma.c */
1301 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1302 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1303 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1304 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1305 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1306 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1307 SI_CPDMA_SKIP_SYNC_AFTER | \
1308 SI_CPDMA_SKIP_SYNC_BEFORE | \
1309 SI_CPDMA_SKIP_GFX_SYNC | \
1310 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1311
1312 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1313 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1314 struct pipe_resource *dst, uint64_t offset,
1315 uint64_t size, unsigned value, unsigned user_flags,
1316 enum si_coherency coher, enum si_cache_policy cache_policy);
1317 void si_cp_dma_copy_buffer(struct si_context *sctx,
1318 struct pipe_resource *dst, struct pipe_resource *src,
1319 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1320 unsigned user_flags, enum si_coherency coher,
1321 enum si_cache_policy cache_policy);
1322 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1323 uint64_t offset, unsigned size);
1324 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1325 void si_test_gds(struct si_context *sctx);
1326 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1327 unsigned offset, unsigned size, unsigned dst_sel,
1328 unsigned engine, const void *data);
1329 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1330 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1331 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1332
1333 /* si_debug.c */
1334 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1335 struct radeon_saved_cs *saved, bool get_buffer_list);
1336 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1337 void si_destroy_saved_cs(struct si_saved_cs *scs);
1338 void si_auto_log_cs(void *data, struct u_log_context *log);
1339 void si_log_hw_flush(struct si_context *sctx);
1340 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1341 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1342 void si_init_debug_functions(struct si_context *sctx);
1343 void si_check_vm_faults(struct si_context *sctx,
1344 struct radeon_saved_cs *saved, enum ring_type ring);
1345 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1346
1347 /* si_dma.c */
1348 void si_init_dma_functions(struct si_context *sctx);
1349
1350 /* si_dma_cs.c */
1351 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1352 uint64_t offset);
1353 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1354 uint64_t offset, uint64_t size, unsigned clear_value);
1355 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1356 struct si_resource *dst, struct si_resource *src);
1357 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1358 struct pipe_fence_handle **fence);
1359 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1360 uint64_t offset, uint64_t size, unsigned value);
1361
1362 /* si_fence.c */
1363 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1364 unsigned event, unsigned event_flags,
1365 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1366 struct si_resource *buf, uint64_t va,
1367 uint32_t new_fence, unsigned query_type);
1368 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1369 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1370 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1371 void si_init_fence_functions(struct si_context *ctx);
1372 void si_init_screen_fence_functions(struct si_screen *screen);
1373 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1374 struct tc_unflushed_batch_token *tc_token);
1375
1376 /* si_get.c */
1377 void si_init_screen_get_functions(struct si_screen *sscreen);
1378
1379 /* si_gfx_cs.c */
1380 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1381 struct pipe_fence_handle **fence);
1382 void si_allocate_gds(struct si_context *ctx);
1383 void si_begin_new_gfx_cs(struct si_context *ctx);
1384 void si_need_gfx_cs_space(struct si_context *ctx);
1385 void si_unref_sdma_uploads(struct si_context *sctx);
1386
1387 /* si_gpu_load.c */
1388 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1389 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1390 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1391 uint64_t begin);
1392
1393 /* si_compute.c */
1394 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1395 unsigned si_get_compute_resource_limits(struct si_screen *sscreen,
1396 unsigned waves_per_threadgroup,
1397 unsigned max_waves_per_sh,
1398 unsigned threadgroups_per_cu);
1399 void si_init_compute_functions(struct si_context *sctx);
1400
1401 /* si_compute_prim_discard.c */
1402 enum si_prim_discard_outcome {
1403 SI_PRIM_DISCARD_ENABLED,
1404 SI_PRIM_DISCARD_DISABLED,
1405 SI_PRIM_DISCARD_DRAW_SPLIT,
1406 };
1407
1408 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1409 enum si_prim_discard_outcome
1410 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1411 const struct pipe_draw_info *info,
1412 bool primitive_restart);
1413 void si_compute_signal_gfx(struct si_context *sctx);
1414 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1415 const struct pipe_draw_info *info,
1416 unsigned index_size,
1417 unsigned base_vertex,
1418 uint64_t input_indexbuf_va,
1419 unsigned input_indexbuf_max_elements);
1420 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1421
1422 /* si_perfcounters.c */
1423 void si_init_perfcounters(struct si_screen *screen);
1424 void si_destroy_perfcounters(struct si_screen *screen);
1425
1426 /* si_pipe.c */
1427 bool si_check_device_reset(struct si_context *sctx);
1428
1429 /* si_query.c */
1430 void si_init_screen_query_functions(struct si_screen *sscreen);
1431 void si_init_query_functions(struct si_context *sctx);
1432 void si_suspend_queries(struct si_context *sctx);
1433 void si_resume_queries(struct si_context *sctx);
1434
1435 /* si_shaderlib_tgsi.c */
1436 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1437 unsigned num_layers);
1438 void *si_create_fixed_func_tcs(struct si_context *sctx);
1439 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1440 unsigned num_dwords_per_thread,
1441 bool dst_stream_cache_policy, bool is_copy);
1442 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1443 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1444 void *si_clear_render_target_shader(struct pipe_context *ctx);
1445 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1446 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1447 void *si_create_query_result_cs(struct si_context *sctx);
1448 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1449
1450 /* gfx10_query.c */
1451 void gfx10_init_query(struct si_context *sctx);
1452 void gfx10_destroy_query(struct si_context *sctx);
1453
1454 /* si_test_dma.c */
1455 void si_test_dma(struct si_screen *sscreen);
1456
1457 /* si_test_clearbuffer.c */
1458 void si_test_dma_perf(struct si_screen *sscreen);
1459
1460 /* si_uvd.c */
1461 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1462 const struct pipe_video_codec *templ);
1463
1464 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1465 const struct pipe_video_buffer *tmpl);
1466
1467 /* si_viewport.c */
1468 void si_update_vs_viewport_state(struct si_context *ctx);
1469 void si_init_viewport_functions(struct si_context *ctx);
1470
1471 /* si_texture.c */
1472 bool si_prepare_for_dma_blit(struct si_context *sctx,
1473 struct si_texture *dst,
1474 unsigned dst_level, unsigned dstx,
1475 unsigned dsty, unsigned dstz,
1476 struct si_texture *src,
1477 unsigned src_level,
1478 const struct pipe_box *src_box);
1479 void si_eliminate_fast_color_clear(struct si_context *sctx,
1480 struct si_texture *tex);
1481 void si_texture_discard_cmask(struct si_screen *sscreen,
1482 struct si_texture *tex);
1483 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1484 struct pipe_resource *texture);
1485 void si_print_texture_info(struct si_screen *sscreen,
1486 struct si_texture *tex, struct u_log_context *log);
1487 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1488 const struct pipe_resource *templ);
1489 bool vi_dcc_formats_compatible(enum pipe_format format1,
1490 enum pipe_format format2);
1491 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1492 unsigned level,
1493 enum pipe_format view_format);
1494 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1495 struct pipe_resource *tex,
1496 unsigned level,
1497 enum pipe_format view_format);
1498 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1499 struct pipe_resource *texture,
1500 const struct pipe_surface *templ,
1501 unsigned width0, unsigned height0,
1502 unsigned width, unsigned height);
1503 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1504 void vi_separate_dcc_try_enable(struct si_context *sctx,
1505 struct si_texture *tex);
1506 void vi_separate_dcc_start_query(struct si_context *sctx,
1507 struct si_texture *tex);
1508 void vi_separate_dcc_stop_query(struct si_context *sctx,
1509 struct si_texture *tex);
1510 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1511 struct si_texture *tex);
1512 bool si_texture_disable_dcc(struct si_context *sctx,
1513 struct si_texture *tex);
1514 void si_init_screen_texture_functions(struct si_screen *sscreen);
1515 void si_init_context_texture_functions(struct si_context *sctx);
1516
1517
1518 /*
1519 * common helpers
1520 */
1521
1522 static inline struct si_resource *si_resource(struct pipe_resource *r)
1523 {
1524 return (struct si_resource*)r;
1525 }
1526
1527 static inline void
1528 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1529 {
1530 pipe_resource_reference((struct pipe_resource **)ptr,
1531 (struct pipe_resource *)res);
1532 }
1533
1534 static inline void
1535 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1536 {
1537 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1538 }
1539
1540 static inline bool
1541 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1542 {
1543 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1544 }
1545
1546 static inline unsigned
1547 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1548 {
1549 if (stencil)
1550 return tex->surface.u.legacy.stencil_tiling_index[level];
1551 else
1552 return tex->surface.u.legacy.tiling_index[level];
1553 }
1554
1555 static inline unsigned
1556 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1557 {
1558 /* Don't count the needed CS space exactly and just use an upper bound.
1559 *
1560 * Also reserve space for stopping queries at the end of IB, because
1561 * the number of active queries is unlimited in theory.
1562 */
1563 return 2048 + sctx->num_cs_dw_queries_suspend;
1564 }
1565
1566 static inline void
1567 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1568 {
1569 if (r) {
1570 /* Add memory usage for need_gfx_cs_space */
1571 sctx->vram += si_resource(r)->vram_usage;
1572 sctx->gtt += si_resource(r)->gart_usage;
1573 }
1574 }
1575
1576 static inline void
1577 si_invalidate_draw_sh_constants(struct si_context *sctx)
1578 {
1579 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1580 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1581 }
1582
1583 static inline unsigned
1584 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1585 {
1586 return 1 << (atom - sctx->atoms.array);
1587 }
1588
1589 static inline void
1590 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1591 {
1592 unsigned bit = si_get_atom_bit(sctx, atom);
1593
1594 if (dirty)
1595 sctx->dirty_atoms |= bit;
1596 else
1597 sctx->dirty_atoms &= ~bit;
1598 }
1599
1600 static inline bool
1601 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1602 {
1603 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1604 }
1605
1606 static inline void
1607 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1608 {
1609 si_set_atom_dirty(sctx, atom, true);
1610 }
1611
1612 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1613 {
1614 if (sctx->gs_shader.cso)
1615 return &sctx->gs_shader;
1616 if (sctx->tes_shader.cso)
1617 return &sctx->tes_shader;
1618
1619 return &sctx->vs_shader;
1620 }
1621
1622 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1623 {
1624 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1625
1626 return vs->cso ? &vs->cso->info : NULL;
1627 }
1628
1629 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1630 {
1631 if (sctx->gs_shader.cso)
1632 return sctx->gs_shader.cso->gs_copy_shader;
1633
1634 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1635 return vs->current ? vs->current : NULL;
1636 }
1637
1638 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1639 unsigned processor)
1640 {
1641 return sscreen->debug_flags & (1 << processor);
1642 }
1643
1644 static inline bool si_get_strmout_en(struct si_context *sctx)
1645 {
1646 return sctx->streamout.streamout_enabled ||
1647 sctx->streamout.prims_gen_query_enabled;
1648 }
1649
1650 static inline unsigned
1651 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1652 {
1653 unsigned alignment, tcc_cache_line_size;
1654
1655 /* If the upload size is less than the cache line size (e.g. 16, 32),
1656 * the whole thing will fit into a cache line if we align it to its size.
1657 * The idea is that multiple small uploads can share a cache line.
1658 * If the upload size is greater, align it to the cache line size.
1659 */
1660 alignment = util_next_power_of_two(upload_size);
1661 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1662 return MIN2(alignment, tcc_cache_line_size);
1663 }
1664
1665 static inline void
1666 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1667 {
1668 if (pipe_reference(&(*dst)->reference, &src->reference))
1669 si_destroy_saved_cs(*dst);
1670
1671 *dst = src;
1672 }
1673
1674 static inline void
1675 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1676 bool shaders_read_metadata, bool dcc_pipe_aligned)
1677 {
1678 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1679 SI_CONTEXT_INV_VCACHE;
1680
1681 if (sctx->chip_class >= GFX9) {
1682 /* Single-sample color is coherent with shaders on GFX9, but
1683 * L2 metadata must be flushed if shaders read metadata.
1684 * (DCC, CMASK).
1685 */
1686 if (num_samples >= 2 ||
1687 (shaders_read_metadata && !dcc_pipe_aligned))
1688 sctx->flags |= SI_CONTEXT_INV_L2;
1689 else if (shaders_read_metadata)
1690 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1691 } else {
1692 /* GFX6-GFX8 */
1693 sctx->flags |= SI_CONTEXT_INV_L2;
1694 }
1695 }
1696
1697 static inline void
1698 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1699 bool include_stencil, bool shaders_read_metadata)
1700 {
1701 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1702 SI_CONTEXT_INV_VCACHE;
1703
1704 if (sctx->chip_class >= GFX9) {
1705 /* Single-sample depth (not stencil) is coherent with shaders
1706 * on GFX9, but L2 metadata must be flushed if shaders read
1707 * metadata.
1708 */
1709 if (num_samples >= 2 || include_stencil)
1710 sctx->flags |= SI_CONTEXT_INV_L2;
1711 else if (shaders_read_metadata)
1712 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1713 } else {
1714 /* GFX6-GFX8 */
1715 sctx->flags |= SI_CONTEXT_INV_L2;
1716 }
1717 }
1718
1719 static inline bool
1720 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1721 {
1722 return (stencil_sampler && tex->can_sample_s) ||
1723 (!stencil_sampler && tex->can_sample_z);
1724 }
1725
1726 static inline bool
1727 si_htile_enabled(struct si_texture *tex, unsigned level)
1728 {
1729 return tex->htile_offset && level == 0;
1730 }
1731
1732 static inline bool
1733 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1734 {
1735 assert(!tex->tc_compatible_htile || tex->htile_offset);
1736 return tex->tc_compatible_htile && level == 0;
1737 }
1738
1739 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1740 {
1741 if (sctx->ps_uses_fbfetch)
1742 return sctx->framebuffer.nr_color_samples;
1743
1744 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1745 }
1746
1747 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1748 {
1749 if (sctx->queued.named.rasterizer->rasterizer_discard)
1750 return 0;
1751
1752 struct si_shader_selector *ps = sctx->ps_shader.cso;
1753 if (!ps)
1754 return 0;
1755
1756 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1757 sctx->queued.named.blend->cb_target_mask;
1758
1759 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1760 colormask &= ps->colors_written_4bit;
1761 else if (!ps->colors_written_4bit)
1762 colormask = 0; /* color0 writes all cbufs, but it's not written */
1763
1764 return colormask;
1765 }
1766
1767 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1768 (1 << PIPE_PRIM_LINE_LOOP) | \
1769 (1 << PIPE_PRIM_LINE_STRIP) | \
1770 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1771 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1772
1773 static inline bool util_prim_is_lines(unsigned prim)
1774 {
1775 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1776 }
1777
1778 static inline bool util_prim_is_points_or_lines(unsigned prim)
1779 {
1780 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1781 (1 << PIPE_PRIM_POINTS))) != 0;
1782 }
1783
1784 /**
1785 * Return true if there is enough memory in VRAM and GTT for the buffers
1786 * added so far.
1787 *
1788 * \param vram VRAM memory size not added to the buffer list yet
1789 * \param gtt GTT memory size not added to the buffer list yet
1790 */
1791 static inline bool
1792 radeon_cs_memory_below_limit(struct si_screen *screen,
1793 struct radeon_cmdbuf *cs,
1794 uint64_t vram, uint64_t gtt)
1795 {
1796 vram += cs->used_vram;
1797 gtt += cs->used_gart;
1798
1799 /* Anything that goes above the VRAM size should go to GTT. */
1800 if (vram > screen->info.vram_size)
1801 gtt += vram - screen->info.vram_size;
1802
1803 /* Now we just need to check if we have enough GTT. */
1804 return gtt < screen->info.gart_size * 0.7;
1805 }
1806
1807 /**
1808 * Add a buffer to the buffer list for the given command stream (CS).
1809 *
1810 * All buffers used by a CS must be added to the list. This tells the kernel
1811 * driver which buffers are used by GPU commands. Other buffers can
1812 * be swapped out (not accessible) during execution.
1813 *
1814 * The buffer list becomes empty after every context flush and must be
1815 * rebuilt.
1816 */
1817 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1818 struct radeon_cmdbuf *cs,
1819 struct si_resource *bo,
1820 enum radeon_bo_usage usage,
1821 enum radeon_bo_priority priority)
1822 {
1823 assert(usage);
1824 sctx->ws->cs_add_buffer(
1825 cs, bo->buf,
1826 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1827 bo->domains, priority);
1828 }
1829
1830 /**
1831 * Same as above, but also checks memory usage and flushes the context
1832 * accordingly.
1833 *
1834 * When this SHOULD NOT be used:
1835 *
1836 * - if si_context_add_resource_size has been called for the buffer
1837 * followed by *_need_cs_space for checking the memory usage
1838 *
1839 * - if si_need_dma_space has been called for the buffer
1840 *
1841 * - when emitting state packets and draw packets (because preceding packets
1842 * can't be re-emitted at that point)
1843 *
1844 * - if shader resource "enabled_mask" is not up-to-date or there is
1845 * a different constraint disallowing a context flush
1846 */
1847 static inline void
1848 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1849 struct si_resource *bo,
1850 enum radeon_bo_usage usage,
1851 enum radeon_bo_priority priority,
1852 bool check_mem)
1853 {
1854 if (check_mem &&
1855 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1856 sctx->vram + bo->vram_usage,
1857 sctx->gtt + bo->gart_usage))
1858 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1859
1860 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1861 }
1862
1863 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1864 {
1865 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1866 }
1867
1868 #define PRINT_ERR(fmt, args...) \
1869 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1870
1871 #endif