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radeonsi/gfx10: set GE_CTNL.PACKET_TO_ONE_PA for NGG
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_UNSAFE_MATH,
149 DBG_SI_SCHED,
150 DBG_GISEL,
151
152 /* Shader compiler options (with no effect on the shader cache): */
153 DBG_CHECK_IR,
154 DBG_MONOLITHIC_SHADERS,
155 DBG_NO_OPT_VARIANT,
156
157 /* Information logging options: */
158 DBG_INFO,
159 DBG_TEX,
160 DBG_COMPUTE,
161 DBG_VM,
162
163 /* Driver options: */
164 DBG_FORCE_DMA,
165 DBG_NO_ASYNC_DMA,
166 DBG_NO_WC,
167 DBG_CHECK_VM,
168 DBG_RESERVE_VMID,
169 DBG_ZERO_VRAM,
170
171 /* 3D engine options: */
172 DBG_ALWAYS_PD,
173 DBG_PD,
174 DBG_NO_PD,
175 DBG_SWITCH_ON_EOP,
176 DBG_NO_OUT_OF_ORDER,
177 DBG_NO_DPBB,
178 DBG_NO_DFSM,
179 DBG_DPBB,
180 DBG_DFSM,
181 DBG_NO_HYPERZ,
182 DBG_NO_RB_PLUS,
183 DBG_NO_2D_TILING,
184 DBG_NO_TILING,
185 DBG_NO_DCC,
186 DBG_NO_DCC_CLEAR,
187 DBG_NO_DCC_FB,
188 DBG_NO_DCC_MSAA,
189 DBG_NO_FMASK,
190
191 /* Tests: */
192 DBG_TEST_DMA,
193 DBG_TEST_VMFAULT_CP,
194 DBG_TEST_VMFAULT_SDMA,
195 DBG_TEST_VMFAULT_SHADER,
196 DBG_TEST_DMA_PERF,
197 DBG_TEST_GDS,
198 DBG_TEST_GDS_MM,
199 DBG_TEST_GDS_OA_MM,
200 };
201
202 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
203 #define DBG(name) (1ull << DBG_##name)
204
205 enum si_cache_policy {
206 L2_BYPASS,
207 L2_STREAM, /* same as SLC=1 */
208 L2_LRU, /* same as SLC=0 */
209 };
210
211 enum si_coherency {
212 SI_COHERENCY_NONE, /* no cache flushes needed */
213 SI_COHERENCY_SHADER,
214 SI_COHERENCY_CB_META,
215 SI_COHERENCY_CP,
216 };
217
218 struct si_compute;
219 struct si_shader_context;
220 struct hash_table;
221 struct u_suballocator;
222
223 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
224 * at the moment.
225 */
226 struct si_resource {
227 struct threaded_resource b;
228
229 /* Winsys objects. */
230 struct pb_buffer *buf;
231 uint64_t gpu_address;
232 /* Memory usage if the buffer placement is optimal. */
233 uint64_t vram_usage;
234 uint64_t gart_usage;
235
236 /* Resource properties. */
237 uint64_t bo_size;
238 unsigned bo_alignment;
239 enum radeon_bo_domain domains;
240 enum radeon_bo_flag flags;
241 unsigned bind_history;
242 int max_forced_staging_uploads;
243
244 /* The buffer range which is initialized (with a write transfer,
245 * streamout, DMA, or as a random access target). The rest of
246 * the buffer is considered invalid and can be mapped unsynchronized.
247 *
248 * This allows unsychronized mapping of a buffer range which hasn't
249 * been used yet. It's for applications which forget to use
250 * the unsynchronized map flag and expect the driver to figure it out.
251 */
252 struct util_range valid_buffer_range;
253
254 /* For buffers only. This indicates that a write operation has been
255 * performed by TC L2, but the cache hasn't been flushed.
256 * Any hw block which doesn't use or bypasses TC L2 should check this
257 * flag and flush the cache before using the buffer.
258 *
259 * For example, TC L2 must be flushed if a buffer which has been
260 * modified by a shader store instruction is about to be used as
261 * an index buffer. The reason is that VGT DMA index fetching doesn't
262 * use TC L2.
263 */
264 bool TC_L2_dirty;
265
266 /* Whether this resource is referenced by bindless handles. */
267 bool texture_handle_allocated;
268 bool image_handle_allocated;
269
270 /* Whether the resource has been exported via resource_get_handle. */
271 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
272 };
273
274 struct si_transfer {
275 struct threaded_transfer b;
276 struct si_resource *staging;
277 unsigned offset;
278 };
279
280 struct si_texture {
281 struct si_resource buffer;
282
283 struct radeon_surf surface;
284 uint64_t size;
285 struct si_texture *flushed_depth_texture;
286
287 /* One texture allocation can contain these buffers:
288 * - image (pixel data)
289 * - FMASK buffer (MSAA compression)
290 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
291 * - HTILE buffer (Z/S compression and fast Z/S clear)
292 * - DCC buffer (color compression and new fast color clear)
293 * - displayable DCC buffer (if the DCC buffer is not displayable)
294 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
295 */
296 uint64_t fmask_offset;
297 uint64_t cmask_offset;
298 uint64_t cmask_base_address_reg;
299 struct si_resource *cmask_buffer;
300 uint64_t dcc_offset; /* 0 = disabled */
301 uint64_t display_dcc_offset;
302 uint64_t dcc_retile_map_offset;
303 unsigned cb_color_info; /* fast clear enable bit */
304 unsigned color_clear_value[2];
305 unsigned last_msaa_resolve_target_micro_mode;
306 unsigned num_level0_transfers;
307
308 /* Depth buffer compression and fast clear. */
309 uint64_t htile_offset;
310 float depth_clear_value;
311 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
312 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
313 enum pipe_format db_render_format:16;
314 uint8_t stencil_clear_value;
315 bool tc_compatible_htile:1;
316 bool htile_stencil_disabled:1;
317 bool depth_cleared:1; /* if it was cleared at least once */
318 bool stencil_cleared:1; /* if it was cleared at least once */
319 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
320 bool is_depth:1;
321 bool db_compatible:1;
322 bool can_sample_z:1;
323 bool can_sample_s:1;
324
325 /* We need to track DCC dirtiness, because st/dri usually calls
326 * flush_resource twice per frame (not a bug) and we don't wanna
327 * decompress DCC twice. Also, the dirty tracking must be done even
328 * if DCC isn't used, because it's required by the DCC usage analysis
329 * for a possible future enablement.
330 */
331 bool separate_dcc_dirty:1;
332 /* Statistics gathering for the DCC enablement heuristic. */
333 bool dcc_gather_statistics:1;
334 /* Counter that should be non-zero if the texture is bound to a
335 * framebuffer.
336 */
337 unsigned framebuffers_bound;
338 /* Whether the texture is a displayable back buffer and needs DCC
339 * decompression, which is expensive. Therefore, it's enabled only
340 * if statistics suggest that it will pay off and it's allocated
341 * separately. It can't be bound as a sampler by apps. Limited to
342 * target == 2D and last_level == 0. If enabled, dcc_offset contains
343 * the absolute GPUVM address, not the relative one.
344 */
345 struct si_resource *dcc_separate_buffer;
346 /* When DCC is temporarily disabled, the separate buffer is here. */
347 struct si_resource *last_dcc_separate_buffer;
348 /* Estimate of how much this color buffer is written to in units of
349 * full-screen draws: ps_invocations / (width * height)
350 * Shader kills, late Z, and blending with trivial discards make it
351 * inaccurate (we need to count CB updates, not PS invocations).
352 */
353 unsigned ps_draw_ratio;
354 /* The number of clears since the last DCC usage analysis. */
355 unsigned num_slow_clears;
356 };
357
358 struct si_surface {
359 struct pipe_surface base;
360
361 /* These can vary with block-compressed textures. */
362 uint16_t width0;
363 uint16_t height0;
364
365 bool color_initialized:1;
366 bool depth_initialized:1;
367
368 /* Misc. color flags. */
369 bool color_is_int8:1;
370 bool color_is_int10:1;
371 bool dcc_incompatible:1;
372
373 /* Color registers. */
374 unsigned cb_color_info;
375 unsigned cb_color_view;
376 unsigned cb_color_attrib;
377 unsigned cb_color_attrib2; /* GFX9 and later */
378 unsigned cb_color_attrib3; /* GFX10 and later */
379 unsigned cb_dcc_control; /* GFX8 and later */
380 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
381 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
382 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
383 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
384
385 /* DB registers. */
386 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
387 uint64_t db_stencil_base;
388 uint64_t db_htile_data_base;
389 unsigned db_depth_info;
390 unsigned db_z_info;
391 unsigned db_z_info2; /* GFX9 only */
392 unsigned db_depth_view;
393 unsigned db_depth_size;
394 unsigned db_depth_slice;
395 unsigned db_stencil_info;
396 unsigned db_stencil_info2; /* GFX9 only */
397 unsigned db_htile_surface;
398 };
399
400 struct si_mmio_counter {
401 unsigned busy;
402 unsigned idle;
403 };
404
405 union si_mmio_counters {
406 struct {
407 /* For global GPU load including SDMA. */
408 struct si_mmio_counter gpu;
409
410 /* GRBM_STATUS */
411 struct si_mmio_counter spi;
412 struct si_mmio_counter gui;
413 struct si_mmio_counter ta;
414 struct si_mmio_counter gds;
415 struct si_mmio_counter vgt;
416 struct si_mmio_counter ia;
417 struct si_mmio_counter sx;
418 struct si_mmio_counter wd;
419 struct si_mmio_counter bci;
420 struct si_mmio_counter sc;
421 struct si_mmio_counter pa;
422 struct si_mmio_counter db;
423 struct si_mmio_counter cp;
424 struct si_mmio_counter cb;
425
426 /* SRBM_STATUS2 */
427 struct si_mmio_counter sdma;
428
429 /* CP_STAT */
430 struct si_mmio_counter pfp;
431 struct si_mmio_counter meq;
432 struct si_mmio_counter me;
433 struct si_mmio_counter surf_sync;
434 struct si_mmio_counter cp_dma;
435 struct si_mmio_counter scratch_ram;
436 } named;
437 unsigned array[0];
438 };
439
440 struct si_memory_object {
441 struct pipe_memory_object b;
442 struct pb_buffer *buf;
443 uint32_t stride;
444 };
445
446 /* Saved CS data for debugging features. */
447 struct radeon_saved_cs {
448 uint32_t *ib;
449 unsigned num_dw;
450
451 struct radeon_bo_list_item *bo_list;
452 unsigned bo_count;
453 };
454
455 struct si_screen {
456 struct pipe_screen b;
457 struct radeon_winsys *ws;
458 struct disk_cache *disk_shader_cache;
459
460 struct radeon_info info;
461 uint64_t debug_flags;
462 char renderer_string[183];
463
464 void (*make_texture_descriptor)(
465 struct si_screen *screen,
466 struct si_texture *tex,
467 bool sampler,
468 enum pipe_texture_target target,
469 enum pipe_format pipe_format,
470 const unsigned char state_swizzle[4],
471 unsigned first_level, unsigned last_level,
472 unsigned first_layer, unsigned last_layer,
473 unsigned width, unsigned height, unsigned depth,
474 uint32_t *state,
475 uint32_t *fmask_state);
476
477 unsigned pa_sc_raster_config;
478 unsigned pa_sc_raster_config_1;
479 unsigned se_tile_repeat;
480 unsigned gs_table_depth;
481 unsigned tess_offchip_block_dw_size;
482 unsigned tess_offchip_ring_size;
483 unsigned tess_factor_ring_size;
484 unsigned vgt_hs_offchip_param;
485 unsigned eqaa_force_coverage_samples;
486 unsigned eqaa_force_z_samples;
487 unsigned eqaa_force_color_samples;
488 bool has_clear_state;
489 bool has_distributed_tess;
490 bool has_draw_indirect_multi;
491 bool has_out_of_order_rast;
492 bool assume_no_z_fights;
493 bool commutative_blend_add;
494 bool has_gfx9_scissor_bug;
495 bool has_msaa_sample_loc_bug;
496 bool has_ls_vgpr_init_bug;
497 bool has_dcc_constant_encode;
498 bool dpbb_allowed;
499 bool dfsm_allowed;
500 bool llvm_has_working_vgpr_indexing;
501
502 struct {
503 #define OPT_BOOL(name, dflt, description) bool name:1;
504 #include "si_debug_options.h"
505 } options;
506
507 /* Whether shaders are monolithic (1-part) or separate (3-part). */
508 bool use_monolithic_shaders;
509 bool record_llvm_ir;
510 bool has_rbplus; /* if RB+ registers exist */
511 bool rbplus_allowed; /* if RB+ is allowed */
512 bool dcc_msaa_allowed;
513 bool cpdma_prefetch_writes_memory;
514
515 struct slab_parent_pool pool_transfers;
516
517 /* Texture filter settings. */
518 int force_aniso; /* -1 = disabled */
519
520 /* Auxiliary context. Mainly used to initialize resources.
521 * It must be locked prior to using and flushed before unlocking. */
522 struct pipe_context *aux_context;
523 mtx_t aux_context_lock;
524
525 /* This must be in the screen, because UE4 uses one context for
526 * compilation and another one for rendering.
527 */
528 unsigned num_compilations;
529 /* Along with ST_DEBUG=precompile, this should show if applications
530 * are loading shaders on demand. This is a monotonic counter.
531 */
532 unsigned num_shaders_created;
533 unsigned num_shader_cache_hits;
534
535 /* GPU load thread. */
536 mtx_t gpu_load_mutex;
537 thrd_t gpu_load_thread;
538 union si_mmio_counters mmio_counters;
539 volatile unsigned gpu_load_stop_thread; /* bool */
540
541 /* Performance counters. */
542 struct si_perfcounters *perfcounters;
543
544 /* If pipe_screen wants to recompute and re-emit the framebuffer,
545 * sampler, and image states of all contexts, it should atomically
546 * increment this.
547 *
548 * Each context will compare this with its own last known value of
549 * the counter before drawing and re-emit the states accordingly.
550 */
551 unsigned dirty_tex_counter;
552 unsigned dirty_buf_counter;
553
554 /* Atomically increment this counter when an existing texture's
555 * metadata is enabled or disabled in a way that requires changing
556 * contexts' compressed texture binding masks.
557 */
558 unsigned compressed_colortex_counter;
559
560 struct {
561 /* Context flags to set so that all writes from earlier jobs
562 * in the CP are seen by L2 clients.
563 */
564 unsigned cp_to_L2;
565
566 /* Context flags to set so that all writes from earlier jobs
567 * that end in L2 are seen by CP.
568 */
569 unsigned L2_to_cp;
570 } barrier_flags;
571
572 mtx_t shader_parts_mutex;
573 struct si_shader_part *vs_prologs;
574 struct si_shader_part *tcs_epilogs;
575 struct si_shader_part *gs_prologs;
576 struct si_shader_part *ps_prologs;
577 struct si_shader_part *ps_epilogs;
578
579 /* Shader cache in memory.
580 *
581 * Design & limitations:
582 * - The shader cache is per screen (= per process), never saved to
583 * disk, and skips redundant shader compilations from TGSI to bytecode.
584 * - It can only be used with one-variant-per-shader support, in which
585 * case only the main (typically middle) part of shaders is cached.
586 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
587 * variants of VS and TES are cached, so LS and ES aren't.
588 * - GS and CS aren't cached, but it's certainly possible to cache
589 * those as well.
590 */
591 mtx_t shader_cache_mutex;
592 struct hash_table *shader_cache;
593
594 /* Shader compiler queue for multithreaded compilation. */
595 struct util_queue shader_compiler_queue;
596 /* Use at most 3 normal compiler threads on quadcore and better.
597 * Hyperthreaded CPUs report the number of threads, but we want
598 * the number of cores. We only need this many threads for shader-db. */
599 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
600
601 struct util_queue shader_compiler_queue_low_priority;
602 /* Use at most 2 low priority threads on quadcore and better.
603 * We want to minimize the impact on multithreaded Mesa. */
604 struct ac_llvm_compiler compiler_lowp[10];
605 };
606
607 struct si_blend_color {
608 struct pipe_blend_color state;
609 bool any_nonzeros;
610 };
611
612 struct si_sampler_view {
613 struct pipe_sampler_view base;
614 /* [0..7] = image descriptor
615 * [4..7] = buffer descriptor */
616 uint32_t state[8];
617 uint32_t fmask_state[8];
618 const struct legacy_surf_level *base_level_info;
619 ubyte base_level;
620 ubyte block_width;
621 bool is_stencil_sampler;
622 bool is_integer;
623 bool dcc_incompatible;
624 };
625
626 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
627
628 struct si_sampler_state {
629 #ifndef NDEBUG
630 unsigned magic;
631 #endif
632 uint32_t val[4];
633 uint32_t integer_val[4];
634 uint32_t upgraded_depth_val[4];
635 };
636
637 struct si_cs_shader_state {
638 struct si_compute *program;
639 struct si_compute *emitted_program;
640 unsigned offset;
641 bool initialized;
642 bool uses_scratch;
643 };
644
645 struct si_samplers {
646 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
647 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
648
649 /* The i-th bit is set if that element is enabled (non-NULL resource). */
650 unsigned enabled_mask;
651 uint32_t needs_depth_decompress_mask;
652 uint32_t needs_color_decompress_mask;
653 };
654
655 struct si_images {
656 struct pipe_image_view views[SI_NUM_IMAGES];
657 uint32_t needs_color_decompress_mask;
658 unsigned enabled_mask;
659 };
660
661 struct si_framebuffer {
662 struct pipe_framebuffer_state state;
663 unsigned colorbuf_enabled_4bit;
664 unsigned spi_shader_col_format;
665 unsigned spi_shader_col_format_alpha;
666 unsigned spi_shader_col_format_blend;
667 unsigned spi_shader_col_format_blend_alpha;
668 ubyte nr_samples:5; /* at most 16xAA */
669 ubyte log_samples:3; /* at most 4 = 16xAA */
670 ubyte nr_color_samples; /* at most 8xAA */
671 ubyte compressed_cb_mask;
672 ubyte uncompressed_cb_mask;
673 ubyte color_is_int8;
674 ubyte color_is_int10;
675 ubyte dirty_cbufs;
676 ubyte dcc_overwrite_combiner_watermark;
677 ubyte min_bytes_per_pixel;
678 bool dirty_zsbuf;
679 bool any_dst_linear;
680 bool CB_has_shader_readable_metadata;
681 bool DB_has_shader_readable_metadata;
682 bool all_DCC_pipe_aligned;
683 };
684
685 enum si_quant_mode {
686 /* This is the list we want to support. */
687 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
688 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
689 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
690 };
691
692 struct si_signed_scissor {
693 int minx;
694 int miny;
695 int maxx;
696 int maxy;
697 enum si_quant_mode quant_mode;
698 };
699
700 struct si_viewports {
701 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
702 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
703 bool y_inverted;
704 };
705
706 struct si_clip_state {
707 struct pipe_clip_state state;
708 bool any_nonzeros;
709 };
710
711 struct si_streamout_target {
712 struct pipe_stream_output_target b;
713
714 /* The buffer where BUFFER_FILLED_SIZE is stored. */
715 struct si_resource *buf_filled_size;
716 unsigned buf_filled_size_offset;
717 bool buf_filled_size_valid;
718
719 unsigned stride_in_dw;
720 };
721
722 struct si_streamout {
723 bool begin_emitted;
724
725 unsigned enabled_mask;
726 unsigned num_targets;
727 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
728
729 unsigned append_bitmask;
730 bool suspended;
731
732 /* External state which comes from the vertex shader,
733 * it must be set explicitly when binding a shader. */
734 uint16_t *stride_in_dw;
735 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
736
737 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
738 unsigned hw_enabled_mask;
739
740 /* The state of VGT_STRMOUT_(CONFIG|EN). */
741 bool streamout_enabled;
742 bool prims_gen_query_enabled;
743 int num_prims_gen_queries;
744 };
745
746 /* A shader state consists of the shader selector, which is a constant state
747 * object shared by multiple contexts and shouldn't be modified, and
748 * the current shader variant selected for this context.
749 */
750 struct si_shader_ctx_state {
751 struct si_shader_selector *cso;
752 struct si_shader *current;
753 };
754
755 #define SI_NUM_VGT_PARAM_KEY_BITS 12
756 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
757
758 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
759 * Some fields are set by state-change calls, most are set by draw_vbo.
760 */
761 union si_vgt_param_key {
762 struct {
763 #ifdef PIPE_ARCH_LITTLE_ENDIAN
764 unsigned prim:4;
765 unsigned uses_instancing:1;
766 unsigned multi_instances_smaller_than_primgroup:1;
767 unsigned primitive_restart:1;
768 unsigned count_from_stream_output:1;
769 unsigned line_stipple_enabled:1;
770 unsigned uses_tess:1;
771 unsigned tess_uses_prim_id:1;
772 unsigned uses_gs:1;
773 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
774 #else /* PIPE_ARCH_BIG_ENDIAN */
775 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
776 unsigned uses_gs:1;
777 unsigned tess_uses_prim_id:1;
778 unsigned uses_tess:1;
779 unsigned line_stipple_enabled:1;
780 unsigned count_from_stream_output:1;
781 unsigned primitive_restart:1;
782 unsigned multi_instances_smaller_than_primgroup:1;
783 unsigned uses_instancing:1;
784 unsigned prim:4;
785 #endif
786 } u;
787 uint32_t index;
788 };
789
790 #define SI_NUM_VGT_STAGES_KEY_BITS 4
791 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
792
793 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
794 * Some fields are set by state-change calls, most are set by draw_vbo.
795 */
796 union si_vgt_stages_key {
797 struct {
798 #ifdef PIPE_ARCH_LITTLE_ENDIAN
799 unsigned tess:1;
800 unsigned gs:1;
801 unsigned ngg:1; /* gfx10+ */
802 unsigned streamout:1; /* only used with NGG */
803 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
804 #else /* PIPE_ARCH_BIG_ENDIAN */
805 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
806 unsigned streamout:1;
807 unsigned ngg:1;
808 unsigned gs:1;
809 unsigned tess:1;
810 #endif
811 } u;
812 uint32_t index;
813 };
814
815 struct si_texture_handle
816 {
817 unsigned desc_slot;
818 bool desc_dirty;
819 struct pipe_sampler_view *view;
820 struct si_sampler_state sstate;
821 };
822
823 struct si_image_handle
824 {
825 unsigned desc_slot;
826 bool desc_dirty;
827 struct pipe_image_view view;
828 };
829
830 struct si_saved_cs {
831 struct pipe_reference reference;
832 struct si_context *ctx;
833 struct radeon_saved_cs gfx;
834 struct radeon_saved_cs compute;
835 struct si_resource *trace_buf;
836 unsigned trace_id;
837
838 unsigned gfx_last_dw;
839 unsigned compute_last_dw;
840 bool flushed;
841 int64_t time_flush;
842 };
843
844 struct si_sdma_upload {
845 struct si_resource *dst;
846 struct si_resource *src;
847 unsigned src_offset;
848 unsigned dst_offset;
849 unsigned size;
850 };
851
852 struct si_context {
853 struct pipe_context b; /* base class */
854
855 enum radeon_family family;
856 enum chip_class chip_class;
857
858 struct radeon_winsys *ws;
859 struct radeon_winsys_ctx *ctx;
860 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
861 struct radeon_cmdbuf *dma_cs;
862 struct pipe_fence_handle *last_gfx_fence;
863 struct pipe_fence_handle *last_sdma_fence;
864 struct si_resource *eop_bug_scratch;
865 struct u_upload_mgr *cached_gtt_allocator;
866 struct threaded_context *tc;
867 struct u_suballocator *allocator_zeroed_memory;
868 struct slab_child_pool pool_transfers;
869 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
870 struct pipe_device_reset_callback device_reset_callback;
871 struct u_log_context *log;
872 void *query_result_shader;
873 void *sh_query_result_shader;
874
875 void (*emit_cache_flush)(struct si_context *ctx);
876
877 struct blitter_context *blitter;
878 void *custom_dsa_flush;
879 void *custom_blend_resolve;
880 void *custom_blend_fmask_decompress;
881 void *custom_blend_eliminate_fastclear;
882 void *custom_blend_dcc_decompress;
883 void *vs_blit_pos;
884 void *vs_blit_pos_layered;
885 void *vs_blit_color;
886 void *vs_blit_color_layered;
887 void *vs_blit_texcoord;
888 void *cs_clear_buffer;
889 void *cs_copy_buffer;
890 void *cs_copy_image;
891 void *cs_copy_image_1d_array;
892 void *cs_clear_render_target;
893 void *cs_clear_render_target_1d_array;
894 void *cs_dcc_retile;
895 struct si_screen *screen;
896 struct pipe_debug_callback debug;
897 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
898 struct si_shader_ctx_state fixed_func_tcs_shader;
899 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
900 struct si_resource *wait_mem_scratch;
901 unsigned wait_mem_number;
902 uint16_t prefetch_L2_mask;
903
904 bool has_graphics;
905 bool gfx_flush_in_progress:1;
906 bool gfx_last_ib_is_busy:1;
907 bool compute_is_busy:1;
908
909 unsigned num_gfx_cs_flushes;
910 unsigned initial_gfx_cs_size;
911 unsigned last_dirty_tex_counter;
912 unsigned last_dirty_buf_counter;
913 unsigned last_compressed_colortex_counter;
914 unsigned last_num_draw_calls;
915 unsigned flags; /* flush flags */
916 /* Current unaccounted memory usage. */
917 uint64_t vram;
918 uint64_t gtt;
919
920 /* Compute-based primitive discard. */
921 unsigned prim_discard_vertex_count_threshold;
922 struct pb_buffer *gds;
923 struct pb_buffer *gds_oa;
924 struct radeon_cmdbuf *prim_discard_compute_cs;
925 unsigned compute_gds_offset;
926 struct si_shader *compute_ib_last_shader;
927 uint32_t compute_rewind_va;
928 unsigned compute_num_prims_in_batch;
929 bool preserve_prim_restart_gds_at_flush;
930 /* index_ring is divided into 2 halves for doublebuffering. */
931 struct si_resource *index_ring;
932 unsigned index_ring_base; /* offset of a per-IB portion */
933 unsigned index_ring_offset; /* offset within a per-IB portion */
934 unsigned index_ring_size_per_ib; /* max available size per IB */
935 bool prim_discard_compute_ib_initialized;
936 /* For tracking the last execution barrier - it can be either
937 * a WRITE_DATA packet or a fence. */
938 uint32_t *last_pkt3_write_data;
939 struct si_resource *barrier_buf;
940 unsigned barrier_buf_offset;
941 struct pipe_fence_handle *last_ib_barrier_fence;
942 struct si_resource *last_ib_barrier_buf;
943 unsigned last_ib_barrier_buf_offset;
944
945 /* Atoms (direct states). */
946 union si_state_atoms atoms;
947 unsigned dirty_atoms; /* mask */
948 /* PM4 states (precomputed immutable states) */
949 unsigned dirty_states;
950 union si_state queued;
951 union si_state emitted;
952
953 /* Atom declarations. */
954 struct si_framebuffer framebuffer;
955 unsigned sample_locs_num_samples;
956 uint16_t sample_mask;
957 unsigned last_cb_target_mask;
958 struct si_blend_color blend_color;
959 struct si_clip_state clip_state;
960 struct si_shader_data shader_pointers;
961 struct si_stencil_ref stencil_ref;
962 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
963 struct si_streamout streamout;
964 struct si_viewports viewports;
965 unsigned num_window_rectangles;
966 bool window_rectangles_include;
967 struct pipe_scissor_state window_rectangles[4];
968
969 /* Precomputed states. */
970 struct si_pm4_state *init_config;
971 struct si_pm4_state *init_config_gs_rings;
972 bool init_config_has_vgt_flush;
973 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
974
975 /* shaders */
976 struct si_shader_ctx_state ps_shader;
977 struct si_shader_ctx_state gs_shader;
978 struct si_shader_ctx_state vs_shader;
979 struct si_shader_ctx_state tcs_shader;
980 struct si_shader_ctx_state tes_shader;
981 struct si_shader_ctx_state cs_prim_discard_state;
982 struct si_cs_shader_state cs_shader_state;
983
984 /* shader information */
985 struct si_vertex_elements *vertex_elements;
986 unsigned sprite_coord_enable;
987 unsigned cs_max_waves_per_sh;
988 bool flatshade;
989 bool do_update_shaders;
990
991 /* vertex buffer descriptors */
992 uint32_t *vb_descriptors_gpu_list;
993 struct si_resource *vb_descriptors_buffer;
994 unsigned vb_descriptors_offset;
995
996 /* shader descriptors */
997 struct si_descriptors descriptors[SI_NUM_DESCS];
998 unsigned descriptors_dirty;
999 unsigned shader_pointers_dirty;
1000 unsigned shader_needs_decompress_mask;
1001 struct si_buffer_resources rw_buffers;
1002 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1003 struct si_samplers samplers[SI_NUM_SHADERS];
1004 struct si_images images[SI_NUM_SHADERS];
1005 bool bo_list_add_all_resident_resources;
1006 bool bo_list_add_all_gfx_resources;
1007 bool bo_list_add_all_compute_resources;
1008
1009 /* other shader resources */
1010 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1011 struct pipe_resource *esgs_ring;
1012 struct pipe_resource *gsvs_ring;
1013 struct pipe_resource *tess_rings;
1014 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1015 struct si_resource *border_color_buffer;
1016 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1017 unsigned border_color_count;
1018 unsigned num_vs_blit_sgprs;
1019 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1020 uint32_t cs_user_data[4];
1021
1022 /* Vertex and index buffers. */
1023 bool vertex_buffers_dirty;
1024 bool vertex_buffer_pointer_dirty;
1025 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1026 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1027
1028 /* MSAA config state. */
1029 int ps_iter_samples;
1030 bool ps_uses_fbfetch;
1031 bool smoothing_enabled;
1032
1033 /* DB render state. */
1034 unsigned ps_db_shader_control;
1035 unsigned dbcb_copy_sample;
1036 bool dbcb_depth_copy_enabled:1;
1037 bool dbcb_stencil_copy_enabled:1;
1038 bool db_flush_depth_inplace:1;
1039 bool db_flush_stencil_inplace:1;
1040 bool db_depth_clear:1;
1041 bool db_depth_disable_expclear:1;
1042 bool db_stencil_clear:1;
1043 bool db_stencil_disable_expclear:1;
1044 bool occlusion_queries_disabled:1;
1045 bool generate_mipmap_for_depth:1;
1046
1047 /* Emitted draw state. */
1048 bool gs_tri_strip_adj_fix:1;
1049 bool ls_vgpr_fix:1;
1050 bool prim_discard_cs_instancing:1;
1051 bool ngg:1;
1052 int last_index_size;
1053 int last_base_vertex;
1054 int last_start_instance;
1055 int last_instance_count;
1056 int last_drawid;
1057 int last_sh_base_reg;
1058 int last_primitive_restart_en;
1059 int last_restart_index;
1060 int last_prim;
1061 int last_multi_vgt_param;
1062 int last_rast_prim;
1063 int last_flatshade_first;
1064 int last_binning_enabled;
1065 unsigned last_sc_line_stipple;
1066 unsigned current_vs_state;
1067 unsigned last_vs_state;
1068 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1069
1070 /* Scratch buffer */
1071 struct si_resource *scratch_buffer;
1072 unsigned scratch_waves;
1073 unsigned spi_tmpring_size;
1074
1075 struct si_resource *compute_scratch_buffer;
1076
1077 /* Emitted derived tessellation state. */
1078 /* Local shader (VS), or HS if LS-HS are merged. */
1079 struct si_shader *last_ls;
1080 struct si_shader_selector *last_tcs;
1081 int last_num_tcs_input_cp;
1082 int last_tes_sh_base;
1083 bool last_tess_uses_primid;
1084 unsigned last_num_patches;
1085 int last_ls_hs_config;
1086
1087 /* Debug state. */
1088 bool is_debug;
1089 struct si_saved_cs *current_saved_cs;
1090 uint64_t dmesg_timestamp;
1091 unsigned apitrace_call_number;
1092
1093 /* Other state */
1094 bool need_check_render_feedback;
1095 bool decompression_enabled;
1096 bool dpbb_force_off;
1097 bool vs_writes_viewport_index;
1098 bool vs_disables_clipping_viewport;
1099
1100 /* Precomputed IA_MULTI_VGT_PARAM */
1101 union si_vgt_param_key ia_multi_vgt_param_key;
1102 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1103
1104 /* Bindless descriptors. */
1105 struct si_descriptors bindless_descriptors;
1106 struct util_idalloc bindless_used_slots;
1107 unsigned num_bindless_descriptors;
1108 bool bindless_descriptors_dirty;
1109 bool graphics_bindless_pointer_dirty;
1110 bool compute_bindless_pointer_dirty;
1111
1112 /* Allocated bindless handles */
1113 struct hash_table *tex_handles;
1114 struct hash_table *img_handles;
1115
1116 /* Resident bindless handles */
1117 struct util_dynarray resident_tex_handles;
1118 struct util_dynarray resident_img_handles;
1119
1120 /* Resident bindless handles which need decompression */
1121 struct util_dynarray resident_tex_needs_color_decompress;
1122 struct util_dynarray resident_img_needs_color_decompress;
1123 struct util_dynarray resident_tex_needs_depth_decompress;
1124
1125 /* Bindless state */
1126 bool uses_bindless_samplers;
1127 bool uses_bindless_images;
1128
1129 /* MSAA sample locations.
1130 * The first index is the sample index.
1131 * The second index is the coordinate: X, Y. */
1132 struct {
1133 float x1[1][2];
1134 float x2[2][2];
1135 float x4[4][2];
1136 float x8[8][2];
1137 float x16[16][2];
1138 } sample_positions;
1139 struct pipe_resource *sample_pos_buffer;
1140
1141 /* Misc stats. */
1142 unsigned num_draw_calls;
1143 unsigned num_decompress_calls;
1144 unsigned num_mrt_draw_calls;
1145 unsigned num_prim_restart_calls;
1146 unsigned num_spill_draw_calls;
1147 unsigned num_compute_calls;
1148 unsigned num_spill_compute_calls;
1149 unsigned num_dma_calls;
1150 unsigned num_cp_dma_calls;
1151 unsigned num_vs_flushes;
1152 unsigned num_ps_flushes;
1153 unsigned num_cs_flushes;
1154 unsigned num_cb_cache_flushes;
1155 unsigned num_db_cache_flushes;
1156 unsigned num_L2_invalidates;
1157 unsigned num_L2_writebacks;
1158 unsigned num_resident_handles;
1159 uint64_t num_alloc_tex_transfer_bytes;
1160 unsigned last_tex_ps_draw_ratio; /* for query */
1161 unsigned compute_num_verts_accepted;
1162 unsigned compute_num_verts_rejected;
1163 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1164 unsigned context_roll;
1165
1166 /* Queries. */
1167 /* Maintain the list of active queries for pausing between IBs. */
1168 int num_occlusion_queries;
1169 int num_perfect_occlusion_queries;
1170 int num_pipeline_stat_queries;
1171 struct list_head active_queries;
1172 unsigned num_cs_dw_queries_suspend;
1173
1174 /* Render condition. */
1175 struct pipe_query *render_cond;
1176 unsigned render_cond_mode;
1177 bool render_cond_invert;
1178 bool render_cond_force_off; /* for u_blitter */
1179
1180 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1181 bool sdma_uploads_in_progress;
1182 struct si_sdma_upload *sdma_uploads;
1183 unsigned num_sdma_uploads;
1184 unsigned max_sdma_uploads;
1185
1186 /* Shader-based queries. */
1187 struct list_head shader_query_buffers;
1188 unsigned num_active_shader_queries;
1189
1190 /* Statistics gathering for the DCC enablement heuristic. It can't be
1191 * in si_texture because si_texture can be shared by multiple
1192 * contexts. This is for back buffers only. We shouldn't get too many
1193 * of those.
1194 *
1195 * X11 DRI3 rotates among a finite set of back buffers. They should
1196 * all fit in this array. If they don't, separate DCC might never be
1197 * enabled by DCC stat gathering.
1198 */
1199 struct {
1200 struct si_texture *tex;
1201 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1202 struct pipe_query *ps_stats[3];
1203 /* If all slots are used and another slot is needed,
1204 * the least recently used slot is evicted based on this. */
1205 int64_t last_use_timestamp;
1206 bool query_active;
1207 } dcc_stats[5];
1208
1209 /* Copy one resource to another using async DMA. */
1210 void (*dma_copy)(struct pipe_context *ctx,
1211 struct pipe_resource *dst,
1212 unsigned dst_level,
1213 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1214 struct pipe_resource *src,
1215 unsigned src_level,
1216 const struct pipe_box *src_box);
1217
1218 struct si_tracked_regs tracked_regs;
1219 };
1220
1221 /* cik_sdma.c */
1222 void cik_init_sdma_functions(struct si_context *sctx);
1223
1224 /* si_blit.c */
1225 enum si_blitter_op /* bitmask */
1226 {
1227 SI_SAVE_TEXTURES = 1,
1228 SI_SAVE_FRAMEBUFFER = 2,
1229 SI_SAVE_FRAGMENT_STATE = 4,
1230 SI_DISABLE_RENDER_COND = 8,
1231 };
1232
1233 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1234 void si_blitter_end(struct si_context *sctx);
1235 void si_init_blit_functions(struct si_context *sctx);
1236 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1237 void si_resource_copy_region(struct pipe_context *ctx,
1238 struct pipe_resource *dst,
1239 unsigned dst_level,
1240 unsigned dstx, unsigned dsty, unsigned dstz,
1241 struct pipe_resource *src,
1242 unsigned src_level,
1243 const struct pipe_box *src_box);
1244 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1245
1246 /* si_buffer.c */
1247 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1248 struct pb_buffer *buf,
1249 enum radeon_bo_usage usage);
1250 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1251 struct si_resource *resource,
1252 unsigned usage);
1253 void si_init_resource_fields(struct si_screen *sscreen,
1254 struct si_resource *res,
1255 uint64_t size, unsigned alignment);
1256 bool si_alloc_resource(struct si_screen *sscreen,
1257 struct si_resource *res);
1258 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1259 unsigned flags, unsigned usage,
1260 unsigned size, unsigned alignment);
1261 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1262 unsigned flags, unsigned usage,
1263 unsigned size, unsigned alignment);
1264 void si_replace_buffer_storage(struct pipe_context *ctx,
1265 struct pipe_resource *dst,
1266 struct pipe_resource *src);
1267 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1268 void si_init_buffer_functions(struct si_context *sctx);
1269
1270 /* si_clear.c */
1271 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1272 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1273 void vi_dcc_clear_level(struct si_context *sctx,
1274 struct si_texture *tex,
1275 unsigned level, unsigned clear_value);
1276 void si_init_clear_functions(struct si_context *sctx);
1277
1278 /* si_compute_blit.c */
1279 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1280 enum si_cache_policy cache_policy);
1281 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1282 uint64_t offset, uint64_t size, uint32_t *clear_value,
1283 uint32_t clear_value_size, enum si_coherency coher,
1284 bool force_cpdma);
1285 void si_copy_buffer(struct si_context *sctx,
1286 struct pipe_resource *dst, struct pipe_resource *src,
1287 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1288 void si_compute_copy_image(struct si_context *sctx,
1289 struct pipe_resource *dst,
1290 unsigned dst_level,
1291 struct pipe_resource *src,
1292 unsigned src_level,
1293 unsigned dstx, unsigned dsty, unsigned dstz,
1294 const struct pipe_box *src_box);
1295 void si_compute_clear_render_target(struct pipe_context *ctx,
1296 struct pipe_surface *dstsurf,
1297 const union pipe_color_union *color,
1298 unsigned dstx, unsigned dsty,
1299 unsigned width, unsigned height,
1300 bool render_condition_enabled);
1301 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1302 void si_init_compute_blit_functions(struct si_context *sctx);
1303
1304 /* si_cp_dma.c */
1305 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1306 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1307 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1308 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1309 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1310 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1311 SI_CPDMA_SKIP_SYNC_AFTER | \
1312 SI_CPDMA_SKIP_SYNC_BEFORE | \
1313 SI_CPDMA_SKIP_GFX_SYNC | \
1314 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1315
1316 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1317 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1318 struct pipe_resource *dst, uint64_t offset,
1319 uint64_t size, unsigned value, unsigned user_flags,
1320 enum si_coherency coher, enum si_cache_policy cache_policy);
1321 void si_cp_dma_copy_buffer(struct si_context *sctx,
1322 struct pipe_resource *dst, struct pipe_resource *src,
1323 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1324 unsigned user_flags, enum si_coherency coher,
1325 enum si_cache_policy cache_policy);
1326 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1327 uint64_t offset, unsigned size);
1328 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1329 void si_test_gds(struct si_context *sctx);
1330 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1331 unsigned offset, unsigned size, unsigned dst_sel,
1332 unsigned engine, const void *data);
1333 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1334 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1335 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1336
1337 /* si_debug.c */
1338 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1339 struct radeon_saved_cs *saved, bool get_buffer_list);
1340 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1341 void si_destroy_saved_cs(struct si_saved_cs *scs);
1342 void si_auto_log_cs(void *data, struct u_log_context *log);
1343 void si_log_hw_flush(struct si_context *sctx);
1344 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1345 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1346 void si_init_debug_functions(struct si_context *sctx);
1347 void si_check_vm_faults(struct si_context *sctx,
1348 struct radeon_saved_cs *saved, enum ring_type ring);
1349 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1350
1351 /* si_dma.c */
1352 void si_init_dma_functions(struct si_context *sctx);
1353
1354 /* si_dma_cs.c */
1355 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1356 uint64_t offset);
1357 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1358 uint64_t offset, uint64_t size, unsigned clear_value);
1359 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1360 struct si_resource *dst, struct si_resource *src);
1361 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1362 struct pipe_fence_handle **fence);
1363 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1364 uint64_t offset, uint64_t size, unsigned value);
1365
1366 /* si_fence.c */
1367 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1368 unsigned event, unsigned event_flags,
1369 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1370 struct si_resource *buf, uint64_t va,
1371 uint32_t new_fence, unsigned query_type);
1372 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1373 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1374 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1375 void si_init_fence_functions(struct si_context *ctx);
1376 void si_init_screen_fence_functions(struct si_screen *screen);
1377 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1378 struct tc_unflushed_batch_token *tc_token);
1379
1380 /* si_get.c */
1381 void si_init_screen_get_functions(struct si_screen *sscreen);
1382
1383 /* si_gfx_cs.c */
1384 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1385 struct pipe_fence_handle **fence);
1386 void si_allocate_gds(struct si_context *ctx);
1387 void si_begin_new_gfx_cs(struct si_context *ctx);
1388 void si_need_gfx_cs_space(struct si_context *ctx);
1389 void si_unref_sdma_uploads(struct si_context *sctx);
1390
1391 /* si_gpu_load.c */
1392 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1393 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1394 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1395 uint64_t begin);
1396
1397 /* si_compute.c */
1398 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1399 void si_init_compute_functions(struct si_context *sctx);
1400
1401 /* si_compute_prim_discard.c */
1402 enum si_prim_discard_outcome {
1403 SI_PRIM_DISCARD_ENABLED,
1404 SI_PRIM_DISCARD_DISABLED,
1405 SI_PRIM_DISCARD_DRAW_SPLIT,
1406 };
1407
1408 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1409 enum si_prim_discard_outcome
1410 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1411 const struct pipe_draw_info *info,
1412 bool primitive_restart);
1413 void si_compute_signal_gfx(struct si_context *sctx);
1414 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1415 const struct pipe_draw_info *info,
1416 unsigned index_size,
1417 unsigned base_vertex,
1418 uint64_t input_indexbuf_va,
1419 unsigned input_indexbuf_max_elements);
1420 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1421
1422 /* si_perfcounters.c */
1423 void si_init_perfcounters(struct si_screen *screen);
1424 void si_destroy_perfcounters(struct si_screen *screen);
1425
1426 /* si_pipe.c */
1427 bool si_check_device_reset(struct si_context *sctx);
1428
1429 /* si_query.c */
1430 void si_init_screen_query_functions(struct si_screen *sscreen);
1431 void si_init_query_functions(struct si_context *sctx);
1432 void si_suspend_queries(struct si_context *sctx);
1433 void si_resume_queries(struct si_context *sctx);
1434
1435 /* si_shaderlib_tgsi.c */
1436 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1437 unsigned num_layers);
1438 void *si_create_fixed_func_tcs(struct si_context *sctx);
1439 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1440 unsigned num_dwords_per_thread,
1441 bool dst_stream_cache_policy, bool is_copy);
1442 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1443 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1444 void *si_clear_render_target_shader(struct pipe_context *ctx);
1445 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1446 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1447 void *si_create_query_result_cs(struct si_context *sctx);
1448 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1449
1450 /* gfx10_query.c */
1451 void gfx10_init_query(struct si_context *sctx);
1452 void gfx10_destroy_query(struct si_context *sctx);
1453
1454 /* si_test_dma.c */
1455 void si_test_dma(struct si_screen *sscreen);
1456
1457 /* si_test_clearbuffer.c */
1458 void si_test_dma_perf(struct si_screen *sscreen);
1459
1460 /* si_uvd.c */
1461 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1462 const struct pipe_video_codec *templ);
1463
1464 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1465 const struct pipe_video_buffer *tmpl);
1466
1467 /* si_viewport.c */
1468 void si_update_vs_viewport_state(struct si_context *ctx);
1469 void si_init_viewport_functions(struct si_context *ctx);
1470
1471 /* si_texture.c */
1472 bool si_prepare_for_dma_blit(struct si_context *sctx,
1473 struct si_texture *dst,
1474 unsigned dst_level, unsigned dstx,
1475 unsigned dsty, unsigned dstz,
1476 struct si_texture *src,
1477 unsigned src_level,
1478 const struct pipe_box *src_box);
1479 void si_eliminate_fast_color_clear(struct si_context *sctx,
1480 struct si_texture *tex);
1481 void si_texture_discard_cmask(struct si_screen *sscreen,
1482 struct si_texture *tex);
1483 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1484 struct pipe_resource *texture);
1485 void si_print_texture_info(struct si_screen *sscreen,
1486 struct si_texture *tex, struct u_log_context *log);
1487 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1488 const struct pipe_resource *templ);
1489 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1490 enum pipe_format format1,
1491 enum pipe_format format2);
1492 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1493 unsigned level,
1494 enum pipe_format view_format);
1495 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1496 struct pipe_resource *tex,
1497 unsigned level,
1498 enum pipe_format view_format);
1499 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1500 struct pipe_resource *texture,
1501 const struct pipe_surface *templ,
1502 unsigned width0, unsigned height0,
1503 unsigned width, unsigned height);
1504 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1505 void vi_separate_dcc_try_enable(struct si_context *sctx,
1506 struct si_texture *tex);
1507 void vi_separate_dcc_start_query(struct si_context *sctx,
1508 struct si_texture *tex);
1509 void vi_separate_dcc_stop_query(struct si_context *sctx,
1510 struct si_texture *tex);
1511 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1512 struct si_texture *tex);
1513 bool si_texture_disable_dcc(struct si_context *sctx,
1514 struct si_texture *tex);
1515 void si_init_screen_texture_functions(struct si_screen *sscreen);
1516 void si_init_context_texture_functions(struct si_context *sctx);
1517
1518
1519 /*
1520 * common helpers
1521 */
1522
1523 static inline struct si_resource *si_resource(struct pipe_resource *r)
1524 {
1525 return (struct si_resource*)r;
1526 }
1527
1528 static inline void
1529 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1530 {
1531 pipe_resource_reference((struct pipe_resource **)ptr,
1532 (struct pipe_resource *)res);
1533 }
1534
1535 static inline void
1536 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1537 {
1538 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1539 }
1540
1541 static inline bool
1542 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1543 {
1544 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1545 }
1546
1547 static inline unsigned
1548 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1549 {
1550 if (stencil)
1551 return tex->surface.u.legacy.stencil_tiling_index[level];
1552 else
1553 return tex->surface.u.legacy.tiling_index[level];
1554 }
1555
1556 static inline unsigned
1557 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1558 {
1559 /* Don't count the needed CS space exactly and just use an upper bound.
1560 *
1561 * Also reserve space for stopping queries at the end of IB, because
1562 * the number of active queries is unlimited in theory.
1563 */
1564 return 2048 + sctx->num_cs_dw_queries_suspend;
1565 }
1566
1567 static inline void
1568 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1569 {
1570 if (r) {
1571 /* Add memory usage for need_gfx_cs_space */
1572 sctx->vram += si_resource(r)->vram_usage;
1573 sctx->gtt += si_resource(r)->gart_usage;
1574 }
1575 }
1576
1577 static inline void
1578 si_invalidate_draw_sh_constants(struct si_context *sctx)
1579 {
1580 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1581 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1582 }
1583
1584 static inline unsigned
1585 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1586 {
1587 return 1 << (atom - sctx->atoms.array);
1588 }
1589
1590 static inline void
1591 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1592 {
1593 unsigned bit = si_get_atom_bit(sctx, atom);
1594
1595 if (dirty)
1596 sctx->dirty_atoms |= bit;
1597 else
1598 sctx->dirty_atoms &= ~bit;
1599 }
1600
1601 static inline bool
1602 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1603 {
1604 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1605 }
1606
1607 static inline void
1608 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1609 {
1610 si_set_atom_dirty(sctx, atom, true);
1611 }
1612
1613 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1614 {
1615 if (sctx->gs_shader.cso)
1616 return &sctx->gs_shader;
1617 if (sctx->tes_shader.cso)
1618 return &sctx->tes_shader;
1619
1620 return &sctx->vs_shader;
1621 }
1622
1623 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1624 {
1625 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1626
1627 return vs->cso ? &vs->cso->info : NULL;
1628 }
1629
1630 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1631 {
1632 if (sctx->gs_shader.cso &&
1633 sctx->gs_shader.current &&
1634 !sctx->gs_shader.current->key.as_ngg)
1635 return sctx->gs_shader.cso->gs_copy_shader;
1636
1637 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1638 return vs->current ? vs->current : NULL;
1639 }
1640
1641 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1642 unsigned processor)
1643 {
1644 return sscreen->debug_flags & (1 << processor);
1645 }
1646
1647 static inline bool si_get_strmout_en(struct si_context *sctx)
1648 {
1649 return sctx->streamout.streamout_enabled ||
1650 sctx->streamout.prims_gen_query_enabled;
1651 }
1652
1653 static inline unsigned
1654 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1655 {
1656 unsigned alignment, tcc_cache_line_size;
1657
1658 /* If the upload size is less than the cache line size (e.g. 16, 32),
1659 * the whole thing will fit into a cache line if we align it to its size.
1660 * The idea is that multiple small uploads can share a cache line.
1661 * If the upload size is greater, align it to the cache line size.
1662 */
1663 alignment = util_next_power_of_two(upload_size);
1664 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1665 return MIN2(alignment, tcc_cache_line_size);
1666 }
1667
1668 static inline void
1669 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1670 {
1671 if (pipe_reference(&(*dst)->reference, &src->reference))
1672 si_destroy_saved_cs(*dst);
1673
1674 *dst = src;
1675 }
1676
1677 static inline void
1678 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1679 bool shaders_read_metadata, bool dcc_pipe_aligned)
1680 {
1681 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1682 SI_CONTEXT_INV_VCACHE;
1683
1684 if (sctx->chip_class >= GFX10) {
1685 if (shaders_read_metadata)
1686 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1687 } else if (sctx->chip_class == GFX9) {
1688 /* Single-sample color is coherent with shaders on GFX9, but
1689 * L2 metadata must be flushed if shaders read metadata.
1690 * (DCC, CMASK).
1691 */
1692 if (num_samples >= 2 ||
1693 (shaders_read_metadata && !dcc_pipe_aligned))
1694 sctx->flags |= SI_CONTEXT_INV_L2;
1695 else if (shaders_read_metadata)
1696 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1697 } else {
1698 /* GFX6-GFX8 */
1699 sctx->flags |= SI_CONTEXT_INV_L2;
1700 }
1701 }
1702
1703 static inline void
1704 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1705 bool include_stencil, bool shaders_read_metadata)
1706 {
1707 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1708 SI_CONTEXT_INV_VCACHE;
1709
1710 if (sctx->chip_class >= GFX10) {
1711 if (shaders_read_metadata)
1712 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1713 } else if (sctx->chip_class == GFX9) {
1714 /* Single-sample depth (not stencil) is coherent with shaders
1715 * on GFX9, but L2 metadata must be flushed if shaders read
1716 * metadata.
1717 */
1718 if (num_samples >= 2 || include_stencil)
1719 sctx->flags |= SI_CONTEXT_INV_L2;
1720 else if (shaders_read_metadata)
1721 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1722 } else {
1723 /* GFX6-GFX8 */
1724 sctx->flags |= SI_CONTEXT_INV_L2;
1725 }
1726 }
1727
1728 static inline bool
1729 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1730 {
1731 return (stencil_sampler && tex->can_sample_s) ||
1732 (!stencil_sampler && tex->can_sample_z);
1733 }
1734
1735 static inline bool
1736 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1737 {
1738 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1739 return false;
1740
1741 return tex->htile_offset && level == 0;
1742 }
1743
1744 static inline bool
1745 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1746 {
1747 assert(!tex->tc_compatible_htile || tex->htile_offset);
1748 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1749 }
1750
1751 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1752 {
1753 if (sctx->ps_uses_fbfetch)
1754 return sctx->framebuffer.nr_color_samples;
1755
1756 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1757 }
1758
1759 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1760 {
1761 if (sctx->queued.named.rasterizer->rasterizer_discard)
1762 return 0;
1763
1764 struct si_shader_selector *ps = sctx->ps_shader.cso;
1765 if (!ps)
1766 return 0;
1767
1768 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1769 sctx->queued.named.blend->cb_target_mask;
1770
1771 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1772 colormask &= ps->colors_written_4bit;
1773 else if (!ps->colors_written_4bit)
1774 colormask = 0; /* color0 writes all cbufs, but it's not written */
1775
1776 return colormask;
1777 }
1778
1779 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1780 (1 << PIPE_PRIM_LINE_LOOP) | \
1781 (1 << PIPE_PRIM_LINE_STRIP) | \
1782 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1783 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1784
1785 static inline bool util_prim_is_lines(unsigned prim)
1786 {
1787 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1788 }
1789
1790 static inline bool util_prim_is_points_or_lines(unsigned prim)
1791 {
1792 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1793 (1 << PIPE_PRIM_POINTS))) != 0;
1794 }
1795
1796 static inline bool util_rast_prim_is_triangles(unsigned prim)
1797 {
1798 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1799 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1800 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1801 (1 << PIPE_PRIM_QUADS) |
1802 (1 << PIPE_PRIM_QUAD_STRIP) |
1803 (1 << PIPE_PRIM_POLYGON) |
1804 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1805 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1806 }
1807
1808 /**
1809 * Return true if there is enough memory in VRAM and GTT for the buffers
1810 * added so far.
1811 *
1812 * \param vram VRAM memory size not added to the buffer list yet
1813 * \param gtt GTT memory size not added to the buffer list yet
1814 */
1815 static inline bool
1816 radeon_cs_memory_below_limit(struct si_screen *screen,
1817 struct radeon_cmdbuf *cs,
1818 uint64_t vram, uint64_t gtt)
1819 {
1820 vram += cs->used_vram;
1821 gtt += cs->used_gart;
1822
1823 /* Anything that goes above the VRAM size should go to GTT. */
1824 if (vram > screen->info.vram_size)
1825 gtt += vram - screen->info.vram_size;
1826
1827 /* Now we just need to check if we have enough GTT. */
1828 return gtt < screen->info.gart_size * 0.7;
1829 }
1830
1831 /**
1832 * Add a buffer to the buffer list for the given command stream (CS).
1833 *
1834 * All buffers used by a CS must be added to the list. This tells the kernel
1835 * driver which buffers are used by GPU commands. Other buffers can
1836 * be swapped out (not accessible) during execution.
1837 *
1838 * The buffer list becomes empty after every context flush and must be
1839 * rebuilt.
1840 */
1841 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1842 struct radeon_cmdbuf *cs,
1843 struct si_resource *bo,
1844 enum radeon_bo_usage usage,
1845 enum radeon_bo_priority priority)
1846 {
1847 assert(usage);
1848 sctx->ws->cs_add_buffer(
1849 cs, bo->buf,
1850 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1851 bo->domains, priority);
1852 }
1853
1854 /**
1855 * Same as above, but also checks memory usage and flushes the context
1856 * accordingly.
1857 *
1858 * When this SHOULD NOT be used:
1859 *
1860 * - if si_context_add_resource_size has been called for the buffer
1861 * followed by *_need_cs_space for checking the memory usage
1862 *
1863 * - if si_need_dma_space has been called for the buffer
1864 *
1865 * - when emitting state packets and draw packets (because preceding packets
1866 * can't be re-emitted at that point)
1867 *
1868 * - if shader resource "enabled_mask" is not up-to-date or there is
1869 * a different constraint disallowing a context flush
1870 */
1871 static inline void
1872 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1873 struct si_resource *bo,
1874 enum radeon_bo_usage usage,
1875 enum radeon_bo_priority priority,
1876 bool check_mem)
1877 {
1878 if (check_mem &&
1879 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1880 sctx->vram + bo->vram_usage,
1881 sctx->gtt + bo->gart_usage))
1882 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1883
1884 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1885 }
1886
1887 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1888 {
1889 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1890 }
1891
1892 #define PRINT_ERR(fmt, args...) \
1893 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1894
1895 #endif