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radeonsi: make sure that rasterizer state != NULL and remove all NULL checking
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_UNSAFE_MATH,
149 DBG_SI_SCHED,
150 DBG_GISEL,
151 DBG_W32_GE,
152 DBG_W32_PS,
153 DBG_W32_CS,
154 DBG_W64_GE,
155 DBG_W64_PS,
156 DBG_W64_CS,
157
158 /* Shader compiler options (with no effect on the shader cache): */
159 DBG_CHECK_IR,
160 DBG_MONOLITHIC_SHADERS,
161 DBG_NO_OPT_VARIANT,
162
163 /* Information logging options: */
164 DBG_INFO,
165 DBG_TEX,
166 DBG_COMPUTE,
167 DBG_VM,
168
169 /* Driver options: */
170 DBG_FORCE_DMA,
171 DBG_NO_ASYNC_DMA,
172 DBG_NO_WC,
173 DBG_CHECK_VM,
174 DBG_RESERVE_VMID,
175 DBG_ZERO_VRAM,
176
177 /* 3D engine options: */
178 DBG_NO_GFX,
179 DBG_ALWAYS_PD,
180 DBG_PD,
181 DBG_NO_PD,
182 DBG_SWITCH_ON_EOP,
183 DBG_NO_OUT_OF_ORDER,
184 DBG_NO_DPBB,
185 DBG_NO_DFSM,
186 DBG_DPBB,
187 DBG_DFSM,
188 DBG_NO_HYPERZ,
189 DBG_NO_RB_PLUS,
190 DBG_NO_2D_TILING,
191 DBG_NO_TILING,
192 DBG_NO_DCC,
193 DBG_NO_DCC_CLEAR,
194 DBG_NO_DCC_FB,
195 DBG_NO_DCC_MSAA,
196 DBG_NO_FMASK,
197
198 /* Tests: */
199 DBG_TEST_DMA,
200 DBG_TEST_VMFAULT_CP,
201 DBG_TEST_VMFAULT_SDMA,
202 DBG_TEST_VMFAULT_SHADER,
203 DBG_TEST_DMA_PERF,
204 DBG_TEST_GDS,
205 DBG_TEST_GDS_MM,
206 DBG_TEST_GDS_OA_MM,
207 };
208
209 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
210 #define DBG(name) (1ull << DBG_##name)
211
212 enum si_cache_policy {
213 L2_BYPASS,
214 L2_STREAM, /* same as SLC=1 */
215 L2_LRU, /* same as SLC=0 */
216 };
217
218 enum si_coherency {
219 SI_COHERENCY_NONE, /* no cache flushes needed */
220 SI_COHERENCY_SHADER,
221 SI_COHERENCY_CB_META,
222 SI_COHERENCY_CP,
223 };
224
225 struct si_compute;
226 struct si_shader_context;
227 struct hash_table;
228 struct u_suballocator;
229
230 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
231 * at the moment.
232 */
233 struct si_resource {
234 struct threaded_resource b;
235
236 /* Winsys objects. */
237 struct pb_buffer *buf;
238 uint64_t gpu_address;
239 /* Memory usage if the buffer placement is optimal. */
240 uint64_t vram_usage;
241 uint64_t gart_usage;
242
243 /* Resource properties. */
244 uint64_t bo_size;
245 unsigned bo_alignment;
246 enum radeon_bo_domain domains;
247 enum radeon_bo_flag flags;
248 unsigned bind_history;
249 int max_forced_staging_uploads;
250
251 /* The buffer range which is initialized (with a write transfer,
252 * streamout, DMA, or as a random access target). The rest of
253 * the buffer is considered invalid and can be mapped unsynchronized.
254 *
255 * This allows unsychronized mapping of a buffer range which hasn't
256 * been used yet. It's for applications which forget to use
257 * the unsynchronized map flag and expect the driver to figure it out.
258 */
259 struct util_range valid_buffer_range;
260
261 /* For buffers only. This indicates that a write operation has been
262 * performed by TC L2, but the cache hasn't been flushed.
263 * Any hw block which doesn't use or bypasses TC L2 should check this
264 * flag and flush the cache before using the buffer.
265 *
266 * For example, TC L2 must be flushed if a buffer which has been
267 * modified by a shader store instruction is about to be used as
268 * an index buffer. The reason is that VGT DMA index fetching doesn't
269 * use TC L2.
270 */
271 bool TC_L2_dirty;
272
273 /* Whether this resource is referenced by bindless handles. */
274 bool texture_handle_allocated;
275 bool image_handle_allocated;
276
277 /* Whether the resource has been exported via resource_get_handle. */
278 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
279 };
280
281 struct si_transfer {
282 struct threaded_transfer b;
283 struct si_resource *staging;
284 unsigned offset;
285 };
286
287 struct si_texture {
288 struct si_resource buffer;
289
290 struct radeon_surf surface;
291 uint64_t size;
292 struct si_texture *flushed_depth_texture;
293
294 /* One texture allocation can contain these buffers:
295 * - image (pixel data)
296 * - FMASK buffer (MSAA compression)
297 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
298 * - HTILE buffer (Z/S compression and fast Z/S clear)
299 * - DCC buffer (color compression and new fast color clear)
300 * - displayable DCC buffer (if the DCC buffer is not displayable)
301 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
302 */
303 uint64_t fmask_offset;
304 uint64_t cmask_offset;
305 uint64_t cmask_base_address_reg;
306 struct si_resource *cmask_buffer;
307 uint64_t dcc_offset; /* 0 = disabled */
308 uint64_t display_dcc_offset;
309 uint64_t dcc_retile_map_offset;
310 unsigned cb_color_info; /* fast clear enable bit */
311 unsigned color_clear_value[2];
312 unsigned last_msaa_resolve_target_micro_mode;
313 unsigned num_level0_transfers;
314
315 /* Depth buffer compression and fast clear. */
316 uint64_t htile_offset;
317 float depth_clear_value;
318 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
319 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
320 enum pipe_format db_render_format:16;
321 uint8_t stencil_clear_value;
322 bool tc_compatible_htile:1;
323 bool htile_stencil_disabled:1;
324 bool depth_cleared:1; /* if it was cleared at least once */
325 bool stencil_cleared:1; /* if it was cleared at least once */
326 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
327 bool is_depth:1;
328 bool db_compatible:1;
329 bool can_sample_z:1;
330 bool can_sample_s:1;
331
332 /* We need to track DCC dirtiness, because st/dri usually calls
333 * flush_resource twice per frame (not a bug) and we don't wanna
334 * decompress DCC twice. Also, the dirty tracking must be done even
335 * if DCC isn't used, because it's required by the DCC usage analysis
336 * for a possible future enablement.
337 */
338 bool separate_dcc_dirty:1;
339 /* Statistics gathering for the DCC enablement heuristic. */
340 bool dcc_gather_statistics:1;
341 /* Counter that should be non-zero if the texture is bound to a
342 * framebuffer.
343 */
344 unsigned framebuffers_bound;
345 /* Whether the texture is a displayable back buffer and needs DCC
346 * decompression, which is expensive. Therefore, it's enabled only
347 * if statistics suggest that it will pay off and it's allocated
348 * separately. It can't be bound as a sampler by apps. Limited to
349 * target == 2D and last_level == 0. If enabled, dcc_offset contains
350 * the absolute GPUVM address, not the relative one.
351 */
352 struct si_resource *dcc_separate_buffer;
353 /* When DCC is temporarily disabled, the separate buffer is here. */
354 struct si_resource *last_dcc_separate_buffer;
355 /* Estimate of how much this color buffer is written to in units of
356 * full-screen draws: ps_invocations / (width * height)
357 * Shader kills, late Z, and blending with trivial discards make it
358 * inaccurate (we need to count CB updates, not PS invocations).
359 */
360 unsigned ps_draw_ratio;
361 /* The number of clears since the last DCC usage analysis. */
362 unsigned num_slow_clears;
363 };
364
365 struct si_surface {
366 struct pipe_surface base;
367
368 /* These can vary with block-compressed textures. */
369 uint16_t width0;
370 uint16_t height0;
371
372 bool color_initialized:1;
373 bool depth_initialized:1;
374
375 /* Misc. color flags. */
376 bool color_is_int8:1;
377 bool color_is_int10:1;
378 bool dcc_incompatible:1;
379
380 /* Color registers. */
381 unsigned cb_color_info;
382 unsigned cb_color_view;
383 unsigned cb_color_attrib;
384 unsigned cb_color_attrib2; /* GFX9 and later */
385 unsigned cb_color_attrib3; /* GFX10 and later */
386 unsigned cb_dcc_control; /* GFX8 and later */
387 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
388 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
389 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
390 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
391
392 /* DB registers. */
393 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
394 uint64_t db_stencil_base;
395 uint64_t db_htile_data_base;
396 unsigned db_depth_info;
397 unsigned db_z_info;
398 unsigned db_z_info2; /* GFX9 only */
399 unsigned db_depth_view;
400 unsigned db_depth_size;
401 unsigned db_depth_slice;
402 unsigned db_stencil_info;
403 unsigned db_stencil_info2; /* GFX9 only */
404 unsigned db_htile_surface;
405 };
406
407 struct si_mmio_counter {
408 unsigned busy;
409 unsigned idle;
410 };
411
412 union si_mmio_counters {
413 struct {
414 /* For global GPU load including SDMA. */
415 struct si_mmio_counter gpu;
416
417 /* GRBM_STATUS */
418 struct si_mmio_counter spi;
419 struct si_mmio_counter gui;
420 struct si_mmio_counter ta;
421 struct si_mmio_counter gds;
422 struct si_mmio_counter vgt;
423 struct si_mmio_counter ia;
424 struct si_mmio_counter sx;
425 struct si_mmio_counter wd;
426 struct si_mmio_counter bci;
427 struct si_mmio_counter sc;
428 struct si_mmio_counter pa;
429 struct si_mmio_counter db;
430 struct si_mmio_counter cp;
431 struct si_mmio_counter cb;
432
433 /* SRBM_STATUS2 */
434 struct si_mmio_counter sdma;
435
436 /* CP_STAT */
437 struct si_mmio_counter pfp;
438 struct si_mmio_counter meq;
439 struct si_mmio_counter me;
440 struct si_mmio_counter surf_sync;
441 struct si_mmio_counter cp_dma;
442 struct si_mmio_counter scratch_ram;
443 } named;
444 unsigned array[0];
445 };
446
447 struct si_memory_object {
448 struct pipe_memory_object b;
449 struct pb_buffer *buf;
450 uint32_t stride;
451 };
452
453 /* Saved CS data for debugging features. */
454 struct radeon_saved_cs {
455 uint32_t *ib;
456 unsigned num_dw;
457
458 struct radeon_bo_list_item *bo_list;
459 unsigned bo_count;
460 };
461
462 struct si_screen {
463 struct pipe_screen b;
464 struct radeon_winsys *ws;
465 struct disk_cache *disk_shader_cache;
466
467 struct radeon_info info;
468 uint64_t debug_flags;
469 char renderer_string[183];
470
471 void (*make_texture_descriptor)(
472 struct si_screen *screen,
473 struct si_texture *tex,
474 bool sampler,
475 enum pipe_texture_target target,
476 enum pipe_format pipe_format,
477 const unsigned char state_swizzle[4],
478 unsigned first_level, unsigned last_level,
479 unsigned first_layer, unsigned last_layer,
480 unsigned width, unsigned height, unsigned depth,
481 uint32_t *state,
482 uint32_t *fmask_state);
483
484 unsigned pa_sc_raster_config;
485 unsigned pa_sc_raster_config_1;
486 unsigned se_tile_repeat;
487 unsigned gs_table_depth;
488 unsigned tess_offchip_block_dw_size;
489 unsigned tess_offchip_ring_size;
490 unsigned tess_factor_ring_size;
491 unsigned vgt_hs_offchip_param;
492 unsigned eqaa_force_coverage_samples;
493 unsigned eqaa_force_z_samples;
494 unsigned eqaa_force_color_samples;
495 bool has_clear_state;
496 bool has_distributed_tess;
497 bool has_draw_indirect_multi;
498 bool has_out_of_order_rast;
499 bool assume_no_z_fights;
500 bool commutative_blend_add;
501 bool has_gfx9_scissor_bug;
502 bool has_msaa_sample_loc_bug;
503 bool has_ls_vgpr_init_bug;
504 bool has_dcc_constant_encode;
505 bool dpbb_allowed;
506 bool dfsm_allowed;
507 bool llvm_has_working_vgpr_indexing;
508
509 struct {
510 #define OPT_BOOL(name, dflt, description) bool name:1;
511 #include "si_debug_options.h"
512 } options;
513
514 /* Whether shaders are monolithic (1-part) or separate (3-part). */
515 bool use_monolithic_shaders;
516 bool record_llvm_ir;
517 bool has_rbplus; /* if RB+ registers exist */
518 bool rbplus_allowed; /* if RB+ is allowed */
519 bool dcc_msaa_allowed;
520 bool cpdma_prefetch_writes_memory;
521
522 struct slab_parent_pool pool_transfers;
523
524 /* Texture filter settings. */
525 int force_aniso; /* -1 = disabled */
526
527 /* Auxiliary context. Mainly used to initialize resources.
528 * It must be locked prior to using and flushed before unlocking. */
529 struct pipe_context *aux_context;
530 mtx_t aux_context_lock;
531
532 /* This must be in the screen, because UE4 uses one context for
533 * compilation and another one for rendering.
534 */
535 unsigned num_compilations;
536 /* Along with ST_DEBUG=precompile, this should show if applications
537 * are loading shaders on demand. This is a monotonic counter.
538 */
539 unsigned num_shaders_created;
540 unsigned num_shader_cache_hits;
541
542 /* GPU load thread. */
543 mtx_t gpu_load_mutex;
544 thrd_t gpu_load_thread;
545 union si_mmio_counters mmio_counters;
546 volatile unsigned gpu_load_stop_thread; /* bool */
547
548 /* Performance counters. */
549 struct si_perfcounters *perfcounters;
550
551 /* If pipe_screen wants to recompute and re-emit the framebuffer,
552 * sampler, and image states of all contexts, it should atomically
553 * increment this.
554 *
555 * Each context will compare this with its own last known value of
556 * the counter before drawing and re-emit the states accordingly.
557 */
558 unsigned dirty_tex_counter;
559 unsigned dirty_buf_counter;
560
561 /* Atomically increment this counter when an existing texture's
562 * metadata is enabled or disabled in a way that requires changing
563 * contexts' compressed texture binding masks.
564 */
565 unsigned compressed_colortex_counter;
566
567 struct {
568 /* Context flags to set so that all writes from earlier jobs
569 * in the CP are seen by L2 clients.
570 */
571 unsigned cp_to_L2;
572
573 /* Context flags to set so that all writes from earlier jobs
574 * that end in L2 are seen by CP.
575 */
576 unsigned L2_to_cp;
577 } barrier_flags;
578
579 mtx_t shader_parts_mutex;
580 struct si_shader_part *vs_prologs;
581 struct si_shader_part *tcs_epilogs;
582 struct si_shader_part *gs_prologs;
583 struct si_shader_part *ps_prologs;
584 struct si_shader_part *ps_epilogs;
585
586 /* Shader cache in memory.
587 *
588 * Design & limitations:
589 * - The shader cache is per screen (= per process), never saved to
590 * disk, and skips redundant shader compilations from TGSI to bytecode.
591 * - It can only be used with one-variant-per-shader support, in which
592 * case only the main (typically middle) part of shaders is cached.
593 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
594 * variants of VS and TES are cached, so LS and ES aren't.
595 * - GS and CS aren't cached, but it's certainly possible to cache
596 * those as well.
597 */
598 mtx_t shader_cache_mutex;
599 struct hash_table *shader_cache;
600
601 /* Shader compiler queue for multithreaded compilation. */
602 struct util_queue shader_compiler_queue;
603 /* Use at most 3 normal compiler threads on quadcore and better.
604 * Hyperthreaded CPUs report the number of threads, but we want
605 * the number of cores. We only need this many threads for shader-db. */
606 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
607
608 struct util_queue shader_compiler_queue_low_priority;
609 /* Use at most 2 low priority threads on quadcore and better.
610 * We want to minimize the impact on multithreaded Mesa. */
611 struct ac_llvm_compiler compiler_lowp[10];
612
613 unsigned compute_wave_size;
614 unsigned ps_wave_size;
615 unsigned ge_wave_size;
616 };
617
618 struct si_blend_color {
619 struct pipe_blend_color state;
620 bool any_nonzeros;
621 };
622
623 struct si_sampler_view {
624 struct pipe_sampler_view base;
625 /* [0..7] = image descriptor
626 * [4..7] = buffer descriptor */
627 uint32_t state[8];
628 uint32_t fmask_state[8];
629 const struct legacy_surf_level *base_level_info;
630 ubyte base_level;
631 ubyte block_width;
632 bool is_stencil_sampler;
633 bool is_integer;
634 bool dcc_incompatible;
635 };
636
637 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
638
639 struct si_sampler_state {
640 #ifndef NDEBUG
641 unsigned magic;
642 #endif
643 uint32_t val[4];
644 uint32_t integer_val[4];
645 uint32_t upgraded_depth_val[4];
646 };
647
648 struct si_cs_shader_state {
649 struct si_compute *program;
650 struct si_compute *emitted_program;
651 unsigned offset;
652 bool initialized;
653 bool uses_scratch;
654 };
655
656 struct si_samplers {
657 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
658 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
659
660 /* The i-th bit is set if that element is enabled (non-NULL resource). */
661 unsigned enabled_mask;
662 uint32_t needs_depth_decompress_mask;
663 uint32_t needs_color_decompress_mask;
664 };
665
666 struct si_images {
667 struct pipe_image_view views[SI_NUM_IMAGES];
668 uint32_t needs_color_decompress_mask;
669 unsigned enabled_mask;
670 };
671
672 struct si_framebuffer {
673 struct pipe_framebuffer_state state;
674 unsigned colorbuf_enabled_4bit;
675 unsigned spi_shader_col_format;
676 unsigned spi_shader_col_format_alpha;
677 unsigned spi_shader_col_format_blend;
678 unsigned spi_shader_col_format_blend_alpha;
679 ubyte nr_samples:5; /* at most 16xAA */
680 ubyte log_samples:3; /* at most 4 = 16xAA */
681 ubyte nr_color_samples; /* at most 8xAA */
682 ubyte compressed_cb_mask;
683 ubyte uncompressed_cb_mask;
684 ubyte color_is_int8;
685 ubyte color_is_int10;
686 ubyte dirty_cbufs;
687 ubyte dcc_overwrite_combiner_watermark;
688 ubyte min_bytes_per_pixel;
689 bool dirty_zsbuf;
690 bool any_dst_linear;
691 bool CB_has_shader_readable_metadata;
692 bool DB_has_shader_readable_metadata;
693 bool all_DCC_pipe_aligned;
694 };
695
696 enum si_quant_mode {
697 /* This is the list we want to support. */
698 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
699 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
700 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
701 };
702
703 struct si_signed_scissor {
704 int minx;
705 int miny;
706 int maxx;
707 int maxy;
708 enum si_quant_mode quant_mode;
709 };
710
711 struct si_viewports {
712 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
713 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
714 bool y_inverted;
715 };
716
717 struct si_clip_state {
718 struct pipe_clip_state state;
719 bool any_nonzeros;
720 };
721
722 struct si_streamout_target {
723 struct pipe_stream_output_target b;
724
725 /* The buffer where BUFFER_FILLED_SIZE is stored. */
726 struct si_resource *buf_filled_size;
727 unsigned buf_filled_size_offset;
728 bool buf_filled_size_valid;
729
730 unsigned stride_in_dw;
731 };
732
733 struct si_streamout {
734 bool begin_emitted;
735
736 unsigned enabled_mask;
737 unsigned num_targets;
738 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
739
740 unsigned append_bitmask;
741 bool suspended;
742
743 /* External state which comes from the vertex shader,
744 * it must be set explicitly when binding a shader. */
745 uint16_t *stride_in_dw;
746 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
747
748 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
749 unsigned hw_enabled_mask;
750
751 /* The state of VGT_STRMOUT_(CONFIG|EN). */
752 bool streamout_enabled;
753 bool prims_gen_query_enabled;
754 int num_prims_gen_queries;
755 };
756
757 /* A shader state consists of the shader selector, which is a constant state
758 * object shared by multiple contexts and shouldn't be modified, and
759 * the current shader variant selected for this context.
760 */
761 struct si_shader_ctx_state {
762 struct si_shader_selector *cso;
763 struct si_shader *current;
764 };
765
766 #define SI_NUM_VGT_PARAM_KEY_BITS 12
767 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
768
769 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
770 * Some fields are set by state-change calls, most are set by draw_vbo.
771 */
772 union si_vgt_param_key {
773 struct {
774 #ifdef PIPE_ARCH_LITTLE_ENDIAN
775 unsigned prim:4;
776 unsigned uses_instancing:1;
777 unsigned multi_instances_smaller_than_primgroup:1;
778 unsigned primitive_restart:1;
779 unsigned count_from_stream_output:1;
780 unsigned line_stipple_enabled:1;
781 unsigned uses_tess:1;
782 unsigned tess_uses_prim_id:1;
783 unsigned uses_gs:1;
784 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
785 #else /* PIPE_ARCH_BIG_ENDIAN */
786 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
787 unsigned uses_gs:1;
788 unsigned tess_uses_prim_id:1;
789 unsigned uses_tess:1;
790 unsigned line_stipple_enabled:1;
791 unsigned count_from_stream_output:1;
792 unsigned primitive_restart:1;
793 unsigned multi_instances_smaller_than_primgroup:1;
794 unsigned uses_instancing:1;
795 unsigned prim:4;
796 #endif
797 } u;
798 uint32_t index;
799 };
800
801 #define SI_NUM_VGT_STAGES_KEY_BITS 4
802 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
803
804 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
805 * Some fields are set by state-change calls, most are set by draw_vbo.
806 */
807 union si_vgt_stages_key {
808 struct {
809 #ifdef PIPE_ARCH_LITTLE_ENDIAN
810 unsigned tess:1;
811 unsigned gs:1;
812 unsigned ngg:1; /* gfx10+ */
813 unsigned streamout:1; /* only used with NGG */
814 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
815 #else /* PIPE_ARCH_BIG_ENDIAN */
816 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
817 unsigned streamout:1;
818 unsigned ngg:1;
819 unsigned gs:1;
820 unsigned tess:1;
821 #endif
822 } u;
823 uint32_t index;
824 };
825
826 struct si_texture_handle
827 {
828 unsigned desc_slot;
829 bool desc_dirty;
830 struct pipe_sampler_view *view;
831 struct si_sampler_state sstate;
832 };
833
834 struct si_image_handle
835 {
836 unsigned desc_slot;
837 bool desc_dirty;
838 struct pipe_image_view view;
839 };
840
841 struct si_saved_cs {
842 struct pipe_reference reference;
843 struct si_context *ctx;
844 struct radeon_saved_cs gfx;
845 struct radeon_saved_cs compute;
846 struct si_resource *trace_buf;
847 unsigned trace_id;
848
849 unsigned gfx_last_dw;
850 unsigned compute_last_dw;
851 bool flushed;
852 int64_t time_flush;
853 };
854
855 struct si_sdma_upload {
856 struct si_resource *dst;
857 struct si_resource *src;
858 unsigned src_offset;
859 unsigned dst_offset;
860 unsigned size;
861 };
862
863 struct si_context {
864 struct pipe_context b; /* base class */
865
866 enum radeon_family family;
867 enum chip_class chip_class;
868
869 struct radeon_winsys *ws;
870 struct radeon_winsys_ctx *ctx;
871 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
872 struct radeon_cmdbuf *dma_cs;
873 struct pipe_fence_handle *last_gfx_fence;
874 struct pipe_fence_handle *last_sdma_fence;
875 struct si_resource *eop_bug_scratch;
876 struct u_upload_mgr *cached_gtt_allocator;
877 struct threaded_context *tc;
878 struct u_suballocator *allocator_zeroed_memory;
879 struct slab_child_pool pool_transfers;
880 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
881 struct pipe_device_reset_callback device_reset_callback;
882 struct u_log_context *log;
883 void *query_result_shader;
884 void *sh_query_result_shader;
885
886 void (*emit_cache_flush)(struct si_context *ctx);
887
888 struct blitter_context *blitter;
889 void *noop_blend;
890 void *noop_dsa;
891 void *discard_rasterizer_state;
892 void *custom_dsa_flush;
893 void *custom_blend_resolve;
894 void *custom_blend_fmask_decompress;
895 void *custom_blend_eliminate_fastclear;
896 void *custom_blend_dcc_decompress;
897 void *vs_blit_pos;
898 void *vs_blit_pos_layered;
899 void *vs_blit_color;
900 void *vs_blit_color_layered;
901 void *vs_blit_texcoord;
902 void *cs_clear_buffer;
903 void *cs_copy_buffer;
904 void *cs_copy_image;
905 void *cs_copy_image_1d_array;
906 void *cs_clear_render_target;
907 void *cs_clear_render_target_1d_array;
908 void *cs_dcc_retile;
909 struct si_screen *screen;
910 struct pipe_debug_callback debug;
911 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
912 struct si_shader_ctx_state fixed_func_tcs_shader;
913 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
914 struct si_resource *wait_mem_scratch;
915 unsigned wait_mem_number;
916 uint16_t prefetch_L2_mask;
917
918 bool has_graphics;
919 bool gfx_flush_in_progress:1;
920 bool gfx_last_ib_is_busy:1;
921 bool compute_is_busy:1;
922
923 unsigned num_gfx_cs_flushes;
924 unsigned initial_gfx_cs_size;
925 unsigned last_dirty_tex_counter;
926 unsigned last_dirty_buf_counter;
927 unsigned last_compressed_colortex_counter;
928 unsigned last_num_draw_calls;
929 unsigned flags; /* flush flags */
930 /* Current unaccounted memory usage. */
931 uint64_t vram;
932 uint64_t gtt;
933
934 /* Compute-based primitive discard. */
935 unsigned prim_discard_vertex_count_threshold;
936 struct pb_buffer *gds;
937 struct pb_buffer *gds_oa;
938 struct radeon_cmdbuf *prim_discard_compute_cs;
939 unsigned compute_gds_offset;
940 struct si_shader *compute_ib_last_shader;
941 uint32_t compute_rewind_va;
942 unsigned compute_num_prims_in_batch;
943 bool preserve_prim_restart_gds_at_flush;
944 /* index_ring is divided into 2 halves for doublebuffering. */
945 struct si_resource *index_ring;
946 unsigned index_ring_base; /* offset of a per-IB portion */
947 unsigned index_ring_offset; /* offset within a per-IB portion */
948 unsigned index_ring_size_per_ib; /* max available size per IB */
949 bool prim_discard_compute_ib_initialized;
950 /* For tracking the last execution barrier - it can be either
951 * a WRITE_DATA packet or a fence. */
952 uint32_t *last_pkt3_write_data;
953 struct si_resource *barrier_buf;
954 unsigned barrier_buf_offset;
955 struct pipe_fence_handle *last_ib_barrier_fence;
956 struct si_resource *last_ib_barrier_buf;
957 unsigned last_ib_barrier_buf_offset;
958
959 /* Atoms (direct states). */
960 union si_state_atoms atoms;
961 unsigned dirty_atoms; /* mask */
962 /* PM4 states (precomputed immutable states) */
963 unsigned dirty_states;
964 union si_state queued;
965 union si_state emitted;
966
967 /* Atom declarations. */
968 struct si_framebuffer framebuffer;
969 unsigned sample_locs_num_samples;
970 uint16_t sample_mask;
971 unsigned last_cb_target_mask;
972 struct si_blend_color blend_color;
973 struct si_clip_state clip_state;
974 struct si_shader_data shader_pointers;
975 struct si_stencil_ref stencil_ref;
976 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
977 struct si_streamout streamout;
978 struct si_viewports viewports;
979 unsigned num_window_rectangles;
980 bool window_rectangles_include;
981 struct pipe_scissor_state window_rectangles[4];
982
983 /* Precomputed states. */
984 struct si_pm4_state *init_config;
985 struct si_pm4_state *init_config_gs_rings;
986 bool init_config_has_vgt_flush;
987 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
988
989 /* shaders */
990 struct si_shader_ctx_state ps_shader;
991 struct si_shader_ctx_state gs_shader;
992 struct si_shader_ctx_state vs_shader;
993 struct si_shader_ctx_state tcs_shader;
994 struct si_shader_ctx_state tes_shader;
995 struct si_shader_ctx_state cs_prim_discard_state;
996 struct si_cs_shader_state cs_shader_state;
997
998 /* shader information */
999 struct si_vertex_elements *vertex_elements;
1000 unsigned sprite_coord_enable;
1001 unsigned cs_max_waves_per_sh;
1002 bool flatshade;
1003 bool do_update_shaders;
1004
1005 /* vertex buffer descriptors */
1006 uint32_t *vb_descriptors_gpu_list;
1007 struct si_resource *vb_descriptors_buffer;
1008 unsigned vb_descriptors_offset;
1009
1010 /* shader descriptors */
1011 struct si_descriptors descriptors[SI_NUM_DESCS];
1012 unsigned descriptors_dirty;
1013 unsigned shader_pointers_dirty;
1014 unsigned shader_needs_decompress_mask;
1015 struct si_buffer_resources rw_buffers;
1016 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1017 struct si_samplers samplers[SI_NUM_SHADERS];
1018 struct si_images images[SI_NUM_SHADERS];
1019 bool bo_list_add_all_resident_resources;
1020 bool bo_list_add_all_gfx_resources;
1021 bool bo_list_add_all_compute_resources;
1022
1023 /* other shader resources */
1024 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1025 struct pipe_resource *esgs_ring;
1026 struct pipe_resource *gsvs_ring;
1027 struct pipe_resource *tess_rings;
1028 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1029 struct si_resource *border_color_buffer;
1030 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1031 unsigned border_color_count;
1032 unsigned num_vs_blit_sgprs;
1033 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1034 uint32_t cs_user_data[4];
1035
1036 /* Vertex and index buffers. */
1037 bool vertex_buffers_dirty;
1038 bool vertex_buffer_pointer_dirty;
1039 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1040 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1041
1042 /* MSAA config state. */
1043 int ps_iter_samples;
1044 bool ps_uses_fbfetch;
1045 bool smoothing_enabled;
1046
1047 /* DB render state. */
1048 unsigned ps_db_shader_control;
1049 unsigned dbcb_copy_sample;
1050 bool dbcb_depth_copy_enabled:1;
1051 bool dbcb_stencil_copy_enabled:1;
1052 bool db_flush_depth_inplace:1;
1053 bool db_flush_stencil_inplace:1;
1054 bool db_depth_clear:1;
1055 bool db_depth_disable_expclear:1;
1056 bool db_stencil_clear:1;
1057 bool db_stencil_disable_expclear:1;
1058 bool occlusion_queries_disabled:1;
1059 bool generate_mipmap_for_depth:1;
1060
1061 /* Emitted draw state. */
1062 bool gs_tri_strip_adj_fix:1;
1063 bool ls_vgpr_fix:1;
1064 bool prim_discard_cs_instancing:1;
1065 bool ngg:1;
1066 int last_index_size;
1067 int last_base_vertex;
1068 int last_start_instance;
1069 int last_instance_count;
1070 int last_drawid;
1071 int last_sh_base_reg;
1072 int last_primitive_restart_en;
1073 int last_restart_index;
1074 int last_prim;
1075 int last_multi_vgt_param;
1076 int last_rast_prim;
1077 int last_flatshade_first;
1078 int last_binning_enabled;
1079 unsigned last_sc_line_stipple;
1080 unsigned current_vs_state;
1081 unsigned last_vs_state;
1082 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1083
1084 /* Scratch buffer */
1085 struct si_resource *scratch_buffer;
1086 unsigned scratch_waves;
1087 unsigned spi_tmpring_size;
1088
1089 struct si_resource *compute_scratch_buffer;
1090
1091 /* Emitted derived tessellation state. */
1092 /* Local shader (VS), or HS if LS-HS are merged. */
1093 struct si_shader *last_ls;
1094 struct si_shader_selector *last_tcs;
1095 int last_num_tcs_input_cp;
1096 int last_tes_sh_base;
1097 bool last_tess_uses_primid;
1098 unsigned last_num_patches;
1099 int last_ls_hs_config;
1100
1101 /* Debug state. */
1102 bool is_debug;
1103 struct si_saved_cs *current_saved_cs;
1104 uint64_t dmesg_timestamp;
1105 unsigned apitrace_call_number;
1106
1107 /* Other state */
1108 bool need_check_render_feedback;
1109 bool decompression_enabled;
1110 bool dpbb_force_off;
1111 bool vs_writes_viewport_index;
1112 bool vs_disables_clipping_viewport;
1113
1114 /* Precomputed IA_MULTI_VGT_PARAM */
1115 union si_vgt_param_key ia_multi_vgt_param_key;
1116 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1117
1118 /* Bindless descriptors. */
1119 struct si_descriptors bindless_descriptors;
1120 struct util_idalloc bindless_used_slots;
1121 unsigned num_bindless_descriptors;
1122 bool bindless_descriptors_dirty;
1123 bool graphics_bindless_pointer_dirty;
1124 bool compute_bindless_pointer_dirty;
1125
1126 /* Allocated bindless handles */
1127 struct hash_table *tex_handles;
1128 struct hash_table *img_handles;
1129
1130 /* Resident bindless handles */
1131 struct util_dynarray resident_tex_handles;
1132 struct util_dynarray resident_img_handles;
1133
1134 /* Resident bindless handles which need decompression */
1135 struct util_dynarray resident_tex_needs_color_decompress;
1136 struct util_dynarray resident_img_needs_color_decompress;
1137 struct util_dynarray resident_tex_needs_depth_decompress;
1138
1139 /* Bindless state */
1140 bool uses_bindless_samplers;
1141 bool uses_bindless_images;
1142
1143 /* MSAA sample locations.
1144 * The first index is the sample index.
1145 * The second index is the coordinate: X, Y. */
1146 struct {
1147 float x1[1][2];
1148 float x2[2][2];
1149 float x4[4][2];
1150 float x8[8][2];
1151 float x16[16][2];
1152 } sample_positions;
1153 struct pipe_resource *sample_pos_buffer;
1154
1155 /* Misc stats. */
1156 unsigned num_draw_calls;
1157 unsigned num_decompress_calls;
1158 unsigned num_mrt_draw_calls;
1159 unsigned num_prim_restart_calls;
1160 unsigned num_spill_draw_calls;
1161 unsigned num_compute_calls;
1162 unsigned num_spill_compute_calls;
1163 unsigned num_dma_calls;
1164 unsigned num_cp_dma_calls;
1165 unsigned num_vs_flushes;
1166 unsigned num_ps_flushes;
1167 unsigned num_cs_flushes;
1168 unsigned num_cb_cache_flushes;
1169 unsigned num_db_cache_flushes;
1170 unsigned num_L2_invalidates;
1171 unsigned num_L2_writebacks;
1172 unsigned num_resident_handles;
1173 uint64_t num_alloc_tex_transfer_bytes;
1174 unsigned last_tex_ps_draw_ratio; /* for query */
1175 unsigned compute_num_verts_accepted;
1176 unsigned compute_num_verts_rejected;
1177 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1178 unsigned context_roll;
1179
1180 /* Queries. */
1181 /* Maintain the list of active queries for pausing between IBs. */
1182 int num_occlusion_queries;
1183 int num_perfect_occlusion_queries;
1184 int num_pipeline_stat_queries;
1185 struct list_head active_queries;
1186 unsigned num_cs_dw_queries_suspend;
1187
1188 /* Render condition. */
1189 struct pipe_query *render_cond;
1190 unsigned render_cond_mode;
1191 bool render_cond_invert;
1192 bool render_cond_force_off; /* for u_blitter */
1193
1194 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1195 bool sdma_uploads_in_progress;
1196 struct si_sdma_upload *sdma_uploads;
1197 unsigned num_sdma_uploads;
1198 unsigned max_sdma_uploads;
1199
1200 /* Shader-based queries. */
1201 struct list_head shader_query_buffers;
1202 unsigned num_active_shader_queries;
1203
1204 /* Statistics gathering for the DCC enablement heuristic. It can't be
1205 * in si_texture because si_texture can be shared by multiple
1206 * contexts. This is for back buffers only. We shouldn't get too many
1207 * of those.
1208 *
1209 * X11 DRI3 rotates among a finite set of back buffers. They should
1210 * all fit in this array. If they don't, separate DCC might never be
1211 * enabled by DCC stat gathering.
1212 */
1213 struct {
1214 struct si_texture *tex;
1215 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1216 struct pipe_query *ps_stats[3];
1217 /* If all slots are used and another slot is needed,
1218 * the least recently used slot is evicted based on this. */
1219 int64_t last_use_timestamp;
1220 bool query_active;
1221 } dcc_stats[5];
1222
1223 /* Copy one resource to another using async DMA. */
1224 void (*dma_copy)(struct pipe_context *ctx,
1225 struct pipe_resource *dst,
1226 unsigned dst_level,
1227 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1228 struct pipe_resource *src,
1229 unsigned src_level,
1230 const struct pipe_box *src_box);
1231
1232 struct si_tracked_regs tracked_regs;
1233 };
1234
1235 /* cik_sdma.c */
1236 void cik_init_sdma_functions(struct si_context *sctx);
1237
1238 /* si_blit.c */
1239 enum si_blitter_op /* bitmask */
1240 {
1241 SI_SAVE_TEXTURES = 1,
1242 SI_SAVE_FRAMEBUFFER = 2,
1243 SI_SAVE_FRAGMENT_STATE = 4,
1244 SI_DISABLE_RENDER_COND = 8,
1245 };
1246
1247 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1248 void si_blitter_end(struct si_context *sctx);
1249 void si_init_blit_functions(struct si_context *sctx);
1250 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1251 void si_resource_copy_region(struct pipe_context *ctx,
1252 struct pipe_resource *dst,
1253 unsigned dst_level,
1254 unsigned dstx, unsigned dsty, unsigned dstz,
1255 struct pipe_resource *src,
1256 unsigned src_level,
1257 const struct pipe_box *src_box);
1258 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1259
1260 /* si_buffer.c */
1261 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1262 struct pb_buffer *buf,
1263 enum radeon_bo_usage usage);
1264 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1265 struct si_resource *resource,
1266 unsigned usage);
1267 void si_init_resource_fields(struct si_screen *sscreen,
1268 struct si_resource *res,
1269 uint64_t size, unsigned alignment);
1270 bool si_alloc_resource(struct si_screen *sscreen,
1271 struct si_resource *res);
1272 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1273 unsigned flags, unsigned usage,
1274 unsigned size, unsigned alignment);
1275 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1276 unsigned flags, unsigned usage,
1277 unsigned size, unsigned alignment);
1278 void si_replace_buffer_storage(struct pipe_context *ctx,
1279 struct pipe_resource *dst,
1280 struct pipe_resource *src);
1281 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1282 void si_init_buffer_functions(struct si_context *sctx);
1283
1284 /* si_clear.c */
1285 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1286 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1287 bool vi_dcc_clear_level(struct si_context *sctx,
1288 struct si_texture *tex,
1289 unsigned level, unsigned clear_value);
1290 void si_init_clear_functions(struct si_context *sctx);
1291
1292 /* si_compute_blit.c */
1293 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1294 enum si_cache_policy cache_policy);
1295 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1296 uint64_t offset, uint64_t size, uint32_t *clear_value,
1297 uint32_t clear_value_size, enum si_coherency coher,
1298 bool force_cpdma);
1299 void si_copy_buffer(struct si_context *sctx,
1300 struct pipe_resource *dst, struct pipe_resource *src,
1301 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1302 void si_compute_copy_image(struct si_context *sctx,
1303 struct pipe_resource *dst,
1304 unsigned dst_level,
1305 struct pipe_resource *src,
1306 unsigned src_level,
1307 unsigned dstx, unsigned dsty, unsigned dstz,
1308 const struct pipe_box *src_box);
1309 void si_compute_clear_render_target(struct pipe_context *ctx,
1310 struct pipe_surface *dstsurf,
1311 const union pipe_color_union *color,
1312 unsigned dstx, unsigned dsty,
1313 unsigned width, unsigned height,
1314 bool render_condition_enabled);
1315 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1316 void si_init_compute_blit_functions(struct si_context *sctx);
1317
1318 /* si_cp_dma.c */
1319 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1320 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1321 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1322 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1323 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1324 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1325 SI_CPDMA_SKIP_SYNC_AFTER | \
1326 SI_CPDMA_SKIP_SYNC_BEFORE | \
1327 SI_CPDMA_SKIP_GFX_SYNC | \
1328 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1329
1330 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1331 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1332 struct pipe_resource *dst, uint64_t offset,
1333 uint64_t size, unsigned value, unsigned user_flags,
1334 enum si_coherency coher, enum si_cache_policy cache_policy);
1335 void si_cp_dma_copy_buffer(struct si_context *sctx,
1336 struct pipe_resource *dst, struct pipe_resource *src,
1337 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1338 unsigned user_flags, enum si_coherency coher,
1339 enum si_cache_policy cache_policy);
1340 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1341 uint64_t offset, unsigned size);
1342 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1343 void si_test_gds(struct si_context *sctx);
1344 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1345 unsigned offset, unsigned size, unsigned dst_sel,
1346 unsigned engine, const void *data);
1347 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1348 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1349 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1350
1351 /* si_debug.c */
1352 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1353 struct radeon_saved_cs *saved, bool get_buffer_list);
1354 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1355 void si_destroy_saved_cs(struct si_saved_cs *scs);
1356 void si_auto_log_cs(void *data, struct u_log_context *log);
1357 void si_log_hw_flush(struct si_context *sctx);
1358 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1359 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1360 void si_init_debug_functions(struct si_context *sctx);
1361 void si_check_vm_faults(struct si_context *sctx,
1362 struct radeon_saved_cs *saved, enum ring_type ring);
1363 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1364
1365 /* si_dma.c */
1366 void si_init_dma_functions(struct si_context *sctx);
1367
1368 /* si_dma_cs.c */
1369 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1370 uint64_t offset);
1371 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1372 uint64_t offset, uint64_t size, unsigned clear_value);
1373 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1374 struct si_resource *dst, struct si_resource *src);
1375 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1376 struct pipe_fence_handle **fence);
1377 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1378 uint64_t offset, uint64_t size, unsigned value);
1379
1380 /* si_fence.c */
1381 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1382 unsigned event, unsigned event_flags,
1383 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1384 struct si_resource *buf, uint64_t va,
1385 uint32_t new_fence, unsigned query_type);
1386 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1387 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1388 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1389 void si_init_fence_functions(struct si_context *ctx);
1390 void si_init_screen_fence_functions(struct si_screen *screen);
1391 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1392 struct tc_unflushed_batch_token *tc_token);
1393
1394 /* si_get.c */
1395 void si_init_screen_get_functions(struct si_screen *sscreen);
1396
1397 /* si_gfx_cs.c */
1398 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1399 struct pipe_fence_handle **fence);
1400 void si_allocate_gds(struct si_context *ctx);
1401 void si_begin_new_gfx_cs(struct si_context *ctx);
1402 void si_need_gfx_cs_space(struct si_context *ctx);
1403 void si_unref_sdma_uploads(struct si_context *sctx);
1404
1405 /* si_gpu_load.c */
1406 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1407 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1408 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1409 uint64_t begin);
1410
1411 /* si_compute.c */
1412 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1413 void si_init_compute_functions(struct si_context *sctx);
1414
1415 /* si_compute_prim_discard.c */
1416 enum si_prim_discard_outcome {
1417 SI_PRIM_DISCARD_ENABLED,
1418 SI_PRIM_DISCARD_DISABLED,
1419 SI_PRIM_DISCARD_DRAW_SPLIT,
1420 };
1421
1422 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1423 enum si_prim_discard_outcome
1424 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1425 const struct pipe_draw_info *info,
1426 bool primitive_restart);
1427 void si_compute_signal_gfx(struct si_context *sctx);
1428 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1429 const struct pipe_draw_info *info,
1430 unsigned index_size,
1431 unsigned base_vertex,
1432 uint64_t input_indexbuf_va,
1433 unsigned input_indexbuf_max_elements);
1434 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1435
1436 /* si_perfcounters.c */
1437 void si_init_perfcounters(struct si_screen *screen);
1438 void si_destroy_perfcounters(struct si_screen *screen);
1439
1440 /* si_pipe.c */
1441 bool si_check_device_reset(struct si_context *sctx);
1442
1443 /* si_query.c */
1444 void si_init_screen_query_functions(struct si_screen *sscreen);
1445 void si_init_query_functions(struct si_context *sctx);
1446 void si_suspend_queries(struct si_context *sctx);
1447 void si_resume_queries(struct si_context *sctx);
1448
1449 /* si_shaderlib_tgsi.c */
1450 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1451 unsigned num_layers);
1452 void *si_create_fixed_func_tcs(struct si_context *sctx);
1453 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1454 unsigned num_dwords_per_thread,
1455 bool dst_stream_cache_policy, bool is_copy);
1456 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1457 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1458 void *si_clear_render_target_shader(struct pipe_context *ctx);
1459 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1460 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1461 void *si_create_query_result_cs(struct si_context *sctx);
1462 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1463
1464 /* gfx10_query.c */
1465 void gfx10_init_query(struct si_context *sctx);
1466 void gfx10_destroy_query(struct si_context *sctx);
1467
1468 /* si_test_dma.c */
1469 void si_test_dma(struct si_screen *sscreen);
1470
1471 /* si_test_clearbuffer.c */
1472 void si_test_dma_perf(struct si_screen *sscreen);
1473
1474 /* si_uvd.c */
1475 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1476 const struct pipe_video_codec *templ);
1477
1478 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1479 const struct pipe_video_buffer *tmpl);
1480
1481 /* si_viewport.c */
1482 void si_update_vs_viewport_state(struct si_context *ctx);
1483 void si_init_viewport_functions(struct si_context *ctx);
1484
1485 /* si_texture.c */
1486 bool si_prepare_for_dma_blit(struct si_context *sctx,
1487 struct si_texture *dst,
1488 unsigned dst_level, unsigned dstx,
1489 unsigned dsty, unsigned dstz,
1490 struct si_texture *src,
1491 unsigned src_level,
1492 const struct pipe_box *src_box);
1493 void si_eliminate_fast_color_clear(struct si_context *sctx,
1494 struct si_texture *tex);
1495 void si_texture_discard_cmask(struct si_screen *sscreen,
1496 struct si_texture *tex);
1497 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1498 struct pipe_resource *texture);
1499 void si_print_texture_info(struct si_screen *sscreen,
1500 struct si_texture *tex, struct u_log_context *log);
1501 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1502 const struct pipe_resource *templ);
1503 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1504 enum pipe_format format1,
1505 enum pipe_format format2);
1506 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1507 unsigned level,
1508 enum pipe_format view_format);
1509 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1510 struct pipe_resource *tex,
1511 unsigned level,
1512 enum pipe_format view_format);
1513 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1514 struct pipe_resource *texture,
1515 const struct pipe_surface *templ,
1516 unsigned width0, unsigned height0,
1517 unsigned width, unsigned height);
1518 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1519 void vi_separate_dcc_try_enable(struct si_context *sctx,
1520 struct si_texture *tex);
1521 void vi_separate_dcc_start_query(struct si_context *sctx,
1522 struct si_texture *tex);
1523 void vi_separate_dcc_stop_query(struct si_context *sctx,
1524 struct si_texture *tex);
1525 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1526 struct si_texture *tex);
1527 bool si_texture_disable_dcc(struct si_context *sctx,
1528 struct si_texture *tex);
1529 void si_init_screen_texture_functions(struct si_screen *sscreen);
1530 void si_init_context_texture_functions(struct si_context *sctx);
1531
1532
1533 /*
1534 * common helpers
1535 */
1536
1537 static inline struct si_resource *si_resource(struct pipe_resource *r)
1538 {
1539 return (struct si_resource*)r;
1540 }
1541
1542 static inline void
1543 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1544 {
1545 pipe_resource_reference((struct pipe_resource **)ptr,
1546 (struct pipe_resource *)res);
1547 }
1548
1549 static inline void
1550 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1551 {
1552 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1553 }
1554
1555 static inline bool
1556 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1557 {
1558 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1559 }
1560
1561 static inline unsigned
1562 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1563 {
1564 if (stencil)
1565 return tex->surface.u.legacy.stencil_tiling_index[level];
1566 else
1567 return tex->surface.u.legacy.tiling_index[level];
1568 }
1569
1570 static inline unsigned
1571 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1572 {
1573 /* Don't count the needed CS space exactly and just use an upper bound.
1574 *
1575 * Also reserve space for stopping queries at the end of IB, because
1576 * the number of active queries is unlimited in theory.
1577 */
1578 return 2048 + sctx->num_cs_dw_queries_suspend;
1579 }
1580
1581 static inline void
1582 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1583 {
1584 if (r) {
1585 /* Add memory usage for need_gfx_cs_space */
1586 sctx->vram += si_resource(r)->vram_usage;
1587 sctx->gtt += si_resource(r)->gart_usage;
1588 }
1589 }
1590
1591 static inline void
1592 si_invalidate_draw_sh_constants(struct si_context *sctx)
1593 {
1594 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1595 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1596 }
1597
1598 static inline unsigned
1599 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1600 {
1601 return 1 << (atom - sctx->atoms.array);
1602 }
1603
1604 static inline void
1605 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1606 {
1607 unsigned bit = si_get_atom_bit(sctx, atom);
1608
1609 if (dirty)
1610 sctx->dirty_atoms |= bit;
1611 else
1612 sctx->dirty_atoms &= ~bit;
1613 }
1614
1615 static inline bool
1616 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1617 {
1618 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1619 }
1620
1621 static inline void
1622 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1623 {
1624 si_set_atom_dirty(sctx, atom, true);
1625 }
1626
1627 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1628 {
1629 if (sctx->gs_shader.cso)
1630 return &sctx->gs_shader;
1631 if (sctx->tes_shader.cso)
1632 return &sctx->tes_shader;
1633
1634 return &sctx->vs_shader;
1635 }
1636
1637 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1638 {
1639 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1640
1641 return vs->cso ? &vs->cso->info : NULL;
1642 }
1643
1644 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1645 {
1646 if (sctx->gs_shader.cso &&
1647 sctx->gs_shader.current &&
1648 !sctx->gs_shader.current->key.as_ngg)
1649 return sctx->gs_shader.cso->gs_copy_shader;
1650
1651 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1652 return vs->current ? vs->current : NULL;
1653 }
1654
1655 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1656 unsigned processor)
1657 {
1658 return sscreen->debug_flags & (1 << processor);
1659 }
1660
1661 static inline bool si_get_strmout_en(struct si_context *sctx)
1662 {
1663 return sctx->streamout.streamout_enabled ||
1664 sctx->streamout.prims_gen_query_enabled;
1665 }
1666
1667 static inline unsigned
1668 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1669 {
1670 unsigned alignment, tcc_cache_line_size;
1671
1672 /* If the upload size is less than the cache line size (e.g. 16, 32),
1673 * the whole thing will fit into a cache line if we align it to its size.
1674 * The idea is that multiple small uploads can share a cache line.
1675 * If the upload size is greater, align it to the cache line size.
1676 */
1677 alignment = util_next_power_of_two(upload_size);
1678 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1679 return MIN2(alignment, tcc_cache_line_size);
1680 }
1681
1682 static inline void
1683 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1684 {
1685 if (pipe_reference(&(*dst)->reference, &src->reference))
1686 si_destroy_saved_cs(*dst);
1687
1688 *dst = src;
1689 }
1690
1691 static inline void
1692 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1693 bool shaders_read_metadata, bool dcc_pipe_aligned)
1694 {
1695 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1696 SI_CONTEXT_INV_VCACHE;
1697
1698 if (sctx->chip_class >= GFX10) {
1699 if (shaders_read_metadata)
1700 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1701 } else if (sctx->chip_class == GFX9) {
1702 /* Single-sample color is coherent with shaders on GFX9, but
1703 * L2 metadata must be flushed if shaders read metadata.
1704 * (DCC, CMASK).
1705 */
1706 if (num_samples >= 2 ||
1707 (shaders_read_metadata && !dcc_pipe_aligned))
1708 sctx->flags |= SI_CONTEXT_INV_L2;
1709 else if (shaders_read_metadata)
1710 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1711 } else {
1712 /* GFX6-GFX8 */
1713 sctx->flags |= SI_CONTEXT_INV_L2;
1714 }
1715 }
1716
1717 static inline void
1718 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1719 bool include_stencil, bool shaders_read_metadata)
1720 {
1721 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1722 SI_CONTEXT_INV_VCACHE;
1723
1724 if (sctx->chip_class >= GFX10) {
1725 if (shaders_read_metadata)
1726 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1727 } else if (sctx->chip_class == GFX9) {
1728 /* Single-sample depth (not stencil) is coherent with shaders
1729 * on GFX9, but L2 metadata must be flushed if shaders read
1730 * metadata.
1731 */
1732 if (num_samples >= 2 || include_stencil)
1733 sctx->flags |= SI_CONTEXT_INV_L2;
1734 else if (shaders_read_metadata)
1735 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1736 } else {
1737 /* GFX6-GFX8 */
1738 sctx->flags |= SI_CONTEXT_INV_L2;
1739 }
1740 }
1741
1742 static inline bool
1743 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1744 {
1745 return (stencil_sampler && tex->can_sample_s) ||
1746 (!stencil_sampler && tex->can_sample_z);
1747 }
1748
1749 static inline bool
1750 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1751 {
1752 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1753 return false;
1754
1755 return tex->htile_offset && level == 0;
1756 }
1757
1758 static inline bool
1759 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1760 {
1761 assert(!tex->tc_compatible_htile || tex->htile_offset);
1762 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1763 }
1764
1765 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1766 {
1767 if (sctx->ps_uses_fbfetch)
1768 return sctx->framebuffer.nr_color_samples;
1769
1770 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1771 }
1772
1773 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1774 {
1775 if (sctx->queued.named.rasterizer->rasterizer_discard)
1776 return 0;
1777
1778 struct si_shader_selector *ps = sctx->ps_shader.cso;
1779 if (!ps)
1780 return 0;
1781
1782 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1783 sctx->queued.named.blend->cb_target_mask;
1784
1785 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1786 colormask &= ps->colors_written_4bit;
1787 else if (!ps->colors_written_4bit)
1788 colormask = 0; /* color0 writes all cbufs, but it's not written */
1789
1790 return colormask;
1791 }
1792
1793 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1794 (1 << PIPE_PRIM_LINE_LOOP) | \
1795 (1 << PIPE_PRIM_LINE_STRIP) | \
1796 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1797 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1798
1799 static inline bool util_prim_is_lines(unsigned prim)
1800 {
1801 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1802 }
1803
1804 static inline bool util_prim_is_points_or_lines(unsigned prim)
1805 {
1806 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1807 (1 << PIPE_PRIM_POINTS))) != 0;
1808 }
1809
1810 static inline bool util_rast_prim_is_triangles(unsigned prim)
1811 {
1812 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1813 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1814 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1815 (1 << PIPE_PRIM_QUADS) |
1816 (1 << PIPE_PRIM_QUAD_STRIP) |
1817 (1 << PIPE_PRIM_POLYGON) |
1818 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1819 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1820 }
1821
1822 /**
1823 * Return true if there is enough memory in VRAM and GTT for the buffers
1824 * added so far.
1825 *
1826 * \param vram VRAM memory size not added to the buffer list yet
1827 * \param gtt GTT memory size not added to the buffer list yet
1828 */
1829 static inline bool
1830 radeon_cs_memory_below_limit(struct si_screen *screen,
1831 struct radeon_cmdbuf *cs,
1832 uint64_t vram, uint64_t gtt)
1833 {
1834 vram += cs->used_vram;
1835 gtt += cs->used_gart;
1836
1837 /* Anything that goes above the VRAM size should go to GTT. */
1838 if (vram > screen->info.vram_size)
1839 gtt += vram - screen->info.vram_size;
1840
1841 /* Now we just need to check if we have enough GTT. */
1842 return gtt < screen->info.gart_size * 0.7;
1843 }
1844
1845 /**
1846 * Add a buffer to the buffer list for the given command stream (CS).
1847 *
1848 * All buffers used by a CS must be added to the list. This tells the kernel
1849 * driver which buffers are used by GPU commands. Other buffers can
1850 * be swapped out (not accessible) during execution.
1851 *
1852 * The buffer list becomes empty after every context flush and must be
1853 * rebuilt.
1854 */
1855 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1856 struct radeon_cmdbuf *cs,
1857 struct si_resource *bo,
1858 enum radeon_bo_usage usage,
1859 enum radeon_bo_priority priority)
1860 {
1861 assert(usage);
1862 sctx->ws->cs_add_buffer(
1863 cs, bo->buf,
1864 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1865 bo->domains, priority);
1866 }
1867
1868 /**
1869 * Same as above, but also checks memory usage and flushes the context
1870 * accordingly.
1871 *
1872 * When this SHOULD NOT be used:
1873 *
1874 * - if si_context_add_resource_size has been called for the buffer
1875 * followed by *_need_cs_space for checking the memory usage
1876 *
1877 * - if si_need_dma_space has been called for the buffer
1878 *
1879 * - when emitting state packets and draw packets (because preceding packets
1880 * can't be re-emitted at that point)
1881 *
1882 * - if shader resource "enabled_mask" is not up-to-date or there is
1883 * a different constraint disallowing a context flush
1884 */
1885 static inline void
1886 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1887 struct si_resource *bo,
1888 enum radeon_bo_usage usage,
1889 enum radeon_bo_priority priority,
1890 bool check_mem)
1891 {
1892 if (check_mem &&
1893 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1894 sctx->vram + bo->vram_usage,
1895 sctx->gtt + bo->gart_usage))
1896 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1897
1898 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1899 }
1900
1901 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1902 {
1903 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1904 }
1905
1906 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1907 enum pipe_shader_type shader_type,
1908 bool ngg, bool es)
1909 {
1910 if (shader_type == PIPE_SHADER_COMPUTE)
1911 return sscreen->compute_wave_size;
1912 else if (shader_type == PIPE_SHADER_FRAGMENT)
1913 return sscreen->ps_wave_size;
1914 else if ((shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1915 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1916 return 64;
1917 else
1918 return sscreen->ge_wave_size;
1919 }
1920
1921 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1922 {
1923 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1924 shader->key.as_ngg, shader->key.as_es);
1925 }
1926
1927 #define PRINT_ERR(fmt, args...) \
1928 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1929
1930 #endif