2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #if UTIL_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119 /* Set a micro tile mode: */
120 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
121 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
122 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) (((x) & 0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
123 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
127 DCC_CLEAR_COLOR_0000
= 0x00000000,
128 DCC_CLEAR_COLOR_0001
= 0x40404040,
129 DCC_CLEAR_COLOR_1110
= 0x80808080,
130 DCC_CLEAR_COLOR_1111
= 0xC0C0C0C0,
131 DCC_CLEAR_COLOR_REG
= 0x20202020,
132 DCC_UNCOMPRESSED
= 0xFFFFFFFF,
135 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
139 /* Shader logging options: */
140 DBG_VS
= PIPE_SHADER_VERTEX
,
141 DBG_PS
= PIPE_SHADER_FRAGMENT
,
142 DBG_GS
= PIPE_SHADER_GEOMETRY
,
143 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
144 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
145 DBG_CS
= PIPE_SHADER_COMPUTE
,
151 /* Shader compiler options the shader cache should be aware of: */
152 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
162 /* Shader compiler options (with no effect on the shader cache): */
164 DBG_MONOLITHIC_SHADERS
,
167 /* Information logging options: */
173 /* Driver options: */
177 DBG_NO_SDMA_COPY_IMAGE
,
183 /* 3D engine options: */
186 DBG_ALWAYS_NGG_CULLING
,
210 DBG_TEST_VMFAULT_SDMA
,
211 DBG_TEST_VMFAULT_SHADER
,
218 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
219 #define DBG(name) (1ull << DBG_##name)
221 enum si_cache_policy
{
223 L2_STREAM
, /* same as SLC=1 */
224 L2_LRU
, /* same as SLC=0 */
228 SI_COHERENCY_NONE
, /* no cache flushes needed */
230 SI_COHERENCY_CB_META
,
235 struct si_shader_context
;
237 struct u_suballocator
;
239 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
243 struct threaded_resource b
;
245 /* Winsys objects. */
246 struct pb_buffer
*buf
;
247 uint64_t gpu_address
;
248 /* Memory usage if the buffer placement is optimal. */
252 /* Resource properties. */
254 unsigned bo_alignment
;
255 enum radeon_bo_domain domains
;
256 enum radeon_bo_flag flags
;
257 unsigned bind_history
;
258 int max_forced_staging_uploads
;
260 /* The buffer range which is initialized (with a write transfer,
261 * streamout, DMA, or as a random access target). The rest of
262 * the buffer is considered invalid and can be mapped unsynchronized.
264 * This allows unsychronized mapping of a buffer range which hasn't
265 * been used yet. It's for applications which forget to use
266 * the unsynchronized map flag and expect the driver to figure it out.
268 struct util_range valid_buffer_range
;
270 /* For buffers only. This indicates that a write operation has been
271 * performed by TC L2, but the cache hasn't been flushed.
272 * Any hw block which doesn't use or bypasses TC L2 should check this
273 * flag and flush the cache before using the buffer.
275 * For example, TC L2 must be flushed if a buffer which has been
276 * modified by a shader store instruction is about to be used as
277 * an index buffer. The reason is that VGT DMA index fetching doesn't
282 /* Whether this resource is referenced by bindless handles. */
283 bool texture_handle_allocated
;
284 bool image_handle_allocated
;
286 /* Whether the resource has been exported via resource_get_handle. */
287 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
291 struct threaded_transfer b
;
292 struct si_resource
*staging
;
297 struct si_resource buffer
;
299 struct radeon_surf surface
;
300 struct si_texture
*flushed_depth_texture
;
302 /* One texture allocation can contain these buffers:
303 * - image (pixel data)
304 * - FMASK buffer (MSAA compression)
305 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
306 * - HTILE buffer (Z/S compression and fast Z/S clear)
307 * - DCC buffer (color compression and new fast color clear)
308 * - displayable DCC buffer (if the DCC buffer is not displayable)
309 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
311 uint64_t cmask_base_address_reg
;
312 struct si_resource
*cmask_buffer
;
313 unsigned cb_color_info
; /* fast clear enable bit */
314 unsigned color_clear_value
[2];
315 unsigned last_msaa_resolve_target_micro_mode
;
316 unsigned num_level0_transfers
;
317 unsigned plane_index
; /* other planes are different pipe_resources */
320 /* Depth buffer compression and fast clear. */
321 float depth_clear_value
;
322 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
323 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
324 enum pipe_format db_render_format
:16;
325 uint8_t stencil_clear_value
;
326 bool fmask_is_identity
:1;
327 bool tc_compatible_htile
:1;
328 bool htile_stencil_disabled
:1;
329 bool depth_cleared
:1; /* if it was cleared at least once */
330 bool stencil_cleared
:1; /* if it was cleared at least once */
331 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
333 bool db_compatible
:1;
337 /* We need to track DCC dirtiness, because st/dri usually calls
338 * flush_resource twice per frame (not a bug) and we don't wanna
339 * decompress DCC twice. Also, the dirty tracking must be done even
340 * if DCC isn't used, because it's required by the DCC usage analysis
341 * for a possible future enablement.
343 bool separate_dcc_dirty
:1;
344 bool displayable_dcc_dirty
:1;
346 /* Statistics gathering for the DCC enablement heuristic. */
347 bool dcc_gather_statistics
:1;
348 /* Counter that should be non-zero if the texture is bound to a
351 unsigned framebuffers_bound
;
352 /* Whether the texture is a displayable back buffer and needs DCC
353 * decompression, which is expensive. Therefore, it's enabled only
354 * if statistics suggest that it will pay off and it's allocated
355 * separately. It can't be bound as a sampler by apps. Limited to
356 * target == 2D and last_level == 0. If enabled, dcc_offset contains
357 * the absolute GPUVM address, not the relative one.
359 struct si_resource
*dcc_separate_buffer
;
360 /* When DCC is temporarily disabled, the separate buffer is here. */
361 struct si_resource
*last_dcc_separate_buffer
;
362 /* Estimate of how much this color buffer is written to in units of
363 * full-screen draws: ps_invocations / (width * height)
364 * Shader kills, late Z, and blending with trivial discards make it
365 * inaccurate (we need to count CB updates, not PS invocations).
367 unsigned ps_draw_ratio
;
368 /* The number of clears since the last DCC usage analysis. */
369 unsigned num_slow_clears
;
373 struct pipe_surface base
;
375 /* These can vary with block-compressed textures. */
379 bool color_initialized
:1;
380 bool depth_initialized
:1;
382 /* Misc. color flags. */
383 bool color_is_int8
:1;
384 bool color_is_int10
:1;
385 bool dcc_incompatible
:1;
387 /* Color registers. */
388 unsigned cb_color_info
;
389 unsigned cb_color_view
;
390 unsigned cb_color_attrib
;
391 unsigned cb_color_attrib2
; /* GFX9 and later */
392 unsigned cb_color_attrib3
; /* GFX10 and later */
393 unsigned cb_dcc_control
; /* GFX8 and later */
394 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
395 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
396 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
397 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
400 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
401 uint64_t db_stencil_base
;
402 uint64_t db_htile_data_base
;
403 unsigned db_depth_info
;
405 unsigned db_z_info2
; /* GFX9 only */
406 unsigned db_depth_view
;
407 unsigned db_depth_size
;
408 unsigned db_depth_slice
;
409 unsigned db_stencil_info
;
410 unsigned db_stencil_info2
; /* GFX9 only */
411 unsigned db_htile_surface
;
414 struct si_mmio_counter
{
419 union si_mmio_counters
{
421 /* For global GPU load including SDMA. */
422 struct si_mmio_counter gpu
;
425 struct si_mmio_counter spi
;
426 struct si_mmio_counter gui
;
427 struct si_mmio_counter ta
;
428 struct si_mmio_counter gds
;
429 struct si_mmio_counter vgt
;
430 struct si_mmio_counter ia
;
431 struct si_mmio_counter sx
;
432 struct si_mmio_counter wd
;
433 struct si_mmio_counter bci
;
434 struct si_mmio_counter sc
;
435 struct si_mmio_counter pa
;
436 struct si_mmio_counter db
;
437 struct si_mmio_counter cp
;
438 struct si_mmio_counter cb
;
441 struct si_mmio_counter sdma
;
444 struct si_mmio_counter pfp
;
445 struct si_mmio_counter meq
;
446 struct si_mmio_counter me
;
447 struct si_mmio_counter surf_sync
;
448 struct si_mmio_counter cp_dma
;
449 struct si_mmio_counter scratch_ram
;
454 struct si_memory_object
{
455 struct pipe_memory_object b
;
456 struct pb_buffer
*buf
;
460 /* Saved CS data for debugging features. */
461 struct radeon_saved_cs
{
465 struct radeon_bo_list_item
*bo_list
;
470 struct pipe_screen b
;
471 struct radeon_winsys
*ws
;
472 struct disk_cache
*disk_shader_cache
;
474 struct radeon_info info
;
475 uint64_t debug_flags
;
476 char renderer_string
[183];
478 void (*make_texture_descriptor
)(
479 struct si_screen
*screen
,
480 struct si_texture
*tex
,
482 enum pipe_texture_target target
,
483 enum pipe_format pipe_format
,
484 const unsigned char state_swizzle
[4],
485 unsigned first_level
, unsigned last_level
,
486 unsigned first_layer
, unsigned last_layer
,
487 unsigned width
, unsigned height
, unsigned depth
,
489 uint32_t *fmask_state
);
491 unsigned num_vbos_in_user_sgprs
;
492 unsigned pa_sc_raster_config
;
493 unsigned pa_sc_raster_config_1
;
494 unsigned se_tile_repeat
;
495 unsigned gs_table_depth
;
496 unsigned tess_offchip_block_dw_size
;
497 unsigned tess_offchip_ring_size
;
498 unsigned tess_factor_ring_size
;
499 unsigned vgt_hs_offchip_param
;
500 unsigned eqaa_force_coverage_samples
;
501 unsigned eqaa_force_z_samples
;
502 unsigned eqaa_force_color_samples
;
503 bool has_draw_indirect_multi
;
504 bool has_out_of_order_rast
;
505 bool assume_no_z_fights
;
506 bool commutative_blend_add
;
509 bool llvm_has_working_vgpr_indexing
;
511 bool use_ngg_culling
;
512 bool always_use_ngg_culling
;
513 bool use_ngg_streamout
;
516 #define OPT_BOOL(name, dflt, description) bool name:1;
517 #include "si_debug_options.h"
520 /* Whether shaders are monolithic (1-part) or separate (3-part). */
521 bool use_monolithic_shaders
;
523 bool dcc_msaa_allowed
;
525 struct slab_parent_pool pool_transfers
;
527 /* Texture filter settings. */
528 int force_aniso
; /* -1 = disabled */
530 /* Auxiliary context. Mainly used to initialize resources.
531 * It must be locked prior to using and flushed before unlocking. */
532 struct pipe_context
*aux_context
;
533 simple_mtx_t aux_context_lock
;
535 /* This must be in the screen, because UE4 uses one context for
536 * compilation and another one for rendering.
538 unsigned num_compilations
;
539 /* Along with ST_DEBUG=precompile, this should show if applications
540 * are loading shaders on demand. This is a monotonic counter.
542 unsigned num_shaders_created
;
543 unsigned num_shader_cache_hits
;
545 /* GPU load thread. */
546 simple_mtx_t gpu_load_mutex
;
547 thrd_t gpu_load_thread
;
548 union si_mmio_counters mmio_counters
;
549 volatile unsigned gpu_load_stop_thread
; /* bool */
551 /* Performance counters. */
552 struct si_perfcounters
*perfcounters
;
554 /* If pipe_screen wants to recompute and re-emit the framebuffer,
555 * sampler, and image states of all contexts, it should atomically
558 * Each context will compare this with its own last known value of
559 * the counter before drawing and re-emit the states accordingly.
561 unsigned dirty_tex_counter
;
562 unsigned dirty_buf_counter
;
564 /* Atomically increment this counter when an existing texture's
565 * metadata is enabled or disabled in a way that requires changing
566 * contexts' compressed texture binding masks.
568 unsigned compressed_colortex_counter
;
571 /* Context flags to set so that all writes from earlier jobs
572 * in the CP are seen by L2 clients.
576 /* Context flags to set so that all writes from earlier jobs
577 * that end in L2 are seen by CP.
582 simple_mtx_t shader_parts_mutex
;
583 struct si_shader_part
*vs_prologs
;
584 struct si_shader_part
*tcs_epilogs
;
585 struct si_shader_part
*gs_prologs
;
586 struct si_shader_part
*ps_prologs
;
587 struct si_shader_part
*ps_epilogs
;
589 /* Shader cache in memory.
591 * Design & limitations:
592 * - The shader cache is per screen (= per process), never saved to
593 * disk, and skips redundant shader compilations from NIR to bytecode.
594 * - It can only be used with one-variant-per-shader support, in which
595 * case only the main (typically middle) part of shaders is cached.
596 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
597 * variants of VS and TES are cached, so LS and ES aren't.
598 * - GS and CS aren't cached, but it's certainly possible to cache
601 simple_mtx_t shader_cache_mutex
;
602 struct hash_table
*shader_cache
;
604 /* Shader compiler queue for multithreaded compilation. */
605 struct util_queue shader_compiler_queue
;
606 /* Use at most 3 normal compiler threads on quadcore and better.
607 * Hyperthreaded CPUs report the number of threads, but we want
608 * the number of cores. We only need this many threads for shader-db. */
609 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
611 struct util_queue shader_compiler_queue_low_priority
;
612 /* Use at most 2 low priority threads on quadcore and better.
613 * We want to minimize the impact on multithreaded Mesa. */
614 struct ac_llvm_compiler compiler_lowp
[10];
616 unsigned compute_wave_size
;
617 unsigned ps_wave_size
;
618 unsigned ge_wave_size
;
621 struct si_blend_color
{
622 struct pipe_blend_color state
;
626 struct si_sampler_view
{
627 struct pipe_sampler_view base
;
628 /* [0..7] = image descriptor
629 * [4..7] = buffer descriptor */
631 uint32_t fmask_state
[8];
632 const struct legacy_surf_level
*base_level_info
;
635 bool is_stencil_sampler
;
637 bool dcc_incompatible
;
640 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
642 struct si_sampler_state
{
647 uint32_t integer_val
[4];
648 uint32_t upgraded_depth_val
[4];
651 struct si_cs_shader_state
{
652 struct si_compute
*program
;
653 struct si_compute
*emitted_program
;
660 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
661 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
663 /* The i-th bit is set if that element is enabled (non-NULL resource). */
664 unsigned enabled_mask
;
665 uint32_t needs_depth_decompress_mask
;
666 uint32_t needs_color_decompress_mask
;
670 struct pipe_image_view views
[SI_NUM_IMAGES
];
671 uint32_t needs_color_decompress_mask
;
672 unsigned enabled_mask
;
675 struct si_framebuffer
{
676 struct pipe_framebuffer_state state
;
677 unsigned colorbuf_enabled_4bit
;
678 unsigned spi_shader_col_format
;
679 unsigned spi_shader_col_format_alpha
;
680 unsigned spi_shader_col_format_blend
;
681 unsigned spi_shader_col_format_blend_alpha
;
682 ubyte nr_samples
:5; /* at most 16xAA */
683 ubyte log_samples
:3; /* at most 4 = 16xAA */
684 ubyte nr_color_samples
; /* at most 8xAA */
685 ubyte compressed_cb_mask
;
686 ubyte uncompressed_cb_mask
;
687 ubyte displayable_dcc_cb_mask
;
689 ubyte color_is_int10
;
691 ubyte dcc_overwrite_combiner_watermark
;
692 ubyte min_bytes_per_pixel
;
695 bool CB_has_shader_readable_metadata
;
696 bool DB_has_shader_readable_metadata
;
697 bool all_DCC_pipe_aligned
;
701 /* This is the list we want to support. */
702 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
703 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
704 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
707 struct si_signed_scissor
{
712 enum si_quant_mode quant_mode
;
715 struct si_viewports
{
716 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
717 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
721 struct si_clip_state
{
722 struct pipe_clip_state state
;
726 struct si_streamout_target
{
727 struct pipe_stream_output_target b
;
729 /* The buffer where BUFFER_FILLED_SIZE is stored. */
730 struct si_resource
*buf_filled_size
;
731 unsigned buf_filled_size_offset
;
732 bool buf_filled_size_valid
;
734 unsigned stride_in_dw
;
737 struct si_streamout
{
740 unsigned enabled_mask
;
741 unsigned num_targets
;
742 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
744 unsigned append_bitmask
;
747 /* External state which comes from the vertex shader,
748 * it must be set explicitly when binding a shader. */
749 uint16_t *stride_in_dw
;
750 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
752 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
753 unsigned hw_enabled_mask
;
755 /* The state of VGT_STRMOUT_(CONFIG|EN). */
756 bool streamout_enabled
;
757 bool prims_gen_query_enabled
;
758 int num_prims_gen_queries
;
761 /* A shader state consists of the shader selector, which is a constant state
762 * object shared by multiple contexts and shouldn't be modified, and
763 * the current shader variant selected for this context.
765 struct si_shader_ctx_state
{
766 struct si_shader_selector
*cso
;
767 struct si_shader
*current
;
770 #define SI_NUM_VGT_PARAM_KEY_BITS 12
771 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
773 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
774 * Some fields are set by state-change calls, most are set by draw_vbo.
776 union si_vgt_param_key
{
778 #if UTIL_ARCH_LITTLE_ENDIAN
780 unsigned uses_instancing
:1;
781 unsigned multi_instances_smaller_than_primgroup
:1;
782 unsigned primitive_restart
:1;
783 unsigned count_from_stream_output
:1;
784 unsigned line_stipple_enabled
:1;
785 unsigned uses_tess
:1;
786 unsigned tess_uses_prim_id
:1;
788 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
789 #else /* UTIL_ARCH_BIG_ENDIAN */
790 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
792 unsigned tess_uses_prim_id
:1;
793 unsigned uses_tess
:1;
794 unsigned line_stipple_enabled
:1;
795 unsigned count_from_stream_output
:1;
796 unsigned primitive_restart
:1;
797 unsigned multi_instances_smaller_than_primgroup
:1;
798 unsigned uses_instancing
:1;
805 #define SI_NUM_VGT_STAGES_KEY_BITS 5
806 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
808 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
809 * Some fields are set by state-change calls, most are set by draw_vbo.
811 union si_vgt_stages_key
{
813 #if UTIL_ARCH_LITTLE_ENDIAN
816 unsigned ngg_passthrough
:1;
817 unsigned ngg
:1; /* gfx10+ */
818 unsigned streamout
:1; /* only used with NGG */
819 unsigned _pad
:32 - SI_NUM_VGT_STAGES_KEY_BITS
;
820 #else /* UTIL_ARCH_BIG_ENDIAN */
821 unsigned _pad
:32 - SI_NUM_VGT_STAGES_KEY_BITS
;
822 unsigned streamout
:1;
824 unsigned ngg_passthrough
:1;
832 struct si_texture_handle
836 struct pipe_sampler_view
*view
;
837 struct si_sampler_state sstate
;
840 struct si_image_handle
844 struct pipe_image_view view
;
848 struct pipe_reference reference
;
849 struct si_context
*ctx
;
850 struct radeon_saved_cs gfx
;
851 struct radeon_saved_cs compute
;
852 struct si_resource
*trace_buf
;
855 unsigned gfx_last_dw
;
856 unsigned compute_last_dw
;
861 struct si_sdma_upload
{
862 struct si_resource
*dst
;
863 struct si_resource
*src
;
869 struct si_small_prim_cull_info
{
870 float scale
[2], translate
[2];
874 struct pipe_context b
; /* base class */
876 enum radeon_family family
;
877 enum chip_class chip_class
;
879 struct radeon_winsys
*ws
;
880 struct radeon_winsys_ctx
*ctx
;
881 struct radeon_cmdbuf
*gfx_cs
; /* compute IB if graphics is disabled */
882 struct radeon_cmdbuf
*sdma_cs
;
883 struct pipe_fence_handle
*last_gfx_fence
;
884 struct pipe_fence_handle
*last_sdma_fence
;
885 struct si_resource
*eop_bug_scratch
;
886 struct u_upload_mgr
*cached_gtt_allocator
;
887 struct threaded_context
*tc
;
888 struct u_suballocator
*allocator_zeroed_memory
;
889 struct slab_child_pool pool_transfers
;
890 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
891 struct pipe_device_reset_callback device_reset_callback
;
892 struct u_log_context
*log
;
893 void *query_result_shader
;
894 void *sh_query_result_shader
;
896 void (*emit_cache_flush
)(struct si_context
*ctx
);
898 struct blitter_context
*blitter
;
901 void *discard_rasterizer_state
;
902 void *custom_dsa_flush
;
903 void *custom_blend_resolve
;
904 void *custom_blend_fmask_decompress
;
905 void *custom_blend_eliminate_fastclear
;
906 void *custom_blend_dcc_decompress
;
908 void *vs_blit_pos_layered
;
910 void *vs_blit_color_layered
;
911 void *vs_blit_texcoord
;
912 void *cs_clear_buffer
;
913 void *cs_copy_buffer
;
915 void *cs_copy_image_1d_array
;
916 void *cs_clear_render_target
;
917 void *cs_clear_render_target_1d_array
;
918 void *cs_clear_12bytes_buffer
;
920 void *cs_fmask_expand
[3][2]; /* [log2(samples)-1][is_array] */
921 struct si_screen
*screen
;
922 struct pipe_debug_callback debug
;
923 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
924 struct si_shader_ctx_state fixed_func_tcs_shader
;
925 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
926 struct si_resource
*wait_mem_scratch
;
927 unsigned wait_mem_number
;
928 uint16_t prefetch_L2_mask
;
931 bool gfx_flush_in_progress
:1;
932 bool gfx_last_ib_is_busy
:1;
933 bool compute_is_busy
:1;
935 unsigned num_gfx_cs_flushes
;
936 unsigned initial_gfx_cs_size
;
937 unsigned last_dirty_tex_counter
;
938 unsigned last_dirty_buf_counter
;
939 unsigned last_compressed_colortex_counter
;
940 unsigned last_num_draw_calls
;
941 unsigned flags
; /* flush flags */
942 /* Current unaccounted memory usage. */
946 /* Compute-based primitive discard. */
947 unsigned prim_discard_vertex_count_threshold
;
948 struct pb_buffer
*gds
;
949 struct pb_buffer
*gds_oa
;
950 struct radeon_cmdbuf
*prim_discard_compute_cs
;
951 unsigned compute_gds_offset
;
952 struct si_shader
*compute_ib_last_shader
;
953 uint32_t compute_rewind_va
;
954 unsigned compute_num_prims_in_batch
;
955 bool preserve_prim_restart_gds_at_flush
;
956 /* index_ring is divided into 2 halves for doublebuffering. */
957 struct si_resource
*index_ring
;
958 unsigned index_ring_base
; /* offset of a per-IB portion */
959 unsigned index_ring_offset
; /* offset within a per-IB portion */
960 unsigned index_ring_size_per_ib
; /* max available size per IB */
961 bool prim_discard_compute_ib_initialized
;
962 /* For tracking the last execution barrier - it can be either
963 * a WRITE_DATA packet or a fence. */
964 uint32_t *last_pkt3_write_data
;
965 struct si_resource
*barrier_buf
;
966 unsigned barrier_buf_offset
;
967 struct pipe_fence_handle
*last_ib_barrier_fence
;
968 struct si_resource
*last_ib_barrier_buf
;
969 unsigned last_ib_barrier_buf_offset
;
971 /* Atoms (direct states). */
972 union si_state_atoms atoms
;
973 unsigned dirty_atoms
; /* mask */
974 /* PM4 states (precomputed immutable states) */
975 unsigned dirty_states
;
976 union si_state queued
;
977 union si_state emitted
;
979 /* Atom declarations. */
980 struct si_framebuffer framebuffer
;
981 unsigned sample_locs_num_samples
;
982 uint16_t sample_mask
;
983 unsigned last_cb_target_mask
;
984 struct si_blend_color blend_color
;
985 struct si_clip_state clip_state
;
986 struct si_shader_data shader_pointers
;
987 struct si_stencil_ref stencil_ref
;
988 struct pipe_scissor_state scissors
[SI_MAX_VIEWPORTS
];
989 struct si_streamout streamout
;
990 struct si_viewports viewports
;
991 unsigned num_window_rectangles
;
992 bool window_rectangles_include
;
993 struct pipe_scissor_state window_rectangles
[4];
995 /* Precomputed states. */
996 struct si_pm4_state
*init_config
;
997 struct si_pm4_state
*init_config_gs_rings
;
998 bool init_config_has_vgt_flush
;
999 struct si_pm4_state
*vgt_shader_config
[SI_NUM_VGT_STAGES_STATES
];
1002 struct si_shader_ctx_state ps_shader
;
1003 struct si_shader_ctx_state gs_shader
;
1004 struct si_shader_ctx_state vs_shader
;
1005 struct si_shader_ctx_state tcs_shader
;
1006 struct si_shader_ctx_state tes_shader
;
1007 struct si_shader_ctx_state cs_prim_discard_state
;
1008 struct si_cs_shader_state cs_shader_state
;
1010 /* shader information */
1011 struct si_vertex_elements
*vertex_elements
;
1012 unsigned num_vertex_elements
;
1013 unsigned sprite_coord_enable
;
1014 unsigned cs_max_waves_per_sh
;
1016 bool do_update_shaders
;
1018 /* shader descriptors */
1019 struct si_descriptors descriptors
[SI_NUM_DESCS
];
1020 unsigned descriptors_dirty
;
1021 unsigned shader_pointers_dirty
;
1022 unsigned shader_needs_decompress_mask
;
1023 struct si_buffer_resources rw_buffers
;
1024 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
1025 struct si_samplers samplers
[SI_NUM_SHADERS
];
1026 struct si_images images
[SI_NUM_SHADERS
];
1027 bool bo_list_add_all_resident_resources
;
1028 bool bo_list_add_all_gfx_resources
;
1029 bool bo_list_add_all_compute_resources
;
1031 /* other shader resources */
1032 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on GFX7 */
1033 struct pipe_resource
*esgs_ring
;
1034 struct pipe_resource
*gsvs_ring
;
1035 struct pipe_resource
*tess_rings
;
1036 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
1037 struct si_resource
*border_color_buffer
;
1038 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
1039 unsigned border_color_count
;
1040 unsigned num_vs_blit_sgprs
;
1041 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
1042 uint32_t cs_user_data
[4];
1044 /* Vertex buffers. */
1045 bool vertex_buffers_dirty
;
1046 bool vertex_buffer_pointer_dirty
;
1047 bool vertex_buffer_user_sgprs_dirty
;
1048 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
1049 uint16_t vertex_buffer_unaligned
; /* bitmask of not dword-aligned buffers */
1050 uint32_t *vb_descriptors_gpu_list
;
1051 struct si_resource
*vb_descriptors_buffer
;
1052 unsigned vb_descriptors_offset
;
1053 unsigned vb_descriptor_user_sgprs
[5*4];
1055 /* MSAA config state. */
1056 int ps_iter_samples
;
1057 bool ps_uses_fbfetch
;
1058 bool smoothing_enabled
;
1060 /* DB render state. */
1061 unsigned ps_db_shader_control
;
1062 unsigned dbcb_copy_sample
;
1063 bool dbcb_depth_copy_enabled
:1;
1064 bool dbcb_stencil_copy_enabled
:1;
1065 bool db_flush_depth_inplace
:1;
1066 bool db_flush_stencil_inplace
:1;
1067 bool db_depth_clear
:1;
1068 bool db_depth_disable_expclear
:1;
1069 bool db_stencil_clear
:1;
1070 bool db_stencil_disable_expclear
:1;
1071 bool occlusion_queries_disabled
:1;
1072 bool generate_mipmap_for_depth
:1;
1074 /* Emitted draw state. */
1075 bool gs_tri_strip_adj_fix
:1;
1077 bool prim_discard_cs_instancing
:1;
1079 uint8_t ngg_culling
;
1080 int last_index_size
;
1081 int last_base_vertex
;
1082 int last_start_instance
;
1083 int last_instance_count
;
1085 int last_sh_base_reg
;
1086 int last_primitive_restart_en
;
1087 int last_restart_index
;
1089 int last_multi_vgt_param
;
1090 int last_gs_out_prim
;
1091 int last_binning_enabled
;
1092 unsigned current_vs_state
;
1093 unsigned last_vs_state
;
1094 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
1096 struct si_small_prim_cull_info last_small_prim_cull_info
;
1097 struct si_resource
*small_prim_cull_info_buf
;
1098 uint64_t small_prim_cull_info_address
;
1099 bool small_prim_cull_info_dirty
;
1101 /* Scratch buffer */
1102 struct si_resource
*scratch_buffer
;
1103 unsigned scratch_waves
;
1104 unsigned spi_tmpring_size
;
1105 unsigned max_seen_scratch_bytes_per_wave
;
1106 unsigned max_seen_compute_scratch_bytes_per_wave
;
1108 struct si_resource
*compute_scratch_buffer
;
1110 /* Emitted derived tessellation state. */
1111 /* Local shader (VS), or HS if LS-HS are merged. */
1112 struct si_shader
*last_ls
;
1113 struct si_shader_selector
*last_tcs
;
1114 int last_num_tcs_input_cp
;
1115 int last_tes_sh_base
;
1116 bool last_tess_uses_primid
;
1117 unsigned last_num_patches
;
1118 int last_ls_hs_config
;
1122 struct si_saved_cs
*current_saved_cs
;
1123 uint64_t dmesg_timestamp
;
1124 unsigned apitrace_call_number
;
1127 bool need_check_render_feedback
;
1128 bool decompression_enabled
;
1129 bool dpbb_force_off
;
1130 bool vs_writes_viewport_index
;
1131 bool vs_disables_clipping_viewport
;
1133 /* Precomputed IA_MULTI_VGT_PARAM */
1134 union si_vgt_param_key ia_multi_vgt_param_key
;
1135 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
1137 /* Bindless descriptors. */
1138 struct si_descriptors bindless_descriptors
;
1139 struct util_idalloc bindless_used_slots
;
1140 unsigned num_bindless_descriptors
;
1141 bool bindless_descriptors_dirty
;
1142 bool graphics_bindless_pointer_dirty
;
1143 bool compute_bindless_pointer_dirty
;
1145 /* Allocated bindless handles */
1146 struct hash_table
*tex_handles
;
1147 struct hash_table
*img_handles
;
1149 /* Resident bindless handles */
1150 struct util_dynarray resident_tex_handles
;
1151 struct util_dynarray resident_img_handles
;
1153 /* Resident bindless handles which need decompression */
1154 struct util_dynarray resident_tex_needs_color_decompress
;
1155 struct util_dynarray resident_img_needs_color_decompress
;
1156 struct util_dynarray resident_tex_needs_depth_decompress
;
1158 /* Bindless state */
1159 bool uses_bindless_samplers
;
1160 bool uses_bindless_images
;
1162 /* MSAA sample locations.
1163 * The first index is the sample index.
1164 * The second index is the coordinate: X, Y. */
1172 struct pipe_resource
*sample_pos_buffer
;
1175 unsigned num_draw_calls
;
1176 unsigned num_decompress_calls
;
1177 unsigned num_mrt_draw_calls
;
1178 unsigned num_prim_restart_calls
;
1179 unsigned num_spill_draw_calls
;
1180 unsigned num_compute_calls
;
1181 unsigned num_spill_compute_calls
;
1182 unsigned num_dma_calls
;
1183 unsigned num_cp_dma_calls
;
1184 unsigned num_vs_flushes
;
1185 unsigned num_ps_flushes
;
1186 unsigned num_cs_flushes
;
1187 unsigned num_cb_cache_flushes
;
1188 unsigned num_db_cache_flushes
;
1189 unsigned num_L2_invalidates
;
1190 unsigned num_L2_writebacks
;
1191 unsigned num_resident_handles
;
1192 uint64_t num_alloc_tex_transfer_bytes
;
1193 unsigned last_tex_ps_draw_ratio
; /* for query */
1194 unsigned compute_num_verts_accepted
;
1195 unsigned compute_num_verts_rejected
;
1196 unsigned compute_num_verts_ineligible
; /* due to low vertex count */
1197 unsigned context_roll
;
1200 /* Maintain the list of active queries for pausing between IBs. */
1201 int num_occlusion_queries
;
1202 int num_perfect_occlusion_queries
;
1203 int num_pipeline_stat_queries
;
1204 struct list_head active_queries
;
1205 unsigned num_cs_dw_queries_suspend
;
1207 /* Render condition. */
1208 struct pipe_query
*render_cond
;
1209 unsigned render_cond_mode
;
1210 bool render_cond_invert
;
1211 bool render_cond_force_off
; /* for u_blitter */
1213 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1214 bool sdma_uploads_in_progress
;
1215 struct si_sdma_upload
*sdma_uploads
;
1216 unsigned num_sdma_uploads
;
1217 unsigned max_sdma_uploads
;
1219 /* Shader-based queries. */
1220 struct list_head shader_query_buffers
;
1221 unsigned num_active_shader_queries
;
1223 /* Statistics gathering for the DCC enablement heuristic. It can't be
1224 * in si_texture because si_texture can be shared by multiple
1225 * contexts. This is for back buffers only. We shouldn't get too many
1228 * X11 DRI3 rotates among a finite set of back buffers. They should
1229 * all fit in this array. If they don't, separate DCC might never be
1230 * enabled by DCC stat gathering.
1233 struct si_texture
*tex
;
1234 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1235 struct pipe_query
*ps_stats
[3];
1236 /* If all slots are used and another slot is needed,
1237 * the least recently used slot is evicted based on this. */
1238 int64_t last_use_timestamp
;
1242 /* Copy one resource to another using async DMA. */
1243 void (*dma_copy
)(struct pipe_context
*ctx
,
1244 struct pipe_resource
*dst
,
1246 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1247 struct pipe_resource
*src
,
1249 const struct pipe_box
*src_box
);
1251 struct si_tracked_regs tracked_regs
;
1255 void cik_init_sdma_functions(struct si_context
*sctx
);
1258 enum si_blitter_op
/* bitmask */
1260 SI_SAVE_TEXTURES
= 1,
1261 SI_SAVE_FRAMEBUFFER
= 2,
1262 SI_SAVE_FRAGMENT_STATE
= 4,
1263 SI_DISABLE_RENDER_COND
= 8,
1266 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1267 void si_blitter_end(struct si_context
*sctx
);
1268 void si_init_blit_functions(struct si_context
*sctx
);
1269 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1270 void si_decompress_subresource(struct pipe_context
*ctx
,
1271 struct pipe_resource
*tex
,
1272 unsigned planes
, unsigned level
,
1273 unsigned first_layer
, unsigned last_layer
);
1274 void si_resource_copy_region(struct pipe_context
*ctx
,
1275 struct pipe_resource
*dst
,
1277 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1278 struct pipe_resource
*src
,
1280 const struct pipe_box
*src_box
);
1281 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1284 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1285 struct pb_buffer
*buf
,
1286 enum radeon_bo_usage usage
);
1287 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1288 struct si_resource
*resource
,
1290 void si_init_resource_fields(struct si_screen
*sscreen
,
1291 struct si_resource
*res
,
1292 uint64_t size
, unsigned alignment
);
1293 bool si_alloc_resource(struct si_screen
*sscreen
,
1294 struct si_resource
*res
);
1295 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1296 unsigned flags
, unsigned usage
,
1297 unsigned size
, unsigned alignment
);
1298 struct si_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1299 unsigned flags
, unsigned usage
,
1300 unsigned size
, unsigned alignment
);
1301 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1302 struct pipe_resource
*dst
,
1303 struct pipe_resource
*src
);
1304 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1305 void si_init_buffer_functions(struct si_context
*sctx
);
1308 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1309 bool vi_alpha_is_on_msb(struct si_screen
*sscreen
, enum pipe_format format
);
1310 bool vi_dcc_clear_level(struct si_context
*sctx
,
1311 struct si_texture
*tex
,
1312 unsigned level
, unsigned clear_value
);
1313 void si_init_clear_functions(struct si_context
*sctx
);
1315 /* si_compute_blit.c */
1316 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1317 enum si_cache_policy cache_policy
);
1318 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1319 uint64_t offset
, uint64_t size
, uint32_t *clear_value
,
1320 uint32_t clear_value_size
, enum si_coherency coher
,
1322 void si_copy_buffer(struct si_context
*sctx
,
1323 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1324 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1325 void si_compute_copy_image(struct si_context
*sctx
,
1326 struct pipe_resource
*dst
,
1328 struct pipe_resource
*src
,
1330 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1331 const struct pipe_box
*src_box
);
1332 void si_compute_clear_render_target(struct pipe_context
*ctx
,
1333 struct pipe_surface
*dstsurf
,
1334 const union pipe_color_union
*color
,
1335 unsigned dstx
, unsigned dsty
,
1336 unsigned width
, unsigned height
,
1337 bool render_condition_enabled
);
1338 void si_retile_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1339 void si_compute_expand_fmask(struct pipe_context
*ctx
, struct pipe_resource
*tex
);
1340 void si_init_compute_blit_functions(struct si_context
*sctx
);
1343 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1344 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1345 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1346 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1347 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1348 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1349 SI_CPDMA_SKIP_SYNC_AFTER | \
1350 SI_CPDMA_SKIP_SYNC_BEFORE | \
1351 SI_CPDMA_SKIP_GFX_SYNC | \
1352 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1354 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1355 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1356 struct pipe_resource
*dst
, uint64_t offset
,
1357 uint64_t size
, unsigned value
, unsigned user_flags
,
1358 enum si_coherency coher
, enum si_cache_policy cache_policy
);
1359 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1360 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1361 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1362 unsigned user_flags
, enum si_coherency coher
,
1363 enum si_cache_policy cache_policy
);
1364 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1365 uint64_t offset
, unsigned size
);
1366 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1367 void si_test_gds(struct si_context
*sctx
);
1368 void si_cp_write_data(struct si_context
*sctx
, struct si_resource
*buf
,
1369 unsigned offset
, unsigned size
, unsigned dst_sel
,
1370 unsigned engine
, const void *data
);
1371 void si_cp_copy_data(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1372 unsigned dst_sel
, struct si_resource
*dst
, unsigned dst_offset
,
1373 unsigned src_sel
, struct si_resource
*src
, unsigned src_offset
);
1376 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1377 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1378 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1379 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1380 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1381 void si_log_hw_flush(struct si_context
*sctx
);
1382 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1383 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1384 void si_init_debug_functions(struct si_context
*sctx
);
1385 void si_check_vm_faults(struct si_context
*sctx
,
1386 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1387 bool si_replace_shader(unsigned num
, struct si_shader_binary
*binary
);
1390 void si_dma_emit_timestamp(struct si_context
*sctx
, struct si_resource
*dst
,
1392 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1393 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1394 void si_sdma_copy_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1395 struct pipe_resource
*src
, uint64_t dst_offset
,
1396 uint64_t src_offset
, uint64_t size
);
1397 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1398 struct si_resource
*dst
, struct si_resource
*src
);
1399 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1400 struct pipe_fence_handle
**fence
);
1401 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1402 uint64_t offset
, uint64_t size
, unsigned value
);
1405 void si_cp_release_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1406 unsigned event
, unsigned event_flags
,
1407 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1408 struct si_resource
*buf
, uint64_t va
,
1409 uint32_t new_fence
, unsigned query_type
);
1410 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1411 void si_cp_wait_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1412 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
);
1413 void si_init_fence_functions(struct si_context
*ctx
);
1414 void si_init_screen_fence_functions(struct si_screen
*screen
);
1415 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1416 struct tc_unflushed_batch_token
*tc_token
);
1419 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1422 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1423 struct pipe_fence_handle
**fence
);
1424 void si_allocate_gds(struct si_context
*ctx
);
1425 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1426 void si_need_gfx_cs_space(struct si_context
*ctx
);
1427 void si_unref_sdma_uploads(struct si_context
*sctx
);
1430 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1431 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1432 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1436 void si_emit_initial_compute_regs(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
);
1437 void si_init_compute_functions(struct si_context
*sctx
);
1439 /* si_compute_prim_discard.c */
1440 enum si_prim_discard_outcome
{
1441 SI_PRIM_DISCARD_ENABLED
,
1442 SI_PRIM_DISCARD_DISABLED
,
1443 SI_PRIM_DISCARD_DRAW_SPLIT
,
1446 void si_build_prim_discard_compute_shader(struct si_shader_context
*ctx
);
1447 enum si_prim_discard_outcome
1448 si_prepare_prim_discard_or_split_draw(struct si_context
*sctx
,
1449 const struct pipe_draw_info
*info
,
1450 bool primitive_restart
);
1451 void si_compute_signal_gfx(struct si_context
*sctx
);
1452 void si_dispatch_prim_discard_cs_and_draw(struct si_context
*sctx
,
1453 const struct pipe_draw_info
*info
,
1454 unsigned index_size
,
1455 unsigned base_vertex
,
1456 uint64_t input_indexbuf_va
,
1457 unsigned input_indexbuf_max_elements
);
1458 void si_initialize_prim_discard_tunables(struct si_screen
*sscreen
,
1459 bool is_aux_context
,
1460 unsigned *prim_discard_vertex_count_threshold
,
1461 unsigned *index_ring_size_per_ib
);
1464 void si_init_compiler(struct si_screen
*sscreen
, struct ac_llvm_compiler
*compiler
);
1466 /* si_perfcounters.c */
1467 void si_init_perfcounters(struct si_screen
*screen
);
1468 void si_destroy_perfcounters(struct si_screen
*screen
);
1471 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1472 void si_init_query_functions(struct si_context
*sctx
);
1473 void si_suspend_queries(struct si_context
*sctx
);
1474 void si_resume_queries(struct si_context
*sctx
);
1476 /* si_shaderlib_tgsi.c */
1477 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1478 unsigned num_layers
);
1479 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1480 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1481 unsigned num_dwords_per_thread
,
1482 bool dst_stream_cache_policy
, bool is_copy
);
1483 void *si_create_copy_image_compute_shader(struct pipe_context
*ctx
);
1484 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context
*ctx
);
1485 void *si_clear_render_target_shader(struct pipe_context
*ctx
);
1486 void *si_clear_render_target_shader_1d_array(struct pipe_context
*ctx
);
1487 void *si_clear_12bytes_buffer_shader(struct pipe_context
*ctx
);
1488 void *si_create_dcc_retile_cs(struct pipe_context
*ctx
);
1489 void *si_create_fmask_expand_cs(struct pipe_context
*ctx
, unsigned num_samples
,
1491 void *si_create_query_result_cs(struct si_context
*sctx
);
1492 void *gfx10_create_sh_query_result_cs(struct si_context
*sctx
);
1495 void gfx10_init_query(struct si_context
*sctx
);
1496 void gfx10_destroy_query(struct si_context
*sctx
);
1499 void si_test_dma(struct si_screen
*sscreen
);
1501 /* si_test_clearbuffer.c */
1502 void si_test_dma_perf(struct si_screen
*sscreen
);
1505 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1506 const struct pipe_video_codec
*templ
);
1508 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1509 const struct pipe_video_buffer
*tmpl
);
1512 void si_update_ngg_small_prim_precision(struct si_context
*ctx
);
1513 void si_get_small_prim_cull_info(struct si_context
*sctx
,
1514 struct si_small_prim_cull_info
*out
);
1515 void si_update_vs_viewport_state(struct si_context
*ctx
);
1516 void si_init_viewport_functions(struct si_context
*ctx
);
1519 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1520 struct si_texture
*dst
,
1521 unsigned dst_level
, unsigned dstx
,
1522 unsigned dsty
, unsigned dstz
,
1523 struct si_texture
*src
,
1525 const struct pipe_box
*src_box
);
1526 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1527 struct si_texture
*tex
);
1528 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1529 struct si_texture
*tex
);
1530 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1531 struct pipe_resource
*texture
);
1532 void si_print_texture_info(struct si_screen
*sscreen
,
1533 struct si_texture
*tex
, struct u_log_context
*log
);
1534 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1535 const struct pipe_resource
*templ
);
1536 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
,
1537 enum pipe_format format1
,
1538 enum pipe_format format2
);
1539 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1541 enum pipe_format view_format
);
1542 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1543 struct pipe_resource
*tex
,
1545 enum pipe_format view_format
);
1546 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1547 struct pipe_resource
*texture
,
1548 const struct pipe_surface
*templ
,
1549 unsigned width0
, unsigned height0
,
1550 unsigned width
, unsigned height
);
1551 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1552 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1553 struct si_texture
*tex
);
1554 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1555 struct si_texture
*tex
);
1556 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1557 struct si_texture
*tex
);
1558 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1559 struct si_texture
*tex
);
1560 bool si_texture_disable_dcc(struct si_context
*sctx
,
1561 struct si_texture
*tex
);
1562 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1563 void si_init_context_texture_functions(struct si_context
*sctx
);
1570 static inline struct si_resource
*si_resource(struct pipe_resource
*r
)
1572 return (struct si_resource
*)r
;
1576 si_resource_reference(struct si_resource
**ptr
, struct si_resource
*res
)
1578 pipe_resource_reference((struct pipe_resource
**)ptr
,
1579 (struct pipe_resource
*)res
);
1583 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1585 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1589 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1591 return tex
->surface
.dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1594 static inline unsigned
1595 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1598 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1600 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1603 static inline unsigned
1604 si_get_minimum_num_gfx_cs_dwords(struct si_context
*sctx
)
1606 /* Don't count the needed CS space exactly and just use an upper bound.
1608 * Also reserve space for stopping queries at the end of IB, because
1609 * the number of active queries is unlimited in theory.
1611 return 2048 + sctx
->num_cs_dw_queries_suspend
;
1615 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1618 /* Add memory usage for need_gfx_cs_space */
1619 sctx
->vram
+= si_resource(r
)->vram_usage
;
1620 sctx
->gtt
+= si_resource(r
)->gart_usage
;
1625 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1627 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1628 sctx
->last_instance_count
= SI_INSTANCE_COUNT_UNKNOWN
;
1631 static inline unsigned
1632 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1634 return 1 << (atom
- sctx
->atoms
.array
);
1638 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1640 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1643 sctx
->dirty_atoms
|= bit
;
1645 sctx
->dirty_atoms
&= ~bit
;
1649 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1651 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1655 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1657 si_set_atom_dirty(sctx
, atom
, true);
1660 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1662 if (sctx
->gs_shader
.cso
)
1663 return &sctx
->gs_shader
;
1664 if (sctx
->tes_shader
.cso
)
1665 return &sctx
->tes_shader
;
1667 return &sctx
->vs_shader
;
1670 static inline struct si_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1672 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1674 return vs
->cso
? &vs
->cso
->info
: NULL
;
1677 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1679 if (sctx
->gs_shader
.cso
&&
1680 sctx
->gs_shader
.current
&&
1681 !sctx
->gs_shader
.current
->key
.as_ngg
)
1682 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1684 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1685 return vs
->current
? vs
->current
: NULL
;
1688 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1691 return sscreen
->debug_flags
& (1 << processor
);
1694 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1696 return sctx
->streamout
.streamout_enabled
||
1697 sctx
->streamout
.prims_gen_query_enabled
;
1700 static inline unsigned
1701 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1703 unsigned alignment
, tcc_cache_line_size
;
1705 /* If the upload size is less than the cache line size (e.g. 16, 32),
1706 * the whole thing will fit into a cache line if we align it to its size.
1707 * The idea is that multiple small uploads can share a cache line.
1708 * If the upload size is greater, align it to the cache line size.
1710 alignment
= util_next_power_of_two(upload_size
);
1711 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1712 return MIN2(alignment
, tcc_cache_line_size
);
1716 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1718 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1719 si_destroy_saved_cs(*dst
);
1725 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1726 bool shaders_read_metadata
, bool dcc_pipe_aligned
)
1728 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1729 SI_CONTEXT_INV_VCACHE
;
1731 if (sctx
->chip_class
>= GFX10
) {
1732 if (sctx
->screen
->info
.tcc_harvested
)
1733 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1734 else if (shaders_read_metadata
)
1735 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1736 } else if (sctx
->chip_class
== GFX9
) {
1737 /* Single-sample color is coherent with shaders on GFX9, but
1738 * L2 metadata must be flushed if shaders read metadata.
1741 if (num_samples
>= 2 ||
1742 (shaders_read_metadata
&& !dcc_pipe_aligned
))
1743 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1744 else if (shaders_read_metadata
)
1745 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1748 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1753 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1754 bool include_stencil
, bool shaders_read_metadata
)
1756 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1757 SI_CONTEXT_INV_VCACHE
;
1759 if (sctx
->chip_class
>= GFX10
) {
1760 if (sctx
->screen
->info
.tcc_harvested
)
1761 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1762 else if (shaders_read_metadata
)
1763 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1764 } else if (sctx
->chip_class
== GFX9
) {
1765 /* Single-sample depth (not stencil) is coherent with shaders
1766 * on GFX9, but L2 metadata must be flushed if shaders read
1769 if (num_samples
>= 2 || include_stencil
)
1770 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1771 else if (shaders_read_metadata
)
1772 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1775 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1780 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1782 return (stencil_sampler
&& tex
->can_sample_s
) ||
1783 (!stencil_sampler
&& tex
->can_sample_z
);
1787 si_htile_enabled(struct si_texture
*tex
, unsigned level
, unsigned zs_mask
)
1789 if (zs_mask
== PIPE_MASK_S
&& tex
->htile_stencil_disabled
)
1792 return tex
->surface
.htile_offset
&& level
== 0;
1796 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
, unsigned zs_mask
)
1798 assert(!tex
->tc_compatible_htile
|| tex
->surface
.htile_offset
);
1799 return tex
->tc_compatible_htile
&& si_htile_enabled(tex
, level
, zs_mask
);
1802 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1804 if (sctx
->ps_uses_fbfetch
)
1805 return sctx
->framebuffer
.nr_color_samples
;
1807 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1810 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1812 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1815 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1819 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1820 sctx
->queued
.named
.blend
->cb_target_mask
;
1822 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1823 colormask
&= ps
->colors_written_4bit
;
1824 else if (!ps
->colors_written_4bit
)
1825 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1830 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1831 (1 << PIPE_PRIM_LINE_LOOP) | \
1832 (1 << PIPE_PRIM_LINE_STRIP) | \
1833 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1834 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1836 static inline bool util_prim_is_lines(unsigned prim
)
1838 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1841 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1843 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1844 (1 << PIPE_PRIM_POINTS
))) != 0;
1847 static inline bool util_rast_prim_is_triangles(unsigned prim
)
1849 return ((1 << prim
) & ((1 << PIPE_PRIM_TRIANGLES
) |
1850 (1 << PIPE_PRIM_TRIANGLE_STRIP
) |
1851 (1 << PIPE_PRIM_TRIANGLE_FAN
) |
1852 (1 << PIPE_PRIM_QUADS
) |
1853 (1 << PIPE_PRIM_QUAD_STRIP
) |
1854 (1 << PIPE_PRIM_POLYGON
) |
1855 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY
) |
1856 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
)));
1860 * Return true if there is enough memory in VRAM and GTT for the buffers
1863 * \param vram VRAM memory size not added to the buffer list yet
1864 * \param gtt GTT memory size not added to the buffer list yet
1867 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1868 struct radeon_cmdbuf
*cs
,
1869 uint64_t vram
, uint64_t gtt
)
1871 vram
+= cs
->used_vram
;
1872 gtt
+= cs
->used_gart
;
1874 /* Anything that goes above the VRAM size should go to GTT. */
1875 if (vram
> screen
->info
.vram_size
)
1876 gtt
+= vram
- screen
->info
.vram_size
;
1878 /* Now we just need to check if we have enough GTT. */
1879 return gtt
< screen
->info
.gart_size
* 0.7;
1883 * Add a buffer to the buffer list for the given command stream (CS).
1885 * All buffers used by a CS must be added to the list. This tells the kernel
1886 * driver which buffers are used by GPU commands. Other buffers can
1887 * be swapped out (not accessible) during execution.
1889 * The buffer list becomes empty after every context flush and must be
1892 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1893 struct radeon_cmdbuf
*cs
,
1894 struct si_resource
*bo
,
1895 enum radeon_bo_usage usage
,
1896 enum radeon_bo_priority priority
)
1899 sctx
->ws
->cs_add_buffer(
1901 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1902 bo
->domains
, priority
);
1906 * Same as above, but also checks memory usage and flushes the context
1909 * When this SHOULD NOT be used:
1911 * - if si_context_add_resource_size has been called for the buffer
1912 * followed by *_need_cs_space for checking the memory usage
1914 * - if si_need_dma_space has been called for the buffer
1916 * - when emitting state packets and draw packets (because preceding packets
1917 * can't be re-emitted at that point)
1919 * - if shader resource "enabled_mask" is not up-to-date or there is
1920 * a different constraint disallowing a context flush
1923 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1924 struct si_resource
*bo
,
1925 enum radeon_bo_usage usage
,
1926 enum radeon_bo_priority priority
,
1930 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1931 sctx
->vram
+ bo
->vram_usage
,
1932 sctx
->gtt
+ bo
->gart_usage
))
1933 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1935 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, bo
, usage
, priority
);
1938 static inline bool si_compute_prim_discard_enabled(struct si_context
*sctx
)
1940 return sctx
->prim_discard_vertex_count_threshold
!= UINT_MAX
;
1943 static inline unsigned si_get_wave_size(struct si_screen
*sscreen
,
1944 enum pipe_shader_type shader_type
,
1947 if (shader_type
== PIPE_SHADER_COMPUTE
)
1948 return sscreen
->compute_wave_size
;
1949 else if (shader_type
== PIPE_SHADER_FRAGMENT
)
1950 return sscreen
->ps_wave_size
;
1951 else if ((shader_type
== PIPE_SHADER_VERTEX
&& es
&& !ngg
) ||
1952 (shader_type
== PIPE_SHADER_TESS_EVAL
&& es
&& !ngg
) ||
1953 (shader_type
== PIPE_SHADER_GEOMETRY
&& !ngg
)) /* legacy GS only supports Wave64 */
1956 return sscreen
->ge_wave_size
;
1959 static inline unsigned si_get_shader_wave_size(struct si_shader
*shader
)
1961 return si_get_wave_size(shader
->selector
->screen
, shader
->selector
->type
,
1962 shader
->key
.as_ngg
, shader
->key
.as_es
);
1965 #define PRINT_ERR(fmt, args...) \
1966 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)