a7d57258591f1cf2f75ff0564804200ff8542224
[mesa.git] / src / gallium / drivers / radeonsi / si_pm4.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27 #include "util/u_memory.h"
28
29 static void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
30 {
31 assert(state->ndw < SI_PM4_MAX_DW);
32 state->last_opcode = opcode;
33 state->last_pm4 = state->ndw++;
34 }
35
36 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
37 {
38 assert(state->ndw < SI_PM4_MAX_DW);
39 state->pm4[state->ndw++] = dw;
40 }
41
42 static void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
43 {
44 unsigned count;
45 count = state->ndw - state->last_pm4 - 2;
46 state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate);
47 }
48
49 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
50 {
51 unsigned opcode;
52
53 if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
54 opcode = PKT3_SET_CONFIG_REG;
55 reg -= SI_CONFIG_REG_OFFSET;
56
57 } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
58 opcode = PKT3_SET_SH_REG;
59 reg -= SI_SH_REG_OFFSET;
60
61 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
62 opcode = PKT3_SET_CONTEXT_REG;
63 reg -= SI_CONTEXT_REG_OFFSET;
64
65 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
66 opcode = PKT3_SET_UCONFIG_REG;
67 reg -= CIK_UCONFIG_REG_OFFSET;
68
69 } else {
70 PRINT_ERR("Invalid register offset %08x!\n", reg);
71 return;
72 }
73
74 reg >>= 2;
75
76 if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
77 si_pm4_cmd_begin(state, opcode);
78 si_pm4_cmd_add(state, reg);
79 }
80
81 state->last_reg = reg;
82 si_pm4_cmd_add(state, val);
83 si_pm4_cmd_end(state, false);
84 }
85
86 void si_pm4_clear_state(struct si_pm4_state *state)
87 {
88 state->ndw = 0;
89 }
90
91 void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx)
92 {
93 if (!state)
94 return;
95
96 if (idx != ~0 && sctx->emitted.array[idx] == state) {
97 sctx->emitted.array[idx] = NULL;
98 }
99
100 si_pm4_clear_state(state);
101 FREE(state);
102 }
103
104 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
105 {
106 struct radeon_cmdbuf *cs = sctx->gfx_cs;
107
108 if (state->shader) {
109 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->shader->bo,
110 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
111 }
112
113 radeon_emit_array(cs, state->pm4, state->ndw);
114
115 if (state->atom.emit)
116 state->atom.emit(sctx);
117 }
118
119 void si_pm4_reset_emitted(struct si_context *sctx)
120 {
121 memset(&sctx->emitted, 0, sizeof(sctx->emitted));
122 sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
123 }