src/gallium/drivers/radeonsi/si_pm4.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "si_build_pm4.h"
  27 #include "sid.h"
  28 #include "util/u_memory.h"
  29
  30 static void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
  31 {
  32    assert(state->ndw < SI_PM4_MAX_DW);
  33    state->last_opcode = opcode;
  34    state->last_pm4 = state->ndw++;
  35 }
  36
  37 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
  38 {
  39    assert(state->ndw < SI_PM4_MAX_DW);
  40    state->pm4[state->ndw++] = dw;
  41 }
  42
  43 static void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
  44 {
  45    unsigned count;
  46    count = state->ndw - state->last_pm4 - 2;
  47    state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate);
  48 }
  49
  50 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
  51 {
  52    unsigned opcode;
  53
  54    SI_CHECK_SHADOWED_REGS(reg, 1);
  55
  56    if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
  57       opcode = PKT3_SET_CONFIG_REG;
  58       reg -= SI_CONFIG_REG_OFFSET;
  59
  60    } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
  61       opcode = PKT3_SET_SH_REG;
  62       reg -= SI_SH_REG_OFFSET;
  63
  64    } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
  65       opcode = PKT3_SET_CONTEXT_REG;
  66       reg -= SI_CONTEXT_REG_OFFSET;
  67
  68    } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
  69       opcode = PKT3_SET_UCONFIG_REG;
  70       reg -= CIK_UCONFIG_REG_OFFSET;
  71
  72    } else {
  73       PRINT_ERR("Invalid register offset %08x!\n", reg);
  74       return;
  75    }
  76
  77    reg >>= 2;
  78
  79    if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
  80       si_pm4_cmd_begin(state, opcode);
  81       si_pm4_cmd_add(state, reg);
  82    }
  83
  84    state->last_reg = reg;
  85    si_pm4_cmd_add(state, val);
  86    si_pm4_cmd_end(state, false);
  87 }
  88
  89 void si_pm4_clear_state(struct si_pm4_state *state)
  90 {
  91    state->ndw = 0;
  92 }
  93
  94 void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx)
  95 {
  96    if (!state)
  97       return;
  98
  99    if (idx != ~0 && sctx->emitted.array[idx] == state) {
 100       sctx->emitted.array[idx] = NULL;
 101    }
 102
 103    si_pm4_clear_state(state);
 104    FREE(state);
 105 }
 106
 107 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 108 {
 109    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 110
 111    if (state->shader) {
 112       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->shader->bo,
 113                                 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 114    }
 115
 116    radeon_emit_array(cs, state->pm4, state->ndw);
 117
 118    if (state->atom.emit)
 119       state->atom.emit(sctx);
 120 }
 121
 122 void si_pm4_reset_emitted(struct si_context *sctx, bool first_cs)
 123 {
 124    if (!first_cs && sctx->shadowed_regs) {
 125       /* Only dirty states that contain buffers, so that they are
 126        * added to the buffer list on the next draw call.
 127        */
 128       for (unsigned i = 0; i < SI_NUM_STATES; i++) {
 129          struct si_pm4_state *state = sctx->emitted.array[i];
 130
 131          if (state && state->shader) {
 132             sctx->emitted.array[i] = NULL;
 133             sctx->dirty_states |= 1 << i;
 134          }
 135       }
 136       return;
 137    }
 138
 139    memset(&sctx->emitted, 0, sizeof(sctx->emitted));
 140    sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
 141 }