src/gallium/drivers/radeonsi/si_pm4.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef SI_PM4_H
  26 #define SI_PM4_H
  27
  28 #include "radeon/radeon_winsys.h"
  29
  30 #define SI_PM4_MAX_DW 176
  31 #define SI_PM4_MAX_BO 3
  32
  33 // forward defines
  34 struct si_context;
  35
  36 /* State atoms are callbacks which write a sequence of packets into a GPU
  37  * command buffer (AKA indirect buffer, AKA IB, AKA command stream, AKA CS).
  38  */
  39 struct si_atom {
  40    void (*emit)(struct si_context *ctx);
  41 };
  42
  43 struct si_pm4_state {
  44    /* optional indirect buffer */
  45    struct si_resource *indirect_buffer;
  46
  47    /* PKT3_SET_*_REG handling */
  48    unsigned last_opcode;
  49    unsigned last_reg;
  50    unsigned last_pm4;
  51
  52    /* commands for the DE */
  53    unsigned ndw;
  54    uint32_t pm4[SI_PM4_MAX_DW];
  55
  56    /* BO's referenced by this state */
  57    unsigned nbo;
  58    struct si_resource *bo[SI_PM4_MAX_BO];
  59    enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
  60    enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
  61
  62    /* For shader states only */
  63    struct si_shader *shader;
  64    struct si_atom atom;
  65 };
  66
  67 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
  68 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
  69 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
  70
  71 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
  72 void si_pm4_add_bo(struct si_pm4_state *state, struct si_resource *bo, enum radeon_bo_usage usage,
  73                    enum radeon_bo_priority priority);
  74 void si_pm4_upload_indirect_buffer(struct si_context *sctx, struct si_pm4_state *state);
  75
  76 void si_pm4_clear_state(struct si_pm4_state *state);
  77 void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx);
  78
  79 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
  80 void si_pm4_reset_emitted(struct si_context *sctx);
  81
  82 #endif