2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_from_mesa.h"
33 #include "ac_binary.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
37 #include "ac_llvm_util.h"
38 #include "si_shader_internal.h"
42 #include "compiler/nir/nir.h"
44 static const char scratch_rsrc_dword0_symbol
[] =
45 "SCRATCH_RSRC_DWORD0";
47 static const char scratch_rsrc_dword1_symbol
[] =
48 "SCRATCH_RSRC_DWORD1";
50 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
51 struct si_screen
*sscreen
,
52 struct ac_llvm_compiler
*compiler
,
55 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
56 struct lp_build_tgsi_context
*bld_base
,
57 struct lp_build_emit_data
*emit_data
);
59 static void si_dump_shader_key(const struct si_shader
*shader
, FILE *f
);
61 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
62 union si_shader_part_key
*key
);
63 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
64 union si_shader_part_key
*key
);
65 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
66 union si_shader_part_key
*key
);
67 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
68 union si_shader_part_key
*key
);
69 static void si_fix_resource_usage(struct si_screen
*sscreen
,
70 struct si_shader
*shader
);
72 /* Ideally pass the sample mask input to the PS epilog as v14, which
73 * is its usual location, so that the shader doesn't have to add v_mov.
75 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
77 static bool llvm_type_is_64bit(struct si_shader_context
*ctx
,
80 if (type
== ctx
->ac
.i64
|| type
== ctx
->ac
.f64
)
86 /** Whether the shader runs as a combination of multiple API shaders */
87 static bool is_multi_part_shader(struct si_shader_context
*ctx
)
89 if (ctx
->screen
->info
.chip_class
<= GFX8
)
92 return ctx
->shader
->key
.as_ls
||
93 ctx
->shader
->key
.as_es
||
94 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
95 ctx
->type
== PIPE_SHADER_GEOMETRY
;
98 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
99 static bool is_merged_shader(struct si_shader_context
*ctx
)
101 return ctx
->shader
->key
.as_ngg
|| is_multi_part_shader(ctx
);
104 void si_init_function_info(struct si_function_info
*fninfo
)
106 fninfo
->num_params
= 0;
107 fninfo
->num_sgpr_params
= 0;
110 unsigned add_arg_assign(struct si_function_info
*fninfo
,
111 enum si_arg_regfile regfile
, LLVMTypeRef type
,
112 LLVMValueRef
*assign
)
114 assert(regfile
!= ARG_SGPR
|| fninfo
->num_sgpr_params
== fninfo
->num_params
);
116 unsigned idx
= fninfo
->num_params
++;
117 assert(idx
< ARRAY_SIZE(fninfo
->types
));
119 if (regfile
== ARG_SGPR
)
120 fninfo
->num_sgpr_params
= fninfo
->num_params
;
122 fninfo
->types
[idx
] = type
;
123 fninfo
->assign
[idx
] = assign
;
127 static unsigned add_arg(struct si_function_info
*fninfo
,
128 enum si_arg_regfile regfile
, LLVMTypeRef type
)
130 return add_arg_assign(fninfo
, regfile
, type
, NULL
);
133 static void add_arg_assign_checked(struct si_function_info
*fninfo
,
134 enum si_arg_regfile regfile
, LLVMTypeRef type
,
135 LLVMValueRef
*assign
, unsigned idx
)
137 ASSERTED
unsigned actual
= add_arg_assign(fninfo
, regfile
, type
, assign
);
138 assert(actual
== idx
);
141 static void add_arg_checked(struct si_function_info
*fninfo
,
142 enum si_arg_regfile regfile
, LLVMTypeRef type
,
145 add_arg_assign_checked(fninfo
, regfile
, type
, NULL
, idx
);
149 * Returns a unique index for a per-patch semantic name and index. The index
150 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
153 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name
, unsigned index
)
155 switch (semantic_name
) {
156 case TGSI_SEMANTIC_TESSOUTER
:
158 case TGSI_SEMANTIC_TESSINNER
:
160 case TGSI_SEMANTIC_PATCH
:
165 assert(!"invalid semantic name");
171 * Returns a unique index for a semantic name and index. The index must be
172 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
175 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
,
178 switch (semantic_name
) {
179 case TGSI_SEMANTIC_POSITION
:
181 case TGSI_SEMANTIC_GENERIC
:
182 /* Since some shader stages use the the highest used IO index
183 * to determine the size to allocate for inputs/outputs
184 * (in LDS, tess and GS rings). GENERIC should be placed right
185 * after POSITION to make that size as small as possible.
187 if (index
< SI_MAX_IO_GENERIC
)
190 assert(!"invalid generic index");
192 case TGSI_SEMANTIC_FOG
:
193 return SI_MAX_IO_GENERIC
+ 1;
194 case TGSI_SEMANTIC_COLOR
:
196 return SI_MAX_IO_GENERIC
+ 2 + index
;
197 case TGSI_SEMANTIC_BCOLOR
:
199 /* If it's a varying, COLOR and BCOLOR alias. */
201 return SI_MAX_IO_GENERIC
+ 2 + index
;
203 return SI_MAX_IO_GENERIC
+ 4 + index
;
204 case TGSI_SEMANTIC_TEXCOORD
:
206 return SI_MAX_IO_GENERIC
+ 6 + index
;
208 /* These are rarely used between LS and HS or ES and GS. */
209 case TGSI_SEMANTIC_CLIPDIST
:
211 return SI_MAX_IO_GENERIC
+ 6 + 8 + index
;
212 case TGSI_SEMANTIC_CLIPVERTEX
:
213 return SI_MAX_IO_GENERIC
+ 6 + 8 + 2;
214 case TGSI_SEMANTIC_PSIZE
:
215 return SI_MAX_IO_GENERIC
+ 6 + 8 + 3;
217 /* These can't be written by LS, HS, and ES. */
218 case TGSI_SEMANTIC_LAYER
:
219 return SI_MAX_IO_GENERIC
+ 6 + 8 + 4;
220 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
221 return SI_MAX_IO_GENERIC
+ 6 + 8 + 5;
222 case TGSI_SEMANTIC_PRIMID
:
223 STATIC_ASSERT(SI_MAX_IO_GENERIC
+ 6 + 8 + 6 <= 63);
224 return SI_MAX_IO_GENERIC
+ 6 + 8 + 6;
226 fprintf(stderr
, "invalid semantic name = %u\n", semantic_name
);
227 assert(!"invalid semantic name");
233 * Get the value of a shader input parameter and extract a bitfield.
235 static LLVMValueRef
unpack_llvm_param(struct si_shader_context
*ctx
,
236 LLVMValueRef value
, unsigned rshift
,
239 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
240 value
= ac_to_integer(&ctx
->ac
, value
);
243 value
= LLVMBuildLShr(ctx
->ac
.builder
, value
,
244 LLVMConstInt(ctx
->i32
, rshift
, 0), "");
246 if (rshift
+ bitwidth
< 32) {
247 unsigned mask
= (1 << bitwidth
) - 1;
248 value
= LLVMBuildAnd(ctx
->ac
.builder
, value
,
249 LLVMConstInt(ctx
->i32
, mask
, 0), "");
255 LLVMValueRef
si_unpack_param(struct si_shader_context
*ctx
,
256 unsigned param
, unsigned rshift
,
259 LLVMValueRef value
= LLVMGetParam(ctx
->main_fn
, param
);
261 return unpack_llvm_param(ctx
, value
, rshift
, bitwidth
);
264 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
267 case PIPE_SHADER_TESS_CTRL
:
268 return unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 0, 8);
270 case PIPE_SHADER_TESS_EVAL
:
271 return LLVMGetParam(ctx
->main_fn
,
272 ctx
->param_tes_rel_patch_id
);
280 /* Tessellation shaders pass outputs to the next shader using LDS.
282 * LS outputs = TCS inputs
283 * TCS outputs = TES inputs
286 * - TCS inputs for patch 0
287 * - TCS inputs for patch 1
288 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
290 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
291 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
292 * - TCS outputs for patch 1
293 * - Per-patch TCS outputs for patch 1
294 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
295 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
298 * All three shaders VS(LS), TCS, TES share the same LDS space.
302 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
304 return si_unpack_param(ctx
, ctx
->param_vs_state_bits
, 8, 13);
307 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context
*ctx
)
309 assert(ctx
->type
== PIPE_SHADER_TESS_CTRL
);
311 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
312 return util_last_bit64(ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
) * 4;
314 return util_last_bit64(ctx
->shader
->selector
->outputs_written
) * 4;
317 static LLVMValueRef
get_tcs_out_vertex_dw_stride(struct si_shader_context
*ctx
)
319 unsigned stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
321 return LLVMConstInt(ctx
->i32
, stride
, 0);
324 static LLVMValueRef
get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
326 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
327 return si_unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 0, 13);
329 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
330 unsigned tcs_out_vertices
= info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
331 unsigned vertex_dw_stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
332 unsigned num_patch_outputs
= util_last_bit64(ctx
->shader
->selector
->patch_outputs_written
);
333 unsigned patch_dw_stride
= tcs_out_vertices
* vertex_dw_stride
+
334 num_patch_outputs
* 4;
335 return LLVMConstInt(ctx
->i32
, patch_dw_stride
, 0);
339 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
341 return LLVMBuildMul(ctx
->ac
.builder
,
343 ctx
->param_tcs_out_lds_offsets
,
345 LLVMConstInt(ctx
->i32
, 4, 0), "");
349 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
351 return LLVMBuildMul(ctx
->ac
.builder
,
353 ctx
->param_tcs_out_lds_offsets
,
355 LLVMConstInt(ctx
->i32
, 4, 0), "");
359 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
361 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
362 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
364 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
368 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
370 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
371 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
372 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
374 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
, patch0_offset
);
378 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
380 LLVMValueRef patch0_patch_data_offset
=
381 get_tcs_out_patch0_patch_data_offset(ctx
);
382 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
383 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
385 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
, patch0_patch_data_offset
);
388 static LLVMValueRef
get_num_tcs_out_vertices(struct si_shader_context
*ctx
)
390 unsigned tcs_out_vertices
=
391 ctx
->shader
->selector
?
392 ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] : 0;
394 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
395 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& tcs_out_vertices
)
396 return LLVMConstInt(ctx
->i32
, tcs_out_vertices
, 0);
398 return si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 6, 6);
401 static LLVMValueRef
get_tcs_in_vertex_dw_stride(struct si_shader_context
*ctx
)
406 case PIPE_SHADER_VERTEX
:
407 stride
= ctx
->shader
->selector
->lshs_vertex_stride
/ 4;
408 return LLVMConstInt(ctx
->i32
, stride
, 0);
410 case PIPE_SHADER_TESS_CTRL
:
411 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
412 ctx
->shader
->is_monolithic
) {
413 stride
= ctx
->shader
->key
.part
.tcs
.ls
->lshs_vertex_stride
/ 4;
414 return LLVMConstInt(ctx
->i32
, stride
, 0);
416 return si_unpack_param(ctx
, ctx
->param_vs_state_bits
, 24, 8);
424 static LLVMValueRef
unpack_sint16(struct si_shader_context
*ctx
,
425 LLVMValueRef i32
, unsigned index
)
430 return LLVMBuildAShr(ctx
->ac
.builder
, i32
,
431 LLVMConstInt(ctx
->i32
, 16, 0), "");
433 return LLVMBuildSExt(ctx
->ac
.builder
,
434 LLVMBuildTrunc(ctx
->ac
.builder
, i32
,
439 void si_llvm_load_input_vs(
440 struct si_shader_context
*ctx
,
441 unsigned input_index
,
444 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
445 unsigned vs_blit_property
= info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
447 if (vs_blit_property
) {
448 LLVMValueRef vertex_id
= ctx
->abi
.vertex_id
;
449 LLVMValueRef sel_x1
= LLVMBuildICmp(ctx
->ac
.builder
,
450 LLVMIntULE
, vertex_id
,
452 /* Use LLVMIntNE, because we have 3 vertices and only
453 * the middle one should use y2.
455 LLVMValueRef sel_y1
= LLVMBuildICmp(ctx
->ac
.builder
,
456 LLVMIntNE
, vertex_id
,
459 if (input_index
== 0) {
461 LLVMValueRef x1y1
= LLVMGetParam(ctx
->main_fn
,
462 ctx
->param_vs_blit_inputs
);
463 LLVMValueRef x2y2
= LLVMGetParam(ctx
->main_fn
,
464 ctx
->param_vs_blit_inputs
+ 1);
466 LLVMValueRef x1
= unpack_sint16(ctx
, x1y1
, 0);
467 LLVMValueRef y1
= unpack_sint16(ctx
, x1y1
, 1);
468 LLVMValueRef x2
= unpack_sint16(ctx
, x2y2
, 0);
469 LLVMValueRef y2
= unpack_sint16(ctx
, x2y2
, 1);
471 LLVMValueRef x
= LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
473 LLVMValueRef y
= LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
476 out
[0] = LLVMBuildSIToFP(ctx
->ac
.builder
, x
, ctx
->f32
, "");
477 out
[1] = LLVMBuildSIToFP(ctx
->ac
.builder
, y
, ctx
->f32
, "");
478 out
[2] = LLVMGetParam(ctx
->main_fn
,
479 ctx
->param_vs_blit_inputs
+ 2);
480 out
[3] = ctx
->ac
.f32_1
;
484 /* Color or texture coordinates: */
485 assert(input_index
== 1);
487 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
488 for (int i
= 0; i
< 4; i
++) {
489 out
[i
] = LLVMGetParam(ctx
->main_fn
,
490 ctx
->param_vs_blit_inputs
+ 3 + i
);
493 assert(vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
);
494 LLVMValueRef x1
= LLVMGetParam(ctx
->main_fn
,
495 ctx
->param_vs_blit_inputs
+ 3);
496 LLVMValueRef y1
= LLVMGetParam(ctx
->main_fn
,
497 ctx
->param_vs_blit_inputs
+ 4);
498 LLVMValueRef x2
= LLVMGetParam(ctx
->main_fn
,
499 ctx
->param_vs_blit_inputs
+ 5);
500 LLVMValueRef y2
= LLVMGetParam(ctx
->main_fn
,
501 ctx
->param_vs_blit_inputs
+ 6);
503 out
[0] = LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
505 out
[1] = LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
507 out
[2] = LLVMGetParam(ctx
->main_fn
,
508 ctx
->param_vs_blit_inputs
+ 7);
509 out
[3] = LLVMGetParam(ctx
->main_fn
,
510 ctx
->param_vs_blit_inputs
+ 8);
515 union si_vs_fix_fetch fix_fetch
;
516 LLVMValueRef t_list_ptr
;
517 LLVMValueRef t_offset
;
519 LLVMValueRef vertex_index
;
522 /* Load the T list */
523 t_list_ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vertex_buffers
);
525 t_offset
= LLVMConstInt(ctx
->i32
, input_index
, 0);
527 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
529 vertex_index
= LLVMGetParam(ctx
->main_fn
,
530 ctx
->param_vertex_index0
+
533 /* Use the open-coded implementation for all loads of doubles and
534 * of dword-sized data that needs fixups. We need to insert conversion
535 * code anyway, and the amd/common code does it for us.
537 * Note: On LLVM <= 8, we can only open-code formats with
538 * channel size >= 4 bytes.
540 bool opencode
= ctx
->shader
->key
.mono
.vs_fetch_opencode
& (1 << input_index
);
541 fix_fetch
.bits
= ctx
->shader
->key
.mono
.vs_fix_fetch
[input_index
].bits
;
543 (fix_fetch
.u
.log_size
== 3 && fix_fetch
.u
.format
== AC_FETCH_FORMAT_FLOAT
) ||
544 (fix_fetch
.u
.log_size
== 2)) {
545 tmp
= ac_build_opencoded_load_format(
546 &ctx
->ac
, fix_fetch
.u
.log_size
, fix_fetch
.u
.num_channels_m1
+ 1,
547 fix_fetch
.u
.format
, fix_fetch
.u
.reverse
, !opencode
,
548 t_list
, vertex_index
, ctx
->ac
.i32_0
, ctx
->ac
.i32_0
, 0, true);
549 for (unsigned i
= 0; i
< 4; ++i
)
550 out
[i
] = LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, LLVMConstInt(ctx
->i32
, i
, false), "");
554 /* Do multiple loads for special formats. */
555 unsigned required_channels
= util_last_bit(info
->input_usage_mask
[input_index
]);
556 LLVMValueRef fetches
[4];
557 unsigned num_fetches
;
558 unsigned fetch_stride
;
559 unsigned channels_per_fetch
;
561 if (fix_fetch
.u
.log_size
<= 1 && fix_fetch
.u
.num_channels_m1
== 2) {
562 num_fetches
= MIN2(required_channels
, 3);
563 fetch_stride
= 1 << fix_fetch
.u
.log_size
;
564 channels_per_fetch
= 1;
568 channels_per_fetch
= required_channels
;
571 for (unsigned i
= 0; i
< num_fetches
; ++i
) {
572 LLVMValueRef voffset
= LLVMConstInt(ctx
->i32
, fetch_stride
* i
, 0);
573 fetches
[i
] = ac_build_buffer_load_format(&ctx
->ac
, t_list
, vertex_index
, voffset
,
574 channels_per_fetch
, 0, true);
577 if (num_fetches
== 1 && channels_per_fetch
> 1) {
578 LLVMValueRef fetch
= fetches
[0];
579 for (unsigned i
= 0; i
< channels_per_fetch
; ++i
) {
580 tmp
= LLVMConstInt(ctx
->i32
, i
, false);
581 fetches
[i
] = LLVMBuildExtractElement(
582 ctx
->ac
.builder
, fetch
, tmp
, "");
584 num_fetches
= channels_per_fetch
;
585 channels_per_fetch
= 1;
588 for (unsigned i
= num_fetches
; i
< 4; ++i
)
589 fetches
[i
] = LLVMGetUndef(ctx
->f32
);
591 if (fix_fetch
.u
.log_size
<= 1 && fix_fetch
.u
.num_channels_m1
== 2 &&
592 required_channels
== 4) {
593 if (fix_fetch
.u
.format
== AC_FETCH_FORMAT_UINT
|| fix_fetch
.u
.format
== AC_FETCH_FORMAT_SINT
)
594 fetches
[3] = ctx
->ac
.i32_1
;
596 fetches
[3] = ctx
->ac
.f32_1
;
597 } else if (fix_fetch
.u
.log_size
== 3 &&
598 (fix_fetch
.u
.format
== AC_FETCH_FORMAT_SNORM
||
599 fix_fetch
.u
.format
== AC_FETCH_FORMAT_SSCALED
||
600 fix_fetch
.u
.format
== AC_FETCH_FORMAT_SINT
) &&
601 required_channels
== 4) {
602 /* For 2_10_10_10, the hardware returns an unsigned value;
603 * convert it to a signed one.
605 LLVMValueRef tmp
= fetches
[3];
606 LLVMValueRef c30
= LLVMConstInt(ctx
->i32
, 30, 0);
608 /* First, recover the sign-extended signed integer value. */
609 if (fix_fetch
.u
.format
== AC_FETCH_FORMAT_SSCALED
)
610 tmp
= LLVMBuildFPToUI(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
612 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
614 /* For the integer-like cases, do a natural sign extension.
616 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
617 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
620 tmp
= LLVMBuildShl(ctx
->ac
.builder
, tmp
,
621 fix_fetch
.u
.format
== AC_FETCH_FORMAT_SNORM
?
622 LLVMConstInt(ctx
->i32
, 7, 0) : c30
, "");
623 tmp
= LLVMBuildAShr(ctx
->ac
.builder
, tmp
, c30
, "");
625 /* Convert back to the right type. */
626 if (fix_fetch
.u
.format
== AC_FETCH_FORMAT_SNORM
) {
628 LLVMValueRef neg_one
= LLVMConstReal(ctx
->f32
, -1.0);
629 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
630 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, tmp
, neg_one
, "");
631 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, tmp
, "");
632 } else if (fix_fetch
.u
.format
== AC_FETCH_FORMAT_SSCALED
) {
633 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
639 for (unsigned i
= 0; i
< 4; ++i
)
640 out
[i
] = ac_to_float(&ctx
->ac
, fetches
[i
]);
643 static void declare_input_vs(
644 struct si_shader_context
*ctx
,
645 unsigned input_index
,
646 const struct tgsi_full_declaration
*decl
,
649 si_llvm_load_input_vs(ctx
, input_index
, out
);
652 LLVMValueRef
si_get_primitive_id(struct si_shader_context
*ctx
,
659 case PIPE_SHADER_VERTEX
:
660 return LLVMGetParam(ctx
->main_fn
,
661 ctx
->param_vs_prim_id
);
662 case PIPE_SHADER_TESS_CTRL
:
663 return ctx
->abi
.tcs_patch_id
;
664 case PIPE_SHADER_TESS_EVAL
:
665 return ctx
->abi
.tes_patch_id
;
666 case PIPE_SHADER_GEOMETRY
:
667 return ctx
->abi
.gs_prim_id
;
675 * Return the value of tgsi_ind_register for indexing.
676 * This is the indirect index with the constant offset added to it.
678 LLVMValueRef
si_get_indirect_index(struct si_shader_context
*ctx
,
679 const struct tgsi_ind_register
*ind
,
685 if (ind
->File
== TGSI_FILE_ADDRESS
) {
686 result
= ctx
->addrs
[ind
->Index
][ind
->Swizzle
];
687 result
= LLVMBuildLoad(ctx
->ac
.builder
, result
, "");
689 struct tgsi_full_src_register src
= {};
691 src
.Register
.File
= ind
->File
;
692 src
.Register
.Index
= ind
->Index
;
694 /* Set the second index to 0 for constants. */
695 if (ind
->File
== TGSI_FILE_CONSTANT
)
696 src
.Register
.Dimension
= 1;
698 result
= ctx
->bld_base
.emit_fetch_funcs
[ind
->File
](&ctx
->bld_base
, &src
,
701 result
= ac_to_integer(&ctx
->ac
, result
);
704 return ac_build_imad(&ctx
->ac
, result
, LLVMConstInt(ctx
->i32
, addr_mul
, 0),
705 LLVMConstInt(ctx
->i32
, rel_index
, 0));
709 * Like si_get_indirect_index, but restricts the return value to a (possibly
710 * undefined) value inside [0..num).
712 LLVMValueRef
si_get_bounded_indirect_index(struct si_shader_context
*ctx
,
713 const struct tgsi_ind_register
*ind
,
714 int rel_index
, unsigned num
)
716 LLVMValueRef result
= si_get_indirect_index(ctx
, ind
, 1, rel_index
);
718 return si_llvm_bound_index(ctx
, result
, num
);
721 static LLVMValueRef
get_dw_address_from_generic_indices(struct si_shader_context
*ctx
,
722 LLVMValueRef vertex_dw_stride
,
723 LLVMValueRef base_addr
,
724 LLVMValueRef vertex_index
,
725 LLVMValueRef param_index
,
726 unsigned input_index
,
731 if (vertex_dw_stride
) {
732 base_addr
= ac_build_imad(&ctx
->ac
, vertex_index
,
733 vertex_dw_stride
, base_addr
);
737 base_addr
= ac_build_imad(&ctx
->ac
, param_index
,
738 LLVMConstInt(ctx
->i32
, 4, 0), base_addr
);
741 int param
= is_patch
?
742 si_shader_io_get_unique_index_patch(name
[input_index
],
743 index
[input_index
]) :
744 si_shader_io_get_unique_index(name
[input_index
],
745 index
[input_index
], false);
747 /* Add the base address of the element. */
748 return LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
749 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
753 * Calculate a dword address given an input or output register and a stride.
755 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
756 const struct tgsi_full_dst_register
*dst
,
757 const struct tgsi_full_src_register
*src
,
758 LLVMValueRef vertex_dw_stride
,
759 LLVMValueRef base_addr
)
761 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
762 ubyte
*name
, *index
, *array_first
;
764 struct tgsi_full_dst_register reg
;
765 LLVMValueRef vertex_index
= NULL
;
766 LLVMValueRef ind_index
= NULL
;
768 /* Set the register description. The address computation is the same
769 * for sources and destinations. */
771 reg
.Register
.File
= src
->Register
.File
;
772 reg
.Register
.Index
= src
->Register
.Index
;
773 reg
.Register
.Indirect
= src
->Register
.Indirect
;
774 reg
.Register
.Dimension
= src
->Register
.Dimension
;
775 reg
.Indirect
= src
->Indirect
;
776 reg
.Dimension
= src
->Dimension
;
777 reg
.DimIndirect
= src
->DimIndirect
;
781 /* If the register is 2-dimensional (e.g. an array of vertices
782 * in a primitive), calculate the base address of the vertex. */
783 if (reg
.Register
.Dimension
) {
784 if (reg
.Dimension
.Indirect
)
785 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
786 1, reg
.Dimension
.Index
);
788 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
791 /* Get information about the register. */
792 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
793 name
= info
->input_semantic_name
;
794 index
= info
->input_semantic_index
;
795 array_first
= info
->input_array_first
;
796 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
797 name
= info
->output_semantic_name
;
798 index
= info
->output_semantic_index
;
799 array_first
= info
->output_array_first
;
805 if (reg
.Register
.Indirect
) {
806 /* Add the relative address of the element. */
807 if (reg
.Indirect
.ArrayID
)
808 input_index
= array_first
[reg
.Indirect
.ArrayID
];
810 input_index
= reg
.Register
.Index
;
812 ind_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
813 1, reg
.Register
.Index
- input_index
);
815 input_index
= reg
.Register
.Index
;
818 return get_dw_address_from_generic_indices(ctx
, vertex_dw_stride
,
819 base_addr
, vertex_index
,
820 ind_index
, input_index
,
822 !reg
.Register
.Dimension
);
825 /* The offchip buffer layout for TCS->TES is
827 * - attribute 0 of patch 0 vertex 0
828 * - attribute 0 of patch 0 vertex 1
829 * - attribute 0 of patch 0 vertex 2
831 * - attribute 0 of patch 1 vertex 0
832 * - attribute 0 of patch 1 vertex 1
834 * - attribute 1 of patch 0 vertex 0
835 * - attribute 1 of patch 0 vertex 1
837 * - per patch attribute 0 of patch 0
838 * - per patch attribute 0 of patch 1
841 * Note that every attribute has 4 components.
843 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
844 LLVMValueRef rel_patch_id
,
845 LLVMValueRef vertex_index
,
846 LLVMValueRef param_index
)
848 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
849 LLVMValueRef param_stride
, constant16
;
851 vertices_per_patch
= get_num_tcs_out_vertices(ctx
);
852 num_patches
= si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 0, 6);
853 total_vertices
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
856 constant16
= LLVMConstInt(ctx
->i32
, 16, 0);
858 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
859 vertices_per_patch
, vertex_index
);
860 param_stride
= total_vertices
;
862 base_addr
= rel_patch_id
;
863 param_stride
= num_patches
;
866 base_addr
= ac_build_imad(&ctx
->ac
, param_index
, param_stride
, base_addr
);
867 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
870 LLVMValueRef patch_data_offset
=
871 si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 12, 20);
873 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
874 patch_data_offset
, "");
879 /* This is a generic helper that can be shared by the NIR and TGSI backends */
880 static LLVMValueRef
get_tcs_tes_buffer_address_from_generic_indices(
881 struct si_shader_context
*ctx
,
882 LLVMValueRef vertex_index
,
883 LLVMValueRef param_index
,
889 unsigned param_index_base
;
891 param_index_base
= is_patch
?
892 si_shader_io_get_unique_index_patch(name
[param_base
], index
[param_base
]) :
893 si_shader_io_get_unique_index(name
[param_base
], index
[param_base
], false);
896 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
897 LLVMConstInt(ctx
->i32
, param_index_base
, 0),
900 param_index
= LLVMConstInt(ctx
->i32
, param_index_base
, 0);
903 return get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
),
904 vertex_index
, param_index
);
907 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
908 struct si_shader_context
*ctx
,
909 const struct tgsi_full_dst_register
*dst
,
910 const struct tgsi_full_src_register
*src
)
912 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
913 ubyte
*name
, *index
, *array_first
;
914 struct tgsi_full_src_register reg
;
915 LLVMValueRef vertex_index
= NULL
;
916 LLVMValueRef param_index
= NULL
;
919 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
921 if (reg
.Register
.Dimension
) {
923 if (reg
.Dimension
.Indirect
)
924 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
925 1, reg
.Dimension
.Index
);
927 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
930 /* Get information about the register. */
931 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
932 name
= info
->input_semantic_name
;
933 index
= info
->input_semantic_index
;
934 array_first
= info
->input_array_first
;
935 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
936 name
= info
->output_semantic_name
;
937 index
= info
->output_semantic_index
;
938 array_first
= info
->output_array_first
;
944 if (reg
.Register
.Indirect
) {
945 if (reg
.Indirect
.ArrayID
)
946 param_base
= array_first
[reg
.Indirect
.ArrayID
];
948 param_base
= reg
.Register
.Index
;
950 param_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
951 1, reg
.Register
.Index
- param_base
);
954 param_base
= reg
.Register
.Index
;
957 return get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
958 param_index
, param_base
,
959 name
, index
, !reg
.Register
.Dimension
);
962 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
963 LLVMTypeRef type
, unsigned swizzle
,
964 LLVMValueRef buffer
, LLVMValueRef offset
,
965 LLVMValueRef base
, bool can_speculate
)
967 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
968 LLVMValueRef value
, value2
;
969 LLVMTypeRef vec_type
= LLVMVectorType(type
, 4);
972 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
973 0, ac_glc
, can_speculate
, false);
975 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
978 if (!llvm_type_is_64bit(ctx
, type
)) {
979 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
980 0, ac_glc
, can_speculate
, false);
982 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
983 return LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
984 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
987 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
988 swizzle
* 4, ac_glc
, can_speculate
, false);
990 value2
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
991 swizzle
* 4 + 4, ac_glc
, can_speculate
, false);
993 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
997 * Load from LSHS LDS storage.
999 * \param type output value type
1000 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1001 * \param dw_addr address in dwords
1003 static LLVMValueRef
lshs_lds_load(struct lp_build_tgsi_context
*bld_base
,
1004 LLVMTypeRef type
, unsigned swizzle
,
1005 LLVMValueRef dw_addr
)
1007 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1010 if (swizzle
== ~0) {
1011 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1013 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
1014 values
[chan
] = lshs_lds_load(bld_base
, type
, chan
, dw_addr
);
1016 return ac_build_gather_values(&ctx
->ac
, values
,
1020 /* Split 64-bit loads. */
1021 if (llvm_type_is_64bit(ctx
, type
)) {
1022 LLVMValueRef lo
, hi
;
1024 lo
= lshs_lds_load(bld_base
, ctx
->i32
, swizzle
, dw_addr
);
1025 hi
= lshs_lds_load(bld_base
, ctx
->i32
, swizzle
+ 1, dw_addr
);
1026 return si_llvm_emit_fetch_64bit(bld_base
, type
, lo
, hi
);
1029 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1030 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
1032 value
= ac_lds_load(&ctx
->ac
, dw_addr
);
1034 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1038 * Store to LSHS LDS storage.
1040 * \param swizzle offset (typically 0..3)
1041 * \param dw_addr address in dwords
1042 * \param value value to store
1044 static void lshs_lds_store(struct si_shader_context
*ctx
,
1045 unsigned dw_offset_imm
, LLVMValueRef dw_addr
,
1048 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1049 LLVMConstInt(ctx
->i32
, dw_offset_imm
, 0), "");
1051 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
1056 TESS_OFFCHIP_RING_TCS
,
1057 TESS_OFFCHIP_RING_TES
,
1060 static LLVMValueRef
get_tess_ring_descriptor(struct si_shader_context
*ctx
,
1061 enum si_tess_ring ring
)
1063 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1064 unsigned param
= ring
== TESS_OFFCHIP_RING_TES
? ctx
->param_tes_offchip_addr
:
1065 ctx
->param_tcs_out_lds_layout
;
1066 LLVMValueRef addr
= LLVMGetParam(ctx
->main_fn
, param
);
1068 /* TCS only receives high 13 bits of the address. */
1069 if (ring
== TESS_OFFCHIP_RING_TCS
|| ring
== TCS_FACTOR_RING
) {
1070 addr
= LLVMBuildAnd(builder
, addr
,
1071 LLVMConstInt(ctx
->i32
, 0xfff80000, 0), "");
1074 if (ring
== TCS_FACTOR_RING
) {
1075 unsigned tf_offset
= ctx
->screen
->tess_offchip_ring_size
;
1076 addr
= LLVMBuildAdd(builder
, addr
,
1077 LLVMConstInt(ctx
->i32
, tf_offset
, 0), "");
1080 uint32_t rsrc3
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1081 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1082 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1083 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1085 if (ctx
->screen
->info
.chip_class
>= GFX10
)
1086 rsrc3
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1087 S_008F0C_OOB_SELECT(3) |
1088 S_008F0C_RESOURCE_LEVEL(1);
1090 rsrc3
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1091 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1093 LLVMValueRef desc
[4];
1095 desc
[1] = LLVMConstInt(ctx
->i32
,
1096 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0);
1097 desc
[2] = LLVMConstInt(ctx
->i32
, 0xffffffff, 0);
1098 desc
[3] = LLVMConstInt(ctx
->i32
, rsrc3
, false);
1100 return ac_build_gather_values(&ctx
->ac
, desc
, 4);
1103 static LLVMValueRef
fetch_input_tcs(
1104 struct lp_build_tgsi_context
*bld_base
,
1105 const struct tgsi_full_src_register
*reg
,
1106 enum tgsi_opcode_type type
, unsigned swizzle_in
)
1108 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1109 LLVMValueRef dw_addr
, stride
;
1110 unsigned swizzle
= swizzle_in
& 0xffff;
1111 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1112 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1113 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1115 return lshs_lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1118 static LLVMValueRef
si_nir_load_tcs_varyings(struct ac_shader_abi
*abi
,
1120 LLVMValueRef vertex_index
,
1121 LLVMValueRef param_index
,
1122 unsigned const_index
,
1124 unsigned driver_location
,
1126 unsigned num_components
,
1131 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1132 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1133 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1134 LLVMValueRef dw_addr
, stride
;
1136 driver_location
= driver_location
/ 4;
1139 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1140 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1144 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1146 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1147 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1152 /* Add the constant index to the indirect index */
1153 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1154 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1156 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1162 names
= info
->input_semantic_name
;
1163 indices
= info
->input_semantic_index
;
1165 names
= info
->output_semantic_name
;
1166 indices
= info
->output_semantic_index
;
1169 dw_addr
= get_dw_address_from_generic_indices(ctx
, stride
, dw_addr
,
1170 vertex_index
, param_index
,
1175 LLVMValueRef value
[4];
1176 for (unsigned i
= 0; i
< num_components
; i
++) {
1177 unsigned offset
= i
;
1178 if (llvm_type_is_64bit(ctx
, type
))
1181 offset
+= component
;
1182 value
[i
+ component
] = lshs_lds_load(bld_base
, type
, offset
, dw_addr
);
1185 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1188 static LLVMValueRef
fetch_output_tcs(
1189 struct lp_build_tgsi_context
*bld_base
,
1190 const struct tgsi_full_src_register
*reg
,
1191 enum tgsi_opcode_type type
, unsigned swizzle_in
)
1193 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1194 LLVMValueRef dw_addr
, stride
;
1195 unsigned swizzle
= (swizzle_in
& 0xffff);
1197 if (reg
->Register
.Dimension
) {
1198 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1199 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1200 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1202 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1203 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1206 return lshs_lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1209 static LLVMValueRef
fetch_input_tes(
1210 struct lp_build_tgsi_context
*bld_base
,
1211 const struct tgsi_full_src_register
*reg
,
1212 enum tgsi_opcode_type type
, unsigned swizzle_in
)
1214 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1215 LLVMValueRef base
, addr
;
1216 unsigned swizzle
= (swizzle_in
& 0xffff);
1218 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1219 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1221 return buffer_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
,
1222 ctx
->tess_offchip_ring
, base
, addr
, true);
1225 LLVMValueRef
si_nir_load_input_tes(struct ac_shader_abi
*abi
,
1227 LLVMValueRef vertex_index
,
1228 LLVMValueRef param_index
,
1229 unsigned const_index
,
1231 unsigned driver_location
,
1233 unsigned num_components
,
1238 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1239 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1240 LLVMValueRef base
, addr
;
1242 driver_location
= driver_location
/ 4;
1244 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1247 /* Add the constant index to the indirect index */
1248 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1249 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1251 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1254 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1255 param_index
, driver_location
,
1256 info
->input_semantic_name
,
1257 info
->input_semantic_index
,
1260 /* TODO: This will generate rather ordinary llvm code, although it
1261 * should be easy for the optimiser to fix up. In future we might want
1262 * to refactor buffer_load(), but for now this maximises code sharing
1263 * between the NIR and TGSI backends.
1265 LLVMValueRef value
[4];
1266 for (unsigned i
= 0; i
< num_components
; i
++) {
1267 unsigned offset
= i
;
1268 if (llvm_type_is_64bit(ctx
, type
)) {
1271 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
,
1274 driver_location
+ 1,
1275 info
->input_semantic_name
,
1276 info
->input_semantic_index
,
1280 offset
= offset
% 4;
1283 offset
+= component
;
1284 value
[i
+ component
] = buffer_load(&ctx
->bld_base
, type
, offset
,
1285 ctx
->tess_offchip_ring
, base
, addr
, true);
1288 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1291 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1292 const struct tgsi_full_instruction
*inst
,
1293 const struct tgsi_opcode_info
*info
,
1295 LLVMValueRef dst
[4])
1297 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1298 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[index
];
1299 const struct tgsi_shader_info
*sh_info
= &ctx
->shader
->selector
->info
;
1300 unsigned chan_index
;
1301 LLVMValueRef dw_addr
, stride
;
1302 LLVMValueRef buffer
, base
, buf_addr
;
1303 LLVMValueRef values
[4];
1304 bool skip_lds_store
;
1305 bool is_tess_factor
= false, is_tess_inner
= false;
1307 /* Only handle per-patch and per-vertex outputs here.
1308 * Vectors will be lowered to scalars and this function will be called again.
1310 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1311 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1312 si_llvm_emit_store(bld_base
, inst
, info
, index
, dst
);
1316 if (reg
->Register
.Dimension
) {
1317 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1318 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1319 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1320 skip_lds_store
= !sh_info
->reads_pervertex_outputs
;
1322 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1323 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1324 skip_lds_store
= !sh_info
->reads_perpatch_outputs
;
1326 if (!reg
->Register
.Indirect
) {
1327 int name
= sh_info
->output_semantic_name
[reg
->Register
.Index
];
1329 /* Always write tess factors into LDS for the TCS epilog. */
1330 if (name
== TGSI_SEMANTIC_TESSINNER
||
1331 name
== TGSI_SEMANTIC_TESSOUTER
) {
1332 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1333 skip_lds_store
= !sh_info
->reads_tessfactor_outputs
&&
1334 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1335 is_tess_factor
= true;
1336 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1341 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
1343 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1344 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1346 uint32_t writemask
= reg
->Register
.WriteMask
;
1348 chan_index
= u_bit_scan(&writemask
);
1349 LLVMValueRef value
= dst
[chan_index
];
1351 if (inst
->Instruction
.Saturate
)
1352 value
= ac_build_clamp(&ctx
->ac
, value
);
1354 /* Skip LDS stores if there is no LDS read of this output. */
1355 if (!skip_lds_store
)
1356 lshs_lds_store(ctx
, chan_index
, dw_addr
, value
);
1358 value
= ac_to_integer(&ctx
->ac
, value
);
1359 values
[chan_index
] = value
;
1361 if (reg
->Register
.WriteMask
!= 0xF && !is_tess_factor
) {
1362 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1364 4 * chan_index
, ac_glc
, false);
1367 /* Write tess factors into VGPRs for the epilog. */
1368 if (is_tess_factor
&&
1369 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1370 if (!is_tess_inner
) {
1371 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1372 ctx
->invoc0_tess_factors
[chan_index
]);
1373 } else if (chan_index
< 2) {
1374 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1375 ctx
->invoc0_tess_factors
[4 + chan_index
]);
1380 if (reg
->Register
.WriteMask
== 0xF && !is_tess_factor
) {
1381 LLVMValueRef value
= ac_build_gather_values(&ctx
->ac
,
1383 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buf_addr
,
1384 base
, 0, ac_glc
, false);
1388 static void si_nir_store_output_tcs(struct ac_shader_abi
*abi
,
1389 const struct nir_variable
*var
,
1390 LLVMValueRef vertex_index
,
1391 LLVMValueRef param_index
,
1392 unsigned const_index
,
1396 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1397 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1398 const unsigned component
= var
->data
.location_frac
;
1399 const bool is_patch
= var
->data
.patch
;
1400 unsigned driver_location
= var
->data
.driver_location
;
1401 LLVMValueRef dw_addr
, stride
;
1402 LLVMValueRef buffer
, base
, addr
;
1403 LLVMValueRef values
[8];
1404 bool skip_lds_store
;
1405 bool is_tess_factor
= false, is_tess_inner
= false;
1407 driver_location
= driver_location
/ 4;
1410 /* Add the constant index to the indirect index */
1411 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1412 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1414 if (const_index
!= 0)
1415 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1419 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1420 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1421 dw_addr
= get_dw_address_from_generic_indices(ctx
, stride
, dw_addr
,
1422 vertex_index
, param_index
,
1424 info
->output_semantic_name
,
1425 info
->output_semantic_index
,
1428 skip_lds_store
= !info
->reads_pervertex_outputs
;
1430 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1431 dw_addr
= get_dw_address_from_generic_indices(ctx
, NULL
, dw_addr
,
1432 vertex_index
, param_index
,
1434 info
->output_semantic_name
,
1435 info
->output_semantic_index
,
1438 skip_lds_store
= !info
->reads_perpatch_outputs
;
1441 int name
= info
->output_semantic_name
[driver_location
];
1443 /* Always write tess factors into LDS for the TCS epilog. */
1444 if (name
== TGSI_SEMANTIC_TESSINNER
||
1445 name
== TGSI_SEMANTIC_TESSOUTER
) {
1446 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1447 skip_lds_store
= !info
->reads_tessfactor_outputs
&&
1448 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1449 is_tess_factor
= true;
1450 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1455 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
1457 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1459 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1460 param_index
, driver_location
,
1461 info
->output_semantic_name
,
1462 info
->output_semantic_index
,
1465 for (unsigned chan
= 0; chan
< 8; chan
++) {
1466 if (!(writemask
& (1 << chan
)))
1468 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1470 unsigned buffer_store_offset
= chan
% 4;
1472 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
,
1475 driver_location
+ 1,
1476 info
->output_semantic_name
,
1477 info
->output_semantic_index
,
1481 /* Skip LDS stores if there is no LDS read of this output. */
1482 if (!skip_lds_store
)
1483 lshs_lds_store(ctx
, chan
, dw_addr
, value
);
1485 value
= ac_to_integer(&ctx
->ac
, value
);
1486 values
[chan
] = value
;
1488 if (writemask
!= 0xF && !is_tess_factor
) {
1489 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1491 4 * buffer_store_offset
,
1495 /* Write tess factors into VGPRs for the epilog. */
1496 if (is_tess_factor
&&
1497 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1498 if (!is_tess_inner
) {
1499 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1500 ctx
->invoc0_tess_factors
[chan
]);
1501 } else if (chan
< 2) {
1502 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1503 ctx
->invoc0_tess_factors
[4 + chan
]);
1508 if (writemask
== 0xF && !is_tess_factor
) {
1509 LLVMValueRef value
= ac_build_gather_values(&ctx
->ac
,
1511 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, addr
,
1512 base
, 0, ac_glc
, false);
1516 LLVMValueRef
si_llvm_load_input_gs(struct ac_shader_abi
*abi
,
1517 unsigned input_index
,
1518 unsigned vtx_offset_param
,
1522 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1523 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1524 struct si_shader
*shader
= ctx
->shader
;
1525 LLVMValueRef vtx_offset
, soffset
;
1526 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1527 unsigned semantic_name
= info
->input_semantic_name
[input_index
];
1528 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1532 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
, false);
1534 /* GFX9 has the ESGS ring in LDS. */
1535 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1536 unsigned index
= vtx_offset_param
;
1538 switch (index
/ 2) {
1540 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx01_offset
,
1541 index
% 2 ? 16 : 0, 16);
1544 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx23_offset
,
1545 index
% 2 ? 16 : 0, 16);
1548 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx45_offset
,
1549 index
% 2 ? 16 : 0, 16);
1556 unsigned offset
= param
* 4 + swizzle
;
1557 vtx_offset
= LLVMBuildAdd(ctx
->ac
.builder
, vtx_offset
,
1558 LLVMConstInt(ctx
->i32
, offset
, false), "");
1560 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, vtx_offset
);
1561 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, ptr
, "");
1562 if (llvm_type_is_64bit(ctx
, type
)) {
1563 ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
,
1564 &ctx
->ac
.i32_1
, 1, "");
1565 LLVMValueRef values
[2] = {
1567 LLVMBuildLoad(ctx
->ac
.builder
, ptr
, "")
1569 value
= ac_build_gather_values(&ctx
->ac
, values
, 2);
1571 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1574 /* GFX6: input load from the ESGS ring in memory. */
1575 if (swizzle
== ~0) {
1576 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1578 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1579 values
[chan
] = si_llvm_load_input_gs(abi
, input_index
, vtx_offset_param
,
1582 return ac_build_gather_values(&ctx
->ac
, values
,
1586 /* Get the vertex offset parameter on GFX6. */
1587 LLVMValueRef gs_vtx_offset
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1589 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, gs_vtx_offset
,
1590 LLVMConstInt(ctx
->i32
, 4, 0), "");
1592 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
) * 256, 0);
1594 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1, ctx
->i32_0
,
1595 vtx_offset
, soffset
, 0, ac_glc
, true, false);
1596 if (llvm_type_is_64bit(ctx
, type
)) {
1597 LLVMValueRef value2
;
1598 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
+ 1) * 256, 0);
1600 value2
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1,
1601 ctx
->i32_0
, vtx_offset
, soffset
,
1602 0, ac_glc
, true, false);
1603 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1605 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1608 static LLVMValueRef
si_nir_load_input_gs(struct ac_shader_abi
*abi
,
1610 unsigned driver_location
,
1612 unsigned num_components
,
1613 unsigned vertex_index
,
1614 unsigned const_index
,
1617 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1619 LLVMValueRef value
[4];
1620 for (unsigned i
= 0; i
< num_components
; i
++) {
1621 unsigned offset
= i
;
1622 if (llvm_type_is_64bit(ctx
, type
))
1625 offset
+= component
;
1626 value
[i
+ component
] = si_llvm_load_input_gs(&ctx
->abi
, driver_location
/ 4,
1627 vertex_index
, type
, offset
);
1630 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1633 static LLVMValueRef
fetch_input_gs(
1634 struct lp_build_tgsi_context
*bld_base
,
1635 const struct tgsi_full_src_register
*reg
,
1636 enum tgsi_opcode_type type
,
1637 unsigned swizzle_in
)
1639 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1640 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1641 unsigned swizzle
= swizzle_in
& 0xffff;
1643 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1644 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1645 return si_get_primitive_id(ctx
, swizzle
);
1647 if (!reg
->Register
.Dimension
)
1650 return si_llvm_load_input_gs(&ctx
->abi
, reg
->Register
.Index
,
1651 reg
->Dimension
.Index
,
1652 tgsi2llvmtype(bld_base
, type
),
1656 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1658 switch (interpolate
) {
1659 case TGSI_INTERPOLATE_CONSTANT
:
1662 case TGSI_INTERPOLATE_LINEAR
:
1663 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1664 return SI_PARAM_LINEAR_SAMPLE
;
1665 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1666 return SI_PARAM_LINEAR_CENTROID
;
1668 return SI_PARAM_LINEAR_CENTER
;
1670 case TGSI_INTERPOLATE_COLOR
:
1671 case TGSI_INTERPOLATE_PERSPECTIVE
:
1672 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1673 return SI_PARAM_PERSP_SAMPLE
;
1674 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1675 return SI_PARAM_PERSP_CENTROID
;
1677 return SI_PARAM_PERSP_CENTER
;
1680 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1685 static LLVMValueRef
si_build_fs_interp(struct si_shader_context
*ctx
,
1686 unsigned attr_index
, unsigned chan
,
1687 LLVMValueRef prim_mask
,
1688 LLVMValueRef i
, LLVMValueRef j
)
1691 return ac_build_fs_interp(&ctx
->ac
,
1692 LLVMConstInt(ctx
->i32
, chan
, 0),
1693 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1696 return ac_build_fs_interp_mov(&ctx
->ac
,
1697 LLVMConstInt(ctx
->i32
, 2, 0), /* P0 */
1698 LLVMConstInt(ctx
->i32
, chan
, 0),
1699 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1704 * Interpolate a fragment shader input.
1706 * @param ctx context
1707 * @param input_index index of the input in hardware
1708 * @param semantic_name TGSI_SEMANTIC_*
1709 * @param semantic_index semantic index
1710 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1711 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1712 * @param interp_param interpolation weights (i,j)
1713 * @param prim_mask SI_PARAM_PRIM_MASK
1714 * @param face SI_PARAM_FRONT_FACE
1715 * @param result the return value (4 components)
1717 static void interp_fs_input(struct si_shader_context
*ctx
,
1718 unsigned input_index
,
1719 unsigned semantic_name
,
1720 unsigned semantic_index
,
1721 unsigned num_interp_inputs
,
1722 unsigned colors_read_mask
,
1723 LLVMValueRef interp_param
,
1724 LLVMValueRef prim_mask
,
1726 LLVMValueRef result
[4])
1728 LLVMValueRef i
= NULL
, j
= NULL
;
1731 /* fs.constant returns the param from the middle vertex, so it's not
1732 * really useful for flat shading. It's meant to be used for custom
1733 * interpolation (but the intrinsic can't fetch from the other two
1736 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1737 * to do the right thing. The only reason we use fs.constant is that
1738 * fs.interp cannot be used on integers, because they can be equal
1741 * When interp is false we will use fs.constant or for newer llvm,
1742 * amdgcn.interp.mov.
1744 bool interp
= interp_param
!= NULL
;
1747 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
1748 LLVMVectorType(ctx
->f32
, 2), "");
1750 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1752 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1756 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1757 ctx
->shader
->key
.part
.ps
.prolog
.color_two_side
) {
1758 LLVMValueRef is_face_positive
;
1760 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1761 * otherwise it's at offset "num_inputs".
1763 unsigned back_attr_offset
= num_interp_inputs
;
1764 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1765 back_attr_offset
+= 1;
1767 is_face_positive
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
1768 face
, ctx
->i32_0
, "");
1770 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1771 LLVMValueRef front
, back
;
1773 front
= si_build_fs_interp(ctx
,
1776 back
= si_build_fs_interp(ctx
,
1777 back_attr_offset
, chan
,
1780 result
[chan
] = LLVMBuildSelect(ctx
->ac
.builder
,
1786 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1787 result
[0] = si_build_fs_interp(ctx
, input_index
,
1788 0, prim_mask
, i
, j
);
1790 result
[2] = LLVMConstReal(ctx
->f32
, 0.0f
);
1791 result
[3] = LLVMConstReal(ctx
->f32
, 1.0f
);
1793 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1794 result
[chan
] = si_build_fs_interp(ctx
,
1801 void si_llvm_load_input_fs(
1802 struct si_shader_context
*ctx
,
1803 unsigned input_index
,
1804 LLVMValueRef out
[4])
1806 struct si_shader
*shader
= ctx
->shader
;
1807 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1808 LLVMValueRef main_fn
= ctx
->main_fn
;
1809 LLVMValueRef interp_param
= NULL
;
1810 int interp_param_idx
;
1811 enum tgsi_semantic semantic_name
= info
->input_semantic_name
[input_index
];
1812 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1813 enum tgsi_interpolate_mode interp_mode
= info
->input_interpolate
[input_index
];
1814 enum tgsi_interpolate_loc interp_loc
= info
->input_interpolate_loc
[input_index
];
1816 /* Get colors from input VGPRs (set by the prolog). */
1817 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1818 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1819 unsigned mask
= colors_read
>> (semantic_index
* 4);
1820 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1821 (semantic_index
? util_bitcount(colors_read
& 0xf) : 0);
1822 LLVMValueRef undef
= LLVMGetUndef(ctx
->f32
);
1824 out
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1825 out
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1826 out
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1827 out
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1831 interp_param_idx
= lookup_interp_param_index(interp_mode
, interp_loc
);
1832 if (interp_param_idx
== -1)
1834 else if (interp_param_idx
) {
1835 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
1838 interp_fs_input(ctx
, input_index
, semantic_name
,
1839 semantic_index
, 0, /* this param is unused */
1840 shader
->selector
->info
.colors_read
, interp_param
,
1842 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1846 static void declare_input_fs(
1847 struct si_shader_context
*ctx
,
1848 unsigned input_index
,
1849 const struct tgsi_full_declaration
*decl
,
1850 LLVMValueRef out
[4])
1852 si_llvm_load_input_fs(ctx
, input_index
, out
);
1855 LLVMValueRef
si_get_sample_id(struct si_shader_context
*ctx
)
1857 return si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 8, 4);
1860 static LLVMValueRef
get_base_vertex(struct ac_shader_abi
*abi
)
1862 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1864 /* For non-indexed draws, the base vertex set by the driver
1865 * (for direct draws) or the CP (for indirect draws) is the
1866 * first vertex ID, but GLSL expects 0 to be returned.
1868 LLVMValueRef vs_state
= LLVMGetParam(ctx
->main_fn
,
1869 ctx
->param_vs_state_bits
);
1870 LLVMValueRef indexed
;
1872 indexed
= LLVMBuildLShr(ctx
->ac
.builder
, vs_state
, ctx
->i32_1
, "");
1873 indexed
= LLVMBuildTrunc(ctx
->ac
.builder
, indexed
, ctx
->i1
, "");
1875 return LLVMBuildSelect(ctx
->ac
.builder
, indexed
, ctx
->abi
.base_vertex
,
1879 static LLVMValueRef
get_block_size(struct ac_shader_abi
*abi
)
1881 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1883 LLVMValueRef values
[3];
1884 LLVMValueRef result
;
1886 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1888 if (properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] != 0) {
1889 unsigned sizes
[3] = {
1890 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1891 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1892 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1895 for (i
= 0; i
< 3; ++i
)
1896 values
[i
] = LLVMConstInt(ctx
->i32
, sizes
[i
], 0);
1898 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
1900 result
= LLVMGetParam(ctx
->main_fn
, ctx
->param_block_size
);
1907 * Load a dword from a constant buffer.
1909 static LLVMValueRef
buffer_load_const(struct si_shader_context
*ctx
,
1910 LLVMValueRef resource
,
1911 LLVMValueRef offset
)
1913 return ac_build_buffer_load(&ctx
->ac
, resource
, 1, NULL
, offset
, NULL
,
1917 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
, LLVMValueRef sample_id
)
1919 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1920 LLVMValueRef desc
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1921 LLVMValueRef buf_index
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_SAMPLE_POSITIONS
, 0);
1922 LLVMValueRef resource
= ac_build_load_to_sgpr(&ctx
->ac
, desc
, buf_index
);
1924 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1925 LLVMValueRef offset0
= LLVMBuildMul(ctx
->ac
.builder
, sample_id
, LLVMConstInt(ctx
->i32
, 8, 0), "");
1926 LLVMValueRef offset1
= LLVMBuildAdd(ctx
->ac
.builder
, offset0
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1928 LLVMValueRef pos
[4] = {
1929 buffer_load_const(ctx
, resource
, offset0
),
1930 buffer_load_const(ctx
, resource
, offset1
),
1931 LLVMConstReal(ctx
->f32
, 0),
1932 LLVMConstReal(ctx
->f32
, 0)
1935 return ac_build_gather_values(&ctx
->ac
, pos
, 4);
1938 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1940 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1941 return ac_to_integer(&ctx
->ac
, abi
->sample_coverage
);
1944 static LLVMValueRef
si_load_tess_coord(struct ac_shader_abi
*abi
)
1946 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1947 LLVMValueRef coord
[4] = {
1948 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_u
),
1949 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_v
),
1954 /* For triangles, the vector should be (u, v, 1-u-v). */
1955 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
1956 PIPE_PRIM_TRIANGLES
) {
1957 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1958 LLVMBuildFAdd(ctx
->ac
.builder
,
1959 coord
[0], coord
[1], ""), "");
1961 return ac_build_gather_values(&ctx
->ac
, coord
, 4);
1964 static LLVMValueRef
load_tess_level(struct si_shader_context
*ctx
,
1965 unsigned semantic_name
)
1967 LLVMValueRef base
, addr
;
1969 int param
= si_shader_io_get_unique_index_patch(semantic_name
, 0);
1971 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1972 addr
= get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
), NULL
,
1973 LLVMConstInt(ctx
->i32
, param
, 0));
1975 return buffer_load(&ctx
->bld_base
, ctx
->f32
,
1976 ~0, ctx
->tess_offchip_ring
, base
, addr
, true);
1980 static LLVMValueRef
si_load_tess_level(struct ac_shader_abi
*abi
,
1981 unsigned varying_id
)
1983 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1984 unsigned semantic_name
;
1986 switch (varying_id
) {
1987 case VARYING_SLOT_TESS_LEVEL_INNER
:
1988 semantic_name
= TGSI_SEMANTIC_TESSINNER
;
1990 case VARYING_SLOT_TESS_LEVEL_OUTER
:
1991 semantic_name
= TGSI_SEMANTIC_TESSOUTER
;
1994 unreachable("unknown tess level");
1997 return load_tess_level(ctx
, semantic_name
);
2001 static LLVMValueRef
si_load_patch_vertices_in(struct ac_shader_abi
*abi
)
2003 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2004 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
2005 return si_unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 13, 6);
2006 else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
)
2007 return get_num_tcs_out_vertices(ctx
);
2009 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2012 void si_load_system_value(struct si_shader_context
*ctx
,
2014 const struct tgsi_full_declaration
*decl
)
2016 LLVMValueRef value
= 0;
2018 assert(index
< RADEON_LLVM_MAX_SYSTEM_VALUES
);
2020 switch (decl
->Semantic
.Name
) {
2021 case TGSI_SEMANTIC_INSTANCEID
:
2022 value
= ctx
->abi
.instance_id
;
2025 case TGSI_SEMANTIC_VERTEXID
:
2026 value
= LLVMBuildAdd(ctx
->ac
.builder
,
2028 ctx
->abi
.base_vertex
, "");
2031 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
2032 /* Unused. Clarify the meaning in indexed vs. non-indexed
2033 * draws if this is ever used again. */
2037 case TGSI_SEMANTIC_BASEVERTEX
:
2038 value
= get_base_vertex(&ctx
->abi
);
2041 case TGSI_SEMANTIC_BASEINSTANCE
:
2042 value
= ctx
->abi
.start_instance
;
2045 case TGSI_SEMANTIC_DRAWID
:
2046 value
= ctx
->abi
.draw_id
;
2049 case TGSI_SEMANTIC_INVOCATIONID
:
2050 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
2051 value
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
2052 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
2053 if (ctx
->screen
->info
.chip_class
>= GFX10
) {
2054 value
= LLVMBuildAnd(ctx
->ac
.builder
,
2055 ctx
->abi
.gs_invocation_id
,
2056 LLVMConstInt(ctx
->i32
, 127, 0), "");
2058 value
= ctx
->abi
.gs_invocation_id
;
2061 assert(!"INVOCATIONID not implemented");
2065 case TGSI_SEMANTIC_POSITION
:
2067 LLVMValueRef pos
[4] = {
2068 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
2069 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
2070 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
2071 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2072 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_W_FLOAT
)),
2074 value
= ac_build_gather_values(&ctx
->ac
, pos
, 4);
2078 case TGSI_SEMANTIC_FACE
:
2079 value
= ctx
->abi
.front_face
;
2082 case TGSI_SEMANTIC_SAMPLEID
:
2083 value
= si_get_sample_id(ctx
);
2086 case TGSI_SEMANTIC_SAMPLEPOS
: {
2087 LLVMValueRef pos
[4] = {
2088 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
2089 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
2090 LLVMConstReal(ctx
->f32
, 0),
2091 LLVMConstReal(ctx
->f32
, 0)
2093 pos
[0] = ac_build_fract(&ctx
->ac
, pos
[0], 32);
2094 pos
[1] = ac_build_fract(&ctx
->ac
, pos
[1], 32);
2095 value
= ac_build_gather_values(&ctx
->ac
, pos
, 4);
2099 case TGSI_SEMANTIC_SAMPLEMASK
:
2100 /* This can only occur with the OpenGL Core profile, which
2101 * doesn't support smoothing.
2103 value
= LLVMGetParam(ctx
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
2106 case TGSI_SEMANTIC_TESSCOORD
:
2107 value
= si_load_tess_coord(&ctx
->abi
);
2110 case TGSI_SEMANTIC_VERTICESIN
:
2111 value
= si_load_patch_vertices_in(&ctx
->abi
);
2114 case TGSI_SEMANTIC_TESSINNER
:
2115 case TGSI_SEMANTIC_TESSOUTER
:
2116 value
= load_tess_level(ctx
, decl
->Semantic
.Name
);
2119 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
2120 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
2122 LLVMValueRef buf
, slot
, val
[4];
2125 slot
= LLVMConstInt(ctx
->i32
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, 0);
2126 buf
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2127 buf
= ac_build_load_to_sgpr(&ctx
->ac
, buf
, slot
);
2128 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
2130 for (i
= 0; i
< 4; i
++)
2131 val
[i
] = buffer_load_const(ctx
, buf
,
2132 LLVMConstInt(ctx
->i32
, (offset
+ i
) * 4, 0));
2133 value
= ac_build_gather_values(&ctx
->ac
, val
, 4);
2137 case TGSI_SEMANTIC_PRIMID
:
2138 value
= si_get_primitive_id(ctx
, 0);
2141 case TGSI_SEMANTIC_GRID_SIZE
:
2142 value
= ctx
->abi
.num_work_groups
;
2145 case TGSI_SEMANTIC_BLOCK_SIZE
:
2146 value
= get_block_size(&ctx
->abi
);
2149 case TGSI_SEMANTIC_BLOCK_ID
:
2151 LLVMValueRef values
[3];
2153 for (int i
= 0; i
< 3; i
++) {
2154 values
[i
] = ctx
->i32_0
;
2155 if (ctx
->abi
.workgroup_ids
[i
]) {
2156 values
[i
] = ctx
->abi
.workgroup_ids
[i
];
2159 value
= ac_build_gather_values(&ctx
->ac
, values
, 3);
2163 case TGSI_SEMANTIC_THREAD_ID
:
2164 value
= ctx
->abi
.local_invocation_ids
;
2167 case TGSI_SEMANTIC_HELPER_INVOCATION
:
2168 value
= ac_build_load_helper_invocation(&ctx
->ac
);
2171 case TGSI_SEMANTIC_SUBGROUP_SIZE
:
2172 value
= LLVMConstInt(ctx
->i32
, ctx
->ac
.wave_size
, 0);
2175 case TGSI_SEMANTIC_SUBGROUP_INVOCATION
:
2176 value
= ac_get_thread_id(&ctx
->ac
);
2179 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK
:
2181 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
2182 if (ctx
->ac
.wave_size
== 64)
2183 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
2184 value
= LLVMBuildShl(ctx
->ac
.builder
,
2185 LLVMConstInt(ctx
->ac
.iN_wavemask
, 1, 0), id
, "");
2186 if (ctx
->ac
.wave_size
== 32)
2187 value
= LLVMBuildZExt(ctx
->ac
.builder
, value
, ctx
->i64
, "");
2188 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
2192 case TGSI_SEMANTIC_SUBGROUP_GE_MASK
:
2193 case TGSI_SEMANTIC_SUBGROUP_GT_MASK
:
2194 case TGSI_SEMANTIC_SUBGROUP_LE_MASK
:
2195 case TGSI_SEMANTIC_SUBGROUP_LT_MASK
:
2197 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
2198 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_GT_MASK
||
2199 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
) {
2200 /* All bits set except LSB */
2201 value
= LLVMConstInt(ctx
->ac
.iN_wavemask
, -2, 0);
2204 value
= LLVMConstInt(ctx
->ac
.iN_wavemask
, -1, 0);
2206 if (ctx
->ac
.wave_size
== 64)
2207 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
2208 value
= LLVMBuildShl(ctx
->ac
.builder
, value
, id
, "");
2209 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
||
2210 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LT_MASK
)
2211 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
2212 if (ctx
->ac
.wave_size
== 32)
2213 value
= LLVMBuildZExt(ctx
->ac
.builder
, value
, ctx
->i64
, "");
2214 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
2218 case TGSI_SEMANTIC_CS_USER_DATA_AMD
:
2219 value
= LLVMGetParam(ctx
->main_fn
, ctx
->param_cs_user_data
);
2223 assert(!"unknown system value");
2227 ctx
->system_values
[index
] = value
;
2230 void si_declare_compute_memory(struct si_shader_context
*ctx
)
2232 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2233 unsigned lds_size
= sel
->info
.properties
[TGSI_PROPERTY_CS_LOCAL_SIZE
];
2235 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, AC_ADDR_SPACE_LDS
);
2238 assert(!ctx
->ac
.lds
);
2240 var
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
2241 LLVMArrayType(ctx
->i8
, lds_size
),
2244 LLVMSetAlignment(var
, 64 * 1024);
2246 ctx
->ac
.lds
= LLVMBuildBitCast(ctx
->ac
.builder
, var
, i8p
, "");
2249 void si_tgsi_declare_compute_memory(struct si_shader_context
*ctx
,
2250 const struct tgsi_full_declaration
*decl
)
2252 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
2253 assert(decl
->Range
.First
== decl
->Range
.Last
);
2255 si_declare_compute_memory(ctx
);
2258 static LLVMValueRef
load_const_buffer_desc_fast_path(struct si_shader_context
*ctx
)
2261 LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2262 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2264 /* Do the bounds checking with a descriptor, because
2265 * doing computation and manual bounds checking of 64-bit
2266 * addresses generates horrible VALU code with very high
2267 * VGPR usage and very low SIMD occupancy.
2269 ptr
= LLVMBuildPtrToInt(ctx
->ac
.builder
, ptr
, ctx
->ac
.intptr
, "");
2271 LLVMValueRef desc0
, desc1
;
2273 desc1
= LLVMConstInt(ctx
->i32
,
2274 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0);
2276 uint32_t rsrc3
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2277 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2278 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2279 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2281 if (ctx
->screen
->info
.chip_class
>= GFX10
)
2282 rsrc3
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2283 S_008F0C_OOB_SELECT(3) |
2284 S_008F0C_RESOURCE_LEVEL(1);
2286 rsrc3
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2287 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2289 LLVMValueRef desc_elems
[] = {
2292 LLVMConstInt(ctx
->i32
, (sel
->info
.const_file_max
[0] + 1) * 16, 0),
2293 LLVMConstInt(ctx
->i32
, rsrc3
, false)
2296 return ac_build_gather_values(&ctx
->ac
, desc_elems
, 4);
2299 static LLVMValueRef
load_const_buffer_desc(struct si_shader_context
*ctx
, int i
)
2301 LLVMValueRef list_ptr
= LLVMGetParam(ctx
->main_fn
,
2302 ctx
->param_const_and_shader_buffers
);
2304 return ac_build_load_to_sgpr(&ctx
->ac
, list_ptr
,
2305 LLVMConstInt(ctx
->i32
, si_get_constbuf_slot(i
), 0));
2308 static LLVMValueRef
load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef index
)
2310 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2311 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2313 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2315 if (sel
->info
.const_buffers_declared
== 1 &&
2316 sel
->info
.shader_buffers_declared
== 0) {
2317 return load_const_buffer_desc_fast_path(ctx
);
2320 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_const_buffers
);
2321 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2322 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2324 return ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2328 load_ssbo(struct ac_shader_abi
*abi
, LLVMValueRef index
, bool write
)
2330 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2331 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
2332 ctx
->param_const_and_shader_buffers
);
2334 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_shader_buffers
);
2335 index
= LLVMBuildSub(ctx
->ac
.builder
,
2336 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
- 1, 0),
2339 return ac_build_load_to_sgpr(&ctx
->ac
, rsrc_ptr
, index
);
2342 static LLVMValueRef
fetch_constant(
2343 struct lp_build_tgsi_context
*bld_base
,
2344 const struct tgsi_full_src_register
*reg
,
2345 enum tgsi_opcode_type type
,
2346 unsigned swizzle_in
)
2348 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2349 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2350 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
2352 unsigned swizzle
= swizzle_in
& 0xffff;
2354 LLVMValueRef addr
, bufp
;
2356 if (swizzle_in
== LP_CHAN_ALL
) {
2358 LLVMValueRef values
[4];
2359 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
2360 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
2362 return ac_build_gather_values(&ctx
->ac
, values
, 4);
2365 /* Split 64-bit loads. */
2366 if (tgsi_type_is_64bit(type
)) {
2367 LLVMValueRef lo
, hi
;
2369 lo
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
);
2370 hi
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, (swizzle_in
>> 16));
2371 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
2375 idx
= reg
->Register
.Index
* 4 + swizzle
;
2376 if (reg
->Register
.Indirect
) {
2377 addr
= si_get_indirect_index(ctx
, ireg
, 16, idx
* 4);
2379 addr
= LLVMConstInt(ctx
->i32
, idx
* 4, 0);
2382 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2383 if (sel
->info
.const_buffers_declared
== 1 &&
2384 sel
->info
.shader_buffers_declared
== 0) {
2385 LLVMValueRef desc
= load_const_buffer_desc_fast_path(ctx
);
2386 LLVMValueRef result
= buffer_load_const(ctx
, desc
, addr
);
2387 return bitcast(bld_base
, type
, result
);
2390 assert(reg
->Register
.Dimension
);
2391 buf
= reg
->Dimension
.Index
;
2393 if (reg
->Dimension
.Indirect
) {
2394 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2396 index
= si_get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
2397 reg
->Dimension
.Index
,
2398 ctx
->num_const_buffers
);
2399 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2400 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2401 bufp
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2403 bufp
= load_const_buffer_desc(ctx
, buf
);
2405 return bitcast(bld_base
, type
, buffer_load_const(ctx
, bufp
, addr
));
2408 /* Initialize arguments for the shader export intrinsic */
2409 static void si_llvm_init_export_args(struct si_shader_context
*ctx
,
2410 LLVMValueRef
*values
,
2412 struct ac_export_args
*args
)
2414 LLVMValueRef f32undef
= LLVMGetUndef(ctx
->ac
.f32
);
2415 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
2417 bool is_int8
, is_int10
;
2419 /* Default is 0xf. Adjusted below depending on the format. */
2420 args
->enabled_channels
= 0xf; /* writemask */
2422 /* Specify whether the EXEC mask represents the valid mask */
2423 args
->valid_mask
= 0;
2425 /* Specify whether this is the last export */
2428 /* Specify the target we are exporting */
2429 args
->target
= target
;
2431 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
2432 const struct si_shader_key
*key
= &ctx
->shader
->key
;
2433 unsigned col_formats
= key
->part
.ps
.epilog
.spi_shader_col_format
;
2434 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
2436 assert(cbuf
>= 0 && cbuf
< 8);
2437 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
2438 is_int8
= (key
->part
.ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
2439 is_int10
= (key
->part
.ps
.epilog
.color_is_int10
>> cbuf
) & 0x1;
2442 args
->compr
= false;
2443 args
->out
[0] = f32undef
;
2444 args
->out
[1] = f32undef
;
2445 args
->out
[2] = f32undef
;
2446 args
->out
[3] = f32undef
;
2448 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2449 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2450 unsigned bits
, bool hi
) = NULL
;
2452 switch (spi_shader_col_format
) {
2453 case V_028714_SPI_SHADER_ZERO
:
2454 args
->enabled_channels
= 0; /* writemask */
2455 args
->target
= V_008DFC_SQ_EXP_NULL
;
2458 case V_028714_SPI_SHADER_32_R
:
2459 args
->enabled_channels
= 1; /* writemask */
2460 args
->out
[0] = values
[0];
2463 case V_028714_SPI_SHADER_32_GR
:
2464 args
->enabled_channels
= 0x3; /* writemask */
2465 args
->out
[0] = values
[0];
2466 args
->out
[1] = values
[1];
2469 case V_028714_SPI_SHADER_32_AR
:
2470 if (ctx
->screen
->info
.chip_class
>= GFX10
) {
2471 args
->enabled_channels
= 0x3; /* writemask */
2472 args
->out
[0] = values
[0];
2473 args
->out
[1] = values
[3];
2475 args
->enabled_channels
= 0x9; /* writemask */
2476 args
->out
[0] = values
[0];
2477 args
->out
[3] = values
[3];
2481 case V_028714_SPI_SHADER_FP16_ABGR
:
2482 packf
= ac_build_cvt_pkrtz_f16
;
2485 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2486 packf
= ac_build_cvt_pknorm_u16
;
2489 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2490 packf
= ac_build_cvt_pknorm_i16
;
2493 case V_028714_SPI_SHADER_UINT16_ABGR
:
2494 packi
= ac_build_cvt_pk_u16
;
2497 case V_028714_SPI_SHADER_SINT16_ABGR
:
2498 packi
= ac_build_cvt_pk_i16
;
2501 case V_028714_SPI_SHADER_32_ABGR
:
2502 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2506 /* Pack f16 or norm_i16/u16. */
2508 for (chan
= 0; chan
< 2; chan
++) {
2509 LLVMValueRef pack_args
[2] = {
2511 values
[2 * chan
+ 1]
2513 LLVMValueRef packed
;
2515 packed
= packf(&ctx
->ac
, pack_args
);
2516 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2518 args
->compr
= 1; /* COMPR flag */
2522 for (chan
= 0; chan
< 2; chan
++) {
2523 LLVMValueRef pack_args
[2] = {
2524 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2525 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2527 LLVMValueRef packed
;
2529 packed
= packi(&ctx
->ac
, pack_args
,
2530 is_int8
? 8 : is_int10
? 10 : 16,
2532 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2534 args
->compr
= 1; /* COMPR flag */
2538 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2541 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2543 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2544 static LLVMRealPredicate cond_map
[PIPE_FUNC_ALWAYS
+ 1] = {
2545 [PIPE_FUNC_LESS
] = LLVMRealOLT
,
2546 [PIPE_FUNC_EQUAL
] = LLVMRealOEQ
,
2547 [PIPE_FUNC_LEQUAL
] = LLVMRealOLE
,
2548 [PIPE_FUNC_GREATER
] = LLVMRealOGT
,
2549 [PIPE_FUNC_NOTEQUAL
] = LLVMRealONE
,
2550 [PIPE_FUNC_GEQUAL
] = LLVMRealOGE
,
2552 LLVMRealPredicate cond
= cond_map
[ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
];
2555 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->main_fn
,
2556 SI_PARAM_ALPHA_REF
);
2557 LLVMValueRef alpha_pass
=
2558 LLVMBuildFCmp(ctx
->ac
.builder
, cond
, alpha
, alpha_ref
, "");
2559 ac_build_kill_if_false(&ctx
->ac
, alpha_pass
);
2561 ac_build_kill_if_false(&ctx
->ac
, ctx
->i1false
);
2565 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2567 unsigned samplemask_param
)
2569 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2570 LLVMValueRef coverage
;
2572 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2573 coverage
= LLVMGetParam(ctx
->main_fn
,
2575 coverage
= ac_to_integer(&ctx
->ac
, coverage
);
2577 coverage
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32",
2579 &coverage
, 1, AC_FUNC_ATTR_READNONE
);
2581 coverage
= LLVMBuildUIToFP(ctx
->ac
.builder
, coverage
,
2584 coverage
= LLVMBuildFMul(ctx
->ac
.builder
, coverage
,
2585 LLVMConstReal(ctx
->f32
,
2586 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2588 return LLVMBuildFMul(ctx
->ac
.builder
, alpha
, coverage
, "");
2591 static void si_llvm_emit_clipvertex(struct si_shader_context
*ctx
,
2592 struct ac_export_args
*pos
, LLVMValueRef
*out_elts
)
2596 unsigned const_chan
;
2597 LLVMValueRef base_elt
;
2598 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2599 LLVMValueRef constbuf_index
= LLVMConstInt(ctx
->i32
,
2600 SI_VS_CONST_CLIP_PLANES
, 0);
2601 LLVMValueRef const_resource
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, constbuf_index
);
2603 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2604 struct ac_export_args
*args
= &pos
[2 + reg_index
];
2609 args
->out
[3] = LLVMConstReal(ctx
->f32
, 0.0f
);
2611 /* Compute dot products of position and user clip plane vectors */
2612 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2613 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2615 LLVMConstInt(ctx
->i32
, ((reg_index
* 4 + chan
) * 4 +
2616 const_chan
) * 4, 0);
2617 base_elt
= buffer_load_const(ctx
, const_resource
,
2619 args
->out
[chan
] = ac_build_fmad(&ctx
->ac
, base_elt
,
2620 out_elts
[const_chan
], args
->out
[chan
]);
2624 args
->enabled_channels
= 0xf;
2625 args
->valid_mask
= 0;
2627 args
->target
= V_008DFC_SQ_EXP_POS
+ 2 + reg_index
;
2632 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2636 if (so
->num_outputs
)
2637 fprintf(stderr
, "STREAMOUT\n");
2639 for (i
= 0; i
< so
->num_outputs
; i
++) {
2640 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2641 so
->output
[i
].start_component
;
2642 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2643 i
, so
->output
[i
].output_buffer
,
2644 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2645 so
->output
[i
].register_index
,
2646 mask
& 1 ? "x" : "",
2647 mask
& 2 ? "y" : "",
2648 mask
& 4 ? "z" : "",
2649 mask
& 8 ? "w" : "");
2653 void si_emit_streamout_output(struct si_shader_context
*ctx
,
2654 LLVMValueRef
const *so_buffers
,
2655 LLVMValueRef
const *so_write_offsets
,
2656 struct pipe_stream_output
*stream_out
,
2657 struct si_shader_output_values
*shader_out
)
2659 unsigned buf_idx
= stream_out
->output_buffer
;
2660 unsigned start
= stream_out
->start_component
;
2661 unsigned num_comps
= stream_out
->num_components
;
2662 LLVMValueRef out
[4];
2664 assert(num_comps
&& num_comps
<= 4);
2665 if (!num_comps
|| num_comps
> 4)
2668 /* Load the output as int. */
2669 for (int j
= 0; j
< num_comps
; j
++) {
2670 assert(stream_out
->stream
== shader_out
->vertex_stream
[start
+ j
]);
2672 out
[j
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ j
]);
2675 /* Pack the output. */
2676 LLVMValueRef vdata
= NULL
;
2678 switch (num_comps
) {
2679 case 1: /* as i32 */
2682 case 2: /* as v2i32 */
2683 case 3: /* as v3i32 */
2684 if (ac_has_vec3_support(ctx
->screen
->info
.chip_class
, false)) {
2685 vdata
= ac_build_gather_values(&ctx
->ac
, out
, num_comps
);
2688 /* as v4i32 (aligned to 4) */
2689 out
[3] = LLVMGetUndef(ctx
->i32
);
2691 case 4: /* as v4i32 */
2692 vdata
= ac_build_gather_values(&ctx
->ac
, out
, util_next_power_of_two(num_comps
));
2696 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf_idx
],
2698 so_write_offsets
[buf_idx
],
2700 stream_out
->dst_offset
* 4, ac_glc
| ac_slc
, false);
2704 * Write streamout data to buffers for vertex stream @p stream (different
2705 * vertex streams can occur for GS copy shaders).
2707 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2708 struct si_shader_output_values
*outputs
,
2709 unsigned noutput
, unsigned stream
)
2711 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2712 struct pipe_stream_output_info
*so
= &sel
->so
;
2713 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2716 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2717 LLVMValueRef so_vtx_count
=
2718 si_unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2720 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2722 /* can_emit = tid < so_vtx_count; */
2723 LLVMValueRef can_emit
=
2724 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2726 /* Emit the streamout code conditionally. This actually avoids
2727 * out-of-bounds buffer access. The hw tells us via the SGPR
2728 * (so_vtx_count) which threads are allowed to emit streamout data. */
2729 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
2731 /* The buffer offset is computed as follows:
2732 * ByteOffset = streamout_offset[buffer_id]*4 +
2733 * (streamout_write_index + thread_id)*stride[buffer_id] +
2737 LLVMValueRef so_write_index
=
2738 LLVMGetParam(ctx
->main_fn
,
2739 ctx
->param_streamout_write_index
);
2741 /* Compute (streamout_write_index + thread_id). */
2742 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2744 /* Load the descriptor and compute the write offset for each
2745 * enabled buffer. */
2746 LLVMValueRef so_write_offset
[4] = {};
2747 LLVMValueRef so_buffers
[4];
2748 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
2749 ctx
->param_rw_buffers
);
2751 for (i
= 0; i
< 4; i
++) {
2755 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
,
2756 SI_VS_STREAMOUT_BUF0
+ i
, 0);
2758 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
2760 LLVMValueRef so_offset
= LLVMGetParam(ctx
->main_fn
,
2761 ctx
->param_streamout_offset
[i
]);
2762 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2764 so_write_offset
[i
] = ac_build_imad(&ctx
->ac
, so_write_index
,
2765 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0),
2769 /* Write streamout data. */
2770 for (i
= 0; i
< so
->num_outputs
; i
++) {
2771 unsigned reg
= so
->output
[i
].register_index
;
2776 if (stream
!= so
->output
[i
].stream
)
2779 si_emit_streamout_output(ctx
, so_buffers
, so_write_offset
,
2780 &so
->output
[i
], &outputs
[reg
]);
2783 ac_build_endif(&ctx
->ac
, 6501);
2786 static void si_export_param(struct si_shader_context
*ctx
, unsigned index
,
2787 LLVMValueRef
*values
)
2789 struct ac_export_args args
;
2791 si_llvm_init_export_args(ctx
, values
,
2792 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2793 ac_build_export(&ctx
->ac
, &args
);
2796 static void si_build_param_exports(struct si_shader_context
*ctx
,
2797 struct si_shader_output_values
*outputs
,
2800 struct si_shader
*shader
= ctx
->shader
;
2801 unsigned param_count
= 0;
2803 for (unsigned i
= 0; i
< noutput
; i
++) {
2804 unsigned semantic_name
= outputs
[i
].semantic_name
;
2805 unsigned semantic_index
= outputs
[i
].semantic_index
;
2807 if (outputs
[i
].vertex_stream
[0] != 0 &&
2808 outputs
[i
].vertex_stream
[1] != 0 &&
2809 outputs
[i
].vertex_stream
[2] != 0 &&
2810 outputs
[i
].vertex_stream
[3] != 0)
2813 switch (semantic_name
) {
2814 case TGSI_SEMANTIC_LAYER
:
2815 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2816 case TGSI_SEMANTIC_CLIPDIST
:
2817 case TGSI_SEMANTIC_COLOR
:
2818 case TGSI_SEMANTIC_BCOLOR
:
2819 case TGSI_SEMANTIC_PRIMID
:
2820 case TGSI_SEMANTIC_FOG
:
2821 case TGSI_SEMANTIC_TEXCOORD
:
2822 case TGSI_SEMANTIC_GENERIC
:
2828 if ((semantic_name
!= TGSI_SEMANTIC_GENERIC
||
2829 semantic_index
< SI_MAX_IO_GENERIC
) &&
2830 shader
->key
.opt
.kill_outputs
&
2831 (1ull << si_shader_io_get_unique_index(semantic_name
,
2832 semantic_index
, true)))
2835 si_export_param(ctx
, param_count
, outputs
[i
].values
);
2837 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2838 shader
->info
.vs_output_param_offset
[i
] = param_count
++;
2841 shader
->info
.nr_param_exports
= param_count
;
2845 * Vertex color clamping.
2847 * This uses a state constant loaded in a user data SGPR and
2848 * an IF statement is added that clamps all colors if the constant
2851 static void si_vertex_color_clamping(struct si_shader_context
*ctx
,
2852 struct si_shader_output_values
*outputs
,
2855 LLVMValueRef addr
[SI_MAX_VS_OUTPUTS
][4];
2856 bool has_colors
= false;
2858 /* Store original colors to alloca variables. */
2859 for (unsigned i
= 0; i
< noutput
; i
++) {
2860 if (outputs
[i
].semantic_name
!= TGSI_SEMANTIC_COLOR
&&
2861 outputs
[i
].semantic_name
!= TGSI_SEMANTIC_BCOLOR
)
2864 for (unsigned j
= 0; j
< 4; j
++) {
2865 addr
[i
][j
] = ac_build_alloca_undef(&ctx
->ac
, ctx
->f32
, "");
2866 LLVMBuildStore(ctx
->ac
.builder
, outputs
[i
].values
[j
], addr
[i
][j
]);
2874 /* The state is in the first bit of the user SGPR. */
2875 LLVMValueRef cond
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vs_state_bits
);
2876 cond
= LLVMBuildTrunc(ctx
->ac
.builder
, cond
, ctx
->i1
, "");
2878 ac_build_ifcc(&ctx
->ac
, cond
, 6502);
2880 /* Store clamped colors to alloca variables within the conditional block. */
2881 for (unsigned i
= 0; i
< noutput
; i
++) {
2882 if (outputs
[i
].semantic_name
!= TGSI_SEMANTIC_COLOR
&&
2883 outputs
[i
].semantic_name
!= TGSI_SEMANTIC_BCOLOR
)
2886 for (unsigned j
= 0; j
< 4; j
++) {
2887 LLVMBuildStore(ctx
->ac
.builder
,
2888 ac_build_clamp(&ctx
->ac
, outputs
[i
].values
[j
]),
2892 ac_build_endif(&ctx
->ac
, 6502);
2894 /* Load clamped colors */
2895 for (unsigned i
= 0; i
< noutput
; i
++) {
2896 if (outputs
[i
].semantic_name
!= TGSI_SEMANTIC_COLOR
&&
2897 outputs
[i
].semantic_name
!= TGSI_SEMANTIC_BCOLOR
)
2900 for (unsigned j
= 0; j
< 4; j
++) {
2901 outputs
[i
].values
[j
] =
2902 LLVMBuildLoad(ctx
->ac
.builder
, addr
[i
][j
], "");
2907 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2908 * (position and parameter data only).
2910 void si_llvm_export_vs(struct si_shader_context
*ctx
,
2911 struct si_shader_output_values
*outputs
,