radeonsi/nir: always lower ballot masks as 64-bit, codegen handles it
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_from_mesa.h"
32
33 #include "ac_binary.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
36 #include "ac_rtld.h"
37 #include "ac_llvm_util.h"
38 #include "si_shader_internal.h"
39 #include "si_pipe.h"
40 #include "sid.h"
41
42 #include "compiler/nir/nir.h"
43
44 static const char scratch_rsrc_dword0_symbol[] =
45 "SCRATCH_RSRC_DWORD0";
46
47 static const char scratch_rsrc_dword1_symbol[] =
48 "SCRATCH_RSRC_DWORD1";
49
50 static void si_init_shader_ctx(struct si_shader_context *ctx,
51 struct si_screen *sscreen,
52 struct ac_llvm_compiler *compiler,
53 unsigned wave_size,
54 bool nir);
55
56 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
57 struct lp_build_tgsi_context *bld_base,
58 struct lp_build_emit_data *emit_data);
59
60 static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
61
62 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
63 union si_shader_part_key *key);
64 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
65 union si_shader_part_key *key);
66 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
67 union si_shader_part_key *key);
68 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
69 union si_shader_part_key *key);
70 static void si_fix_resource_usage(struct si_screen *sscreen,
71 struct si_shader *shader);
72
73 /* Ideally pass the sample mask input to the PS epilog as v14, which
74 * is its usual location, so that the shader doesn't have to add v_mov.
75 */
76 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
77
78 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
79 LLVMTypeRef type)
80 {
81 if (type == ctx->ac.i64 || type == ctx->ac.f64)
82 return true;
83
84 return false;
85 }
86
87 /** Whether the shader runs as a combination of multiple API shaders */
88 static bool is_multi_part_shader(struct si_shader_context *ctx)
89 {
90 if (ctx->screen->info.chip_class <= GFX8)
91 return false;
92
93 return ctx->shader->key.as_ls ||
94 ctx->shader->key.as_es ||
95 ctx->type == PIPE_SHADER_TESS_CTRL ||
96 ctx->type == PIPE_SHADER_GEOMETRY;
97 }
98
99 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
100 static bool is_merged_shader(struct si_shader_context *ctx)
101 {
102 return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
103 }
104
105 void si_init_function_info(struct si_function_info *fninfo)
106 {
107 fninfo->num_params = 0;
108 fninfo->num_sgpr_params = 0;
109 }
110
111 unsigned add_arg_assign(struct si_function_info *fninfo,
112 enum si_arg_regfile regfile, LLVMTypeRef type,
113 LLVMValueRef *assign)
114 {
115 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
116
117 unsigned idx = fninfo->num_params++;
118 assert(idx < ARRAY_SIZE(fninfo->types));
119
120 if (regfile == ARG_SGPR)
121 fninfo->num_sgpr_params = fninfo->num_params;
122
123 fninfo->types[idx] = type;
124 fninfo->assign[idx] = assign;
125 return idx;
126 }
127
128 static unsigned add_arg(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type)
130 {
131 return add_arg_assign(fninfo, regfile, type, NULL);
132 }
133
134 static void add_arg_assign_checked(struct si_function_info *fninfo,
135 enum si_arg_regfile regfile, LLVMTypeRef type,
136 LLVMValueRef *assign, unsigned idx)
137 {
138 ASSERTED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
139 assert(actual == idx);
140 }
141
142 static void add_arg_checked(struct si_function_info *fninfo,
143 enum si_arg_regfile regfile, LLVMTypeRef type,
144 unsigned idx)
145 {
146 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
147 }
148
149 /**
150 * Returns a unique index for a per-patch semantic name and index. The index
151 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
152 * can be calculated.
153 */
154 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
155 {
156 switch (semantic_name) {
157 case TGSI_SEMANTIC_TESSOUTER:
158 return 0;
159 case TGSI_SEMANTIC_TESSINNER:
160 return 1;
161 case TGSI_SEMANTIC_PATCH:
162 assert(index < 30);
163 return 2 + index;
164
165 default:
166 assert(!"invalid semantic name");
167 return 0;
168 }
169 }
170
171 /**
172 * Returns a unique index for a semantic name and index. The index must be
173 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
174 * calculated.
175 */
176 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
177 unsigned is_varying)
178 {
179 switch (semantic_name) {
180 case TGSI_SEMANTIC_POSITION:
181 return 0;
182 case TGSI_SEMANTIC_GENERIC:
183 /* Since some shader stages use the the highest used IO index
184 * to determine the size to allocate for inputs/outputs
185 * (in LDS, tess and GS rings). GENERIC should be placed right
186 * after POSITION to make that size as small as possible.
187 */
188 if (index < SI_MAX_IO_GENERIC)
189 return 1 + index;
190
191 assert(!"invalid generic index");
192 return 0;
193 case TGSI_SEMANTIC_FOG:
194 return SI_MAX_IO_GENERIC + 1;
195 case TGSI_SEMANTIC_COLOR:
196 assert(index < 2);
197 return SI_MAX_IO_GENERIC + 2 + index;
198 case TGSI_SEMANTIC_BCOLOR:
199 assert(index < 2);
200 /* If it's a varying, COLOR and BCOLOR alias. */
201 if (is_varying)
202 return SI_MAX_IO_GENERIC + 2 + index;
203 else
204 return SI_MAX_IO_GENERIC + 4 + index;
205 case TGSI_SEMANTIC_TEXCOORD:
206 assert(index < 8);
207 return SI_MAX_IO_GENERIC + 6 + index;
208
209 /* These are rarely used between LS and HS or ES and GS. */
210 case TGSI_SEMANTIC_CLIPDIST:
211 assert(index < 2);
212 return SI_MAX_IO_GENERIC + 6 + 8 + index;
213 case TGSI_SEMANTIC_CLIPVERTEX:
214 return SI_MAX_IO_GENERIC + 6 + 8 + 2;
215 case TGSI_SEMANTIC_PSIZE:
216 return SI_MAX_IO_GENERIC + 6 + 8 + 3;
217
218 /* These can't be written by LS, HS, and ES. */
219 case TGSI_SEMANTIC_LAYER:
220 return SI_MAX_IO_GENERIC + 6 + 8 + 4;
221 case TGSI_SEMANTIC_VIEWPORT_INDEX:
222 return SI_MAX_IO_GENERIC + 6 + 8 + 5;
223 case TGSI_SEMANTIC_PRIMID:
224 STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
225 return SI_MAX_IO_GENERIC + 6 + 8 + 6;
226 default:
227 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
228 assert(!"invalid semantic name");
229 return 0;
230 }
231 }
232
233 /**
234 * Get the value of a shader input parameter and extract a bitfield.
235 */
236 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
237 LLVMValueRef value, unsigned rshift,
238 unsigned bitwidth)
239 {
240 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
241 value = ac_to_integer(&ctx->ac, value);
242
243 if (rshift)
244 value = LLVMBuildLShr(ctx->ac.builder, value,
245 LLVMConstInt(ctx->i32, rshift, 0), "");
246
247 if (rshift + bitwidth < 32) {
248 unsigned mask = (1 << bitwidth) - 1;
249 value = LLVMBuildAnd(ctx->ac.builder, value,
250 LLVMConstInt(ctx->i32, mask, 0), "");
251 }
252
253 return value;
254 }
255
256 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
257 unsigned param, unsigned rshift,
258 unsigned bitwidth)
259 {
260 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
261
262 return unpack_llvm_param(ctx, value, rshift, bitwidth);
263 }
264
265 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
266 {
267 switch (ctx->type) {
268 case PIPE_SHADER_TESS_CTRL:
269 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
270
271 case PIPE_SHADER_TESS_EVAL:
272 return LLVMGetParam(ctx->main_fn,
273 ctx->param_tes_rel_patch_id);
274
275 default:
276 assert(0);
277 return NULL;
278 }
279 }
280
281 /* Tessellation shaders pass outputs to the next shader using LDS.
282 *
283 * LS outputs = TCS inputs
284 * TCS outputs = TES inputs
285 *
286 * The LDS layout is:
287 * - TCS inputs for patch 0
288 * - TCS inputs for patch 1
289 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
290 * - ...
291 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
292 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
293 * - TCS outputs for patch 1
294 * - Per-patch TCS outputs for patch 1
295 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
296 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
297 * - ...
298 *
299 * All three shaders VS(LS), TCS, TES share the same LDS space.
300 */
301
302 static LLVMValueRef
303 get_tcs_in_patch_stride(struct si_shader_context *ctx)
304 {
305 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
306 }
307
308 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
309 {
310 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
311
312 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
313 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
314
315 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
316 }
317
318 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
319 {
320 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
321
322 return LLVMConstInt(ctx->i32, stride, 0);
323 }
324
325 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
326 {
327 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
328 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
329
330 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
331 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
332 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
333 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
334 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
335 num_patch_outputs * 4;
336 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
337 }
338
339 static LLVMValueRef
340 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
341 {
342 return LLVMBuildMul(ctx->ac.builder,
343 si_unpack_param(ctx,
344 ctx->param_tcs_out_lds_offsets,
345 0, 16),
346 LLVMConstInt(ctx->i32, 4, 0), "");
347 }
348
349 static LLVMValueRef
350 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
351 {
352 return LLVMBuildMul(ctx->ac.builder,
353 si_unpack_param(ctx,
354 ctx->param_tcs_out_lds_offsets,
355 16, 16),
356 LLVMConstInt(ctx->i32, 4, 0), "");
357 }
358
359 static LLVMValueRef
360 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
361 {
362 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
363 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
364
365 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
366 }
367
368 static LLVMValueRef
369 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
370 {
371 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
372 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
373 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
374
375 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
376 }
377
378 static LLVMValueRef
379 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
380 {
381 LLVMValueRef patch0_patch_data_offset =
382 get_tcs_out_patch0_patch_data_offset(ctx);
383 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
384 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
385
386 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
387 }
388
389 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
390 {
391 unsigned tcs_out_vertices =
392 ctx->shader->selector ?
393 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
394
395 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
396 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
397 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
398
399 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
400 }
401
402 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
403 {
404 unsigned stride;
405
406 switch (ctx->type) {
407 case PIPE_SHADER_VERTEX:
408 stride = ctx->shader->selector->lshs_vertex_stride / 4;
409 return LLVMConstInt(ctx->i32, stride, 0);
410
411 case PIPE_SHADER_TESS_CTRL:
412 if (ctx->screen->info.chip_class >= GFX9 &&
413 ctx->shader->is_monolithic) {
414 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
415 return LLVMConstInt(ctx->i32, stride, 0);
416 }
417 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
418
419 default:
420 assert(0);
421 return NULL;
422 }
423 }
424
425 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
426 LLVMValueRef i32, unsigned index)
427 {
428 assert(index <= 1);
429
430 if (index == 1)
431 return LLVMBuildAShr(ctx->ac.builder, i32,
432 LLVMConstInt(ctx->i32, 16, 0), "");
433
434 return LLVMBuildSExt(ctx->ac.builder,
435 LLVMBuildTrunc(ctx->ac.builder, i32,
436 ctx->ac.i16, ""),
437 ctx->i32, "");
438 }
439
440 void si_llvm_load_input_vs(
441 struct si_shader_context *ctx,
442 unsigned input_index,
443 LLVMValueRef out[4])
444 {
445 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
446 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
447
448 if (vs_blit_property) {
449 LLVMValueRef vertex_id = ctx->abi.vertex_id;
450 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
451 LLVMIntULE, vertex_id,
452 ctx->i32_1, "");
453 /* Use LLVMIntNE, because we have 3 vertices and only
454 * the middle one should use y2.
455 */
456 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
457 LLVMIntNE, vertex_id,
458 ctx->i32_1, "");
459
460 if (input_index == 0) {
461 /* Position: */
462 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
463 ctx->param_vs_blit_inputs);
464 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
465 ctx->param_vs_blit_inputs + 1);
466
467 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
468 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
469 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
470 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
471
472 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
473 x1, x2, "");
474 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
475 y1, y2, "");
476
477 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
478 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
479 out[2] = LLVMGetParam(ctx->main_fn,
480 ctx->param_vs_blit_inputs + 2);
481 out[3] = ctx->ac.f32_1;
482 return;
483 }
484
485 /* Color or texture coordinates: */
486 assert(input_index == 1);
487
488 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
489 for (int i = 0; i < 4; i++) {
490 out[i] = LLVMGetParam(ctx->main_fn,
491 ctx->param_vs_blit_inputs + 3 + i);
492 }
493 } else {
494 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
495 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
496 ctx->param_vs_blit_inputs + 3);
497 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
498 ctx->param_vs_blit_inputs + 4);
499 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
500 ctx->param_vs_blit_inputs + 5);
501 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs + 6);
503
504 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
505 x1, x2, "");
506 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
507 y1, y2, "");
508 out[2] = LLVMGetParam(ctx->main_fn,
509 ctx->param_vs_blit_inputs + 7);
510 out[3] = LLVMGetParam(ctx->main_fn,
511 ctx->param_vs_blit_inputs + 8);
512 }
513 return;
514 }
515
516 union si_vs_fix_fetch fix_fetch;
517 LLVMValueRef t_list_ptr;
518 LLVMValueRef t_offset;
519 LLVMValueRef t_list;
520 LLVMValueRef vertex_index;
521 LLVMValueRef tmp;
522
523 /* Load the T list */
524 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
525
526 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
527
528 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
529
530 vertex_index = LLVMGetParam(ctx->main_fn,
531 ctx->param_vertex_index0 +
532 input_index);
533
534 /* Use the open-coded implementation for all loads of doubles and
535 * of dword-sized data that needs fixups. We need to insert conversion
536 * code anyway, and the amd/common code does it for us.
537 *
538 * Note: On LLVM <= 8, we can only open-code formats with
539 * channel size >= 4 bytes.
540 */
541 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
542 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
543 if (opencode ||
544 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
545 (fix_fetch.u.log_size == 2)) {
546 tmp = ac_build_opencoded_load_format(
547 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
548 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
549 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
550 for (unsigned i = 0; i < 4; ++i)
551 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
552 return;
553 }
554
555 /* Do multiple loads for special formats. */
556 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
557 LLVMValueRef fetches[4];
558 unsigned num_fetches;
559 unsigned fetch_stride;
560 unsigned channels_per_fetch;
561
562 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
563 num_fetches = MIN2(required_channels, 3);
564 fetch_stride = 1 << fix_fetch.u.log_size;
565 channels_per_fetch = 1;
566 } else {
567 num_fetches = 1;
568 fetch_stride = 0;
569 channels_per_fetch = required_channels;
570 }
571
572 for (unsigned i = 0; i < num_fetches; ++i) {
573 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
574 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
575 channels_per_fetch, 0, true);
576 }
577
578 if (num_fetches == 1 && channels_per_fetch > 1) {
579 LLVMValueRef fetch = fetches[0];
580 for (unsigned i = 0; i < channels_per_fetch; ++i) {
581 tmp = LLVMConstInt(ctx->i32, i, false);
582 fetches[i] = LLVMBuildExtractElement(
583 ctx->ac.builder, fetch, tmp, "");
584 }
585 num_fetches = channels_per_fetch;
586 channels_per_fetch = 1;
587 }
588
589 for (unsigned i = num_fetches; i < 4; ++i)
590 fetches[i] = LLVMGetUndef(ctx->f32);
591
592 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
593 required_channels == 4) {
594 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
595 fetches[3] = ctx->ac.i32_1;
596 else
597 fetches[3] = ctx->ac.f32_1;
598 } else if (fix_fetch.u.log_size == 3 &&
599 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
600 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
601 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
602 required_channels == 4) {
603 /* For 2_10_10_10, the hardware returns an unsigned value;
604 * convert it to a signed one.
605 */
606 LLVMValueRef tmp = fetches[3];
607 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
608
609 /* First, recover the sign-extended signed integer value. */
610 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
611 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
612 else
613 tmp = ac_to_integer(&ctx->ac, tmp);
614
615 /* For the integer-like cases, do a natural sign extension.
616 *
617 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
618 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
619 * exponent.
620 */
621 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
622 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
623 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
624 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
625
626 /* Convert back to the right type. */
627 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
628 LLVMValueRef clamp;
629 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
630 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
631 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
632 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
633 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
634 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
635 }
636
637 fetches[3] = tmp;
638 }
639
640 for (unsigned i = 0; i < 4; ++i)
641 out[i] = ac_to_float(&ctx->ac, fetches[i]);
642 }
643
644 static void declare_input_vs(
645 struct si_shader_context *ctx,
646 unsigned input_index,
647 const struct tgsi_full_declaration *decl,
648 LLVMValueRef out[4])
649 {
650 si_llvm_load_input_vs(ctx, input_index, out);
651 }
652
653 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
654 unsigned swizzle)
655 {
656 if (swizzle > 0)
657 return ctx->i32_0;
658
659 switch (ctx->type) {
660 case PIPE_SHADER_VERTEX:
661 return LLVMGetParam(ctx->main_fn,
662 ctx->param_vs_prim_id);
663 case PIPE_SHADER_TESS_CTRL:
664 return ctx->abi.tcs_patch_id;
665 case PIPE_SHADER_TESS_EVAL:
666 return ctx->abi.tes_patch_id;
667 case PIPE_SHADER_GEOMETRY:
668 return ctx->abi.gs_prim_id;
669 default:
670 assert(0);
671 return ctx->i32_0;
672 }
673 }
674
675 /**
676 * Return the value of tgsi_ind_register for indexing.
677 * This is the indirect index with the constant offset added to it.
678 */
679 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
680 const struct tgsi_ind_register *ind,
681 unsigned addr_mul,
682 int rel_index)
683 {
684 LLVMValueRef result;
685
686 if (ind->File == TGSI_FILE_ADDRESS) {
687 result = ctx->addrs[ind->Index][ind->Swizzle];
688 result = LLVMBuildLoad(ctx->ac.builder, result, "");
689 } else {
690 struct tgsi_full_src_register src = {};
691
692 src.Register.File = ind->File;
693 src.Register.Index = ind->Index;
694
695 /* Set the second index to 0 for constants. */
696 if (ind->File == TGSI_FILE_CONSTANT)
697 src.Register.Dimension = 1;
698
699 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
700 TGSI_TYPE_SIGNED,
701 ind->Swizzle);
702 result = ac_to_integer(&ctx->ac, result);
703 }
704
705 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
706 LLVMConstInt(ctx->i32, rel_index, 0));
707 }
708
709 /**
710 * Like si_get_indirect_index, but restricts the return value to a (possibly
711 * undefined) value inside [0..num).
712 */
713 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
714 const struct tgsi_ind_register *ind,
715 int rel_index, unsigned num)
716 {
717 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
718
719 return si_llvm_bound_index(ctx, result, num);
720 }
721
722 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
723 LLVMValueRef vertex_dw_stride,
724 LLVMValueRef base_addr,
725 LLVMValueRef vertex_index,
726 LLVMValueRef param_index,
727 unsigned input_index,
728 ubyte *name,
729 ubyte *index,
730 bool is_patch)
731 {
732 if (vertex_dw_stride) {
733 base_addr = ac_build_imad(&ctx->ac, vertex_index,
734 vertex_dw_stride, base_addr);
735 }
736
737 if (param_index) {
738 base_addr = ac_build_imad(&ctx->ac, param_index,
739 LLVMConstInt(ctx->i32, 4, 0), base_addr);
740 }
741
742 int param = is_patch ?
743 si_shader_io_get_unique_index_patch(name[input_index],
744 index[input_index]) :
745 si_shader_io_get_unique_index(name[input_index],
746 index[input_index], false);
747
748 /* Add the base address of the element. */
749 return LLVMBuildAdd(ctx->ac.builder, base_addr,
750 LLVMConstInt(ctx->i32, param * 4, 0), "");
751 }
752
753 /**
754 * Calculate a dword address given an input or output register and a stride.
755 */
756 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
757 const struct tgsi_full_dst_register *dst,
758 const struct tgsi_full_src_register *src,
759 LLVMValueRef vertex_dw_stride,
760 LLVMValueRef base_addr)
761 {
762 struct tgsi_shader_info *info = &ctx->shader->selector->info;
763 ubyte *name, *index, *array_first;
764 int input_index;
765 struct tgsi_full_dst_register reg;
766 LLVMValueRef vertex_index = NULL;
767 LLVMValueRef ind_index = NULL;
768
769 /* Set the register description. The address computation is the same
770 * for sources and destinations. */
771 if (src) {
772 reg.Register.File = src->Register.File;
773 reg.Register.Index = src->Register.Index;
774 reg.Register.Indirect = src->Register.Indirect;
775 reg.Register.Dimension = src->Register.Dimension;
776 reg.Indirect = src->Indirect;
777 reg.Dimension = src->Dimension;
778 reg.DimIndirect = src->DimIndirect;
779 } else
780 reg = *dst;
781
782 /* If the register is 2-dimensional (e.g. an array of vertices
783 * in a primitive), calculate the base address of the vertex. */
784 if (reg.Register.Dimension) {
785 if (reg.Dimension.Indirect)
786 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
787 1, reg.Dimension.Index);
788 else
789 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
790 }
791
792 /* Get information about the register. */
793 if (reg.Register.File == TGSI_FILE_INPUT) {
794 name = info->input_semantic_name;
795 index = info->input_semantic_index;
796 array_first = info->input_array_first;
797 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
798 name = info->output_semantic_name;
799 index = info->output_semantic_index;
800 array_first = info->output_array_first;
801 } else {
802 assert(0);
803 return NULL;
804 }
805
806 if (reg.Register.Indirect) {
807 /* Add the relative address of the element. */
808 if (reg.Indirect.ArrayID)
809 input_index = array_first[reg.Indirect.ArrayID];
810 else
811 input_index = reg.Register.Index;
812
813 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
814 1, reg.Register.Index - input_index);
815 } else {
816 input_index = reg.Register.Index;
817 }
818
819 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
820 base_addr, vertex_index,
821 ind_index, input_index,
822 name, index,
823 !reg.Register.Dimension);
824 }
825
826 /* The offchip buffer layout for TCS->TES is
827 *
828 * - attribute 0 of patch 0 vertex 0
829 * - attribute 0 of patch 0 vertex 1
830 * - attribute 0 of patch 0 vertex 2
831 * ...
832 * - attribute 0 of patch 1 vertex 0
833 * - attribute 0 of patch 1 vertex 1
834 * ...
835 * - attribute 1 of patch 0 vertex 0
836 * - attribute 1 of patch 0 vertex 1
837 * ...
838 * - per patch attribute 0 of patch 0
839 * - per patch attribute 0 of patch 1
840 * ...
841 *
842 * Note that every attribute has 4 components.
843 */
844 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
845 LLVMValueRef rel_patch_id,
846 LLVMValueRef vertex_index,
847 LLVMValueRef param_index)
848 {
849 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
850 LLVMValueRef param_stride, constant16;
851
852 vertices_per_patch = get_num_tcs_out_vertices(ctx);
853 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
854 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
855 num_patches, "");
856
857 constant16 = LLVMConstInt(ctx->i32, 16, 0);
858 if (vertex_index) {
859 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
860 vertices_per_patch, vertex_index);
861 param_stride = total_vertices;
862 } else {
863 base_addr = rel_patch_id;
864 param_stride = num_patches;
865 }
866
867 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
868 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
869
870 if (!vertex_index) {
871 LLVMValueRef patch_data_offset =
872 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
873
874 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
875 patch_data_offset, "");
876 }
877 return base_addr;
878 }
879
880 /* This is a generic helper that can be shared by the NIR and TGSI backends */
881 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
882 struct si_shader_context *ctx,
883 LLVMValueRef vertex_index,
884 LLVMValueRef param_index,
885 unsigned param_base,
886 ubyte *name,
887 ubyte *index,
888 bool is_patch)
889 {
890 unsigned param_index_base;
891
892 param_index_base = is_patch ?
893 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
894 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
895
896 if (param_index) {
897 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
898 LLVMConstInt(ctx->i32, param_index_base, 0),
899 "");
900 } else {
901 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
902 }
903
904 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
905 vertex_index, param_index);
906 }
907
908 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
909 struct si_shader_context *ctx,
910 const struct tgsi_full_dst_register *dst,
911 const struct tgsi_full_src_register *src)
912 {
913 struct tgsi_shader_info *info = &ctx->shader->selector->info;
914 ubyte *name, *index, *array_first;
915 struct tgsi_full_src_register reg;
916 LLVMValueRef vertex_index = NULL;
917 LLVMValueRef param_index = NULL;
918 unsigned param_base;
919
920 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
921
922 if (reg.Register.Dimension) {
923
924 if (reg.Dimension.Indirect)
925 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
926 1, reg.Dimension.Index);
927 else
928 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
929 }
930
931 /* Get information about the register. */
932 if (reg.Register.File == TGSI_FILE_INPUT) {
933 name = info->input_semantic_name;
934 index = info->input_semantic_index;
935 array_first = info->input_array_first;
936 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
937 name = info->output_semantic_name;
938 index = info->output_semantic_index;
939 array_first = info->output_array_first;
940 } else {
941 assert(0);
942 return NULL;
943 }
944
945 if (reg.Register.Indirect) {
946 if (reg.Indirect.ArrayID)
947 param_base = array_first[reg.Indirect.ArrayID];
948 else
949 param_base = reg.Register.Index;
950
951 param_index = si_get_indirect_index(ctx, &reg.Indirect,
952 1, reg.Register.Index - param_base);
953
954 } else {
955 param_base = reg.Register.Index;
956 }
957
958 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
959 param_index, param_base,
960 name, index, !reg.Register.Dimension);
961 }
962
963 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
964 LLVMTypeRef type, unsigned swizzle,
965 LLVMValueRef buffer, LLVMValueRef offset,
966 LLVMValueRef base, bool can_speculate)
967 {
968 struct si_shader_context *ctx = si_shader_context(bld_base);
969 LLVMValueRef value, value2;
970 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
971
972 if (swizzle == ~0) {
973 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
974 0, ac_glc, can_speculate, false);
975
976 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
977 }
978
979 if (!llvm_type_is_64bit(ctx, type)) {
980 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
981 0, ac_glc, can_speculate, false);
982
983 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
984 return LLVMBuildExtractElement(ctx->ac.builder, value,
985 LLVMConstInt(ctx->i32, swizzle, 0), "");
986 }
987
988 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
989 swizzle * 4, ac_glc, can_speculate, false);
990
991 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
992 swizzle * 4 + 4, ac_glc, can_speculate, false);
993
994 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
995 }
996
997 /**
998 * Load from LSHS LDS storage.
999 *
1000 * \param type output value type
1001 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1002 * \param dw_addr address in dwords
1003 */
1004 static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
1005 LLVMTypeRef type, unsigned swizzle,
1006 LLVMValueRef dw_addr)
1007 {
1008 struct si_shader_context *ctx = si_shader_context(bld_base);
1009 LLVMValueRef value;
1010
1011 if (swizzle == ~0) {
1012 LLVMValueRef values[TGSI_NUM_CHANNELS];
1013
1014 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1015 values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);
1016
1017 return ac_build_gather_values(&ctx->ac, values,
1018 TGSI_NUM_CHANNELS);
1019 }
1020
1021 /* Split 64-bit loads. */
1022 if (llvm_type_is_64bit(ctx, type)) {
1023 LLVMValueRef lo, hi;
1024
1025 lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1026 hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1027 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1028 }
1029
1030 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1031 LLVMConstInt(ctx->i32, swizzle, 0), "");
1032
1033 value = ac_lds_load(&ctx->ac, dw_addr);
1034
1035 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1036 }
1037
1038 /**
1039 * Store to LSHS LDS storage.
1040 *
1041 * \param swizzle offset (typically 0..3)
1042 * \param dw_addr address in dwords
1043 * \param value value to store
1044 */
1045 static void lshs_lds_store(struct si_shader_context *ctx,
1046 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1047 LLVMValueRef value)
1048 {
1049 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1050 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1051
1052 ac_lds_store(&ctx->ac, dw_addr, value);
1053 }
1054
1055 enum si_tess_ring {
1056 TCS_FACTOR_RING,
1057 TESS_OFFCHIP_RING_TCS,
1058 TESS_OFFCHIP_RING_TES,
1059 };
1060
1061 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1062 enum si_tess_ring ring)
1063 {
1064 LLVMBuilderRef builder = ctx->ac.builder;
1065 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1066 ctx->param_tcs_out_lds_layout;
1067 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1068
1069 /* TCS only receives high 13 bits of the address. */
1070 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1071 addr = LLVMBuildAnd(builder, addr,
1072 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1073 }
1074
1075 if (ring == TCS_FACTOR_RING) {
1076 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1077 addr = LLVMBuildAdd(builder, addr,
1078 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1079 }
1080
1081 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1082 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1083 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1084 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1085
1086 if (ctx->screen->info.chip_class >= GFX10)
1087 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1088 S_008F0C_OOB_SELECT(3) |
1089 S_008F0C_RESOURCE_LEVEL(1);
1090 else
1091 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1092 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1093
1094 LLVMValueRef desc[4];
1095 desc[0] = addr;
1096 desc[1] = LLVMConstInt(ctx->i32,
1097 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1098 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1099 desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);
1100
1101 return ac_build_gather_values(&ctx->ac, desc, 4);
1102 }
1103
1104 static LLVMValueRef fetch_input_tcs(
1105 struct lp_build_tgsi_context *bld_base,
1106 const struct tgsi_full_src_register *reg,
1107 enum tgsi_opcode_type type, unsigned swizzle_in)
1108 {
1109 struct si_shader_context *ctx = si_shader_context(bld_base);
1110 LLVMValueRef dw_addr, stride;
1111 unsigned swizzle = swizzle_in & 0xffff;
1112 stride = get_tcs_in_vertex_dw_stride(ctx);
1113 dw_addr = get_tcs_in_current_patch_offset(ctx);
1114 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1115
1116 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1117 }
1118
1119 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1120 LLVMTypeRef type,
1121 LLVMValueRef vertex_index,
1122 LLVMValueRef param_index,
1123 unsigned const_index,
1124 unsigned location,
1125 unsigned driver_location,
1126 unsigned component,
1127 unsigned num_components,
1128 bool is_patch,
1129 bool is_compact,
1130 bool load_input)
1131 {
1132 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1133 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1134 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1135 LLVMValueRef dw_addr, stride;
1136
1137 driver_location = driver_location / 4;
1138
1139 if (load_input) {
1140 stride = get_tcs_in_vertex_dw_stride(ctx);
1141 dw_addr = get_tcs_in_current_patch_offset(ctx);
1142 } else {
1143 if (is_patch) {
1144 stride = NULL;
1145 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1146 } else {
1147 stride = get_tcs_out_vertex_dw_stride(ctx);
1148 dw_addr = get_tcs_out_current_patch_offset(ctx);
1149 }
1150 }
1151
1152 if (param_index) {
1153 /* Add the constant index to the indirect index */
1154 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1155 LLVMConstInt(ctx->i32, const_index, 0), "");
1156 } else {
1157 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1158 }
1159
1160 ubyte *names;
1161 ubyte *indices;
1162 if (load_input) {
1163 names = info->input_semantic_name;
1164 indices = info->input_semantic_index;
1165 } else {
1166 names = info->output_semantic_name;
1167 indices = info->output_semantic_index;
1168 }
1169
1170 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1171 vertex_index, param_index,
1172 driver_location,
1173 names, indices,
1174 is_patch);
1175
1176 LLVMValueRef value[4];
1177 for (unsigned i = 0; i < num_components; i++) {
1178 unsigned offset = i;
1179 if (llvm_type_is_64bit(ctx, type))
1180 offset *= 2;
1181
1182 offset += component;
1183 value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
1184 }
1185
1186 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1187 }
1188
1189 static LLVMValueRef fetch_output_tcs(
1190 struct lp_build_tgsi_context *bld_base,
1191 const struct tgsi_full_src_register *reg,
1192 enum tgsi_opcode_type type, unsigned swizzle_in)
1193 {
1194 struct si_shader_context *ctx = si_shader_context(bld_base);
1195 LLVMValueRef dw_addr, stride;
1196 unsigned swizzle = (swizzle_in & 0xffff);
1197
1198 if (reg->Register.Dimension) {
1199 stride = get_tcs_out_vertex_dw_stride(ctx);
1200 dw_addr = get_tcs_out_current_patch_offset(ctx);
1201 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1202 } else {
1203 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1204 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1205 }
1206
1207 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1208 }
1209
1210 static LLVMValueRef fetch_input_tes(
1211 struct lp_build_tgsi_context *bld_base,
1212 const struct tgsi_full_src_register *reg,
1213 enum tgsi_opcode_type type, unsigned swizzle_in)
1214 {
1215 struct si_shader_context *ctx = si_shader_context(bld_base);
1216 LLVMValueRef base, addr;
1217 unsigned swizzle = (swizzle_in & 0xffff);
1218
1219 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1220 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1221
1222 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1223 ctx->tess_offchip_ring, base, addr, true);
1224 }
1225
1226 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1227 LLVMTypeRef type,
1228 LLVMValueRef vertex_index,
1229 LLVMValueRef param_index,
1230 unsigned const_index,
1231 unsigned location,
1232 unsigned driver_location,
1233 unsigned component,
1234 unsigned num_components,
1235 bool is_patch,
1236 bool is_compact,
1237 bool load_input)
1238 {
1239 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1240 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1241 LLVMValueRef base, addr;
1242
1243 driver_location = driver_location / 4;
1244
1245 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1246
1247 if (param_index) {
1248 /* Add the constant index to the indirect index */
1249 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1250 LLVMConstInt(ctx->i32, const_index, 0), "");
1251 } else {
1252 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1253 }
1254
1255 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1256 param_index, driver_location,
1257 info->input_semantic_name,
1258 info->input_semantic_index,
1259 is_patch);
1260
1261 /* TODO: This will generate rather ordinary llvm code, although it
1262 * should be easy for the optimiser to fix up. In future we might want
1263 * to refactor buffer_load(), but for now this maximises code sharing
1264 * between the NIR and TGSI backends.
1265 */
1266 LLVMValueRef value[4];
1267 for (unsigned i = 0; i < num_components; i++) {
1268 unsigned offset = i;
1269 if (llvm_type_is_64bit(ctx, type)) {
1270 offset *= 2;
1271 if (offset == 4) {
1272 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1273 vertex_index,
1274 param_index,
1275 driver_location + 1,
1276 info->input_semantic_name,
1277 info->input_semantic_index,
1278 is_patch);
1279 }
1280
1281 offset = offset % 4;
1282 }
1283
1284 offset += component;
1285 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1286 ctx->tess_offchip_ring, base, addr, true);
1287 }
1288
1289 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1290 }
1291
1292 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1293 const struct tgsi_full_instruction *inst,
1294 const struct tgsi_opcode_info *info,
1295 unsigned index,
1296 LLVMValueRef dst[4])
1297 {
1298 struct si_shader_context *ctx = si_shader_context(bld_base);
1299 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1300 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1301 unsigned chan_index;
1302 LLVMValueRef dw_addr, stride;
1303 LLVMValueRef buffer, base, buf_addr;
1304 LLVMValueRef values[4];
1305 bool skip_lds_store;
1306 bool is_tess_factor = false, is_tess_inner = false;
1307
1308 /* Only handle per-patch and per-vertex outputs here.
1309 * Vectors will be lowered to scalars and this function will be called again.
1310 */
1311 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1312 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1313 si_llvm_emit_store(bld_base, inst, info, index, dst);
1314 return;
1315 }
1316
1317 if (reg->Register.Dimension) {
1318 stride = get_tcs_out_vertex_dw_stride(ctx);
1319 dw_addr = get_tcs_out_current_patch_offset(ctx);
1320 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1321 skip_lds_store = !sh_info->reads_pervertex_outputs;
1322 } else {
1323 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1324 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1325 skip_lds_store = !sh_info->reads_perpatch_outputs;
1326
1327 if (!reg->Register.Indirect) {
1328 int name = sh_info->output_semantic_name[reg->Register.Index];
1329
1330 /* Always write tess factors into LDS for the TCS epilog. */
1331 if (name == TGSI_SEMANTIC_TESSINNER ||
1332 name == TGSI_SEMANTIC_TESSOUTER) {
1333 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1334 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1335 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1336 is_tess_factor = true;
1337 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1338 }
1339 }
1340 }
1341
1342 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1343
1344 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1345 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1346
1347 uint32_t writemask = reg->Register.WriteMask;
1348 while (writemask) {
1349 chan_index = u_bit_scan(&writemask);
1350 LLVMValueRef value = dst[chan_index];
1351
1352 if (inst->Instruction.Saturate)
1353 value = ac_build_clamp(&ctx->ac, value);
1354
1355 /* Skip LDS stores if there is no LDS read of this output. */
1356 if (!skip_lds_store)
1357 lshs_lds_store(ctx, chan_index, dw_addr, value);
1358
1359 value = ac_to_integer(&ctx->ac, value);
1360 values[chan_index] = value;
1361
1362 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1363 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1364 buf_addr, base,
1365 4 * chan_index, ac_glc, false);
1366 }
1367
1368 /* Write tess factors into VGPRs for the epilog. */
1369 if (is_tess_factor &&
1370 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1371 if (!is_tess_inner) {
1372 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1373 ctx->invoc0_tess_factors[chan_index]);
1374 } else if (chan_index < 2) {
1375 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1376 ctx->invoc0_tess_factors[4 + chan_index]);
1377 }
1378 }
1379 }
1380
1381 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1382 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1383 values, 4);
1384 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1385 base, 0, ac_glc, false);
1386 }
1387 }
1388
1389 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1390 const struct nir_variable *var,
1391 LLVMValueRef vertex_index,
1392 LLVMValueRef param_index,
1393 unsigned const_index,
1394 LLVMValueRef src,
1395 unsigned writemask)
1396 {
1397 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1398 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1399 const unsigned component = var->data.location_frac;
1400 const bool is_patch = var->data.patch;
1401 unsigned driver_location = var->data.driver_location;
1402 LLVMValueRef dw_addr, stride;
1403 LLVMValueRef buffer, base, addr;
1404 LLVMValueRef values[8];
1405 bool skip_lds_store;
1406 bool is_tess_factor = false, is_tess_inner = false;
1407
1408 driver_location = driver_location / 4;
1409
1410 if (param_index) {
1411 /* Add the constant index to the indirect index */
1412 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1413 LLVMConstInt(ctx->i32, const_index, 0), "");
1414 } else {
1415 if (const_index != 0)
1416 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1417 }
1418
1419 if (!is_patch) {
1420 stride = get_tcs_out_vertex_dw_stride(ctx);
1421 dw_addr = get_tcs_out_current_patch_offset(ctx);
1422 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1423 vertex_index, param_index,
1424 driver_location,
1425 info->output_semantic_name,
1426 info->output_semantic_index,
1427 is_patch);
1428
1429 skip_lds_store = !info->reads_pervertex_outputs;
1430 } else {
1431 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1432 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1433 vertex_index, param_index,
1434 driver_location,
1435 info->output_semantic_name,
1436 info->output_semantic_index,
1437 is_patch);
1438
1439 skip_lds_store = !info->reads_perpatch_outputs;
1440
1441 if (!param_index) {
1442 int name = info->output_semantic_name[driver_location];
1443
1444 /* Always write tess factors into LDS for the TCS epilog. */
1445 if (name == TGSI_SEMANTIC_TESSINNER ||
1446 name == TGSI_SEMANTIC_TESSOUTER) {
1447 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1448 skip_lds_store = !info->reads_tessfactor_outputs &&
1449 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1450 is_tess_factor = true;
1451 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1452 }
1453 }
1454 }
1455
1456 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1457
1458 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1459
1460 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1461 param_index, driver_location,
1462 info->output_semantic_name,
1463 info->output_semantic_index,
1464 is_patch);
1465
1466 for (unsigned chan = 0; chan < 8; chan++) {
1467 if (!(writemask & (1 << chan)))
1468 continue;
1469 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1470
1471 unsigned buffer_store_offset = chan % 4;
1472 if (chan == 4) {
1473 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1474 vertex_index,
1475 param_index,
1476 driver_location + 1,
1477 info->output_semantic_name,
1478 info->output_semantic_index,
1479 is_patch);
1480 }
1481
1482 /* Skip LDS stores if there is no LDS read of this output. */
1483 if (!skip_lds_store)
1484 lshs_lds_store(ctx, chan, dw_addr, value);
1485
1486 value = ac_to_integer(&ctx->ac, value);
1487 values[chan] = value;
1488
1489 if (writemask != 0xF && !is_tess_factor) {
1490 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1491 addr, base,
1492 4 * buffer_store_offset,
1493 ac_glc, false);
1494 }
1495
1496 /* Write tess factors into VGPRs for the epilog. */
1497 if (is_tess_factor &&
1498 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1499 if (!is_tess_inner) {
1500 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1501 ctx->invoc0_tess_factors[chan]);
1502 } else if (chan < 2) {
1503 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1504 ctx->invoc0_tess_factors[4 + chan]);
1505 }
1506 }
1507 }
1508
1509 if (writemask == 0xF && !is_tess_factor) {
1510 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1511 values, 4);
1512 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1513 base, 0, ac_glc, false);
1514 }
1515 }
1516
1517 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1518 unsigned input_index,
1519 unsigned vtx_offset_param,
1520 LLVMTypeRef type,
1521 unsigned swizzle)
1522 {
1523 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1524 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1525 struct si_shader *shader = ctx->shader;
1526 LLVMValueRef vtx_offset, soffset;
1527 struct tgsi_shader_info *info = &shader->selector->info;
1528 unsigned semantic_name = info->input_semantic_name[input_index];
1529 unsigned semantic_index = info->input_semantic_index[input_index];
1530 unsigned param;
1531 LLVMValueRef value;
1532
1533 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1534
1535 /* GFX9 has the ESGS ring in LDS. */
1536 if (ctx->screen->info.chip_class >= GFX9) {
1537 unsigned index = vtx_offset_param;
1538
1539 switch (index / 2) {
1540 case 0:
1541 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1542 index % 2 ? 16 : 0, 16);
1543 break;
1544 case 1:
1545 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1546 index % 2 ? 16 : 0, 16);
1547 break;
1548 case 2:
1549 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1550 index % 2 ? 16 : 0, 16);
1551 break;
1552 default:
1553 assert(0);
1554 return NULL;
1555 }
1556
1557 unsigned offset = param * 4 + swizzle;
1558 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1559 LLVMConstInt(ctx->i32, offset, false), "");
1560
1561 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1562 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1563 if (llvm_type_is_64bit(ctx, type)) {
1564 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1565 &ctx->ac.i32_1, 1, "");
1566 LLVMValueRef values[2] = {
1567 value,
1568 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1569 };
1570 value = ac_build_gather_values(&ctx->ac, values, 2);
1571 }
1572 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1573 }
1574
1575 /* GFX6: input load from the ESGS ring in memory. */
1576 if (swizzle == ~0) {
1577 LLVMValueRef values[TGSI_NUM_CHANNELS];
1578 unsigned chan;
1579 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1580 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1581 type, chan);
1582 }
1583 return ac_build_gather_values(&ctx->ac, values,
1584 TGSI_NUM_CHANNELS);
1585 }
1586
1587 /* Get the vertex offset parameter on GFX6. */
1588 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1589
1590 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1591 LLVMConstInt(ctx->i32, 4, 0), "");
1592
1593 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1594
1595 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1596 vtx_offset, soffset, 0, ac_glc, true, false);
1597 if (llvm_type_is_64bit(ctx, type)) {
1598 LLVMValueRef value2;
1599 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1600
1601 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1602 ctx->i32_0, vtx_offset, soffset,
1603 0, ac_glc, true, false);
1604 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1605 }
1606 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1607 }
1608
1609 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1610 unsigned location,
1611 unsigned driver_location,
1612 unsigned component,
1613 unsigned num_components,
1614 unsigned vertex_index,
1615 unsigned const_index,
1616 LLVMTypeRef type)
1617 {
1618 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1619
1620 LLVMValueRef value[4];
1621 for (unsigned i = 0; i < num_components; i++) {
1622 unsigned offset = i;
1623 if (llvm_type_is_64bit(ctx, type))
1624 offset *= 2;
1625
1626 offset += component;
1627 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1628 vertex_index, type, offset);
1629 }
1630
1631 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1632 }
1633
1634 static LLVMValueRef fetch_input_gs(
1635 struct lp_build_tgsi_context *bld_base,
1636 const struct tgsi_full_src_register *reg,
1637 enum tgsi_opcode_type type,
1638 unsigned swizzle_in)
1639 {
1640 struct si_shader_context *ctx = si_shader_context(bld_base);
1641 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1642 unsigned swizzle = swizzle_in & 0xffff;
1643
1644 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1645 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1646 return si_get_primitive_id(ctx, swizzle);
1647
1648 if (!reg->Register.Dimension)
1649 return NULL;
1650
1651 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1652 reg->Dimension.Index,
1653 tgsi2llvmtype(bld_base, type),
1654 swizzle);
1655 }
1656
1657 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1658 {
1659 switch (interpolate) {
1660 case TGSI_INTERPOLATE_CONSTANT:
1661 return 0;
1662
1663 case TGSI_INTERPOLATE_LINEAR:
1664 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1665 return SI_PARAM_LINEAR_SAMPLE;
1666 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1667 return SI_PARAM_LINEAR_CENTROID;
1668 else
1669 return SI_PARAM_LINEAR_CENTER;
1670 break;
1671 case TGSI_INTERPOLATE_COLOR:
1672 case TGSI_INTERPOLATE_PERSPECTIVE:
1673 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1674 return SI_PARAM_PERSP_SAMPLE;
1675 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1676 return SI_PARAM_PERSP_CENTROID;
1677 else
1678 return SI_PARAM_PERSP_CENTER;
1679 break;
1680 default:
1681 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1682 return -1;
1683 }
1684 }
1685
1686 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1687 unsigned attr_index, unsigned chan,
1688 LLVMValueRef prim_mask,
1689 LLVMValueRef i, LLVMValueRef j)
1690 {
1691 if (i || j) {
1692 return ac_build_fs_interp(&ctx->ac,
1693 LLVMConstInt(ctx->i32, chan, 0),
1694 LLVMConstInt(ctx->i32, attr_index, 0),
1695 prim_mask, i, j);
1696 }
1697 return ac_build_fs_interp_mov(&ctx->ac,
1698 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1699 LLVMConstInt(ctx->i32, chan, 0),
1700 LLVMConstInt(ctx->i32, attr_index, 0),
1701 prim_mask);
1702 }
1703
1704 /**
1705 * Interpolate a fragment shader input.
1706 *
1707 * @param ctx context
1708 * @param input_index index of the input in hardware
1709 * @param semantic_name TGSI_SEMANTIC_*
1710 * @param semantic_index semantic index
1711 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1712 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1713 * @param interp_param interpolation weights (i,j)
1714 * @param prim_mask SI_PARAM_PRIM_MASK
1715 * @param face SI_PARAM_FRONT_FACE
1716 * @param result the return value (4 components)
1717 */
1718 static void interp_fs_input(struct si_shader_context *ctx,
1719 unsigned input_index,
1720 unsigned semantic_name,
1721 unsigned semantic_index,
1722 unsigned num_interp_inputs,
1723 unsigned colors_read_mask,
1724 LLVMValueRef interp_param,
1725 LLVMValueRef prim_mask,
1726 LLVMValueRef face,
1727 LLVMValueRef result[4])
1728 {
1729 LLVMValueRef i = NULL, j = NULL;
1730 unsigned chan;
1731
1732 /* fs.constant returns the param from the middle vertex, so it's not
1733 * really useful for flat shading. It's meant to be used for custom
1734 * interpolation (but the intrinsic can't fetch from the other two
1735 * vertices).
1736 *
1737 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1738 * to do the right thing. The only reason we use fs.constant is that
1739 * fs.interp cannot be used on integers, because they can be equal
1740 * to NaN.
1741 *
1742 * When interp is false we will use fs.constant or for newer llvm,
1743 * amdgcn.interp.mov.
1744 */
1745 bool interp = interp_param != NULL;
1746
1747 if (interp) {
1748 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1749 LLVMVectorType(ctx->f32, 2), "");
1750
1751 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1752 ctx->i32_0, "");
1753 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1754 ctx->i32_1, "");
1755 }
1756
1757 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1758 ctx->shader->key.part.ps.prolog.color_two_side) {
1759 LLVMValueRef is_face_positive;
1760
1761 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1762 * otherwise it's at offset "num_inputs".
1763 */
1764 unsigned back_attr_offset = num_interp_inputs;
1765 if (semantic_index == 1 && colors_read_mask & 0xf)
1766 back_attr_offset += 1;
1767
1768 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1769 face, ctx->i32_0, "");
1770
1771 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1772 LLVMValueRef front, back;
1773
1774 front = si_build_fs_interp(ctx,
1775 input_index, chan,
1776 prim_mask, i, j);
1777 back = si_build_fs_interp(ctx,
1778 back_attr_offset, chan,
1779 prim_mask, i, j);
1780
1781 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1782 is_face_positive,
1783 front,
1784 back,
1785 "");
1786 }
1787 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1788 result[0] = si_build_fs_interp(ctx, input_index,
1789 0, prim_mask, i, j);
1790 result[1] =
1791 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1792 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1793 } else {
1794 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1795 result[chan] = si_build_fs_interp(ctx,
1796 input_index, chan,
1797 prim_mask, i, j);
1798 }
1799 }
1800 }
1801
1802 void si_llvm_load_input_fs(
1803 struct si_shader_context *ctx,
1804 unsigned input_index,
1805 LLVMValueRef out[4])
1806 {
1807 struct si_shader *shader = ctx->shader;
1808 struct tgsi_shader_info *info = &shader->selector->info;
1809 LLVMValueRef main_fn = ctx->main_fn;
1810 LLVMValueRef interp_param = NULL;
1811 int interp_param_idx;
1812 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1813 unsigned semantic_index = info->input_semantic_index[input_index];
1814 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1815 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1816
1817 /* Get colors from input VGPRs (set by the prolog). */
1818 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1819 unsigned colors_read = shader->selector->info.colors_read;
1820 unsigned mask = colors_read >> (semantic_index * 4);
1821 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1822 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1823 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1824
1825 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1826 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1827 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1828 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1829 return;
1830 }
1831
1832 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1833 if (interp_param_idx == -1)
1834 return;
1835 else if (interp_param_idx) {
1836 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1837 }
1838
1839 interp_fs_input(ctx, input_index, semantic_name,
1840 semantic_index, 0, /* this param is unused */
1841 shader->selector->info.colors_read, interp_param,
1842 ctx->abi.prim_mask,
1843 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1844 &out[0]);
1845 }
1846
1847 static void declare_input_fs(
1848 struct si_shader_context *ctx,
1849 unsigned input_index,
1850 const struct tgsi_full_declaration *decl,
1851 LLVMValueRef out[4])
1852 {
1853 si_llvm_load_input_fs(ctx, input_index, out);
1854 }
1855
1856 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1857 {
1858 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1859 }
1860
1861 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1862 {
1863 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1864
1865 /* For non-indexed draws, the base vertex set by the driver
1866 * (for direct draws) or the CP (for indirect draws) is the
1867 * first vertex ID, but GLSL expects 0 to be returned.
1868 */
1869 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1870 ctx->param_vs_state_bits);
1871 LLVMValueRef indexed;
1872
1873 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1874 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1875
1876 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1877 ctx->i32_0, "");
1878 }
1879
1880 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1881 {
1882 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1883
1884 LLVMValueRef values[3];
1885 LLVMValueRef result;
1886 unsigned i;
1887 unsigned *properties = ctx->shader->selector->info.properties;
1888
1889 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1890 unsigned sizes[3] = {
1891 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1892 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1893 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1894 };
1895
1896 for (i = 0; i < 3; ++i)
1897 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1898
1899 result = ac_build_gather_values(&ctx->ac, values, 3);
1900 } else {
1901 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1902 }
1903
1904 return result;
1905 }
1906
1907 /**
1908 * Load a dword from a constant buffer.
1909 */
1910 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1911 LLVMValueRef resource,
1912 LLVMValueRef offset)
1913 {
1914 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1915 0, 0, true, true);
1916 }
1917
1918 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1919 {
1920 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1921 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1922 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1923 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1924
1925 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1926 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1927 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1928
1929 LLVMValueRef pos[4] = {
1930 buffer_load_const(ctx, resource, offset0),
1931 buffer_load_const(ctx, resource, offset1),
1932 LLVMConstReal(ctx->f32, 0),
1933 LLVMConstReal(ctx->f32, 0)
1934 };
1935
1936 return ac_build_gather_values(&ctx->ac, pos, 4);
1937 }
1938
1939 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1940 {
1941 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1942 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1943 }
1944
1945 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1946 {
1947 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1948 LLVMValueRef coord[4] = {
1949 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1950 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1951 ctx->ac.f32_0,
1952 ctx->ac.f32_0
1953 };
1954
1955 /* For triangles, the vector should be (u, v, 1-u-v). */
1956 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1957 PIPE_PRIM_TRIANGLES) {
1958 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1959 LLVMBuildFAdd(ctx->ac.builder,
1960 coord[0], coord[1], ""), "");
1961 }
1962 return ac_build_gather_values(&ctx->ac, coord, 4);
1963 }
1964
1965 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1966 unsigned semantic_name)
1967 {
1968 LLVMValueRef base, addr;
1969
1970 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1971
1972 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1973 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1974 LLVMConstInt(ctx->i32, param, 0));
1975
1976 return buffer_load(&ctx->bld_base, ctx->f32,
1977 ~0, ctx->tess_offchip_ring, base, addr, true);
1978
1979 }
1980
1981 static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx,
1982 unsigned semantic_name)
1983 {
1984 LLVMValueRef buf, slot, val[4];
1985 int i, offset;
1986
1987 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1988 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1989 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1990 offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;
1991
1992 for (i = 0; i < 4; i++)
1993 val[i] = buffer_load_const(ctx, buf,
1994 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1995 return ac_build_gather_values(&ctx->ac, val, 4);
1996 }
1997
1998 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1999 unsigned varying_id,
2000 bool load_default_state)
2001 {
2002 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2003 unsigned semantic_name;
2004
2005 if (load_default_state) {
2006 switch (varying_id) {
2007 case VARYING_SLOT_TESS_LEVEL_INNER:
2008 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
2009 break;
2010 case VARYING_SLOT_TESS_LEVEL_OUTER:
2011 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
2012 break;
2013 default:
2014 unreachable("unknown tess level");
2015 }
2016 return load_tess_level_default(ctx, semantic_name);
2017 }
2018
2019 switch (varying_id) {
2020 case VARYING_SLOT_TESS_LEVEL_INNER:
2021 semantic_name = TGSI_SEMANTIC_TESSINNER;
2022 break;
2023 case VARYING_SLOT_TESS_LEVEL_OUTER:
2024 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2025 break;
2026 default:
2027 unreachable("unknown tess level");
2028 }
2029
2030 return load_tess_level(ctx, semantic_name);
2031
2032 }
2033
2034 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2035 {
2036 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2037 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2038 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2039 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2040 return get_num_tcs_out_vertices(ctx);
2041 else
2042 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2043 }
2044
2045 void si_load_system_value(struct si_shader_context *ctx,
2046 unsigned index,
2047 const struct tgsi_full_declaration *decl)
2048 {
2049 LLVMValueRef value = 0;
2050
2051 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2052
2053 switch (decl->Semantic.Name) {
2054 case TGSI_SEMANTIC_INSTANCEID:
2055 value = ctx->abi.instance_id;
2056 break;
2057
2058 case TGSI_SEMANTIC_VERTEXID:
2059 value = LLVMBuildAdd(ctx->ac.builder,
2060 ctx->abi.vertex_id,
2061 ctx->abi.base_vertex, "");
2062 break;
2063
2064 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2065 /* Unused. Clarify the meaning in indexed vs. non-indexed
2066 * draws if this is ever used again. */
2067 assert(false);
2068 break;
2069
2070 case TGSI_SEMANTIC_BASEVERTEX:
2071 value = get_base_vertex(&ctx->abi);
2072 break;
2073
2074 case TGSI_SEMANTIC_BASEINSTANCE:
2075 value = ctx->abi.start_instance;
2076 break;
2077
2078 case TGSI_SEMANTIC_DRAWID:
2079 value = ctx->abi.draw_id;
2080 break;
2081
2082 case TGSI_SEMANTIC_INVOCATIONID:
2083 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
2084 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2085 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
2086 if (ctx->screen->info.chip_class >= GFX10) {
2087 value = LLVMBuildAnd(ctx->ac.builder,
2088 ctx->abi.gs_invocation_id,
2089 LLVMConstInt(ctx->i32, 127, 0), "");
2090 } else {
2091 value = ctx->abi.gs_invocation_id;
2092 }
2093 } else {
2094 assert(!"INVOCATIONID not implemented");
2095 }
2096 break;
2097
2098 case TGSI_SEMANTIC_POSITION:
2099 {
2100 LLVMValueRef pos[4] = {
2101 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2102 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2103 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2104 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2105 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2106 };
2107 value = ac_build_gather_values(&ctx->ac, pos, 4);
2108 break;
2109 }
2110
2111 case TGSI_SEMANTIC_FACE:
2112 value = ctx->abi.front_face;
2113 break;
2114
2115 case TGSI_SEMANTIC_SAMPLEID:
2116 value = si_get_sample_id(ctx);
2117 break;
2118
2119 case TGSI_SEMANTIC_SAMPLEPOS: {
2120 LLVMValueRef pos[4] = {
2121 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2122 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2123 LLVMConstReal(ctx->f32, 0),
2124 LLVMConstReal(ctx->f32, 0)
2125 };
2126 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2127 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2128 value = ac_build_gather_values(&ctx->ac, pos, 4);
2129 break;
2130 }
2131
2132 case TGSI_SEMANTIC_SAMPLEMASK:
2133 /* This can only occur with the OpenGL Core profile, which
2134 * doesn't support smoothing.
2135 */
2136 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2137 break;
2138
2139 case TGSI_SEMANTIC_TESSCOORD:
2140 value = si_load_tess_coord(&ctx->abi);
2141 break;
2142
2143 case TGSI_SEMANTIC_VERTICESIN:
2144 value = si_load_patch_vertices_in(&ctx->abi);
2145 break;
2146
2147 case TGSI_SEMANTIC_TESSINNER:
2148 case TGSI_SEMANTIC_TESSOUTER:
2149 value = load_tess_level(ctx, decl->Semantic.Name);
2150 break;
2151
2152 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
2153 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
2154 value = load_tess_level_default(ctx, decl->Semantic.Name);
2155 break;
2156
2157 case TGSI_SEMANTIC_PRIMID:
2158 value = si_get_primitive_id(ctx, 0);
2159 break;
2160
2161 case TGSI_SEMANTIC_GRID_SIZE:
2162 value = ctx->abi.num_work_groups;
2163 break;
2164
2165 case TGSI_SEMANTIC_BLOCK_SIZE:
2166 value = get_block_size(&ctx->abi);
2167 break;
2168
2169 case TGSI_SEMANTIC_BLOCK_ID:
2170 {
2171 LLVMValueRef values[3];
2172
2173 for (int i = 0; i < 3; i++) {
2174 values[i] = ctx->i32_0;
2175 if (ctx->abi.workgroup_ids[i]) {
2176 values[i] = ctx->abi.workgroup_ids[i];
2177 }
2178 }
2179 value = ac_build_gather_values(&ctx->ac, values, 3);
2180 break;
2181 }
2182
2183 case TGSI_SEMANTIC_THREAD_ID:
2184 value = ctx->abi.local_invocation_ids;
2185 break;
2186
2187 case TGSI_SEMANTIC_HELPER_INVOCATION:
2188 value = ac_build_load_helper_invocation(&ctx->ac);
2189 break;
2190
2191 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2192 value = LLVMConstInt(ctx->i32, ctx->ac.wave_size, 0);
2193 break;
2194
2195 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2196 value = ac_get_thread_id(&ctx->ac);
2197 break;
2198
2199 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2200 {
2201 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2202 if (ctx->ac.wave_size == 64)
2203 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2204 value = LLVMBuildShl(ctx->ac.builder,
2205 LLVMConstInt(ctx->ac.iN_wavemask, 1, 0), id, "");
2206 if (ctx->ac.wave_size == 32)
2207 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2208 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2209 break;
2210 }
2211
2212 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2213 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2214 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2215 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2216 {
2217 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2218 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2219 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2220 /* All bits set except LSB */
2221 value = LLVMConstInt(ctx->ac.iN_wavemask, -2, 0);
2222 } else {
2223 /* All bits set */
2224 value = LLVMConstInt(ctx->ac.iN_wavemask, -1, 0);
2225 }
2226 if (ctx->ac.wave_size == 64)
2227 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2228 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2229 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2230 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2231 value = LLVMBuildNot(ctx->ac.builder, value, "");
2232 if (ctx->ac.wave_size == 32)
2233 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2234 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2235 break;
2236 }
2237
2238 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
2239 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2240 break;
2241
2242 default:
2243 assert(!"unknown system value");
2244 return;
2245 }
2246
2247 ctx->system_values[index] = value;
2248 }
2249
2250 void si_declare_compute_memory(struct si_shader_context *ctx)
2251 {
2252 struct si_shader_selector *sel = ctx->shader->selector;
2253 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2254
2255 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2256 LLVMValueRef var;
2257
2258 assert(!ctx->ac.lds);
2259
2260 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2261 LLVMArrayType(ctx->i8, lds_size),
2262 "compute_lds",
2263 AC_ADDR_SPACE_LDS);
2264 LLVMSetAlignment(var, 64 * 1024);
2265
2266 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2267 }
2268
2269 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2270 const struct tgsi_full_declaration *decl)
2271 {
2272 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2273 assert(decl->Range.First == decl->Range.Last);
2274
2275 si_declare_compute_memory(ctx);
2276 }
2277
2278 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2279 {
2280 LLVMValueRef ptr =
2281 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2282 struct si_shader_selector *sel = ctx->shader->selector;
2283
2284 /* Do the bounds checking with a descriptor, because
2285 * doing computation and manual bounds checking of 64-bit
2286 * addresses generates horrible VALU code with very high
2287 * VGPR usage and very low SIMD occupancy.
2288 */
2289 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2290
2291 LLVMValueRef desc0, desc1;
2292 desc0 = ptr;
2293 desc1 = LLVMConstInt(ctx->i32,
2294 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2295
2296 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2297 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2298 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2299 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2300
2301 if (ctx->screen->info.chip_class >= GFX10)
2302 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2303 S_008F0C_OOB_SELECT(3) |
2304 S_008F0C_RESOURCE_LEVEL(1);
2305 else
2306 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2307 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2308
2309 LLVMValueRef desc_elems[] = {
2310 desc0,
2311 desc1,
2312 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2313 LLVMConstInt(ctx->i32, rsrc3, false)
2314 };
2315
2316 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2317 }
2318
2319 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2320 {
2321 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2322 ctx->param_const_and_shader_buffers);
2323
2324 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2325 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2326 }
2327
2328 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2329 {
2330 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2331 struct si_shader_selector *sel = ctx->shader->selector;
2332
2333 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2334
2335 if (sel->info.const_buffers_declared == 1 &&
2336 sel->info.shader_buffers_declared == 0) {
2337 return load_const_buffer_desc_fast_path(ctx);
2338 }
2339
2340 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2341 index = LLVMBuildAdd(ctx->ac.builder, index,
2342 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2343
2344 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2345 }
2346
2347 static LLVMValueRef
2348 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2349 {
2350 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2351 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2352 ctx->param_const_and_shader_buffers);
2353
2354 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2355 index = LLVMBuildSub(ctx->ac.builder,
2356 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2357 index, "");
2358
2359 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2360 }
2361
2362 static LLVMValueRef fetch_constant(
2363 struct lp_build_tgsi_context *bld_base,
2364 const struct tgsi_full_src_register *reg,
2365 enum tgsi_opcode_type type,
2366 unsigned swizzle_in)
2367 {
2368 struct si_shader_context *ctx = si_shader_context(bld_base);
2369 struct si_shader_selector *sel = ctx->shader->selector;
2370 const struct tgsi_ind_register *ireg = &reg->Indirect;
2371 unsigned buf, idx;
2372 unsigned swizzle = swizzle_in & 0xffff;
2373
2374 LLVMValueRef addr, bufp;
2375
2376 if (swizzle_in == LP_CHAN_ALL) {
2377 unsigned chan;
2378 LLVMValueRef values[4];
2379 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2380 values[chan] = fetch_constant(bld_base, reg, type, chan);
2381
2382 return ac_build_gather_values(&ctx->ac, values, 4);
2383 }
2384
2385 /* Split 64-bit loads. */
2386 if (tgsi_type_is_64bit(type)) {
2387 LLVMValueRef lo, hi;
2388
2389 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2390 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2391 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2392 lo, hi);
2393 }
2394
2395 idx = reg->Register.Index * 4 + swizzle;
2396 if (reg->Register.Indirect) {
2397 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2398 } else {
2399 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2400 }
2401
2402 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2403 if (sel->info.const_buffers_declared == 1 &&
2404 sel->info.shader_buffers_declared == 0) {
2405 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2406 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2407 return bitcast(bld_base, type, result);
2408 }
2409
2410 assert(reg->Register.Dimension);
2411 buf = reg->Dimension.Index;
2412
2413 if (reg->Dimension.Indirect) {
2414 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2415 LLVMValueRef index;
2416 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2417 reg->Dimension.Index,
2418 ctx->num_const_buffers);
2419 index = LLVMBuildAdd(ctx->ac.builder, index,
2420 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2421 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2422 } else
2423 bufp = load_const_buffer_desc(ctx, buf);
2424
2425 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2426 }
2427
2428 /* Initialize arguments for the shader export intrinsic */
2429 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2430 LLVMValueRef *values,
2431 unsigned target,
2432 struct ac_export_args *args)
2433 {
2434 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2435 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2436 unsigned chan;
2437 bool is_int8, is_int10;
2438
2439 /* Default is 0xf. Adjusted below depending on the format. */
2440 args->enabled_channels = 0xf; /* writemask */
2441
2442 /* Specify whether the EXEC mask represents the valid mask */
2443 args->valid_mask = 0;
2444
2445 /* Specify whether this is the last export */
2446 args->done = 0;
2447
2448 /* Specify the target we are exporting */
2449 args->target = target;
2450
2451 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2452 const struct si_shader_key *key = &ctx->shader->key;
2453 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2454 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2455
2456 assert(cbuf >= 0 && cbuf < 8);
2457 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2458 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2459 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2460 }
2461
2462 args->compr = false;
2463 args->out[0] = f32undef;
2464 args->out[1] = f32undef;
2465 args->out[2] = f32undef;
2466 args->out[3] = f32undef;
2467
2468 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2469 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2470 unsigned bits, bool hi) = NULL;
2471
2472 switch (spi_shader_col_format) {
2473 case V_028714_SPI_SHADER_ZERO:
2474 args->enabled_channels = 0; /* writemask */
2475 args->target = V_008DFC_SQ_EXP_NULL;
2476 break;
2477
2478 case V_028714_SPI_SHADER_32_R:
2479 args->enabled_channels = 1; /* writemask */
2480 args->out[0] = values[0];
2481 break;
2482
2483 case V_028714_SPI_SHADER_32_GR:
2484 args->enabled_channels = 0x3; /* writemask */
2485 args->out[0] = values[0];
2486 args->out[1] = values[1];
2487 break;
2488
2489 case V_028714_SPI_SHADER_32_AR:
2490 if (ctx->screen->info.chip_class >= GFX10) {
2491 args->enabled_channels = 0x3; /* writemask */
2492 args->out[0] = values[0];
2493 args->out[1] = values[3];
2494 } else {
2495 args->enabled_channels = 0x9; /* writemask */
2496 args->out[0] = values[0];
2497 args->out[3] = values[3];
2498 }
2499 break;
2500
2501 case V_028714_SPI_SHADER_FP16_ABGR:
2502 packf = ac_build_cvt_pkrtz_f16;
2503 break;
2504
2505 case V_028714_SPI_SHADER_UNORM16_ABGR:
2506 packf = ac_build_cvt_pknorm_u16;
2507 break;
2508
2509 case V_028714_SPI_SHADER_SNORM16_ABGR:
2510 packf = ac_build_cvt_pknorm_i16;
2511 break;
2512
2513 case V_028714_SPI_SHADER_UINT16_ABGR:
2514 packi = ac_build_cvt_pk_u16;
2515 break;
2516
2517 case V_028714_SPI_SHADER_SINT16_ABGR:
2518 packi = ac_build_cvt_pk_i16;
2519 break;
2520
2521 case V_028714_SPI_SHADER_32_ABGR:
2522 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2523 break;
2524 }
2525
2526 /* Pack f16 or norm_i16/u16. */
2527 if (packf) {
2528 for (chan = 0; chan < 2; chan++) {
2529 LLVMValueRef pack_args[2] = {
2530 values[2 * chan],
2531 values[2 * chan + 1]
2532 };
2533 LLVMValueRef packed;
2534
2535 packed = packf(&ctx->ac, pack_args);
2536 args->out[chan] = ac_to_float(&ctx->ac, packed);
2537 }
2538 args->compr = 1; /* COMPR flag */
2539 }
2540 /* Pack i16/u16. */
2541 if (packi) {
2542 for (chan = 0; chan < 2; chan++) {
2543 LLVMValueRef pack_args[2] = {
2544 ac_to_integer(&ctx->ac, values[2 * chan]),
2545 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2546 };
2547 LLVMValueRef packed;
2548
2549 packed = packi(&ctx->ac, pack_args,
2550 is_int8 ? 8 : is_int10 ? 10 : 16,
2551 chan == 1);
2552 args->out[chan] = ac_to_float(&ctx->ac, packed);
2553 }
2554 args->compr = 1; /* COMPR flag */
2555 }
2556 }
2557
2558 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2559 LLVMValueRef alpha)
2560 {
2561 struct si_shader_context *ctx = si_shader_context(bld_base);
2562
2563 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2564 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2565 [PIPE_FUNC_LESS] = LLVMRealOLT,
2566 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2567 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2568 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2569 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2570 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2571 };
2572 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2573 assert(cond);
2574
2575 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2576 SI_PARAM_ALPHA_REF);
2577 LLVMValueRef alpha_pass =
2578 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2579 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2580 } else {
2581 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2582 }
2583 }
2584
2585 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2586 LLVMValueRef alpha,
2587 unsigned samplemask_param)
2588 {
2589 struct si_shader_context *ctx = si_shader_context(bld_base);
2590 LLVMValueRef coverage;
2591
2592 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2593 coverage = LLVMGetParam(ctx->main_fn,
2594 samplemask_param);
2595 coverage = ac_to_integer(&ctx->ac, coverage);
2596
2597 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2598 ctx->i32,
2599 &coverage, 1, AC_FUNC_ATTR_READNONE);
2600
2601 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2602 ctx->f32, "");
2603
2604 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2605 LLVMConstReal(ctx->f32,
2606 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2607
2608 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2609 }
2610
2611 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2612 struct ac_export_args *pos, LLVMValueRef *out_elts)
2613 {
2614 unsigned reg_index;
2615 unsigned chan;
2616 unsigned const_chan;
2617 LLVMValueRef base_elt;
2618 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2619 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2620 SI_VS_CONST_CLIP_PLANES, 0);
2621 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2622
2623 for (reg_index = 0; reg_index < 2; reg_index ++) {
2624 struct ac_export_args *args = &pos[2 + reg_index];
2625
2626 args->out[0] =
2627 args->out[1] =
2628 args->out[2] =
2629 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2630
2631 /* Compute dot products of position and user clip plane vectors */
2632 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2633 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2634 LLVMValueRef addr =
2635 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2636 const_chan) * 4, 0);
2637 base_elt = buffer_load_const(ctx, const_resource,
2638 addr);
2639 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2640 out_elts[const_chan], args->out[chan]);
2641 }
2642 }
2643
2644 args->enabled_channels = 0xf;
2645 args->valid_mask = 0;
2646 args->done = 0;
2647 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2648 args->compr = 0;
2649 }
2650 }
2651
2652 static void si_dump_streamout(struct pipe_stream_output_info *so)
2653 {
2654 unsigned i;
2655
2656 if (so->num_outputs)
2657 fprintf(stderr, "STREAMOUT\n");
2658
2659 for (i = 0; i < so->num_outputs; i++) {
2660 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2661 so->output[i].start_component;
2662 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2663 i, so->output[i].output_buffer,
2664 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2665 so->output[i].register_index,
2666 mask & 1 ? "x" : "",
2667 mask & 2 ? "y" : "",
2668 mask & 4 ? "z" : "",
2669 mask & 8 ? "w" : "");
2670 }
2671 }
2672
2673 void si_emit_streamout_output(struct si_shader_context *ctx,
2674 LLVMValueRef const *so_buffers,
2675 LLVMValueRef const *so_write_offsets,
2676 struct pipe_stream_output *stream_out,
2677 struct si_shader_output_values *shader_out)
2678 {
2679 unsigned buf_idx = stream_out->output_buffer;
2680 unsigned start = stream_out->start_component;
2681 unsigned num_comps = stream_out->num_components;
2682 LLVMValueRef out[4];
2683
2684 assert(num_comps && num_comps <= 4);
2685 if (!num_comps || num_comps > 4)
2686 return;
2687
2688 /* Load the output as int. */
2689 for (int j = 0; j < num_comps; j++) {
2690 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2691
2692 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2693 }
2694
2695 /* Pack the output. */
2696 LLVMValueRef vdata = NULL;
2697
2698 switch (num_comps) {
2699 case 1: /* as i32 */
2700 vdata = out[0];
2701 break;
2702 case 2: /* as v2i32 */
2703 case 3: /* as v3i32 */
2704 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2705 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2706 break;
2707 }
2708 /* as v4i32 (aligned to 4) */
2709 out[3] = LLVMGetUndef(ctx->i32);
2710 /* fall through */
2711 case 4: /* as v4i32 */
2712 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2713 break;
2714 }
2715
2716 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2717 vdata, num_comps,
2718 so_write_offsets[buf_idx],
2719 ctx->i32_0,
2720 stream_out->dst_offset * 4, ac_glc | ac_slc, false);
2721 }
2722
2723 /**
2724 * Write streamout data to buffers for vertex stream @p stream (different
2725 * vertex streams can occur for GS copy shaders).
2726 */
2727 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2728 struct si_shader_output_values *outputs,
2729 unsigned noutput, unsigned stream)
2730 {
2731 struct si_shader_selector *sel = ctx->shader->selector;
2732 struct pipe_stream_output_info *so = &sel->so;
2733 LLVMBuilderRef builder = ctx->ac.builder;
2734 int i;
2735
2736 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2737 LLVMValueRef so_vtx_count =
2738 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2739
2740 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2741
2742 /* can_emit = tid < so_vtx_count; */
2743 LLVMValueRef can_emit =
2744 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2745
2746 /* Emit the streamout code conditionally. This actually avoids
2747 * out-of-bounds buffer access. The hw tells us via the SGPR
2748 * (so_vtx_count) which threads are allowed to emit streamout data. */
2749 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2750 {
2751 /* The buffer offset is computed as follows:
2752 * ByteOffset = streamout_offset[buffer_id]*4 +
2753 * (streamout_write_index + thread_id)*stride[buffer_id] +
2754 * attrib_offset
2755 */
2756
2757 LLVMValueRef so_write_index =
2758 LLVMGetParam(ctx->main_fn,
2759 ctx->param_streamout_write_index);
2760
2761 /* Compute (streamout_write_index + thread_id). */
2762 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2763
2764 /* Load the descriptor and compute the write offset for each
2765 * enabled buffer. */
2766 LLVMValueRef so_write_offset[4] = {};
2767 LLVMValueRef so_buffers[4];
2768 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2769 ctx->param_rw_buffers);
2770
2771 for (i = 0; i < 4; i++) {
2772 if (!so->stride[i])
2773 continue;
2774
2775 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2776 SI_VS_STREAMOUT_BUF0 + i, 0);
2777
2778 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2779
2780 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2781 ctx->param_streamout_offset[i]);
2782 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2783
2784 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2785 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2786 so_offset);
2787 }
2788
2789 /* Write streamout data. */
2790 for (i = 0; i < so->num_outputs; i++) {
2791 unsigned reg = so->output[i].register_index;
2792
2793 if (reg >= noutput)
2794 continue;
2795
2796 if (stream != so->output[i].stream)
2797 continue;
2798
2799 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
2800 &so->output[i], &outputs[reg]);
2801 }
2802 }
2803 ac_build_endif(&ctx->ac, 6501);
2804 }
2805
2806 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2807 LLVMValueRef *values)
2808 {
2809 struct ac_export_args args;
2810
2811 si_llvm_init_export_args(ctx, values,
2812 V_008DFC_SQ_EXP_PARAM + index, &args);
2813 ac_build_export(&ctx->ac, &args);
2814 }
2815
2816 static void si_build_param_exports(struct si_shader_context *ctx,
2817 struct si_shader_output_values *outputs,
2818 unsigned noutput)
2819 {
2820 struct si_shader *shader = ctx->shader;
2821 unsigned param_count = 0;
2822
2823 for (unsigned i = 0; i < noutput; i++) {
2824 unsigned semantic_name = outputs[i].semantic_name;
2825 unsigned semantic_index = outputs[i].semantic_index;
2826
2827 if (outputs[i].vertex_stream[0] != 0 &&
2828 outputs[i].vertex_stream[1] != 0 &&
2829 outputs[i].vertex_stream[2] != 0 &&
2830 outputs[i].vertex_stream[3] != 0)
2831 continue;
2832
2833 switch (semantic_name) {
2834 case TGSI_SEMANTIC_LAYER:
2835 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2836 case TGSI_SEMANTIC_CLIPDIST:
2837 case TGSI_SEMANTIC_COLOR:
2838 case TGSI_SEMANTIC_BCOLOR:
2839 case TGSI_SEMANTIC_PRIMID:
2840 case TGSI_SEMANTIC_FOG:
2841 case TGSI_SEMANTIC_TEXCOORD:
2842 case TGSI_SEMANTIC_GENERIC:
2843 break;
2844 default:
2845 continue;
2846 }
2847
2848 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2849 semantic_index < SI_MAX_IO_GENERIC) &&
2850 shader->key.opt.kill_outputs &
2851 (1ull << si_shader_io_get_unique_index(semantic_name,
2852 semantic_index, true)))
2853 continue;
2854
2855 si_export_param(ctx, param_count, outputs[i].values);
2856
2857 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2858 shader->info.vs_output_param_offset[i] = param_count++;
2859 }
2860
2861 shader->info.nr_param_exports = param_count;
2862 }
2863
2864 /**
2865 * Vertex color clamping.
2866 *
2867 * This uses a state constant loaded in a user data SGPR and
2868 * an IF statement is added that clamps all colors if the constant
2869 * is true.
2870 */
2871 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2872 struct si_shader_output_values *outputs,
2873 unsigned noutput)
2874 {
2875 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2876 bool has_colors = false;
2877
2878 /* Store original colors to alloca variables. */
2879 for (unsigned i = 0; i < noutput; i++) {
2880 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2881 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2882 continue;
2883
2884 for (unsigned j = 0; j < 4; j++) {
2885 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2886 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2887 }
2888 has_colors = true;
2889 }
2890
2891 if (!has_colors)
2892 return;
2893
2894 /* The state is in the first bit of the user SGPR. */
2895 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2896 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2897
2898 ac_build_ifcc(&ctx->ac, cond, 6502);
2899
2900 /* Store clamped colors to alloca variables within the conditional block. */
2901 for (unsigned i = 0; i < noutput; i++) {
2902 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2903 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2904 continue;
2905
2906 for (unsigned j = 0; j < 4; j++) {
2907 LLVMBuildStore(ctx->ac.builder,
2908 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2909 addr[i][j]);
2910 }
2911 }
2912 ac_build_endif(&ctx->ac, 6502);
2913
2914