radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_from_mesa.h"
32
33 #include "ac_binary.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
36 #include "ac_rtld.h"
37 #include "ac_llvm_util.h"
38 #include "si_shader_internal.h"
39 #include "si_pipe.h"
40 #include "sid.h"
41
42 #include "compiler/nir/nir.h"
43
44 static const char scratch_rsrc_dword0_symbol[] =
45 "SCRATCH_RSRC_DWORD0";
46
47 static const char scratch_rsrc_dword1_symbol[] =
48 "SCRATCH_RSRC_DWORD1";
49
50 static void si_init_shader_ctx(struct si_shader_context *ctx,
51 struct si_screen *sscreen,
52 struct ac_llvm_compiler *compiler,
53 unsigned wave_size,
54 bool nir);
55
56 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
57 struct lp_build_tgsi_context *bld_base,
58 struct lp_build_emit_data *emit_data);
59
60 static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
61
62 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
63 union si_shader_part_key *key);
64 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
65 union si_shader_part_key *key);
66 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
67 union si_shader_part_key *key);
68 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
69 union si_shader_part_key *key);
70 static void si_fix_resource_usage(struct si_screen *sscreen,
71 struct si_shader *shader);
72
73 /* Ideally pass the sample mask input to the PS epilog as v14, which
74 * is its usual location, so that the shader doesn't have to add v_mov.
75 */
76 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
77
78 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
79 LLVMTypeRef type)
80 {
81 if (type == ctx->ac.i64 || type == ctx->ac.f64)
82 return true;
83
84 return false;
85 }
86
87 /** Whether the shader runs as a combination of multiple API shaders */
88 static bool is_multi_part_shader(struct si_shader_context *ctx)
89 {
90 if (ctx->screen->info.chip_class <= GFX8)
91 return false;
92
93 return ctx->shader->key.as_ls ||
94 ctx->shader->key.as_es ||
95 ctx->type == PIPE_SHADER_TESS_CTRL ||
96 ctx->type == PIPE_SHADER_GEOMETRY;
97 }
98
99 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
100 static bool is_merged_shader(struct si_shader_context *ctx)
101 {
102 return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
103 }
104
105 void si_init_function_info(struct si_function_info *fninfo)
106 {
107 fninfo->num_params = 0;
108 fninfo->num_sgpr_params = 0;
109 }
110
111 unsigned add_arg_assign(struct si_function_info *fninfo,
112 enum si_arg_regfile regfile, LLVMTypeRef type,
113 LLVMValueRef *assign)
114 {
115 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
116
117 unsigned idx = fninfo->num_params++;
118 assert(idx < ARRAY_SIZE(fninfo->types));
119
120 if (regfile == ARG_SGPR)
121 fninfo->num_sgpr_params = fninfo->num_params;
122
123 fninfo->types[idx] = type;
124 fninfo->assign[idx] = assign;
125 return idx;
126 }
127
128 static unsigned add_arg(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type)
130 {
131 return add_arg_assign(fninfo, regfile, type, NULL);
132 }
133
134 static void add_arg_assign_checked(struct si_function_info *fninfo,
135 enum si_arg_regfile regfile, LLVMTypeRef type,
136 LLVMValueRef *assign, unsigned idx)
137 {
138 ASSERTED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
139 assert(actual == idx);
140 }
141
142 static void add_arg_checked(struct si_function_info *fninfo,
143 enum si_arg_regfile regfile, LLVMTypeRef type,
144 unsigned idx)
145 {
146 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
147 }
148
149 /**
150 * Returns a unique index for a per-patch semantic name and index. The index
151 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
152 * can be calculated.
153 */
154 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
155 {
156 switch (semantic_name) {
157 case TGSI_SEMANTIC_TESSOUTER:
158 return 0;
159 case TGSI_SEMANTIC_TESSINNER:
160 return 1;
161 case TGSI_SEMANTIC_PATCH:
162 assert(index < 30);
163 return 2 + index;
164
165 default:
166 assert(!"invalid semantic name");
167 return 0;
168 }
169 }
170
171 /**
172 * Returns a unique index for a semantic name and index. The index must be
173 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
174 * calculated.
175 */
176 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
177 unsigned is_varying)
178 {
179 switch (semantic_name) {
180 case TGSI_SEMANTIC_POSITION:
181 return 0;
182 case TGSI_SEMANTIC_GENERIC:
183 /* Since some shader stages use the the highest used IO index
184 * to determine the size to allocate for inputs/outputs
185 * (in LDS, tess and GS rings). GENERIC should be placed right
186 * after POSITION to make that size as small as possible.
187 */
188 if (index < SI_MAX_IO_GENERIC)
189 return 1 + index;
190
191 assert(!"invalid generic index");
192 return 0;
193 case TGSI_SEMANTIC_FOG:
194 return SI_MAX_IO_GENERIC + 1;
195 case TGSI_SEMANTIC_COLOR:
196 assert(index < 2);
197 return SI_MAX_IO_GENERIC + 2 + index;
198 case TGSI_SEMANTIC_BCOLOR:
199 assert(index < 2);
200 /* If it's a varying, COLOR and BCOLOR alias. */
201 if (is_varying)
202 return SI_MAX_IO_GENERIC + 2 + index;
203 else
204 return SI_MAX_IO_GENERIC + 4 + index;
205 case TGSI_SEMANTIC_TEXCOORD:
206 assert(index < 8);
207 return SI_MAX_IO_GENERIC + 6 + index;
208
209 /* These are rarely used between LS and HS or ES and GS. */
210 case TGSI_SEMANTIC_CLIPDIST:
211 assert(index < 2);
212 return SI_MAX_IO_GENERIC + 6 + 8 + index;
213 case TGSI_SEMANTIC_CLIPVERTEX:
214 return SI_MAX_IO_GENERIC + 6 + 8 + 2;
215 case TGSI_SEMANTIC_PSIZE:
216 return SI_MAX_IO_GENERIC + 6 + 8 + 3;
217
218 /* These can't be written by LS, HS, and ES. */
219 case TGSI_SEMANTIC_LAYER:
220 return SI_MAX_IO_GENERIC + 6 + 8 + 4;
221 case TGSI_SEMANTIC_VIEWPORT_INDEX:
222 return SI_MAX_IO_GENERIC + 6 + 8 + 5;
223 case TGSI_SEMANTIC_PRIMID:
224 STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
225 return SI_MAX_IO_GENERIC + 6 + 8 + 6;
226 default:
227 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
228 assert(!"invalid semantic name");
229 return 0;
230 }
231 }
232
233 /**
234 * Get the value of a shader input parameter and extract a bitfield.
235 */
236 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
237 LLVMValueRef value, unsigned rshift,
238 unsigned bitwidth)
239 {
240 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
241 value = ac_to_integer(&ctx->ac, value);
242
243 if (rshift)
244 value = LLVMBuildLShr(ctx->ac.builder, value,
245 LLVMConstInt(ctx->i32, rshift, 0), "");
246
247 if (rshift + bitwidth < 32) {
248 unsigned mask = (1 << bitwidth) - 1;
249 value = LLVMBuildAnd(ctx->ac.builder, value,
250 LLVMConstInt(ctx->i32, mask, 0), "");
251 }
252
253 return value;
254 }
255
256 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
257 unsigned param, unsigned rshift,
258 unsigned bitwidth)
259 {
260 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
261
262 return unpack_llvm_param(ctx, value, rshift, bitwidth);
263 }
264
265 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
266 {
267 switch (ctx->type) {
268 case PIPE_SHADER_TESS_CTRL:
269 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
270
271 case PIPE_SHADER_TESS_EVAL:
272 return LLVMGetParam(ctx->main_fn,
273 ctx->param_tes_rel_patch_id);
274
275 default:
276 assert(0);
277 return NULL;
278 }
279 }
280
281 /* Tessellation shaders pass outputs to the next shader using LDS.
282 *
283 * LS outputs = TCS inputs
284 * TCS outputs = TES inputs
285 *
286 * The LDS layout is:
287 * - TCS inputs for patch 0
288 * - TCS inputs for patch 1
289 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
290 * - ...
291 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
292 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
293 * - TCS outputs for patch 1
294 * - Per-patch TCS outputs for patch 1
295 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
296 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
297 * - ...
298 *
299 * All three shaders VS(LS), TCS, TES share the same LDS space.
300 */
301
302 static LLVMValueRef
303 get_tcs_in_patch_stride(struct si_shader_context *ctx)
304 {
305 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
306 }
307
308 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
309 {
310 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
311
312 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
313 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
314
315 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
316 }
317
318 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
319 {
320 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
321
322 return LLVMConstInt(ctx->i32, stride, 0);
323 }
324
325 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
326 {
327 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
328 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
329
330 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
331 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
332 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
333 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
334 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
335 num_patch_outputs * 4;
336 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
337 }
338
339 static LLVMValueRef
340 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
341 {
342 return LLVMBuildMul(ctx->ac.builder,
343 si_unpack_param(ctx,
344 ctx->param_tcs_out_lds_offsets,
345 0, 16),
346 LLVMConstInt(ctx->i32, 4, 0), "");
347 }
348
349 static LLVMValueRef
350 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
351 {
352 return LLVMBuildMul(ctx->ac.builder,
353 si_unpack_param(ctx,
354 ctx->param_tcs_out_lds_offsets,
355 16, 16),
356 LLVMConstInt(ctx->i32, 4, 0), "");
357 }
358
359 static LLVMValueRef
360 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
361 {
362 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
363 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
364
365 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
366 }
367
368 static LLVMValueRef
369 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
370 {
371 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
372 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
373 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
374
375 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
376 }
377
378 static LLVMValueRef
379 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
380 {
381 LLVMValueRef patch0_patch_data_offset =
382 get_tcs_out_patch0_patch_data_offset(ctx);
383 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
384 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
385
386 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
387 }
388
389 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
390 {
391 unsigned tcs_out_vertices =
392 ctx->shader->selector ?
393 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
394
395 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
396 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
397 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
398
399 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
400 }
401
402 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
403 {
404 unsigned stride;
405
406 switch (ctx->type) {
407 case PIPE_SHADER_VERTEX:
408 stride = ctx->shader->selector->lshs_vertex_stride / 4;
409 return LLVMConstInt(ctx->i32, stride, 0);
410
411 case PIPE_SHADER_TESS_CTRL:
412 if (ctx->screen->info.chip_class >= GFX9 &&
413 ctx->shader->is_monolithic) {
414 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
415 return LLVMConstInt(ctx->i32, stride, 0);
416 }
417 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
418
419 default:
420 assert(0);
421 return NULL;
422 }
423 }
424
425 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
426 LLVMValueRef i32, unsigned index)
427 {
428 assert(index <= 1);
429
430 if (index == 1)
431 return LLVMBuildAShr(ctx->ac.builder, i32,
432 LLVMConstInt(ctx->i32, 16, 0), "");
433
434 return LLVMBuildSExt(ctx->ac.builder,
435 LLVMBuildTrunc(ctx->ac.builder, i32,
436 ctx->ac.i16, ""),
437 ctx->i32, "");
438 }
439
440 void si_llvm_load_input_vs(
441 struct si_shader_context *ctx,
442 unsigned input_index,
443 LLVMValueRef out[4])
444 {
445 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
446 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
447
448 if (vs_blit_property) {
449 LLVMValueRef vertex_id = ctx->abi.vertex_id;
450 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
451 LLVMIntULE, vertex_id,
452 ctx->i32_1, "");
453 /* Use LLVMIntNE, because we have 3 vertices and only
454 * the middle one should use y2.
455 */
456 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
457 LLVMIntNE, vertex_id,
458 ctx->i32_1, "");
459
460 if (input_index == 0) {
461 /* Position: */
462 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
463 ctx->param_vs_blit_inputs);
464 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
465 ctx->param_vs_blit_inputs + 1);
466
467 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
468 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
469 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
470 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
471
472 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
473 x1, x2, "");
474 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
475 y1, y2, "");
476
477 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
478 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
479 out[2] = LLVMGetParam(ctx->main_fn,
480 ctx->param_vs_blit_inputs + 2);
481 out[3] = ctx->ac.f32_1;
482 return;
483 }
484
485 /* Color or texture coordinates: */
486 assert(input_index == 1);
487
488 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
489 for (int i = 0; i < 4; i++) {
490 out[i] = LLVMGetParam(ctx->main_fn,
491 ctx->param_vs_blit_inputs + 3 + i);
492 }
493 } else {
494 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
495 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
496 ctx->param_vs_blit_inputs + 3);
497 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
498 ctx->param_vs_blit_inputs + 4);
499 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
500 ctx->param_vs_blit_inputs + 5);
501 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs + 6);
503
504 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
505 x1, x2, "");
506 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
507 y1, y2, "");
508 out[2] = LLVMGetParam(ctx->main_fn,
509 ctx->param_vs_blit_inputs + 7);
510 out[3] = LLVMGetParam(ctx->main_fn,
511 ctx->param_vs_blit_inputs + 8);
512 }
513 return;
514 }
515
516 union si_vs_fix_fetch fix_fetch;
517 LLVMValueRef t_list_ptr;
518 LLVMValueRef t_offset;
519 LLVMValueRef t_list;
520 LLVMValueRef vertex_index;
521 LLVMValueRef tmp;
522
523 /* Load the T list */
524 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
525
526 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
527
528 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
529
530 vertex_index = LLVMGetParam(ctx->main_fn,
531 ctx->param_vertex_index0 +
532 input_index);
533
534 /* Use the open-coded implementation for all loads of doubles and
535 * of dword-sized data that needs fixups. We need to insert conversion
536 * code anyway, and the amd/common code does it for us.
537 *
538 * Note: On LLVM <= 8, we can only open-code formats with
539 * channel size >= 4 bytes.
540 */
541 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
542 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
543 if (opencode ||
544 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
545 (fix_fetch.u.log_size == 2)) {
546 tmp = ac_build_opencoded_load_format(
547 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
548 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
549 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
550 for (unsigned i = 0; i < 4; ++i)
551 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
552 return;
553 }
554
555 /* Do multiple loads for special formats. */
556 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
557 LLVMValueRef fetches[4];
558 unsigned num_fetches;
559 unsigned fetch_stride;
560 unsigned channels_per_fetch;
561
562 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
563 num_fetches = MIN2(required_channels, 3);
564 fetch_stride = 1 << fix_fetch.u.log_size;
565 channels_per_fetch = 1;
566 } else {
567 num_fetches = 1;
568 fetch_stride = 0;
569 channels_per_fetch = required_channels;
570 }
571
572 for (unsigned i = 0; i < num_fetches; ++i) {
573 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
574 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
575 channels_per_fetch, 0, true);
576 }
577
578 if (num_fetches == 1 && channels_per_fetch > 1) {
579 LLVMValueRef fetch = fetches[0];
580 for (unsigned i = 0; i < channels_per_fetch; ++i) {
581 tmp = LLVMConstInt(ctx->i32, i, false);
582 fetches[i] = LLVMBuildExtractElement(
583 ctx->ac.builder, fetch, tmp, "");
584 }
585 num_fetches = channels_per_fetch;
586 channels_per_fetch = 1;
587 }
588
589 for (unsigned i = num_fetches; i < 4; ++i)
590 fetches[i] = LLVMGetUndef(ctx->f32);
591
592 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
593 required_channels == 4) {
594 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
595 fetches[3] = ctx->ac.i32_1;
596 else
597 fetches[3] = ctx->ac.f32_1;
598 } else if (fix_fetch.u.log_size == 3 &&
599 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
600 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
601 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
602 required_channels == 4) {
603 /* For 2_10_10_10, the hardware returns an unsigned value;
604 * convert it to a signed one.
605 */
606 LLVMValueRef tmp = fetches[3];
607 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
608
609 /* First, recover the sign-extended signed integer value. */
610 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
611 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
612 else
613 tmp = ac_to_integer(&ctx->ac, tmp);
614
615 /* For the integer-like cases, do a natural sign extension.
616 *
617 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
618 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
619 * exponent.
620 */
621 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
622 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
623 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
624 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
625
626 /* Convert back to the right type. */
627 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
628 LLVMValueRef clamp;
629 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
630 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
631 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
632 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
633 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
634 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
635 }
636
637 fetches[3] = tmp;
638 }
639
640 for (unsigned i = 0; i < 4; ++i)
641 out[i] = ac_to_float(&ctx->ac, fetches[i]);
642 }
643
644 static void declare_input_vs(
645 struct si_shader_context *ctx,
646 unsigned input_index,
647 const struct tgsi_full_declaration *decl,
648 LLVMValueRef out[4])
649 {
650 si_llvm_load_input_vs(ctx, input_index, out);
651 }
652
653 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
654 unsigned swizzle)
655 {
656 if (swizzle > 0)
657 return ctx->i32_0;
658
659 switch (ctx->type) {
660 case PIPE_SHADER_VERTEX:
661 return LLVMGetParam(ctx->main_fn,
662 ctx->param_vs_prim_id);
663 case PIPE_SHADER_TESS_CTRL:
664 return ctx->abi.tcs_patch_id;
665 case PIPE_SHADER_TESS_EVAL:
666 return ctx->abi.tes_patch_id;
667 case PIPE_SHADER_GEOMETRY:
668 return ctx->abi.gs_prim_id;
669 default:
670 assert(0);
671 return ctx->i32_0;
672 }
673 }
674
675 /**
676 * Return the value of tgsi_ind_register for indexing.
677 * This is the indirect index with the constant offset added to it.
678 */
679 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
680 const struct tgsi_ind_register *ind,
681 unsigned addr_mul,
682 int rel_index)
683 {
684 LLVMValueRef result;
685
686 if (ind->File == TGSI_FILE_ADDRESS) {
687 result = ctx->addrs[ind->Index][ind->Swizzle];
688 result = LLVMBuildLoad(ctx->ac.builder, result, "");
689 } else {
690 struct tgsi_full_src_register src = {};
691
692 src.Register.File = ind->File;
693 src.Register.Index = ind->Index;
694
695 /* Set the second index to 0 for constants. */
696 if (ind->File == TGSI_FILE_CONSTANT)
697 src.Register.Dimension = 1;
698
699 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
700 TGSI_TYPE_SIGNED,
701 ind->Swizzle);
702 result = ac_to_integer(&ctx->ac, result);
703 }
704
705 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
706 LLVMConstInt(ctx->i32, rel_index, 0));
707 }
708
709 /**
710 * Like si_get_indirect_index, but restricts the return value to a (possibly
711 * undefined) value inside [0..num).
712 */
713 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
714 const struct tgsi_ind_register *ind,
715 int rel_index, unsigned num)
716 {
717 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
718
719 return si_llvm_bound_index(ctx, result, num);
720 }
721
722 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
723 LLVMValueRef vertex_dw_stride,
724 LLVMValueRef base_addr,
725 LLVMValueRef vertex_index,
726 LLVMValueRef param_index,
727 unsigned input_index,
728 ubyte *name,
729 ubyte *index,
730 bool is_patch)
731 {
732 if (vertex_dw_stride) {
733 base_addr = ac_build_imad(&ctx->ac, vertex_index,
734 vertex_dw_stride, base_addr);
735 }
736
737 if (param_index) {
738 base_addr = ac_build_imad(&ctx->ac, param_index,
739 LLVMConstInt(ctx->i32, 4, 0), base_addr);
740 }
741
742 int param = is_patch ?
743 si_shader_io_get_unique_index_patch(name[input_index],
744 index[input_index]) :
745 si_shader_io_get_unique_index(name[input_index],
746 index[input_index], false);
747
748 /* Add the base address of the element. */
749 return LLVMBuildAdd(ctx->ac.builder, base_addr,
750 LLVMConstInt(ctx->i32, param * 4, 0), "");
751 }
752
753 /**
754 * Calculate a dword address given an input or output register and a stride.
755 */
756 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
757 const struct tgsi_full_dst_register *dst,
758 const struct tgsi_full_src_register *src,
759 LLVMValueRef vertex_dw_stride,
760 LLVMValueRef base_addr)
761 {
762 struct tgsi_shader_info *info = &ctx->shader->selector->info;
763 ubyte *name, *index, *array_first;
764 int input_index;
765 struct tgsi_full_dst_register reg;
766 LLVMValueRef vertex_index = NULL;
767 LLVMValueRef ind_index = NULL;
768
769 /* Set the register description. The address computation is the same
770 * for sources and destinations. */
771 if (src) {
772 reg.Register.File = src->Register.File;
773 reg.Register.Index = src->Register.Index;
774 reg.Register.Indirect = src->Register.Indirect;
775 reg.Register.Dimension = src->Register.Dimension;
776 reg.Indirect = src->Indirect;
777 reg.Dimension = src->Dimension;
778 reg.DimIndirect = src->DimIndirect;
779 } else
780 reg = *dst;
781
782 /* If the register is 2-dimensional (e.g. an array of vertices
783 * in a primitive), calculate the base address of the vertex. */
784 if (reg.Register.Dimension) {
785 if (reg.Dimension.Indirect)
786 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
787 1, reg.Dimension.Index);
788 else
789 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
790 }
791
792 /* Get information about the register. */
793 if (reg.Register.File == TGSI_FILE_INPUT) {
794 name = info->input_semantic_name;
795 index = info->input_semantic_index;
796 array_first = info->input_array_first;
797 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
798 name = info->output_semantic_name;
799 index = info->output_semantic_index;
800 array_first = info->output_array_first;
801 } else {
802 assert(0);
803 return NULL;
804 }
805
806 if (reg.Register.Indirect) {
807 /* Add the relative address of the element. */
808 if (reg.Indirect.ArrayID)
809 input_index = array_first[reg.Indirect.ArrayID];
810 else
811 input_index = reg.Register.Index;
812
813 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
814 1, reg.Register.Index - input_index);
815 } else {
816 input_index = reg.Register.Index;
817 }
818
819 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
820 base_addr, vertex_index,
821 ind_index, input_index,
822 name, index,
823 !reg.Register.Dimension);
824 }
825
826 /* The offchip buffer layout for TCS->TES is
827 *
828 * - attribute 0 of patch 0 vertex 0
829 * - attribute 0 of patch 0 vertex 1
830 * - attribute 0 of patch 0 vertex 2
831 * ...
832 * - attribute 0 of patch 1 vertex 0
833 * - attribute 0 of patch 1 vertex 1
834 * ...
835 * - attribute 1 of patch 0 vertex 0
836 * - attribute 1 of patch 0 vertex 1
837 * ...
838 * - per patch attribute 0 of patch 0
839 * - per patch attribute 0 of patch 1
840 * ...
841 *
842 * Note that every attribute has 4 components.
843 */
844 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
845 LLVMValueRef rel_patch_id,
846 LLVMValueRef vertex_index,
847 LLVMValueRef param_index)
848 {
849 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
850 LLVMValueRef param_stride, constant16;
851
852 vertices_per_patch = get_num_tcs_out_vertices(ctx);
853 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
854 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
855 num_patches, "");
856
857 constant16 = LLVMConstInt(ctx->i32, 16, 0);
858 if (vertex_index) {
859 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
860 vertices_per_patch, vertex_index);
861 param_stride = total_vertices;
862 } else {
863 base_addr = rel_patch_id;
864 param_stride = num_patches;
865 }
866
867 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
868 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
869
870 if (!vertex_index) {
871 LLVMValueRef patch_data_offset =
872 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
873
874 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
875 patch_data_offset, "");
876 }
877 return base_addr;
878 }
879
880 /* This is a generic helper that can be shared by the NIR and TGSI backends */
881 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
882 struct si_shader_context *ctx,
883 LLVMValueRef vertex_index,
884 LLVMValueRef param_index,
885 unsigned param_base,
886 ubyte *name,
887 ubyte *index,
888 bool is_patch)
889 {
890 unsigned param_index_base;
891
892 param_index_base = is_patch ?
893 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
894 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
895
896 if (param_index) {
897 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
898 LLVMConstInt(ctx->i32, param_index_base, 0),
899 "");
900 } else {
901 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
902 }
903
904 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
905 vertex_index, param_index);
906 }
907
908 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
909 struct si_shader_context *ctx,
910 const struct tgsi_full_dst_register *dst,
911 const struct tgsi_full_src_register *src)
912 {
913 struct tgsi_shader_info *info = &ctx->shader->selector->info;
914 ubyte *name, *index, *array_first;
915 struct tgsi_full_src_register reg;
916 LLVMValueRef vertex_index = NULL;
917 LLVMValueRef param_index = NULL;
918 unsigned param_base;
919
920 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
921
922 if (reg.Register.Dimension) {
923
924 if (reg.Dimension.Indirect)
925 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
926 1, reg.Dimension.Index);
927 else
928 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
929 }
930
931 /* Get information about the register. */
932 if (reg.Register.File == TGSI_FILE_INPUT) {
933 name = info->input_semantic_name;
934 index = info->input_semantic_index;
935 array_first = info->input_array_first;
936 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
937 name = info->output_semantic_name;
938 index = info->output_semantic_index;
939 array_first = info->output_array_first;
940 } else {
941 assert(0);
942 return NULL;
943 }
944
945 if (reg.Register.Indirect) {
946 if (reg.Indirect.ArrayID)
947 param_base = array_first[reg.Indirect.ArrayID];
948 else
949 param_base = reg.Register.Index;
950
951 param_index = si_get_indirect_index(ctx, &reg.Indirect,
952 1, reg.Register.Index - param_base);
953
954 } else {
955 param_base = reg.Register.Index;
956 }
957
958 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
959 param_index, param_base,
960 name, index, !reg.Register.Dimension);
961 }
962
963 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
964 LLVMTypeRef type, unsigned swizzle,
965 LLVMValueRef buffer, LLVMValueRef offset,
966 LLVMValueRef base, bool can_speculate)
967 {
968 struct si_shader_context *ctx = si_shader_context(bld_base);
969 LLVMValueRef value, value2;
970 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
971
972 if (swizzle == ~0) {
973 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
974 0, ac_glc, can_speculate, false);
975
976 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
977 }
978
979 if (!llvm_type_is_64bit(ctx, type)) {
980 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
981 0, ac_glc, can_speculate, false);
982
983 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
984 return LLVMBuildExtractElement(ctx->ac.builder, value,
985 LLVMConstInt(ctx->i32, swizzle, 0), "");
986 }
987
988 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
989 swizzle * 4, ac_glc, can_speculate, false);
990
991 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
992 swizzle * 4 + 4, ac_glc, can_speculate, false);
993
994 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
995 }
996
997 /**
998 * Load from LSHS LDS storage.
999 *
1000 * \param type output value type
1001 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1002 * \param dw_addr address in dwords
1003 */
1004 static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
1005 LLVMTypeRef type, unsigned swizzle,
1006 LLVMValueRef dw_addr)
1007 {
1008 struct si_shader_context *ctx = si_shader_context(bld_base);
1009 LLVMValueRef value;
1010
1011 if (swizzle == ~0) {
1012 LLVMValueRef values[TGSI_NUM_CHANNELS];
1013
1014 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1015 values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);
1016
1017 return ac_build_gather_values(&ctx->ac, values,
1018 TGSI_NUM_CHANNELS);
1019 }
1020
1021 /* Split 64-bit loads. */
1022 if (llvm_type_is_64bit(ctx, type)) {
1023 LLVMValueRef lo, hi;
1024
1025 lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1026 hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1027 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1028 }
1029
1030 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1031 LLVMConstInt(ctx->i32, swizzle, 0), "");
1032
1033 value = ac_lds_load(&ctx->ac, dw_addr);
1034
1035 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1036 }
1037
1038 /**
1039 * Store to LSHS LDS storage.
1040 *
1041 * \param swizzle offset (typically 0..3)
1042 * \param dw_addr address in dwords
1043 * \param value value to store
1044 */
1045 static void lshs_lds_store(struct si_shader_context *ctx,
1046 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1047 LLVMValueRef value)
1048 {
1049 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1050 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1051
1052 ac_lds_store(&ctx->ac, dw_addr, value);
1053 }
1054
1055 enum si_tess_ring {
1056 TCS_FACTOR_RING,
1057 TESS_OFFCHIP_RING_TCS,
1058 TESS_OFFCHIP_RING_TES,
1059 };
1060
1061 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1062 enum si_tess_ring ring)
1063 {
1064 LLVMBuilderRef builder = ctx->ac.builder;
1065 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1066 ctx->param_tcs_out_lds_layout;
1067 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1068
1069 /* TCS only receives high 13 bits of the address. */
1070 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1071 addr = LLVMBuildAnd(builder, addr,
1072 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1073 }
1074
1075 if (ring == TCS_FACTOR_RING) {
1076 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1077 addr = LLVMBuildAdd(builder, addr,
1078 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1079 }
1080
1081 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1082 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1083 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1084 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1085
1086 if (ctx->screen->info.chip_class >= GFX10)
1087 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1088 S_008F0C_OOB_SELECT(3) |
1089 S_008F0C_RESOURCE_LEVEL(1);
1090 else
1091 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1092 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1093
1094 LLVMValueRef desc[4];
1095 desc[0] = addr;
1096 desc[1] = LLVMConstInt(ctx->i32,
1097 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1098 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1099 desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);
1100
1101 return ac_build_gather_values(&ctx->ac, desc, 4);
1102 }
1103
1104 static LLVMValueRef fetch_input_tcs(
1105 struct lp_build_tgsi_context *bld_base,
1106 const struct tgsi_full_src_register *reg,
1107 enum tgsi_opcode_type type, unsigned swizzle_in)
1108 {
1109 struct si_shader_context *ctx = si_shader_context(bld_base);
1110 LLVMValueRef dw_addr, stride;
1111 unsigned swizzle = swizzle_in & 0xffff;
1112 stride = get_tcs_in_vertex_dw_stride(ctx);
1113 dw_addr = get_tcs_in_current_patch_offset(ctx);
1114 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1115
1116 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1117 }
1118
1119 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1120 LLVMTypeRef type,
1121 LLVMValueRef vertex_index,
1122 LLVMValueRef param_index,
1123 unsigned const_index,
1124 unsigned location,
1125 unsigned driver_location,
1126 unsigned component,
1127 unsigned num_components,
1128 bool is_patch,
1129 bool is_compact,
1130 bool load_input)
1131 {
1132 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1133 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1134 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1135 LLVMValueRef dw_addr, stride;
1136
1137 driver_location = driver_location / 4;
1138
1139 if (load_input) {
1140 stride = get_tcs_in_vertex_dw_stride(ctx);
1141 dw_addr = get_tcs_in_current_patch_offset(ctx);
1142 } else {
1143 if (is_patch) {
1144 stride = NULL;
1145 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1146 } else {
1147 stride = get_tcs_out_vertex_dw_stride(ctx);
1148 dw_addr = get_tcs_out_current_patch_offset(ctx);
1149 }
1150 }
1151
1152 if (!param_index) {
1153 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1154 }
1155
1156 ubyte *names;
1157 ubyte *indices;
1158 if (load_input) {
1159 names = info->input_semantic_name;
1160 indices = info->input_semantic_index;
1161 } else {
1162 names = info->output_semantic_name;
1163 indices = info->output_semantic_index;
1164 }
1165
1166 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1167 vertex_index, param_index,
1168 driver_location,
1169 names, indices,
1170 is_patch);
1171
1172 LLVMValueRef value[4];
1173 for (unsigned i = 0; i < num_components; i++) {
1174 unsigned offset = i;
1175 if (llvm_type_is_64bit(ctx, type))
1176 offset *= 2;
1177
1178 offset += component;
1179 value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
1180 }
1181
1182 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1183 }
1184
1185 static LLVMValueRef fetch_output_tcs(
1186 struct lp_build_tgsi_context *bld_base,
1187 const struct tgsi_full_src_register *reg,
1188 enum tgsi_opcode_type type, unsigned swizzle_in)
1189 {
1190 struct si_shader_context *ctx = si_shader_context(bld_base);
1191 LLVMValueRef dw_addr, stride;
1192 unsigned swizzle = (swizzle_in & 0xffff);
1193
1194 if (reg->Register.Dimension) {
1195 stride = get_tcs_out_vertex_dw_stride(ctx);
1196 dw_addr = get_tcs_out_current_patch_offset(ctx);
1197 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1198 } else {
1199 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1200 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1201 }
1202
1203 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1204 }
1205
1206 static LLVMValueRef fetch_input_tes(
1207 struct lp_build_tgsi_context *bld_base,
1208 const struct tgsi_full_src_register *reg,
1209 enum tgsi_opcode_type type, unsigned swizzle_in)
1210 {
1211 struct si_shader_context *ctx = si_shader_context(bld_base);
1212 LLVMValueRef base, addr;
1213 unsigned swizzle = (swizzle_in & 0xffff);
1214
1215 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1216 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1217
1218 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1219 ctx->tess_offchip_ring, base, addr, true);
1220 }
1221
1222 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1223 LLVMTypeRef type,
1224 LLVMValueRef vertex_index,
1225 LLVMValueRef param_index,
1226 unsigned const_index,
1227 unsigned location,
1228 unsigned driver_location,
1229 unsigned component,
1230 unsigned num_components,
1231 bool is_patch,
1232 bool is_compact,
1233 bool load_input)
1234 {
1235 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1236 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1237 LLVMValueRef base, addr;
1238
1239 driver_location = driver_location / 4;
1240
1241 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1242
1243 if (!param_index) {
1244 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1245 }
1246
1247 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1248 param_index, driver_location,
1249 info->input_semantic_name,
1250 info->input_semantic_index,
1251 is_patch);
1252
1253 /* TODO: This will generate rather ordinary llvm code, although it
1254 * should be easy for the optimiser to fix up. In future we might want
1255 * to refactor buffer_load(), but for now this maximises code sharing
1256 * between the NIR and TGSI backends.
1257 */
1258 LLVMValueRef value[4];
1259 for (unsigned i = 0; i < num_components; i++) {
1260 unsigned offset = i;
1261 if (llvm_type_is_64bit(ctx, type)) {
1262 offset *= 2;
1263 if (offset == 4) {
1264 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1265 vertex_index,
1266 param_index,
1267 driver_location + 1,
1268 info->input_semantic_name,
1269 info->input_semantic_index,
1270 is_patch);
1271 }
1272
1273 offset = offset % 4;
1274 }
1275
1276 offset += component;
1277 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1278 ctx->tess_offchip_ring, base, addr, true);
1279 }
1280
1281 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1282 }
1283
1284 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1285 const struct tgsi_full_instruction *inst,
1286 const struct tgsi_opcode_info *info,
1287 unsigned index,
1288 LLVMValueRef dst[4])
1289 {
1290 struct si_shader_context *ctx = si_shader_context(bld_base);
1291 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1292 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1293 unsigned chan_index;
1294 LLVMValueRef dw_addr, stride;
1295 LLVMValueRef buffer, base, buf_addr;
1296 LLVMValueRef values[4];
1297 bool skip_lds_store;
1298 bool is_tess_factor = false, is_tess_inner = false;
1299
1300 /* Only handle per-patch and per-vertex outputs here.
1301 * Vectors will be lowered to scalars and this function will be called again.
1302 */
1303 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1304 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1305 si_llvm_emit_store(bld_base, inst, info, index, dst);
1306 return;
1307 }
1308
1309 if (reg->Register.Dimension) {
1310 stride = get_tcs_out_vertex_dw_stride(ctx);
1311 dw_addr = get_tcs_out_current_patch_offset(ctx);
1312 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1313 skip_lds_store = !sh_info->reads_pervertex_outputs;
1314 } else {
1315 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1316 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1317 skip_lds_store = !sh_info->reads_perpatch_outputs;
1318
1319 if (!reg->Register.Indirect) {
1320 int name = sh_info->output_semantic_name[reg->Register.Index];
1321
1322 /* Always write tess factors into LDS for the TCS epilog. */
1323 if (name == TGSI_SEMANTIC_TESSINNER ||
1324 name == TGSI_SEMANTIC_TESSOUTER) {
1325 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1326 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1327 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1328 is_tess_factor = true;
1329 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1330 }
1331 }
1332 }
1333
1334 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1335
1336 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1337 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1338
1339 uint32_t writemask = reg->Register.WriteMask;
1340 while (writemask) {
1341 chan_index = u_bit_scan(&writemask);
1342 LLVMValueRef value = dst[chan_index];
1343
1344 if (inst->Instruction.Saturate)
1345 value = ac_build_clamp(&ctx->ac, value);
1346
1347 /* Skip LDS stores if there is no LDS read of this output. */
1348 if (!skip_lds_store)
1349 lshs_lds_store(ctx, chan_index, dw_addr, value);
1350
1351 value = ac_to_integer(&ctx->ac, value);
1352 values[chan_index] = value;
1353
1354 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1355 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1356 buf_addr, base,
1357 4 * chan_index, ac_glc, false);
1358 }
1359
1360 /* Write tess factors into VGPRs for the epilog. */
1361 if (is_tess_factor &&
1362 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1363 if (!is_tess_inner) {
1364 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1365 ctx->invoc0_tess_factors[chan_index]);
1366 } else if (chan_index < 2) {
1367 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1368 ctx->invoc0_tess_factors[4 + chan_index]);
1369 }
1370 }
1371 }
1372
1373 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1374 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1375 values, 4);
1376 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1377 base, 0, ac_glc, false);
1378 }
1379 }
1380
1381 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1382 const struct nir_variable *var,
1383 LLVMValueRef vertex_index,
1384 LLVMValueRef param_index,
1385 unsigned const_index,
1386 LLVMValueRef src,
1387 unsigned writemask)
1388 {
1389 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1390 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1391 const unsigned component = var->data.location_frac;
1392 const bool is_patch = var->data.patch;
1393 unsigned driver_location = var->data.driver_location;
1394 LLVMValueRef dw_addr, stride;
1395 LLVMValueRef buffer, base, addr;
1396 LLVMValueRef values[8];
1397 bool skip_lds_store;
1398 bool is_tess_factor = false, is_tess_inner = false;
1399
1400 driver_location = driver_location / 4;
1401
1402 bool is_const = !param_index;
1403 if (!param_index)
1404 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1405
1406 if (!is_patch) {
1407 stride = get_tcs_out_vertex_dw_stride(ctx);
1408 dw_addr = get_tcs_out_current_patch_offset(ctx);
1409 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1410 vertex_index, param_index,
1411 driver_location,
1412 info->output_semantic_name,
1413 info->output_semantic_index,
1414 is_patch);
1415
1416 skip_lds_store = !info->reads_pervertex_outputs;
1417 } else {
1418 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1419 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1420 vertex_index, param_index,
1421 driver_location,
1422 info->output_semantic_name,
1423 info->output_semantic_index,
1424 is_patch);
1425
1426 skip_lds_store = !info->reads_perpatch_outputs;
1427
1428 if (is_const && const_index == 0) {
1429 int name = info->output_semantic_name[driver_location];
1430
1431 /* Always write tess factors into LDS for the TCS epilog. */
1432 if (name == TGSI_SEMANTIC_TESSINNER ||
1433 name == TGSI_SEMANTIC_TESSOUTER) {
1434 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1435 skip_lds_store = !info->reads_tessfactor_outputs &&
1436 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1437 is_tess_factor = true;
1438 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1439 }
1440 }
1441 }
1442
1443 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1444
1445 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1446
1447 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1448 param_index, driver_location,
1449 info->output_semantic_name,
1450 info->output_semantic_index,
1451 is_patch);
1452
1453 for (unsigned chan = 0; chan < 8; chan++) {
1454 if (!(writemask & (1 << chan)))
1455 continue;
1456 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1457
1458 unsigned buffer_store_offset = chan % 4;
1459 if (chan == 4) {
1460 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1461 vertex_index,
1462 param_index,
1463 driver_location + 1,
1464 info->output_semantic_name,
1465 info->output_semantic_index,
1466 is_patch);
1467 }
1468
1469 /* Skip LDS stores if there is no LDS read of this output. */
1470 if (!skip_lds_store)
1471 lshs_lds_store(ctx, chan, dw_addr, value);
1472
1473 value = ac_to_integer(&ctx->ac, value);
1474 values[chan] = value;
1475
1476 if (writemask != 0xF && !is_tess_factor) {
1477 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1478 addr, base,
1479 4 * buffer_store_offset,
1480 ac_glc, false);
1481 }
1482
1483 /* Write tess factors into VGPRs for the epilog. */
1484 if (is_tess_factor &&
1485 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1486 if (!is_tess_inner) {
1487 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1488 ctx->invoc0_tess_factors[chan]);
1489 } else if (chan < 2) {
1490 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1491 ctx->invoc0_tess_factors[4 + chan]);
1492 }
1493 }
1494 }
1495
1496 if (writemask == 0xF && !is_tess_factor) {
1497 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1498 values, 4);
1499 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1500 base, 0, ac_glc, false);
1501 }
1502 }
1503
1504 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1505 unsigned input_index,
1506 unsigned vtx_offset_param,
1507 LLVMTypeRef type,
1508 unsigned swizzle)
1509 {
1510 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1511 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1512 struct si_shader *shader = ctx->shader;
1513 LLVMValueRef vtx_offset, soffset;
1514 struct tgsi_shader_info *info = &shader->selector->info;
1515 unsigned semantic_name = info->input_semantic_name[input_index];
1516 unsigned semantic_index = info->input_semantic_index[input_index];
1517 unsigned param;
1518 LLVMValueRef value;
1519
1520 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1521
1522 /* GFX9 has the ESGS ring in LDS. */
1523 if (ctx->screen->info.chip_class >= GFX9) {
1524 unsigned index = vtx_offset_param;
1525
1526 switch (index / 2) {
1527 case 0:
1528 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1529 index % 2 ? 16 : 0, 16);
1530 break;
1531 case 1:
1532 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1533 index % 2 ? 16 : 0, 16);
1534 break;
1535 case 2:
1536 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1537 index % 2 ? 16 : 0, 16);
1538 break;
1539 default:
1540 assert(0);
1541 return NULL;
1542 }
1543
1544 unsigned offset = param * 4 + swizzle;
1545 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1546 LLVMConstInt(ctx->i32, offset, false), "");
1547
1548 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1549 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1550 if (llvm_type_is_64bit(ctx, type)) {
1551 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1552 &ctx->ac.i32_1, 1, "");
1553 LLVMValueRef values[2] = {
1554 value,
1555 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1556 };
1557 value = ac_build_gather_values(&ctx->ac, values, 2);
1558 }
1559 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1560 }
1561
1562 /* GFX6: input load from the ESGS ring in memory. */
1563 if (swizzle == ~0) {
1564 LLVMValueRef values[TGSI_NUM_CHANNELS];
1565 unsigned chan;
1566 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1567 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1568 type, chan);
1569 }
1570 return ac_build_gather_values(&ctx->ac, values,
1571 TGSI_NUM_CHANNELS);
1572 }
1573
1574 /* Get the vertex offset parameter on GFX6. */
1575 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1576
1577 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1578 LLVMConstInt(ctx->i32, 4, 0), "");
1579
1580 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1581
1582 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1583 vtx_offset, soffset, 0, ac_glc, true, false);
1584 if (llvm_type_is_64bit(ctx, type)) {
1585 LLVMValueRef value2;
1586 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1587
1588 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1589 ctx->i32_0, vtx_offset, soffset,
1590 0, ac_glc, true, false);
1591 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1592 }
1593 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1594 }
1595
1596 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1597 unsigned location,
1598 unsigned driver_location,
1599 unsigned component,
1600 unsigned num_components,
1601 unsigned vertex_index,
1602 unsigned const_index,
1603 LLVMTypeRef type)
1604 {
1605 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1606
1607 LLVMValueRef value[4];
1608 for (unsigned i = 0; i < num_components; i++) {
1609 unsigned offset = i;
1610 if (llvm_type_is_64bit(ctx, type))
1611 offset *= 2;
1612
1613 offset += component;
1614 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4 + const_index,
1615 vertex_index, type, offset);
1616 }
1617
1618 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1619 }
1620
1621 static LLVMValueRef fetch_input_gs(
1622 struct lp_build_tgsi_context *bld_base,
1623 const struct tgsi_full_src_register *reg,
1624 enum tgsi_opcode_type type,
1625 unsigned swizzle_in)
1626 {
1627 struct si_shader_context *ctx = si_shader_context(bld_base);
1628 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1629 unsigned swizzle = swizzle_in & 0xffff;
1630
1631 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1632 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1633 return si_get_primitive_id(ctx, swizzle);
1634
1635 if (!reg->Register.Dimension)
1636 return NULL;
1637
1638 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1639 reg->Dimension.Index,
1640 tgsi2llvmtype(bld_base, type),
1641 swizzle);
1642 }
1643
1644 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1645 {
1646 switch (interpolate) {
1647 case TGSI_INTERPOLATE_CONSTANT:
1648 return 0;
1649
1650 case TGSI_INTERPOLATE_LINEAR:
1651 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1652 return SI_PARAM_LINEAR_SAMPLE;
1653 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1654 return SI_PARAM_LINEAR_CENTROID;
1655 else
1656 return SI_PARAM_LINEAR_CENTER;
1657 break;
1658 case TGSI_INTERPOLATE_COLOR:
1659 case TGSI_INTERPOLATE_PERSPECTIVE:
1660 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1661 return SI_PARAM_PERSP_SAMPLE;
1662 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1663 return SI_PARAM_PERSP_CENTROID;
1664 else
1665 return SI_PARAM_PERSP_CENTER;
1666 break;
1667 default:
1668 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1669 return -1;
1670 }
1671 }
1672
1673 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1674 unsigned attr_index, unsigned chan,
1675 LLVMValueRef prim_mask,
1676 LLVMValueRef i, LLVMValueRef j)
1677 {
1678 if (i || j) {
1679 return ac_build_fs_interp(&ctx->ac,
1680 LLVMConstInt(ctx->i32, chan, 0),
1681 LLVMConstInt(ctx->i32, attr_index, 0),
1682 prim_mask, i, j);
1683 }
1684 return ac_build_fs_interp_mov(&ctx->ac,
1685 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1686 LLVMConstInt(ctx->i32, chan, 0),
1687 LLVMConstInt(ctx->i32, attr_index, 0),
1688 prim_mask);
1689 }
1690
1691 /**
1692 * Interpolate a fragment shader input.
1693 *
1694 * @param ctx context
1695 * @param input_index index of the input in hardware
1696 * @param semantic_name TGSI_SEMANTIC_*
1697 * @param semantic_index semantic index
1698 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1699 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1700 * @param interp_param interpolation weights (i,j)
1701 * @param prim_mask SI_PARAM_PRIM_MASK
1702 * @param face SI_PARAM_FRONT_FACE
1703 * @param result the return value (4 components)
1704 */
1705 static void interp_fs_input(struct si_shader_context *ctx,
1706 unsigned input_index,
1707 unsigned semantic_name,
1708 unsigned semantic_index,
1709 unsigned num_interp_inputs,
1710 unsigned colors_read_mask,
1711 LLVMValueRef interp_param,
1712 LLVMValueRef prim_mask,
1713 LLVMValueRef face,
1714 LLVMValueRef result[4])
1715 {
1716 LLVMValueRef i = NULL, j = NULL;
1717 unsigned chan;
1718
1719 /* fs.constant returns the param from the middle vertex, so it's not
1720 * really useful for flat shading. It's meant to be used for custom
1721 * interpolation (but the intrinsic can't fetch from the other two
1722 * vertices).
1723 *
1724 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1725 * to do the right thing. The only reason we use fs.constant is that
1726 * fs.interp cannot be used on integers, because they can be equal
1727 * to NaN.
1728 *
1729 * When interp is false we will use fs.constant or for newer llvm,
1730 * amdgcn.interp.mov.
1731 */
1732 bool interp = interp_param != NULL;
1733
1734 if (interp) {
1735 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1736 LLVMVectorType(ctx->f32, 2), "");
1737
1738 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1739 ctx->i32_0, "");
1740 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1741 ctx->i32_1, "");
1742 }
1743
1744 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1745 ctx->shader->key.part.ps.prolog.color_two_side) {
1746 LLVMValueRef is_face_positive;
1747
1748 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1749 * otherwise it's at offset "num_inputs".
1750 */
1751 unsigned back_attr_offset = num_interp_inputs;
1752 if (semantic_index == 1 && colors_read_mask & 0xf)
1753 back_attr_offset += 1;
1754
1755 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1756 face, ctx->i32_0, "");
1757
1758 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1759 LLVMValueRef front, back;
1760
1761 front = si_build_fs_interp(ctx,
1762 input_index, chan,
1763 prim_mask, i, j);
1764 back = si_build_fs_interp(ctx,
1765 back_attr_offset, chan,
1766 prim_mask, i, j);
1767
1768 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1769 is_face_positive,
1770 front,
1771 back,
1772 "");
1773 }
1774 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1775 result[0] = si_build_fs_interp(ctx, input_index,
1776 0, prim_mask, i, j);
1777 result[1] =
1778 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1779 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1780 } else {
1781 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1782 result[chan] = si_build_fs_interp(ctx,
1783 input_index, chan,
1784 prim_mask, i, j);
1785 }
1786 }
1787 }
1788
1789 void si_llvm_load_input_fs(
1790 struct si_shader_context *ctx,
1791 unsigned input_index,
1792 LLVMValueRef out[4])
1793 {
1794 struct si_shader *shader = ctx->shader;
1795 struct tgsi_shader_info *info = &shader->selector->info;
1796 LLVMValueRef main_fn = ctx->main_fn;
1797 LLVMValueRef interp_param = NULL;
1798 int interp_param_idx;
1799 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1800 unsigned semantic_index = info->input_semantic_index[input_index];
1801 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1802 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1803
1804 /* Get colors from input VGPRs (set by the prolog). */
1805 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1806 unsigned colors_read = shader->selector->info.colors_read;
1807 unsigned mask = colors_read >> (semantic_index * 4);
1808 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1809 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1810 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1811
1812 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1813 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1814 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1815 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1816 return;
1817 }
1818
1819 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1820 if (interp_param_idx == -1)
1821 return;
1822 else if (interp_param_idx) {
1823 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1824 }
1825
1826 interp_fs_input(ctx, input_index, semantic_name,
1827 semantic_index, 0, /* this param is unused */
1828 shader->selector->info.colors_read, interp_param,
1829 ctx->abi.prim_mask,
1830 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1831 &out[0]);
1832 }
1833
1834 static void declare_input_fs(
1835 struct si_shader_context *ctx,
1836 unsigned input_index,
1837 const struct tgsi_full_declaration *decl,
1838 LLVMValueRef out[4])
1839 {
1840 si_llvm_load_input_fs(ctx, input_index, out);
1841 }
1842
1843 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1844 {
1845 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1846 }
1847
1848 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1849 {
1850 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1851
1852 /* For non-indexed draws, the base vertex set by the driver
1853 * (for direct draws) or the CP (for indirect draws) is the
1854 * first vertex ID, but GLSL expects 0 to be returned.
1855 */
1856 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1857 ctx->param_vs_state_bits);
1858 LLVMValueRef indexed;
1859
1860 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1861 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1862
1863 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1864 ctx->i32_0, "");
1865 }
1866
1867 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1868 {
1869 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1870
1871 LLVMValueRef values[3];
1872 LLVMValueRef result;
1873 unsigned i;
1874 unsigned *properties = ctx->shader->selector->info.properties;
1875
1876 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1877 unsigned sizes[3] = {
1878 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1879 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1880 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1881 };
1882
1883 for (i = 0; i < 3; ++i)
1884 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1885
1886 result = ac_build_gather_values(&ctx->ac, values, 3);
1887 } else {
1888 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1889 }
1890
1891 return result;
1892 }
1893
1894 /**
1895 * Load a dword from a constant buffer.
1896 */
1897 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1898 LLVMValueRef resource,
1899 LLVMValueRef offset)
1900 {
1901 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1902 0, 0, true, true);
1903 }
1904
1905 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1906 {
1907 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1908 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1909 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1910 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1911
1912 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1913 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1914 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1915
1916 LLVMValueRef pos[4] = {
1917 buffer_load_const(ctx, resource, offset0),
1918 buffer_load_const(ctx, resource, offset1),
1919 LLVMConstReal(ctx->f32, 0),
1920 LLVMConstReal(ctx->f32, 0)
1921 };
1922
1923 return ac_build_gather_values(&ctx->ac, pos, 4);
1924 }
1925
1926 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1927 {
1928 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1929 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1930 }
1931
1932 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1933 {
1934 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1935 LLVMValueRef coord[4] = {
1936 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1937 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1938 ctx->ac.f32_0,
1939 ctx->ac.f32_0
1940 };
1941
1942 /* For triangles, the vector should be (u, v, 1-u-v). */
1943 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1944 PIPE_PRIM_TRIANGLES) {
1945 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1946 LLVMBuildFAdd(ctx->ac.builder,
1947 coord[0], coord[1], ""), "");
1948 }
1949 return ac_build_gather_values(&ctx->ac, coord, 4);
1950 }
1951
1952 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1953 unsigned semantic_name)
1954 {
1955 LLVMValueRef base, addr;
1956
1957 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1958
1959 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1960 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1961 LLVMConstInt(ctx->i32, param, 0));
1962
1963 return buffer_load(&ctx->bld_base, ctx->f32,
1964 ~0, ctx->tess_offchip_ring, base, addr, true);
1965
1966 }
1967
1968 static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx,
1969 unsigned semantic_name)
1970 {
1971 LLVMValueRef buf, slot, val[4];
1972 int i, offset;
1973
1974 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1975 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1976 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1977 offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;
1978
1979 for (i = 0; i < 4; i++)
1980 val[i] = buffer_load_const(ctx, buf,
1981 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1982 return ac_build_gather_values(&ctx->ac, val, 4);
1983 }
1984
1985 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1986 unsigned varying_id,
1987 bool load_default_state)
1988 {
1989 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1990 unsigned semantic_name;
1991
1992 if (load_default_state) {
1993 switch (varying_id) {
1994 case VARYING_SLOT_TESS_LEVEL_INNER:
1995 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
1996 break;
1997 case VARYING_SLOT_TESS_LEVEL_OUTER:
1998 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
1999 break;
2000 default:
2001 unreachable("unknown tess level");
2002 }
2003 return load_tess_level_default(ctx, semantic_name);
2004 }
2005
2006 switch (varying_id) {
2007 case VARYING_SLOT_TESS_LEVEL_INNER:
2008 semantic_name = TGSI_SEMANTIC_TESSINNER;
2009 break;
2010 case VARYING_SLOT_TESS_LEVEL_OUTER:
2011 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2012 break;
2013 default:
2014 unreachable("unknown tess level");
2015 }
2016
2017 return load_tess_level(ctx, semantic_name);
2018
2019 }
2020
2021 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2022 {
2023 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2024 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2025 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2026 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2027 return get_num_tcs_out_vertices(ctx);
2028 else
2029 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2030 }
2031
2032 void si_load_system_value(struct si_shader_context *ctx,
2033 unsigned index,
2034 const struct tgsi_full_declaration *decl)
2035 {
2036 LLVMValueRef value = 0;
2037
2038 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2039
2040 switch (decl->Semantic.Name) {
2041 case TGSI_SEMANTIC_INSTANCEID:
2042 value = ctx->abi.instance_id;
2043 break;
2044
2045 case TGSI_SEMANTIC_VERTEXID:
2046 value = LLVMBuildAdd(ctx->ac.builder,
2047 ctx->abi.vertex_id,
2048 ctx->abi.base_vertex, "");
2049 break;
2050
2051 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2052 /* Unused. Clarify the meaning in indexed vs. non-indexed
2053 * draws if this is ever used again. */
2054 assert(false);
2055 break;
2056
2057 case TGSI_SEMANTIC_BASEVERTEX:
2058 value = get_base_vertex(&ctx->abi);
2059 break;
2060
2061 case TGSI_SEMANTIC_BASEINSTANCE:
2062 value = ctx->abi.start_instance;
2063 break;
2064
2065 case TGSI_SEMANTIC_DRAWID:
2066 value = ctx->abi.draw_id;
2067 break;
2068
2069 case TGSI_SEMANTIC_INVOCATIONID:
2070 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
2071 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2072 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
2073 if (ctx->screen->info.chip_class >= GFX10) {
2074 value = LLVMBuildAnd(ctx->ac.builder,
2075 ctx->abi.gs_invocation_id,
2076 LLVMConstInt(ctx->i32, 127, 0), "");
2077 } else {
2078 value = ctx->abi.gs_invocation_id;
2079 }
2080 } else {
2081 assert(!"INVOCATIONID not implemented");
2082 }
2083 break;
2084
2085 case TGSI_SEMANTIC_POSITION:
2086 {
2087 LLVMValueRef pos[4] = {
2088 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2089 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2090 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2091 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2092 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2093 };
2094 value = ac_build_gather_values(&ctx->ac, pos, 4);
2095 break;
2096 }
2097
2098 case TGSI_SEMANTIC_FACE:
2099 value = ctx->abi.front_face;
2100 break;
2101
2102 case TGSI_SEMANTIC_SAMPLEID:
2103 value = si_get_sample_id(ctx);
2104 break;
2105
2106 case TGSI_SEMANTIC_SAMPLEPOS: {
2107 LLVMValueRef pos[4] = {
2108 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2109 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2110 LLVMConstReal(ctx->f32, 0),
2111 LLVMConstReal(ctx->f32, 0)
2112 };
2113 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2114 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2115 value = ac_build_gather_values(&ctx->ac, pos, 4);
2116 break;
2117 }
2118
2119 case TGSI_SEMANTIC_SAMPLEMASK:
2120 /* This can only occur with the OpenGL Core profile, which
2121 * doesn't support smoothing.
2122 */
2123 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2124 break;
2125
2126 case TGSI_SEMANTIC_TESSCOORD:
2127 value = si_load_tess_coord(&ctx->abi);
2128 break;
2129
2130 case TGSI_SEMANTIC_VERTICESIN:
2131 value = si_load_patch_vertices_in(&ctx->abi);
2132 break;
2133
2134 case TGSI_SEMANTIC_TESSINNER:
2135 case TGSI_SEMANTIC_TESSOUTER:
2136 value = load_tess_level(ctx, decl->Semantic.Name);
2137 break;
2138
2139 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
2140 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
2141 value = load_tess_level_default(ctx, decl->Semantic.Name);
2142 break;
2143
2144 case TGSI_SEMANTIC_PRIMID:
2145 value = si_get_primitive_id(ctx, 0);
2146 break;
2147
2148 case TGSI_SEMANTIC_GRID_SIZE:
2149 value = ctx->abi.num_work_groups;
2150 break;
2151
2152 case TGSI_SEMANTIC_BLOCK_SIZE:
2153 value = get_block_size(&ctx->abi);
2154 break;
2155
2156 case TGSI_SEMANTIC_BLOCK_ID:
2157 {
2158 LLVMValueRef values[3];
2159
2160 for (int i = 0; i < 3; i++) {
2161 values[i] = ctx->i32_0;
2162 if (ctx->abi.workgroup_ids[i]) {
2163 values[i] = ctx->abi.workgroup_ids[i];
2164 }
2165 }
2166 value = ac_build_gather_values(&ctx->ac, values, 3);
2167 break;
2168 }
2169
2170 case TGSI_SEMANTIC_THREAD_ID:
2171 value = ctx->abi.local_invocation_ids;
2172 break;
2173
2174 case TGSI_SEMANTIC_HELPER_INVOCATION:
2175 value = ac_build_load_helper_invocation(&ctx->ac);
2176 break;
2177
2178 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2179 value = LLVMConstInt(ctx->i32, ctx->ac.wave_size, 0);
2180 break;
2181
2182 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2183 value = ac_get_thread_id(&ctx->ac);
2184 break;
2185
2186 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2187 {
2188 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2189 if (ctx->ac.wave_size == 64)
2190 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2191 value = LLVMBuildShl(ctx->ac.builder,
2192 LLVMConstInt(ctx->ac.iN_wavemask, 1, 0), id, "");
2193 if (ctx->ac.wave_size == 32)
2194 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2195 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2196 break;
2197 }
2198
2199 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2200 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2201 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2202 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2203 {
2204 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2205 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2206 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2207 /* All bits set except LSB */
2208 value = LLVMConstInt(ctx->ac.iN_wavemask, -2, 0);
2209 } else {
2210 /* All bits set */
2211 value = LLVMConstInt(ctx->ac.iN_wavemask, -1, 0);
2212 }
2213 if (ctx->ac.wave_size == 64)
2214 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2215 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2216 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2217 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2218 value = LLVMBuildNot(ctx->ac.builder, value, "");
2219 if (ctx->ac.wave_size == 32)
2220 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2221 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2222 break;
2223 }
2224
2225 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
2226 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2227 break;
2228
2229 default:
2230 assert(!"unknown system value");
2231 return;
2232 }
2233
2234 ctx->system_values[index] = value;
2235 }
2236
2237 void si_declare_compute_memory(struct si_shader_context *ctx)
2238 {
2239 struct si_shader_selector *sel = ctx->shader->selector;
2240 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2241
2242 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2243 LLVMValueRef var;
2244
2245 assert(!ctx->ac.lds);
2246
2247 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2248 LLVMArrayType(ctx->i8, lds_size),
2249 "compute_lds",
2250 AC_ADDR_SPACE_LDS);
2251 LLVMSetAlignment(var, 64 * 1024);
2252
2253 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2254 }
2255
2256 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2257 const struct tgsi_full_declaration *decl)
2258 {
2259 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2260 assert(decl->Range.First == decl->Range.Last);
2261
2262 si_declare_compute_memory(ctx);
2263 }
2264
2265 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2266 {
2267 LLVMValueRef ptr =
2268 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2269 struct si_shader_selector *sel = ctx->shader->selector;
2270
2271 /* Do the bounds checking with a descriptor, because
2272 * doing computation and manual bounds checking of 64-bit
2273 * addresses generates horrible VALU code with very high
2274 * VGPR usage and very low SIMD occupancy.
2275 */
2276 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2277
2278 LLVMValueRef desc0, desc1;
2279 desc0 = ptr;
2280 desc1 = LLVMConstInt(ctx->i32,
2281 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2282
2283 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2284 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2285 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2286 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2287
2288 if (ctx->screen->info.chip_class >= GFX10)
2289 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2290 S_008F0C_OOB_SELECT(3) |
2291 S_008F0C_RESOURCE_LEVEL(1);
2292 else
2293 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2294 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2295
2296 LLVMValueRef desc_elems[] = {
2297 desc0,
2298 desc1,
2299 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2300 LLVMConstInt(ctx->i32, rsrc3, false)
2301 };
2302
2303 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2304 }
2305
2306 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2307 {
2308 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2309 ctx->param_const_and_shader_buffers);
2310
2311 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2312 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2313 }
2314
2315 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2316 {
2317 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2318 struct si_shader_selector *sel = ctx->shader->selector;
2319
2320 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2321
2322 if (sel->info.const_buffers_declared == 1 &&
2323 sel->info.shader_buffers_declared == 0) {
2324 return load_const_buffer_desc_fast_path(ctx);
2325 }
2326
2327 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2328 index = LLVMBuildAdd(ctx->ac.builder, index,
2329 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2330
2331 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2332 }
2333
2334 static LLVMValueRef
2335 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2336 {
2337 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2338 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2339 ctx->param_const_and_shader_buffers);
2340
2341 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2342 index = LLVMBuildSub(ctx->ac.builder,
2343 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2344 index, "");
2345
2346 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2347 }
2348
2349 static LLVMValueRef fetch_constant(
2350 struct lp_build_tgsi_context *bld_base,
2351 const struct tgsi_full_src_register *reg,
2352 enum tgsi_opcode_type type,
2353 unsigned swizzle_in)
2354 {
2355 struct si_shader_context *ctx = si_shader_context(bld_base);
2356 struct si_shader_selector *sel = ctx->shader->selector;
2357 const struct tgsi_ind_register *ireg = &reg->Indirect;
2358 unsigned buf, idx;
2359 unsigned swizzle = swizzle_in & 0xffff;
2360
2361 LLVMValueRef addr, bufp;
2362
2363 if (swizzle_in == LP_CHAN_ALL) {
2364 unsigned chan;
2365 LLVMValueRef values[4];
2366 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2367 values[chan] = fetch_constant(bld_base, reg, type, chan);
2368
2369 return ac_build_gather_values(&ctx->ac, values, 4);
2370 }
2371
2372 /* Split 64-bit loads. */
2373 if (tgsi_type_is_64bit(type)) {
2374 LLVMValueRef lo, hi;
2375
2376 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2377 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2378 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2379 lo, hi);
2380 }
2381
2382 idx = reg->Register.Index * 4 + swizzle;
2383 if (reg->Register.Indirect) {
2384 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2385 } else {
2386 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2387 }
2388
2389 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2390 if (sel->info.const_buffers_declared == 1 &&
2391 sel->info.shader_buffers_declared == 0) {
2392 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2393 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2394 return bitcast(bld_base, type, result);
2395 }
2396
2397 assert(reg->Register.Dimension);
2398 buf = reg->Dimension.Index;
2399
2400 if (reg->Dimension.Indirect) {
2401 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2402 LLVMValueRef index;
2403 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2404 reg->Dimension.Index,
2405 ctx->num_const_buffers);
2406 index = LLVMBuildAdd(ctx->ac.builder, index,
2407 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2408 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2409 } else
2410 bufp = load_const_buffer_desc(ctx, buf);
2411
2412 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2413 }
2414
2415 /* Initialize arguments for the shader export intrinsic */
2416 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2417 LLVMValueRef *values,
2418 unsigned target,
2419 struct ac_export_args *args)
2420 {
2421 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2422 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2423 unsigned chan;
2424 bool is_int8, is_int10;
2425
2426 /* Default is 0xf. Adjusted below depending on the format. */
2427 args->enabled_channels = 0xf; /* writemask */
2428
2429 /* Specify whether the EXEC mask represents the valid mask */
2430 args->valid_mask = 0;
2431
2432 /* Specify whether this is the last export */
2433 args->done = 0;
2434
2435 /* Specify the target we are exporting */
2436 args->target = target;
2437
2438 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2439 const struct si_shader_key *key = &ctx->shader->key;
2440 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2441 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2442
2443 assert(cbuf >= 0 && cbuf < 8);
2444 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2445 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2446 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2447 }
2448
2449 args->compr = false;
2450 args->out[0] = f32undef;
2451 args->out[1] = f32undef;
2452 args->out[2] = f32undef;
2453 args->out[3] = f32undef;
2454
2455 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2456 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2457 unsigned bits, bool hi) = NULL;
2458
2459 switch (spi_shader_col_format) {
2460 case V_028714_SPI_SHADER_ZERO:
2461 args->enabled_channels = 0; /* writemask */
2462 args->target = V_008DFC_SQ_EXP_NULL;
2463 break;
2464
2465 case V_028714_SPI_SHADER_32_R:
2466 args->enabled_channels = 1; /* writemask */
2467 args->out[0] = values[0];
2468 break;
2469
2470 case V_028714_SPI_SHADER_32_GR:
2471 args->enabled_channels = 0x3; /* writemask */
2472 args->out[0] = values[0];
2473 args->out[1] = values[1];
2474 break;
2475
2476 case V_028714_SPI_SHADER_32_AR:
2477 if (ctx->screen->info.chip_class >= GFX10) {
2478 args->enabled_channels = 0x3; /* writemask */
2479 args->out[0] = values[0];
2480 args->out[1] = values[3];
2481 } else {
2482 args->enabled_channels = 0x9; /* writemask */
2483 args->out[0] = values[0];
2484 args->out[3] = values[3];
2485 }
2486 break;
2487
2488 case V_028714_SPI_SHADER_FP16_ABGR:
2489 packf = ac_build_cvt_pkrtz_f16;
2490 break;
2491
2492 case V_028714_SPI_SHADER_UNORM16_ABGR:
2493 packf = ac_build_cvt_pknorm_u16;
2494 break;
2495
2496 case V_028714_SPI_SHADER_SNORM16_ABGR:
2497 packf = ac_build_cvt_pknorm_i16;
2498 break;
2499
2500 case V_028714_SPI_SHADER_UINT16_ABGR:
2501 packi = ac_build_cvt_pk_u16;
2502 break;
2503
2504 case V_028714_SPI_SHADER_SINT16_ABGR:
2505 packi = ac_build_cvt_pk_i16;
2506 break;
2507
2508 case V_028714_SPI_SHADER_32_ABGR:
2509 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2510 break;
2511 }
2512
2513 /* Pack f16 or norm_i16/u16. */
2514 if (packf) {
2515 for (chan = 0; chan < 2; chan++) {
2516 LLVMValueRef pack_args[2] = {
2517 values[2 * chan],
2518 values[2 * chan + 1]
2519 };
2520 LLVMValueRef packed;
2521
2522 packed = packf(&ctx->ac, pack_args);
2523 args->out[chan] = ac_to_float(&ctx->ac, packed);
2524 }
2525 args->compr = 1; /* COMPR flag */
2526 }
2527 /* Pack i16/u16. */
2528 if (packi) {
2529 for (chan = 0; chan < 2; chan++) {
2530 LLVMValueRef pack_args[2] = {
2531 ac_to_integer(&ctx->ac, values[2 * chan]),
2532 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2533 };
2534 LLVMValueRef packed;
2535
2536 packed = packi(&ctx->ac, pack_args,
2537 is_int8 ? 8 : is_int10 ? 10 : 16,
2538 chan == 1);
2539 args->out[chan] = ac_to_float(&ctx->ac, packed);
2540 }
2541 args->compr = 1; /* COMPR flag */
2542 }
2543 }
2544
2545 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2546 LLVMValueRef alpha)
2547 {
2548 struct si_shader_context *ctx = si_shader_context(bld_base);
2549
2550 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2551 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2552 [PIPE_FUNC_LESS] = LLVMRealOLT,
2553 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2554 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2555 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2556 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2557 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2558 };
2559 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2560 assert(cond);
2561
2562 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2563 SI_PARAM_ALPHA_REF);
2564 LLVMValueRef alpha_pass =
2565 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2566 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2567 } else {
2568 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2569 }
2570 }
2571
2572 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2573 LLVMValueRef alpha,
2574 unsigned samplemask_param)
2575 {
2576 struct si_shader_context *ctx = si_shader_context(bld_base);
2577 LLVMValueRef coverage;
2578
2579 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2580 coverage = LLVMGetParam(ctx->main_fn,
2581 samplemask_param);
2582 coverage = ac_to_integer(&ctx->ac, coverage);
2583
2584 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2585 ctx->i32,
2586 &coverage, 1, AC_FUNC_ATTR_READNONE);
2587
2588 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2589 ctx->f32, "");
2590
2591 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2592 LLVMConstReal(ctx->f32,
2593 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2594
2595 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2596 }
2597
2598 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2599 struct ac_export_args *pos, LLVMValueRef *out_elts)
2600 {
2601 unsigned reg_index;
2602 unsigned chan;
2603 unsigned const_chan;
2604 LLVMValueRef base_elt;
2605 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2606 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2607 SI_VS_CONST_CLIP_PLANES, 0);
2608 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2609
2610 for (reg_index = 0; reg_index < 2; reg_index ++) {
2611 struct ac_export_args *args = &pos[2 + reg_index];
2612
2613 args->out[0] =
2614 args->out[1] =
2615 args->out[2] =
2616 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2617
2618 /* Compute dot products of position and user clip plane vectors */
2619 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2620 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2621 LLVMValueRef addr =
2622 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2623 const_chan) * 4, 0);
2624 base_elt = buffer_load_const(ctx, const_resource,
2625 addr);
2626 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2627 out_elts[const_chan], args->out[chan]);
2628 }
2629 }
2630
2631 args->enabled_channels = 0xf;
2632 args->valid_mask = 0;
2633 args->done = 0;
2634 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2635 args->compr = 0;
2636 }
2637 }
2638
2639 static void si_dump_streamout(struct pipe_stream_output_info *so)
2640 {
2641 unsigned i;
2642
2643 if (so->num_outputs)
2644 fprintf(stderr, "STREAMOUT\n");
2645
2646 for (i = 0; i < so->num_outputs; i++) {
2647 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2648 so->output[i].start_component;
2649 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2650 i, so->output[i].output_buffer,
2651 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2652 so->output[i].register_index,
2653 mask & 1 ? "x" : "",
2654 mask & 2 ? "y" : "",
2655 mask & 4 ? "z" : "",
2656 mask & 8 ? "w" : "");
2657 }
2658 }
2659
2660 void si_emit_streamout_output(struct si_shader_context *ctx,
2661 LLVMValueRef const *so_buffers,
2662 LLVMValueRef const *so_write_offsets,
2663 struct pipe_stream_output *stream_out,
2664 struct si_shader_output_values *shader_out)
2665 {
2666 unsigned buf_idx = stream_out->output_buffer;
2667 unsigned start = stream_out->start_component;
2668 unsigned num_comps = stream_out->num_components;
2669 LLVMValueRef out[4];
2670
2671 assert(num_comps && num_comps <= 4);
2672 if (!num_comps || num_comps > 4)
2673 return;
2674
2675 /* Load the output as int. */
2676 for (int j = 0; j < num_comps; j++) {
2677 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2678
2679 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2680 }
2681
2682 /* Pack the output. */
2683 LLVMValueRef vdata = NULL;
2684
2685 switch (num_comps) {
2686 case 1: /* as i32 */
2687 vdata = out[0];
2688 break;
2689 case 2: /* as v2i32 */
2690 case 3: /* as v3i32 */
2691 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2692 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2693 break;
2694 }
2695 /* as v4i32 (aligned to 4) */
2696 out[3] = LLVMGetUndef(ctx->i32);
2697 /* fall through */
2698 case 4: /* as v4i32 */
2699 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2700 break;
2701 }
2702
2703 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2704 vdata, num_comps,
2705 so_write_offsets[buf_idx],
2706 ctx->i32_0,
2707 stream_out->dst_offset * 4, ac_glc | ac_slc, false);
2708 }
2709
2710 /**
2711 * Write streamout data to buffers for vertex stream @p stream (different
2712 * vertex streams can occur for GS copy shaders).
2713 */
2714 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2715 struct si_shader_output_values *outputs,
2716 unsigned noutput, unsigned stream)
2717 {
2718 struct si_shader_selector *sel = ctx->shader->selector;
2719 struct pipe_stream_output_info *so = &sel->so;
2720 LLVMBuilderRef builder = ctx->ac.builder;
2721 int i;
2722
2723 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2724 LLVMValueRef so_vtx_count =
2725 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2726
2727 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2728
2729 /* can_emit = tid < so_vtx_count; */
2730 LLVMValueRef can_emit =
2731 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2732
2733 /* Emit the streamout code conditionally. This actually avoids
2734 * out-of-bounds buffer access. The hw tells us via the SGPR
2735 * (so_vtx_count) which threads are allowed to emit streamout data. */
2736 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2737 {
2738 /* The buffer offset is computed as follows:
2739 * ByteOffset = streamout_offset[buffer_id]*4 +
2740 * (streamout_write_index + thread_id)*stride[buffer_id] +
2741 * attrib_offset
2742 */
2743
2744 LLVMValueRef so_write_index =
2745 LLVMGetParam(ctx->main_fn,
2746 ctx->param_streamout_write_index);
2747
2748 /* Compute (streamout_write_index + thread_id). */
2749 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2750
2751 /* Load the descriptor and compute the write offset for each
2752 * enabled buffer. */
2753 LLVMValueRef so_write_offset[4] = {};
2754 LLVMValueRef so_buffers[4];
2755 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2756 ctx->param_rw_buffers);
2757
2758 for (i = 0; i < 4; i++) {
2759 if (!so->stride[i])
2760 continue;
2761
2762 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2763 SI_VS_STREAMOUT_BUF0 + i, 0);
2764
2765 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2766
2767 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2768 ctx->param_streamout_offset[i]);
2769 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2770
2771 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2772 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2773 so_offset);
2774 }
2775
2776 /* Write streamout data. */
2777 for (i = 0; i < so->num_outputs; i++) {
2778 unsigned reg = so->output[i].register_index;
2779
2780 if (reg >= noutput)
2781 continue;
2782
2783 if (stream != so->output[i].stream)
2784 continue;
2785
2786 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
2787 &so->output[i], &outputs[reg]);
2788 }
2789 }
2790 ac_build_endif(&ctx->ac, 6501);
2791 }
2792
2793 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2794 LLVMValueRef *values)
2795 {
2796 struct ac_export_args args;
2797
2798 si_llvm_init_export_args(ctx, values,
2799 V_008DFC_SQ_EXP_PARAM + index, &args);
2800 ac_build_export(&ctx->ac, &args);
2801 }
2802
2803 static void si_build_param_exports(struct si_shader_context *ctx,
2804 struct si_shader_output_values *outputs,
2805 unsigned noutput)
2806 {
2807 struct si_shader *shader = ctx->shader;
2808 unsigned param_count = 0;
2809
2810 for (unsigned i = 0; i < noutput; i++) {
2811 unsigned semantic_name = outputs[i].semantic_name;
2812 unsigned semantic_index = outputs[i].semantic_index;
2813
2814 if (outputs[i].vertex_stream[0] != 0 &&
2815 outputs[i].vertex_stream[1] != 0 &&
2816 outputs[i].vertex_stream[2] != 0 &&
2817 outputs[i].vertex_stream[3] != 0)
2818 continue;
2819
2820 switch (semantic_name) {
2821 case TGSI_SEMANTIC_LAYER:
2822 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2823 case TGSI_SEMANTIC_CLIPDIST:
2824 case TGSI_SEMANTIC_COLOR:
2825 case TGSI_SEMANTIC_BCOLOR:
2826 case TGSI_SEMANTIC_PRIMID:
2827 case TGSI_SEMANTIC_FOG:
2828 case TGSI_SEMANTIC_TEXCOORD:
2829 case TGSI_SEMANTIC_GENERIC:
2830 break;
2831 default:
2832 continue;
2833 }
2834
2835 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2836 semantic_index < SI_MAX_IO_GENERIC) &&
2837 shader->key.opt.kill_outputs &
2838 (1ull << si_shader_io_get_unique_index(semantic_name,
2839 semantic_index, true)))
2840 continue;
2841
2842 si_export_param(ctx, param_count, outputs[i].values);
2843
2844 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2845 shader->info.vs_output_param_offset[i] = param_count++;
2846 }
2847
2848 shader->info.nr_param_exports = param_count;
2849 }
2850
2851 /**
2852 * Vertex color clamping.
2853 *
2854 * This uses a state constant loaded in a user data SGPR and
2855 * an IF statement is added that clamps all colors if the constant
2856 * is true.
2857 */
2858 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2859 struct si_shader_output_values *outputs,
2860 unsigned noutput)
2861 {
2862 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2863 bool has_colors = false;
2864
2865 /* Store original colors to alloca variables. */
2866 for (unsigned i = 0; i < noutput; i++) {
2867 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2868 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2869 continue;
2870
2871 for (unsigned j = 0; j < 4; j++) {
2872 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2873 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2874 }
2875 has_colors = true;
2876 }
2877
2878 if (!has_colors)
2879 return;
2880
2881 /* The state is in the first bit of the user SGPR. */
2882 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2883 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2884
2885 ac_build_ifcc(&ctx->ac, cond, 6502);
2886
2887 /* Store clamped colors to alloca variables within the conditional block. */
2888 for (unsigned i = 0; i < noutput; i++) {
2889 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2890 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2891 continue;
2892
2893 for (unsigned j = 0; j < 4; j++) {
2894 LLVMBuildStore(ctx->ac.builder,
2895 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2896 addr[i][j]);
2897 }
2898 }
2899 ac_build_endif(&ctx->ac, 6502);
2900
2901 /* Load clamped colors */
2902 for (unsigned i = 0; i < noutput; i++) {
2903 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2904 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2905 continue;
2906
2907 for (unsigned j = 0; j < 4; j++) {
2908 outputs[i].values[j] =
2909 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2910 }
2911 }
2912 }
2913
2914 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2915 * (position and parameter data only).