radeonsi: clean up si_shader_info
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <llvm/Config/llvm-config.h>
26
27 #include "util/u_memory.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "ac_exp_param.h"
32 #include "ac_shader_util.h"
33 #include "ac_rtld.h"
34 #include "ac_llvm_util.h"
35 #include "si_shader_internal.h"
36 #include "si_pipe.h"
37 #include "sid.h"
38
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_serialize.h"
41
42 static const char scratch_rsrc_dword0_symbol[] =
43 "SCRATCH_RSRC_DWORD0";
44
45 static const char scratch_rsrc_dword1_symbol[] =
46 "SCRATCH_RSRC_DWORD1";
47
48 static void si_llvm_emit_barrier(struct si_shader_context *ctx);
49
50 static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
51
52 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
53 union si_shader_part_key *key);
54 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
55 union si_shader_part_key *key);
56 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
57 union si_shader_part_key *key);
58 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
59 union si_shader_part_key *key);
60 static void si_fix_resource_usage(struct si_screen *sscreen,
61 struct si_shader *shader);
62
63 /* Ideally pass the sample mask input to the PS epilog as v14, which
64 * is its usual location, so that the shader doesn't have to add v_mov.
65 */
66 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
67
68 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
69 LLVMTypeRef type)
70 {
71 if (type == ctx->ac.i64 || type == ctx->ac.f64)
72 return true;
73
74 return false;
75 }
76
77 /** Whether the shader runs as a combination of multiple API shaders */
78 static bool is_multi_part_shader(struct si_shader_context *ctx)
79 {
80 if (ctx->screen->info.chip_class <= GFX8)
81 return false;
82
83 return ctx->shader->key.as_ls ||
84 ctx->shader->key.as_es ||
85 ctx->type == PIPE_SHADER_TESS_CTRL ||
86 ctx->type == PIPE_SHADER_GEOMETRY;
87 }
88
89 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
90 static bool is_merged_shader(struct si_shader_context *ctx)
91 {
92 return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
93 }
94
95 /**
96 * Returns a unique index for a per-patch semantic name and index. The index
97 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
98 * can be calculated.
99 */
100 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
101 {
102 switch (semantic_name) {
103 case TGSI_SEMANTIC_TESSOUTER:
104 return 0;
105 case TGSI_SEMANTIC_TESSINNER:
106 return 1;
107 case TGSI_SEMANTIC_PATCH:
108 assert(index < 30);
109 return 2 + index;
110
111 default:
112 assert(!"invalid semantic name");
113 return 0;
114 }
115 }
116
117 /**
118 * Returns a unique index for a semantic name and index. The index must be
119 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
120 * calculated.
121 */
122 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
123 unsigned is_varying)
124 {
125 switch (semantic_name) {
126 case TGSI_SEMANTIC_POSITION:
127 return 0;
128 case TGSI_SEMANTIC_GENERIC:
129 /* Since some shader stages use the the highest used IO index
130 * to determine the size to allocate for inputs/outputs
131 * (in LDS, tess and GS rings). GENERIC should be placed right
132 * after POSITION to make that size as small as possible.
133 */
134 if (index < SI_MAX_IO_GENERIC)
135 return 1 + index;
136
137 assert(!"invalid generic index");
138 return 0;
139 case TGSI_SEMANTIC_FOG:
140 return SI_MAX_IO_GENERIC + 1;
141 case TGSI_SEMANTIC_COLOR:
142 assert(index < 2);
143 return SI_MAX_IO_GENERIC + 2 + index;
144 case TGSI_SEMANTIC_BCOLOR:
145 assert(index < 2);
146 /* If it's a varying, COLOR and BCOLOR alias. */
147 if (is_varying)
148 return SI_MAX_IO_GENERIC + 2 + index;
149 else
150 return SI_MAX_IO_GENERIC + 4 + index;
151 case TGSI_SEMANTIC_TEXCOORD:
152 assert(index < 8);
153 return SI_MAX_IO_GENERIC + 6 + index;
154
155 /* These are rarely used between LS and HS or ES and GS. */
156 case TGSI_SEMANTIC_CLIPDIST:
157 assert(index < 2);
158 return SI_MAX_IO_GENERIC + 6 + 8 + index;
159 case TGSI_SEMANTIC_CLIPVERTEX:
160 return SI_MAX_IO_GENERIC + 6 + 8 + 2;
161 case TGSI_SEMANTIC_PSIZE:
162 return SI_MAX_IO_GENERIC + 6 + 8 + 3;
163
164 /* These can't be written by LS, HS, and ES. */
165 case TGSI_SEMANTIC_LAYER:
166 return SI_MAX_IO_GENERIC + 6 + 8 + 4;
167 case TGSI_SEMANTIC_VIEWPORT_INDEX:
168 return SI_MAX_IO_GENERIC + 6 + 8 + 5;
169 case TGSI_SEMANTIC_PRIMID:
170 STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
171 return SI_MAX_IO_GENERIC + 6 + 8 + 6;
172 default:
173 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
174 assert(!"invalid semantic name");
175 return 0;
176 }
177 }
178
179 /**
180 * Get the value of a shader input parameter and extract a bitfield.
181 */
182 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
183 LLVMValueRef value, unsigned rshift,
184 unsigned bitwidth)
185 {
186 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
187 value = ac_to_integer(&ctx->ac, value);
188
189 if (rshift)
190 value = LLVMBuildLShr(ctx->ac.builder, value,
191 LLVMConstInt(ctx->i32, rshift, 0), "");
192
193 if (rshift + bitwidth < 32) {
194 unsigned mask = (1 << bitwidth) - 1;
195 value = LLVMBuildAnd(ctx->ac.builder, value,
196 LLVMConstInt(ctx->i32, mask, 0), "");
197 }
198
199 return value;
200 }
201
202 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
203 struct ac_arg param, unsigned rshift,
204 unsigned bitwidth)
205 {
206 LLVMValueRef value = ac_get_arg(&ctx->ac, param);
207
208 return unpack_llvm_param(ctx, value, rshift, bitwidth);
209 }
210
211 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
212 {
213 switch (ctx->type) {
214 case PIPE_SHADER_TESS_CTRL:
215 return si_unpack_param(ctx, ctx->args.tcs_rel_ids, 0, 8);
216
217 case PIPE_SHADER_TESS_EVAL:
218 return ac_get_arg(&ctx->ac, ctx->tes_rel_patch_id);
219
220 default:
221 assert(0);
222 return NULL;
223 }
224 }
225
226 /* Tessellation shaders pass outputs to the next shader using LDS.
227 *
228 * LS outputs = TCS inputs
229 * TCS outputs = TES inputs
230 *
231 * The LDS layout is:
232 * - TCS inputs for patch 0
233 * - TCS inputs for patch 1
234 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
235 * - ...
236 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
237 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
238 * - TCS outputs for patch 1
239 * - Per-patch TCS outputs for patch 1
240 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
241 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
242 * - ...
243 *
244 * All three shaders VS(LS), TCS, TES share the same LDS space.
245 */
246
247 static LLVMValueRef
248 get_tcs_in_patch_stride(struct si_shader_context *ctx)
249 {
250 return si_unpack_param(ctx, ctx->vs_state_bits, 8, 13);
251 }
252
253 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
254 {
255 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
256
257 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
258 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
259
260 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
261 }
262
263 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
264 {
265 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
266
267 return LLVMConstInt(ctx->i32, stride, 0);
268 }
269
270 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
271 {
272 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
273 return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 0, 13);
274
275 const struct si_shader_info *info = &ctx->shader->selector->info;
276 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
277 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
278 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
279 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
280 num_patch_outputs * 4;
281 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
282 }
283
284 static LLVMValueRef
285 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
286 {
287 return LLVMBuildMul(ctx->ac.builder,
288 si_unpack_param(ctx, ctx->tcs_out_lds_offsets, 0, 16),
289 LLVMConstInt(ctx->i32, 4, 0), "");
290 }
291
292 static LLVMValueRef
293 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
294 {
295 return LLVMBuildMul(ctx->ac.builder,
296 si_unpack_param(ctx, ctx->tcs_out_lds_offsets, 16, 16),
297 LLVMConstInt(ctx->i32, 4, 0), "");
298 }
299
300 static LLVMValueRef
301 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
302 {
303 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
304 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
305
306 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
307 }
308
309 static LLVMValueRef
310 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
311 {
312 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
313 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
314 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
315
316 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
321 {
322 LLVMValueRef patch0_patch_data_offset =
323 get_tcs_out_patch0_patch_data_offset(ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
326
327 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
328 }
329
330 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
331 {
332 unsigned tcs_out_vertices =
333 ctx->shader->selector ?
334 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
335
336 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
337 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
338 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
339
340 return si_unpack_param(ctx, ctx->tcs_offchip_layout, 6, 6);
341 }
342
343 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
344 {
345 unsigned stride;
346
347 switch (ctx->type) {
348 case PIPE_SHADER_VERTEX:
349 stride = ctx->shader->selector->lshs_vertex_stride / 4;
350 return LLVMConstInt(ctx->i32, stride, 0);
351
352 case PIPE_SHADER_TESS_CTRL:
353 if (ctx->screen->info.chip_class >= GFX9 &&
354 ctx->shader->is_monolithic) {
355 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
356 return LLVMConstInt(ctx->i32, stride, 0);
357 }
358 return si_unpack_param(ctx, ctx->vs_state_bits, 24, 8);
359
360 default:
361 assert(0);
362 return NULL;
363 }
364 }
365
366 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
367 LLVMValueRef i32, unsigned index)
368 {
369 assert(index <= 1);
370
371 if (index == 1)
372 return LLVMBuildAShr(ctx->ac.builder, i32,
373 LLVMConstInt(ctx->i32, 16, 0), "");
374
375 return LLVMBuildSExt(ctx->ac.builder,
376 LLVMBuildTrunc(ctx->ac.builder, i32,
377 ctx->ac.i16, ""),
378 ctx->i32, "");
379 }
380
381 void si_llvm_load_input_vs(
382 struct si_shader_context *ctx,
383 unsigned input_index,
384 LLVMValueRef out[4])
385 {
386 const struct si_shader_info *info = &ctx->shader->selector->info;
387 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
388
389 if (vs_blit_property) {
390 LLVMValueRef vertex_id = ctx->abi.vertex_id;
391 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
392 LLVMIntULE, vertex_id,
393 ctx->i32_1, "");
394 /* Use LLVMIntNE, because we have 3 vertices and only
395 * the middle one should use y2.
396 */
397 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
398 LLVMIntNE, vertex_id,
399 ctx->i32_1, "");
400
401 unsigned param_vs_blit_inputs = ctx->vs_blit_inputs.arg_index;
402 if (input_index == 0) {
403 /* Position: */
404 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
405 param_vs_blit_inputs);
406 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
407 param_vs_blit_inputs + 1);
408
409 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
410 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
411 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
412 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
413
414 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
415 x1, x2, "");
416 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
417 y1, y2, "");
418
419 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
420 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
421 out[2] = LLVMGetParam(ctx->main_fn,
422 param_vs_blit_inputs + 2);
423 out[3] = ctx->ac.f32_1;
424 return;
425 }
426
427 /* Color or texture coordinates: */
428 assert(input_index == 1);
429
430 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
431 for (int i = 0; i < 4; i++) {
432 out[i] = LLVMGetParam(ctx->main_fn,
433 param_vs_blit_inputs + 3 + i);
434 }
435 } else {
436 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
437 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
438 param_vs_blit_inputs + 3);
439 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
440 param_vs_blit_inputs + 4);
441 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
442 param_vs_blit_inputs + 5);
443 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
444 param_vs_blit_inputs + 6);
445
446 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
447 x1, x2, "");
448 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
449 y1, y2, "");
450 out[2] = LLVMGetParam(ctx->main_fn,
451 param_vs_blit_inputs + 7);
452 out[3] = LLVMGetParam(ctx->main_fn,
453 param_vs_blit_inputs + 8);
454 }
455 return;
456 }
457
458 unsigned num_vbos_in_user_sgprs = ctx->shader->selector->num_vbos_in_user_sgprs;
459 union si_vs_fix_fetch fix_fetch;
460 LLVMValueRef vb_desc;
461 LLVMValueRef vertex_index;
462 LLVMValueRef tmp;
463
464 if (input_index < num_vbos_in_user_sgprs) {
465 vb_desc = ac_get_arg(&ctx->ac, ctx->vb_descriptors[input_index]);
466 } else {
467 unsigned index= input_index - num_vbos_in_user_sgprs;
468 vb_desc = ac_build_load_to_sgpr(&ctx->ac,
469 ac_get_arg(&ctx->ac, ctx->vertex_buffers),
470 LLVMConstInt(ctx->i32, index, 0));
471 }
472
473 vertex_index = LLVMGetParam(ctx->main_fn,
474 ctx->vertex_index0.arg_index +
475 input_index);
476
477 /* Use the open-coded implementation for all loads of doubles and
478 * of dword-sized data that needs fixups. We need to insert conversion
479 * code anyway, and the amd/common code does it for us.
480 *
481 * Note: On LLVM <= 8, we can only open-code formats with
482 * channel size >= 4 bytes.
483 */
484 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
485 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
486 if (opencode ||
487 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
488 (fix_fetch.u.log_size == 2)) {
489 tmp = ac_build_opencoded_load_format(
490 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
491 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
492 vb_desc, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
493 for (unsigned i = 0; i < 4; ++i)
494 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
495 return;
496 }
497
498 /* Do multiple loads for special formats. */
499 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
500 LLVMValueRef fetches[4];
501 unsigned num_fetches;
502 unsigned fetch_stride;
503 unsigned channels_per_fetch;
504
505 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
506 num_fetches = MIN2(required_channels, 3);
507 fetch_stride = 1 << fix_fetch.u.log_size;
508 channels_per_fetch = 1;
509 } else {
510 num_fetches = 1;
511 fetch_stride = 0;
512 channels_per_fetch = required_channels;
513 }
514
515 for (unsigned i = 0; i < num_fetches; ++i) {
516 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
517 fetches[i] = ac_build_buffer_load_format(&ctx->ac, vb_desc, vertex_index, voffset,
518 channels_per_fetch, 0, true);
519 }
520
521 if (num_fetches == 1 && channels_per_fetch > 1) {
522 LLVMValueRef fetch = fetches[0];
523 for (unsigned i = 0; i < channels_per_fetch; ++i) {
524 tmp = LLVMConstInt(ctx->i32, i, false);
525 fetches[i] = LLVMBuildExtractElement(
526 ctx->ac.builder, fetch, tmp, "");
527 }
528 num_fetches = channels_per_fetch;
529 channels_per_fetch = 1;
530 }
531
532 for (unsigned i = num_fetches; i < 4; ++i)
533 fetches[i] = LLVMGetUndef(ctx->f32);
534
535 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
536 required_channels == 4) {
537 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
538 fetches[3] = ctx->ac.i32_1;
539 else
540 fetches[3] = ctx->ac.f32_1;
541 } else if (fix_fetch.u.log_size == 3 &&
542 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
543 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
544 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
545 required_channels == 4) {
546 /* For 2_10_10_10, the hardware returns an unsigned value;
547 * convert it to a signed one.
548 */
549 LLVMValueRef tmp = fetches[3];
550 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
551
552 /* First, recover the sign-extended signed integer value. */
553 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
554 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
555 else
556 tmp = ac_to_integer(&ctx->ac, tmp);
557
558 /* For the integer-like cases, do a natural sign extension.
559 *
560 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
561 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
562 * exponent.
563 */
564 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
565 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
566 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
567 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
568
569 /* Convert back to the right type. */
570 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
571 LLVMValueRef clamp;
572 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
573 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
574 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
575 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
576 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
577 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
578 }
579
580 fetches[3] = tmp;
581 }
582
583 for (unsigned i = 0; i < 4; ++i)
584 out[i] = ac_to_float(&ctx->ac, fetches[i]);
585 }
586
587 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
588 unsigned swizzle)
589 {
590 if (swizzle > 0)
591 return ctx->i32_0;
592
593 switch (ctx->type) {
594 case PIPE_SHADER_VERTEX:
595 return ac_get_arg(&ctx->ac, ctx->vs_prim_id);
596 case PIPE_SHADER_TESS_CTRL:
597 return ac_get_arg(&ctx->ac, ctx->args.tcs_patch_id);
598 case PIPE_SHADER_TESS_EVAL:
599 return ac_get_arg(&ctx->ac, ctx->args.tes_patch_id);
600 case PIPE_SHADER_GEOMETRY:
601 return ac_get_arg(&ctx->ac, ctx->args.gs_prim_id);
602 default:
603 assert(0);
604 return ctx->i32_0;
605 }
606 }
607
608 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
609 LLVMValueRef vertex_dw_stride,
610 LLVMValueRef base_addr,
611 LLVMValueRef vertex_index,
612 LLVMValueRef param_index,
613 ubyte name, ubyte index)
614 {
615 if (vertex_dw_stride) {
616 base_addr = ac_build_imad(&ctx->ac, vertex_index,
617 vertex_dw_stride, base_addr);
618 }
619
620 if (param_index) {
621 base_addr = ac_build_imad(&ctx->ac, param_index,
622 LLVMConstInt(ctx->i32, 4, 0), base_addr);
623 }
624
625 int param = name == TGSI_SEMANTIC_PATCH ||
626 name == TGSI_SEMANTIC_TESSINNER ||
627 name == TGSI_SEMANTIC_TESSOUTER ?
628 si_shader_io_get_unique_index_patch(name, index) :
629 si_shader_io_get_unique_index(name, index, false);
630
631 /* Add the base address of the element. */
632 return LLVMBuildAdd(ctx->ac.builder, base_addr,
633 LLVMConstInt(ctx->i32, param * 4, 0), "");
634 }
635
636 /* The offchip buffer layout for TCS->TES is
637 *
638 * - attribute 0 of patch 0 vertex 0
639 * - attribute 0 of patch 0 vertex 1
640 * - attribute 0 of patch 0 vertex 2
641 * ...
642 * - attribute 0 of patch 1 vertex 0
643 * - attribute 0 of patch 1 vertex 1
644 * ...
645 * - attribute 1 of patch 0 vertex 0
646 * - attribute 1 of patch 0 vertex 1
647 * ...
648 * - per patch attribute 0 of patch 0
649 * - per patch attribute 0 of patch 1
650 * ...
651 *
652 * Note that every attribute has 4 components.
653 */
654 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
655 LLVMValueRef rel_patch_id,
656 LLVMValueRef vertex_index,
657 LLVMValueRef param_index)
658 {
659 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
660 LLVMValueRef param_stride, constant16;
661
662 vertices_per_patch = get_num_tcs_out_vertices(ctx);
663 num_patches = si_unpack_param(ctx, ctx->tcs_offchip_layout, 0, 6);
664 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
665 num_patches, "");
666
667 constant16 = LLVMConstInt(ctx->i32, 16, 0);
668 if (vertex_index) {
669 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
670 vertices_per_patch, vertex_index);
671 param_stride = total_vertices;
672 } else {
673 base_addr = rel_patch_id;
674 param_stride = num_patches;
675 }
676
677 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
678 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
679
680 if (!vertex_index) {
681 LLVMValueRef patch_data_offset =
682 si_unpack_param(ctx, ctx->tcs_offchip_layout, 12, 20);
683
684 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
685 patch_data_offset, "");
686 }
687 return base_addr;
688 }
689
690 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
691 struct si_shader_context *ctx,
692 LLVMValueRef vertex_index,
693 LLVMValueRef param_index,
694 ubyte name, ubyte index)
695 {
696 unsigned param_index_base;
697
698 param_index_base = name == TGSI_SEMANTIC_PATCH ||
699 name == TGSI_SEMANTIC_TESSINNER ||
700 name == TGSI_SEMANTIC_TESSOUTER ?
701 si_shader_io_get_unique_index_patch(name, index) :
702 si_shader_io_get_unique_index(name, index, false);
703
704 if (param_index) {
705 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
706 LLVMConstInt(ctx->i32, param_index_base, 0),
707 "");
708 } else {
709 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
710 }
711
712 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
713 vertex_index, param_index);
714 }
715
716 static LLVMValueRef si_build_gather_64bit(struct si_shader_context *ctx,
717 LLVMTypeRef type,
718 LLVMValueRef val1,
719 LLVMValueRef val2)
720 {
721 LLVMValueRef values[2] = {
722 ac_to_integer(&ctx->ac, val1),
723 ac_to_integer(&ctx->ac, val2),
724 };
725 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
726 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
727 }
728
729 static LLVMValueRef buffer_load(struct si_shader_context *ctx,
730 LLVMTypeRef type, unsigned swizzle,
731 LLVMValueRef buffer, LLVMValueRef offset,
732 LLVMValueRef base, bool can_speculate)
733 {
734 LLVMValueRef value, value2;
735 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
736
737 if (swizzle == ~0) {
738 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
739 0, ac_glc, can_speculate, false);
740
741 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
742 }
743
744 if (!llvm_type_is_64bit(ctx, type)) {
745 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
746 0, ac_glc, can_speculate, false);
747
748 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
749 return LLVMBuildExtractElement(ctx->ac.builder, value,
750 LLVMConstInt(ctx->i32, swizzle, 0), "");
751 }
752
753 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
754 swizzle * 4, ac_glc, can_speculate, false);
755
756 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
757 swizzle * 4 + 4, ac_glc, can_speculate, false);
758
759 return si_build_gather_64bit(ctx, type, value, value2);
760 }
761
762 /**
763 * Load from LSHS LDS storage.
764 *
765 * \param type output value type
766 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
767 * \param dw_addr address in dwords
768 */
769 static LLVMValueRef lshs_lds_load(struct si_shader_context *ctx,
770 LLVMTypeRef type, unsigned swizzle,
771 LLVMValueRef dw_addr)
772 {
773 LLVMValueRef value;
774
775 if (swizzle == ~0) {
776 LLVMValueRef values[4];
777
778 for (unsigned chan = 0; chan < 4; chan++)
779 values[chan] = lshs_lds_load(ctx, type, chan, dw_addr);
780
781 return ac_build_gather_values(&ctx->ac, values, 4);
782 }
783
784 /* Split 64-bit loads. */
785 if (llvm_type_is_64bit(ctx, type)) {
786 LLVMValueRef lo, hi;
787
788 lo = lshs_lds_load(ctx, ctx->i32, swizzle, dw_addr);
789 hi = lshs_lds_load(ctx, ctx->i32, swizzle + 1, dw_addr);
790 return si_build_gather_64bit(ctx, type, lo, hi);
791 }
792
793 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
794 LLVMConstInt(ctx->i32, swizzle, 0), "");
795
796 value = ac_lds_load(&ctx->ac, dw_addr);
797
798 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
799 }
800
801 /**
802 * Store to LSHS LDS storage.
803 *
804 * \param swizzle offset (typically 0..3)
805 * \param dw_addr address in dwords
806 * \param value value to store
807 */
808 static void lshs_lds_store(struct si_shader_context *ctx,
809 unsigned dw_offset_imm, LLVMValueRef dw_addr,
810 LLVMValueRef value)
811 {
812 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
813 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
814
815 ac_lds_store(&ctx->ac, dw_addr, value);
816 }
817
818 enum si_tess_ring {
819 TCS_FACTOR_RING,
820 TESS_OFFCHIP_RING_TCS,
821 TESS_OFFCHIP_RING_TES,
822 };
823
824 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
825 enum si_tess_ring ring)
826 {
827 LLVMBuilderRef builder = ctx->ac.builder;
828 LLVMValueRef addr = ac_get_arg(&ctx->ac,
829 ring == TESS_OFFCHIP_RING_TES ?
830 ctx->tes_offchip_addr :
831 ctx->tcs_out_lds_layout);
832
833 /* TCS only receives high 13 bits of the address. */
834 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
835 addr = LLVMBuildAnd(builder, addr,
836 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
837 }
838
839 if (ring == TCS_FACTOR_RING) {
840 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
841 addr = LLVMBuildAdd(builder, addr,
842 LLVMConstInt(ctx->i32, tf_offset, 0), "");
843 }
844
845 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
846 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
847 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
848 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
849
850 if (ctx->screen->info.chip_class >= GFX10)
851 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
852 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
853 S_008F0C_RESOURCE_LEVEL(1);
854 else
855 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
856 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
857
858 LLVMValueRef desc[4];
859 desc[0] = addr;
860 desc[1] = LLVMConstInt(ctx->i32,
861 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
862 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
863 desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);
864
865 return ac_build_gather_values(&ctx->ac, desc, 4);
866 }
867
868 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
869 LLVMTypeRef type,
870 LLVMValueRef vertex_index,
871 LLVMValueRef param_index,
872 unsigned const_index,
873 unsigned location,
874 unsigned driver_location,
875 unsigned component,
876 unsigned num_components,
877 bool is_patch,
878 bool is_compact,
879 bool load_input)
880 {
881 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
882 struct si_shader_info *info = &ctx->shader->selector->info;
883 LLVMValueRef dw_addr, stride;
884 ubyte name, index;
885
886 driver_location = driver_location / 4;
887
888 if (load_input) {
889 name = info->input_semantic_name[driver_location];
890 index = info->input_semantic_index[driver_location];
891 } else {
892 name = info->output_semantic_name[driver_location];
893 index = info->output_semantic_index[driver_location];
894 }
895
896 assert((name == TGSI_SEMANTIC_PATCH ||
897 name == TGSI_SEMANTIC_TESSINNER ||
898 name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
899
900 if (load_input) {
901 stride = get_tcs_in_vertex_dw_stride(ctx);
902 dw_addr = get_tcs_in_current_patch_offset(ctx);
903 } else {
904 if (is_patch) {
905 stride = NULL;
906 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
907 } else {
908 stride = get_tcs_out_vertex_dw_stride(ctx);
909 dw_addr = get_tcs_out_current_patch_offset(ctx);
910 }
911 }
912
913 if (!param_index) {
914 param_index = LLVMConstInt(ctx->i32, const_index, 0);
915 }
916
917 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
918 vertex_index, param_index,
919 name, index);
920
921 LLVMValueRef value[4];
922 for (unsigned i = 0; i < num_components; i++) {
923 unsigned offset = i;
924 if (llvm_type_is_64bit(ctx, type))
925 offset *= 2;
926
927 offset += component;
928 value[i + component] = lshs_lds_load(ctx, type, offset, dw_addr);
929 }
930
931 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
932 }
933
934 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
935 LLVMTypeRef type,
936 LLVMValueRef vertex_index,
937 LLVMValueRef param_index,
938 unsigned const_index,
939 unsigned location,
940 unsigned driver_location,
941 unsigned component,
942 unsigned num_components,
943 bool is_patch,
944 bool is_compact,
945 bool load_input)
946 {
947 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
948 struct si_shader_info *info = &ctx->shader->selector->info;
949 LLVMValueRef base, addr;
950
951 driver_location = driver_location / 4;
952 ubyte name = info->input_semantic_name[driver_location];
953 ubyte index = info->input_semantic_index[driver_location];
954
955 assert((name == TGSI_SEMANTIC_PATCH ||
956 name == TGSI_SEMANTIC_TESSINNER ||
957 name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
958
959 base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
960
961 if (!param_index) {
962 param_index = LLVMConstInt(ctx->i32, const_index, 0);
963 }
964
965 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
966 param_index,
967 name, index);
968
969 /* TODO: This will generate rather ordinary llvm code, although it
970 * should be easy for the optimiser to fix up. In future we might want
971 * to refactor buffer_load().
972 */
973 LLVMValueRef value[4];
974 for (unsigned i = 0; i < num_components; i++) {
975 unsigned offset = i;
976 if (llvm_type_is_64bit(ctx, type)) {
977 offset *= 2;
978 if (offset == 4) {
979 ubyte name = info->input_semantic_name[driver_location + 1];
980 ubyte index = info->input_semantic_index[driver_location + 1];
981 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
982 vertex_index,
983 param_index,
984 name, index);
985 }
986
987 offset = offset % 4;
988 }
989
990 offset += component;
991 value[i + component] = buffer_load(ctx, type, offset,
992 ctx->tess_offchip_ring, base, addr, true);
993 }
994
995 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
996 }
997
998 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
999 const struct nir_variable *var,
1000 LLVMValueRef vertex_index,
1001 LLVMValueRef param_index,
1002 unsigned const_index,
1003 LLVMValueRef src,
1004 unsigned writemask)
1005 {
1006 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1007 struct si_shader_info *info = &ctx->shader->selector->info;
1008 const unsigned component = var->data.location_frac;
1009 unsigned driver_location = var->data.driver_location;
1010 LLVMValueRef dw_addr, stride;
1011 LLVMValueRef buffer, base, addr;
1012 LLVMValueRef values[8];
1013 bool skip_lds_store;
1014 bool is_tess_factor = false, is_tess_inner = false;
1015
1016 driver_location = driver_location / 4;
1017 ubyte name = info->output_semantic_name[driver_location];
1018 ubyte index = info->output_semantic_index[driver_location];
1019
1020 bool is_const = !param_index;
1021 if (!param_index)
1022 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1023
1024 const bool is_patch = var->data.patch ||
1025 var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
1026 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER;
1027
1028 assert((name == TGSI_SEMANTIC_PATCH ||
1029 name == TGSI_SEMANTIC_TESSINNER ||
1030 name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
1031
1032 if (!is_patch) {
1033 stride = get_tcs_out_vertex_dw_stride(ctx);
1034 dw_addr = get_tcs_out_current_patch_offset(ctx);
1035 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1036 vertex_index, param_index,
1037 name, index);
1038
1039 skip_lds_store = !info->reads_pervertex_outputs;
1040 } else {
1041 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1042 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1043 vertex_index, param_index,
1044 name, index);
1045
1046 skip_lds_store = !info->reads_perpatch_outputs;
1047
1048 if (is_const && const_index == 0) {
1049 int name = info->output_semantic_name[driver_location];
1050
1051 /* Always write tess factors into LDS for the TCS epilog. */
1052 if (name == TGSI_SEMANTIC_TESSINNER ||
1053 name == TGSI_SEMANTIC_TESSOUTER) {
1054 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1055 skip_lds_store = !info->reads_tessfactor_outputs &&
1056 ctx->shader->selector->info.tessfactors_are_def_in_all_invocs;
1057 is_tess_factor = true;
1058 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1059 }
1060 }
1061 }
1062
1063 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1064
1065 base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
1066
1067 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1068 param_index, name, index);
1069
1070 for (unsigned chan = component; chan < 8; chan++) {
1071 if (!(writemask & (1 << chan)))
1072 continue;
1073 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1074
1075 unsigned buffer_store_offset = chan % 4;
1076 if (chan == 4) {
1077 ubyte name = info->output_semantic_name[driver_location + 1];
1078 ubyte index = info->output_semantic_index[driver_location + 1];
1079 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1080 vertex_index,
1081 param_index,
1082 name, index);
1083 }
1084
1085 /* Skip LDS stores if there is no LDS read of this output. */
1086 if (!skip_lds_store)
1087 lshs_lds_store(ctx, chan, dw_addr, value);
1088
1089 value = ac_to_integer(&ctx->ac, value);
1090 values[chan] = value;
1091
1092 if (writemask != 0xF && !is_tess_factor) {
1093 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1094 addr, base,
1095 4 * buffer_store_offset,
1096 ac_glc);
1097 }
1098
1099 /* Write tess factors into VGPRs for the epilog. */
1100 if (is_tess_factor &&
1101 ctx->shader->selector->info.tessfactors_are_def_in_all_invocs) {
1102 if (!is_tess_inner) {
1103 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1104 ctx->invoc0_tess_factors[chan]);
1105 } else if (chan < 2) {
1106 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1107 ctx->invoc0_tess_factors[4 + chan]);
1108 }
1109 }
1110 }
1111
1112 if (writemask == 0xF && !is_tess_factor) {
1113 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1114 values, 4);
1115 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1116 base, 0, ac_glc);
1117 }
1118 }
1119
1120 static LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1121 unsigned input_index,
1122 unsigned vtx_offset_param,
1123 LLVMTypeRef type,
1124 unsigned swizzle)
1125 {
1126 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1127 struct si_shader *shader = ctx->shader;
1128 LLVMValueRef vtx_offset, soffset;
1129 struct si_shader_info *info = &shader->selector->info;
1130 unsigned semantic_name = info->input_semantic_name[input_index];
1131 unsigned semantic_index = info->input_semantic_index[input_index];
1132 unsigned param;
1133 LLVMValueRef value;
1134
1135 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1136
1137 /* GFX9 has the ESGS ring in LDS. */
1138 if (ctx->screen->info.chip_class >= GFX9) {
1139 unsigned index = vtx_offset_param;
1140
1141 switch (index / 2) {
1142 case 0:
1143 vtx_offset = si_unpack_param(ctx, ctx->gs_vtx01_offset,
1144 index % 2 ? 16 : 0, 16);
1145 break;
1146 case 1:
1147 vtx_offset = si_unpack_param(ctx, ctx->gs_vtx23_offset,
1148 index % 2 ? 16 : 0, 16);
1149 break;
1150 case 2:
1151 vtx_offset = si_unpack_param(ctx, ctx->gs_vtx45_offset,
1152 index % 2 ? 16 : 0, 16);
1153 break;
1154 default:
1155 assert(0);
1156 return NULL;
1157 }
1158
1159 unsigned offset = param * 4 + swizzle;
1160 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1161 LLVMConstInt(ctx->i32, offset, false), "");
1162
1163 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1164 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1165 if (llvm_type_is_64bit(ctx, type)) {
1166 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1167 &ctx->ac.i32_1, 1, "");
1168 LLVMValueRef values[2] = {
1169 value,
1170 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1171 };
1172 value = ac_build_gather_values(&ctx->ac, values, 2);
1173 }
1174 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1175 }
1176
1177 /* GFX6: input load from the ESGS ring in memory. */
1178 if (swizzle == ~0) {
1179 LLVMValueRef values[4];
1180 unsigned chan;
1181 for (chan = 0; chan < 4; chan++) {
1182 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1183 type, chan);
1184 }
1185 return ac_build_gather_values(&ctx->ac, values, 4);
1186 }
1187
1188 /* Get the vertex offset parameter on GFX6. */
1189 LLVMValueRef gs_vtx_offset = ac_get_arg(&ctx->ac,
1190 ctx->gs_vtx_offset[vtx_offset_param]);
1191
1192 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1193 LLVMConstInt(ctx->i32, 4, 0), "");
1194
1195 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1196
1197 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1198 vtx_offset, soffset, 0, ac_glc, true, false);
1199 if (llvm_type_is_64bit(ctx, type)) {
1200 LLVMValueRef value2;
1201 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1202
1203 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1204 ctx->i32_0, vtx_offset, soffset,
1205 0, ac_glc, true, false);
1206 return si_build_gather_64bit(ctx, type, value, value2);
1207 }
1208 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1209 }
1210
1211 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1212 unsigned location,
1213 unsigned driver_location,
1214 unsigned component,
1215 unsigned num_components,
1216 unsigned vertex_index,
1217 unsigned const_index,
1218 LLVMTypeRef type)
1219 {
1220 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1221
1222 LLVMValueRef value[4];
1223 for (unsigned i = 0; i < num_components; i++) {
1224 unsigned offset = i;
1225 if (llvm_type_is_64bit(ctx, type))
1226 offset *= 2;
1227
1228 offset += component;
1229 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4 + const_index,
1230 vertex_index, type, offset);
1231 }
1232
1233 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1234 }
1235
1236 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1237 unsigned attr_index, unsigned chan,
1238 LLVMValueRef prim_mask,
1239 LLVMValueRef i, LLVMValueRef j)
1240 {
1241 if (i || j) {
1242 return ac_build_fs_interp(&ctx->ac,
1243 LLVMConstInt(ctx->i32, chan, 0),
1244 LLVMConstInt(ctx->i32, attr_index, 0),
1245 prim_mask, i, j);
1246 }
1247 return ac_build_fs_interp_mov(&ctx->ac,
1248 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1249 LLVMConstInt(ctx->i32, chan, 0),
1250 LLVMConstInt(ctx->i32, attr_index, 0),
1251 prim_mask);
1252 }
1253
1254 /**
1255 * Interpolate a fragment shader input.
1256 *
1257 * @param ctx context
1258 * @param input_index index of the input in hardware
1259 * @param semantic_name TGSI_SEMANTIC_*
1260 * @param semantic_index semantic index
1261 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1262 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1263 * @param interp_param interpolation weights (i,j)
1264 * @param prim_mask SI_PARAM_PRIM_MASK
1265 * @param face SI_PARAM_FRONT_FACE
1266 * @param result the return value (4 components)
1267 */
1268 static void interp_fs_color(struct si_shader_context *ctx,
1269 unsigned input_index,
1270 unsigned semantic_index,
1271 unsigned num_interp_inputs,
1272 unsigned colors_read_mask,
1273 LLVMValueRef interp_param,
1274 LLVMValueRef prim_mask,
1275 LLVMValueRef face,
1276 LLVMValueRef result[4])
1277 {
1278 LLVMValueRef i = NULL, j = NULL;
1279 unsigned chan;
1280
1281 /* fs.constant returns the param from the middle vertex, so it's not
1282 * really useful for flat shading. It's meant to be used for custom
1283 * interpolation (but the intrinsic can't fetch from the other two
1284 * vertices).
1285 *
1286 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1287 * to do the right thing. The only reason we use fs.constant is that
1288 * fs.interp cannot be used on integers, because they can be equal
1289 * to NaN.
1290 *
1291 * When interp is false we will use fs.constant or for newer llvm,
1292 * amdgcn.interp.mov.
1293 */
1294 bool interp = interp_param != NULL;
1295
1296 if (interp) {
1297 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1298 LLVMVectorType(ctx->f32, 2), "");
1299
1300 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1301 ctx->i32_0, "");
1302 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1303 ctx->i32_1, "");
1304 }
1305
1306 if (ctx->shader->key.part.ps.prolog.color_two_side) {
1307 LLVMValueRef is_face_positive;
1308
1309 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1310 * otherwise it's at offset "num_inputs".
1311 */
1312 unsigned back_attr_offset = num_interp_inputs;
1313 if (semantic_index == 1 && colors_read_mask & 0xf)
1314 back_attr_offset += 1;
1315
1316 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1317 face, ctx->i32_0, "");
1318
1319 for (chan = 0; chan < 4; chan++) {
1320 LLVMValueRef front, back;
1321
1322 front = si_build_fs_interp(ctx,
1323 input_index, chan,
1324 prim_mask, i, j);
1325 back = si_build_fs_interp(ctx,
1326 back_attr_offset, chan,
1327 prim_mask, i, j);
1328
1329 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1330 is_face_positive,
1331 front,
1332 back,
1333 "");
1334 }
1335 } else {
1336 for (chan = 0; chan < 4; chan++) {
1337 result[chan] = si_build_fs_interp(ctx,
1338 input_index, chan,
1339 prim_mask, i, j);
1340 }
1341 }
1342 }
1343
1344 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1345 {
1346 return si_unpack_param(ctx, ctx->args.ancillary, 8, 4);
1347 }
1348
1349 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1350 {
1351 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1352
1353 /* For non-indexed draws, the base vertex set by the driver
1354 * (for direct draws) or the CP (for indirect draws) is the
1355 * first vertex ID, but GLSL expects 0 to be returned.
1356 */
1357 LLVMValueRef vs_state = ac_get_arg(&ctx->ac,
1358 ctx->vs_state_bits);
1359 LLVMValueRef indexed;
1360
1361 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1362 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1363
1364 return LLVMBuildSelect(ctx->ac.builder, indexed,
1365 ac_get_arg(&ctx->ac, ctx->args.base_vertex),
1366 ctx->i32_0, "");
1367 }
1368
1369 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1370 {
1371 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1372
1373 LLVMValueRef values[3];
1374 LLVMValueRef result;
1375 unsigned i;
1376 unsigned *properties = ctx->shader->selector->info.properties;
1377
1378 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1379 unsigned sizes[3] = {
1380 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1381 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1382 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1383 };
1384
1385 for (i = 0; i < 3; ++i)
1386 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1387
1388 result = ac_build_gather_values(&ctx->ac, values, 3);
1389 } else {
1390 result = ac_get_arg(&ctx->ac, ctx->block_size);
1391 }
1392
1393 return result;
1394 }
1395
1396 /**
1397 * Load a dword from a constant buffer.
1398 */
1399 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1400 LLVMValueRef resource,
1401 LLVMValueRef offset)
1402 {
1403 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1404 0, 0, true, true);
1405 }
1406
1407 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1408 {
1409 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1410 LLVMValueRef desc = ac_get_arg(&ctx->ac, ctx->rw_buffers);
1411 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1412 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1413
1414 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1415 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1416 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1417
1418 LLVMValueRef pos[4] = {
1419 buffer_load_const(ctx, resource, offset0),
1420 buffer_load_const(ctx, resource, offset1),
1421 LLVMConstReal(ctx->f32, 0),
1422 LLVMConstReal(ctx->f32, 0)
1423 };
1424
1425 return ac_build_gather_values(&ctx->ac, pos, 4);
1426 }
1427
1428 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1429 {
1430 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1431 return ac_to_integer(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args.sample_coverage));
1432 }
1433
1434 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1435 {
1436 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1437 LLVMValueRef coord[4] = {
1438 ac_get_arg(&ctx->ac, ctx->tes_u),
1439 ac_get_arg(&ctx->ac, ctx->tes_v),
1440 ctx->ac.f32_0,
1441 ctx->ac.f32_0
1442 };
1443
1444 /* For triangles, the vector should be (u, v, 1-u-v). */
1445 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1446 PIPE_PRIM_TRIANGLES) {
1447 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1448 LLVMBuildFAdd(ctx->ac.builder,
1449 coord[0], coord[1], ""), "");
1450 }
1451 return ac_build_gather_values(&ctx->ac, coord, 4);
1452 }
1453
1454 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1455 unsigned semantic_name)
1456 {
1457 LLVMValueRef base, addr;
1458
1459 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1460
1461 base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
1462 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1463 LLVMConstInt(ctx->i32, param, 0));
1464
1465 return buffer_load(ctx, ctx->f32,
1466 ~0, ctx->tess_offchip_ring, base, addr, true);
1467
1468 }
1469
1470 static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx,
1471 unsigned semantic_name)
1472 {
1473 LLVMValueRef buf, slot, val[4];
1474 int i, offset;
1475
1476 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1477 buf = ac_get_arg(&ctx->ac, ctx->rw_buffers);
1478 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1479 offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;
1480
1481 for (i = 0; i < 4; i++)
1482 val[i] = buffer_load_const(ctx, buf,
1483 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1484 return ac_build_gather_values(&ctx->ac, val, 4);
1485 }
1486
1487 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1488 unsigned varying_id,
1489 bool load_default_state)
1490 {
1491 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1492 unsigned semantic_name;
1493
1494 if (load_default_state) {
1495 switch (varying_id) {
1496 case VARYING_SLOT_TESS_LEVEL_INNER:
1497 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
1498 break;
1499 case VARYING_SLOT_TESS_LEVEL_OUTER:
1500 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
1501 break;
1502 default:
1503 unreachable("unknown tess level");
1504 }
1505 return load_tess_level_default(ctx, semantic_name);
1506 }
1507
1508 switch (varying_id) {
1509 case VARYING_SLOT_TESS_LEVEL_INNER:
1510 semantic_name = TGSI_SEMANTIC_TESSINNER;
1511 break;
1512 case VARYING_SLOT_TESS_LEVEL_OUTER:
1513 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1514 break;
1515 default:
1516 unreachable("unknown tess level");
1517 }
1518
1519 return load_tess_level(ctx, semantic_name);
1520
1521 }
1522
1523 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1524 {
1525 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1526 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1527 return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 13, 6);
1528 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1529 return get_num_tcs_out_vertices(ctx);
1530 else
1531 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1532 }
1533
1534 void si_declare_compute_memory(struct si_shader_context *ctx)
1535 {
1536 struct si_shader_selector *sel = ctx->shader->selector;
1537 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
1538
1539 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
1540 LLVMValueRef var;
1541
1542 assert(!ctx->ac.lds);
1543
1544 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1545 LLVMArrayType(ctx->i8, lds_size),
1546 "compute_lds",
1547 AC_ADDR_SPACE_LDS);
1548 LLVMSetAlignment(var, 64 * 1024);
1549
1550 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
1551 }
1552
1553 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
1554 {
1555 LLVMValueRef ptr =
1556 ac_get_arg(&ctx->ac, ctx->const_and_shader_buffers);
1557 struct si_shader_selector *sel = ctx->shader->selector;
1558
1559 /* Do the bounds checking with a descriptor, because
1560 * doing computation and manual bounds checking of 64-bit
1561 * addresses generates horrible VALU code with very high
1562 * VGPR usage and very low SIMD occupancy.
1563 */
1564 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
1565
1566 LLVMValueRef desc0, desc1;
1567 desc0 = ptr;
1568 desc1 = LLVMConstInt(ctx->i32,
1569 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1570
1571 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1572 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1573 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1574 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1575
1576 if (ctx->screen->info.chip_class >= GFX10)
1577 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1578 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
1579 S_008F0C_RESOURCE_LEVEL(1);
1580 else
1581 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1582 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1583
1584 LLVMValueRef desc_elems[] = {
1585 desc0,
1586 desc1,
1587 LLVMConstInt(ctx->i32, sel->info.constbuf0_num_slots * 16, 0),
1588 LLVMConstInt(ctx->i32, rsrc3, false)
1589 };
1590
1591 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
1592 }
1593
1594 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1595 {
1596 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1597 struct si_shader_selector *sel = ctx->shader->selector;
1598
1599 LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->const_and_shader_buffers);
1600
1601 if (sel->info.const_buffers_declared == 1 &&
1602 sel->info.shader_buffers_declared == 0) {
1603 return load_const_buffer_desc_fast_path(ctx);
1604 }
1605
1606 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1607 index = LLVMBuildAdd(ctx->ac.builder, index,
1608 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1609
1610 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
1611 }
1612
1613 static LLVMValueRef
1614 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
1615 {
1616 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1617 LLVMValueRef rsrc_ptr = ac_get_arg(&ctx->ac,
1618 ctx->const_and_shader_buffers);
1619
1620 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
1621 index = LLVMBuildSub(ctx->ac.builder,
1622 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
1623 index, "");
1624
1625 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
1626 }
1627
1628 /* Initialize arguments for the shader export intrinsic */
1629 static void si_llvm_init_export_args(struct si_shader_context *ctx,
1630 LLVMValueRef *values,
1631 unsigned target,
1632 struct ac_export_args *args)
1633 {
1634 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
1635 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1636 unsigned chan;
1637 bool is_int8, is_int10;
1638
1639 /* Default is 0xf. Adjusted below depending on the format. */
1640 args->enabled_channels = 0xf; /* writemask */
1641
1642 /* Specify whether the EXEC mask represents the valid mask */
1643 args->valid_mask = 0;
1644
1645 /* Specify whether this is the last export */
1646 args->done = 0;
1647
1648 /* Specify the target we are exporting */
1649 args->target = target;
1650
1651 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1652 const struct si_shader_key *key = &ctx->shader->key;
1653 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1654 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1655
1656 assert(cbuf >= 0 && cbuf < 8);
1657 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1658 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1659 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1660 }
1661
1662 args->compr = false;
1663 args->out[0] = f32undef;
1664 args->out[1] = f32undef;
1665 args->out[2] = f32undef;
1666 args->out[3] = f32undef;
1667
1668 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1669 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1670 unsigned bits, bool hi) = NULL;
1671
1672 switch (spi_shader_col_format) {
1673 case V_028714_SPI_SHADER_ZERO:
1674 args->enabled_channels = 0; /* writemask */
1675 args->target = V_008DFC_SQ_EXP_NULL;
1676 break;
1677
1678 case V_028714_SPI_SHADER_32_R:
1679 args->enabled_channels = 1; /* writemask */
1680 args->out[0] = values[0];
1681 break;
1682
1683 case V_028714_SPI_SHADER_32_GR:
1684 args->enabled_channels = 0x3; /* writemask */
1685 args->out[0] = values[0];
1686 args->out[1] = values[1];
1687 break;
1688
1689 case V_028714_SPI_SHADER_32_AR:
1690 if (ctx->screen->info.chip_class >= GFX10) {
1691 args->enabled_channels = 0x3; /* writemask */
1692 args->out[0] = values[0];
1693 args->out[1] = values[3];
1694 } else {
1695 args->enabled_channels = 0x9; /* writemask */
1696 args->out[0] = values[0];
1697 args->out[3] = values[3];
1698 }
1699 break;
1700
1701 case V_028714_SPI_SHADER_FP16_ABGR:
1702 packf = ac_build_cvt_pkrtz_f16;
1703 break;
1704
1705 case V_028714_SPI_SHADER_UNORM16_ABGR:
1706 packf = ac_build_cvt_pknorm_u16;
1707 break;
1708
1709 case V_028714_SPI_SHADER_SNORM16_ABGR:
1710 packf = ac_build_cvt_pknorm_i16;
1711 break;
1712
1713 case V_028714_SPI_SHADER_UINT16_ABGR:
1714 packi = ac_build_cvt_pk_u16;
1715 break;
1716
1717 case V_028714_SPI_SHADER_SINT16_ABGR:
1718 packi = ac_build_cvt_pk_i16;
1719 break;
1720
1721 case V_028714_SPI_SHADER_32_ABGR:
1722 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1723 break;
1724 }
1725
1726 /* Pack f16 or norm_i16/u16. */
1727 if (packf) {
1728 for (chan = 0; chan < 2; chan++) {
1729 LLVMValueRef pack_args[2] = {
1730 values[2 * chan],
1731 values[2 * chan + 1]
1732 };
1733 LLVMValueRef packed;
1734
1735 packed = packf(&ctx->ac, pack_args);
1736 args->out[chan] = ac_to_float(&ctx->ac, packed);
1737 }
1738 args->compr = 1; /* COMPR flag */
1739 }
1740 /* Pack i16/u16. */
1741 if (packi) {
1742 for (chan = 0; chan < 2; chan++) {
1743 LLVMValueRef pack_args[2] = {
1744 ac_to_integer(&ctx->ac, values[2 * chan]),
1745 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1746 };
1747 LLVMValueRef packed;
1748
1749 packed = packi(&ctx->ac, pack_args,
1750 is_int8 ? 8 : is_int10 ? 10 : 16,
1751 chan == 1);
1752 args->out[chan] = ac_to_float(&ctx->ac, packed);
1753 }
1754 args->compr = 1; /* COMPR flag */
1755 }
1756 }
1757
1758 static void si_alpha_test(struct si_shader_context *ctx, LLVMValueRef alpha)
1759 {
1760 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1761 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
1762 [PIPE_FUNC_LESS] = LLVMRealOLT,
1763 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
1764 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
1765 [PIPE_FUNC_GREATER] = LLVMRealOGT,
1766 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
1767 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
1768 };
1769 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
1770 assert(cond);
1771
1772 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1773 SI_PARAM_ALPHA_REF);
1774 LLVMValueRef alpha_pass =
1775 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
1776 ac_build_kill_if_false(&ctx->ac, alpha_pass);
1777 } else {
1778 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
1779 }
1780 }
1781
1782 static LLVMValueRef si_scale_alpha_by_sample_mask(struct si_shader_context *ctx,
1783 LLVMValueRef alpha,
1784 unsigned samplemask_param)
1785 {
1786 LLVMValueRef coverage;
1787
1788 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1789 coverage = LLVMGetParam(ctx->main_fn,
1790 samplemask_param);
1791 coverage = ac_to_integer(&ctx->ac, coverage);
1792
1793 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
1794 ctx->i32,
1795 &coverage, 1, AC_FUNC_ATTR_READNONE);
1796
1797 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
1798 ctx->f32, "");
1799
1800 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
1801 LLVMConstReal(ctx->f32,
1802 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1803
1804 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
1805 }
1806
1807 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
1808 struct ac_export_args *pos, LLVMValueRef *out_elts)
1809 {
1810 unsigned reg_index;
1811 unsigned chan;
1812 unsigned const_chan;
1813 LLVMValueRef base_elt;
1814 LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
1815 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
1816 SI_VS_CONST_CLIP_PLANES, 0);
1817 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
1818
1819 for (reg_index = 0; reg_index < 2; reg_index ++) {
1820 struct ac_export_args *args = &pos[2 + reg_index];
1821
1822 args->out[0] =
1823 args->out[1] =
1824 args->out[2] =
1825 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
1826
1827 /* Compute dot products of position and user clip plane vectors */
1828 for (chan = 0; chan < 4; chan++) {
1829 for (const_chan = 0; const_chan < 4; const_chan++) {
1830 LLVMValueRef addr =
1831 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
1832 const_chan) * 4, 0);
1833 base_elt = buffer_load_const(ctx, const_resource,
1834 addr);
1835 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
1836 out_elts[const_chan], args->out[chan]);
1837 }
1838 }
1839
1840 args->enabled_channels = 0xf;
1841 args->valid_mask = 0;
1842 args->done = 0;
1843 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
1844 args->compr = 0;
1845 }
1846 }
1847
1848 static void si_dump_streamout(struct pipe_stream_output_info *so)
1849 {
1850 unsigned i;
1851
1852 if (so->num_outputs)
1853 fprintf(stderr, "STREAMOUT\n");
1854
1855 for (i = 0; i < so->num_outputs; i++) {
1856 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1857 so->output[i].start_component;
1858 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1859 i, so->output[i].output_buffer,
1860 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1861 so->output[i].register_index,
1862 mask & 1 ? "x" : "",
1863 mask & 2 ? "y" : "",
1864 mask & 4 ? "z" : "",
1865 mask & 8 ? "w" : "");
1866 }
1867 }
1868
1869 void si_emit_streamout_output(struct si_shader_context *ctx,
1870 LLVMValueRef const *so_buffers,
1871 LLVMValueRef const *so_write_offsets,
1872 struct pipe_stream_output *stream_out,
1873 struct si_shader_output_values *shader_out)
1874 {
1875 unsigned buf_idx = stream_out->output_buffer;
1876 unsigned start = stream_out->start_component;
1877 unsigned num_comps = stream_out->num_components;
1878 LLVMValueRef out[4];
1879
1880 assert(num_comps && num_comps <= 4);
1881 if (!num_comps || num_comps > 4)
1882 return;
1883
1884 /* Load the output as int. */
1885 for (int j = 0; j < num_comps; j++) {
1886 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
1887
1888 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
1889 }
1890
1891 /* Pack the output. */
1892 LLVMValueRef vdata = NULL;
1893
1894 switch (num_comps) {
1895 case 1: /* as i32 */
1896 vdata = out[0];
1897 break;
1898 case 2: /* as v2i32 */
1899 case 3: /* as v3i32 */
1900 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
1901 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
1902 break;
1903 }
1904 /* as v4i32 (aligned to 4) */
1905 out[3] = LLVMGetUndef(ctx->i32);
1906 /* fall through */
1907 case 4: /* as v4i32 */
1908 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
1909 break;
1910 }
1911
1912 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
1913 vdata, num_comps,
1914 so_write_offsets[buf_idx],
1915 ctx->i32_0,
1916 stream_out->dst_offset * 4, ac_glc | ac_slc);
1917 }
1918
1919 /**
1920 * Write streamout data to buffers for vertex stream @p stream (different
1921 * vertex streams can occur for GS copy shaders).
1922 */
1923 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1924 struct si_shader_output_values *outputs,
1925 unsigned noutput, unsigned stream)
1926 {
1927 struct si_shader_selector *sel = ctx->shader->selector;
1928 struct pipe_stream_output_info *so = &sel->so;
1929 LLVMBuilderRef builder = ctx->ac.builder;
1930 int i;
1931
1932 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1933 LLVMValueRef so_vtx_count =
1934 si_unpack_param(ctx, ctx->streamout_config, 16, 7);
1935
1936 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1937
1938 /* can_emit = tid < so_vtx_count; */
1939 LLVMValueRef can_emit =
1940 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1941
1942 /* Emit the streamout code conditionally. This actually avoids
1943 * out-of-bounds buffer access. The hw tells us via the SGPR
1944 * (so_vtx_count) which threads are allowed to emit streamout data. */
1945 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1946 {
1947 /* The buffer offset is computed as follows:
1948 * ByteOffset = streamout_offset[buffer_id]*4 +
1949 * (streamout_write_index + thread_id)*stride[buffer_id] +
1950 * attrib_offset
1951 */
1952
1953 LLVMValueRef so_write_index =
1954 ac_get_arg(&ctx->ac,
1955 ctx->streamout_write_index);
1956
1957 /* Compute (streamout_write_index + thread_id). */
1958 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1959
1960 /* Load the descriptor and compute the write offset for each
1961 * enabled buffer. */
1962 LLVMValueRef so_write_offset[4] = {};
1963 LLVMValueRef so_buffers[4];
1964 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac,
1965 ctx->rw_buffers);
1966
1967 for (i = 0; i < 4; i++) {
1968 if (!so->stride[i])
1969 continue;
1970
1971 LLVMValueRef offset = LLVMConstInt(ctx->i32,
1972 SI_VS_STREAMOUT_BUF0 + i, 0);
1973
1974 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
1975
1976 LLVMValueRef so_offset = ac_get_arg(&ctx->ac,
1977 ctx->streamout_offset[i]);
1978 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1979
1980 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
1981 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
1982 so_offset);
1983 }
1984
1985 /* Write streamout data. */
1986 for (i = 0; i < so->num_outputs; i++) {
1987 unsigned reg = so->output[i].register_index;
1988
1989 if (reg >= noutput)
1990 continue;
1991
1992 if (stream != so->output[i].stream)
1993 continue;
1994
1995 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
1996 &so->output[i], &outputs[reg]);
1997 }
1998 }
1999 ac_build_endif(&ctx->ac, 6501);
2000 }
2001
2002 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2003 LLVMValueRef *values)
2004 {
2005 struct ac_export_args args;
2006
2007 si_llvm_init_export_args(ctx, values,
2008 V_008DFC_SQ_EXP_PARAM + index, &args);
2009 ac_build_export(&ctx->ac, &args);
2010 }
2011
2012 static void si_build_param_exports(struct si_shader_context *ctx,
2013 struct si_shader_output_values *outputs,
2014 unsigned noutput)
2015 {
2016 struct si_shader *shader = ctx->shader;
2017 unsigned param_count = 0;
2018
2019 for (unsigned i = 0; i < noutput; i++) {
2020 unsigned semantic_name = outputs[i].semantic_name;
2021 unsigned semantic_index = outputs[i].semantic_index;
2022
2023 if (outputs[i].vertex_stream[0] != 0 &&
2024 outputs[i].vertex_stream[1] != 0 &&
2025 outputs[i].vertex_stream[2] != 0 &&
2026 outputs[i].vertex_stream[3] != 0)
2027 continue;
2028
2029 switch (semantic_name) {
2030 case TGSI_SEMANTIC_LAYER:
2031 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2032 case TGSI_SEMANTIC_CLIPDIST:
2033 case TGSI_SEMANTIC_COLOR:
2034 case TGSI_SEMANTIC_BCOLOR:
2035 case TGSI_SEMANTIC_PRIMID:
2036 case TGSI_SEMANTIC_FOG:
2037 case TGSI_SEMANTIC_TEXCOORD:
2038 case TGSI_SEMANTIC_GENERIC:
2039 break;
2040 default:
2041 continue;
2042 }
2043
2044 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2045 semantic_index < SI_MAX_IO_GENERIC) &&
2046 shader->key.opt.kill_outputs &
2047 (1ull << si_shader_io_get_unique_index(semantic_name,
2048 semantic_index, true)))
2049 continue;
2050
2051 si_export_param(ctx, param_count, outputs[i].values);
2052
2053 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2054 shader->info.vs_output_param_offset[i] = param_count++;
2055 }
2056
2057 shader->info.nr_param_exports = param_count;
2058 }
2059
2060 /**
2061 * Vertex color clamping.
2062 *
2063 * This uses a state constant loaded in a user data SGPR and
2064 * an IF statement is added that clamps all colors if the constant
2065 * is true.
2066 */
2067 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2068 struct si_shader_output_values *outputs,
2069 unsigned noutput)
2070 {
2071 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2072 bool has_colors = false;
2073
2074 /* Store original colors to alloca variables. */
2075 for (unsigned i = 0; i < noutput; i++) {
2076 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2077 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2078 continue;
2079
2080 for (unsigned j = 0; j < 4; j++) {
2081 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2082 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2083 }
2084 has_colors = true;
2085 }
2086
2087 if (!has_colors)
2088 return;
2089
2090 /* The state is in the first bit of the user SGPR. */
2091 LLVMValueRef cond = ac_get_arg(&ctx->ac, ctx->vs_state_bits);
2092 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2093
2094 ac_build_ifcc(&ctx->ac, cond, 6502);
2095
2096 /* Store clamped colors to alloca variables within the conditional block. */
2097 for (unsigned i = 0; i < noutput; i++) {
2098 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2099 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2100 continue;
2101
2102 for (unsigned j = 0; j < 4; j++) {
2103 LLVMBuildStore(ctx->ac.builder,
2104 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2105 addr[i][j]);
2106 }
2107 }
2108 ac_build_endif(&ctx->ac, 6502);
2109
2110 /* Load clamped colors */
2111 for (unsigned i = 0; i < noutput; i++) {
2112 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2113 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2114 continue;
2115
2116 for (unsigned j = 0; j < 4; j++) {
2117 outputs[i].values[j] =
2118 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2119 }
2120 }
2121 }
2122
2123 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2124 * (position and parameter data only).
2125 */
2126 void si_llvm_export_vs(struct si_shader_context *ctx,
2127 struct si_shader_output_values *outputs,
2128 unsigned noutput)
2129 {
2130 struct si_shader *shader = ctx->shader;
2131 struct ac_export_args pos_args[4] = {};
2132 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2133 unsigned pos_idx;
2134 int i;
2135
2136 si_vertex_color_clamping(ctx, outputs, noutput);
2137
2138 /* Build position exports. */
2139 for (i = 0; i < noutput; i++) {
2140 switch (outputs[i].semantic_name) {
2141 case TGSI_SEMANTIC_POSITION:
2142 si_llvm_init_export_args(ctx, outputs[i].values,
2143 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2144 break;
2145 case TGSI_SEMANTIC_PSIZE:
2146 psize_value = outputs[i].values[0];
2147 break;
2148 case TGSI_SEMANTIC_LAYER:
2149 layer_value = outputs[i].values[0];
2150 break;
2151 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2152 viewport_index_value = outputs[i].values[0];
2153 break;
2154 case TGSI_SEMANTIC_EDGEFLAG:
2155 edgeflag_value = outputs[i].values[0];
2156 break;
2157 case TGSI_SEMANTIC_CLIPDIST:
2158 if (!shader->key.opt.clip_disable) {
2159 unsigned index = 2 + outputs[i].semantic_index;
2160 si_llvm_init_export_args(ctx, outputs[i].values,
2161 V_008DFC_SQ_EXP_POS + index,
2162 &pos_args[index]);
2163 }
2164 break;
2165 case TGSI_SEMANTIC_CLIPVERTEX:
2166 if (!shader->key.opt.clip_disable) {
2167 si_llvm_emit_clipvertex(ctx, pos_args,
2168 outputs[i].values);
2169 }
2170 break;
2171 }
2172 }
2173
2174 /* We need to add the position output manually if it's missing. */
2175 if (!pos_args[0].out[0]) {
2176 pos_args[0].enabled_channels = 0xf; /* writemask */
2177 pos_args[0].valid_mask = 0; /* EXEC mask */
2178 pos_args[0].done = 0; /* last export? */
2179 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2180 pos_args[0].compr = 0; /* COMPR flag */
2181 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2182 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2183 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2184 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2185 }
2186
2187 bool pos_writes_edgeflag = shader->selector->info.writes_edgeflag &&
2188 !shader->key.as_ngg;
2189
2190 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2191 if (shader->selector->info.writes_psize ||
2192 pos_writes_edgeflag ||
2193 shader->selector->info.writes_viewport_index ||
2194 shader->selector->info.writes_layer) {
2195 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2196 (pos_writes_edgeflag << 1) |
2197 (shader->selector->info.writes_layer << 2);
2198
2199 pos_args[1].valid_mask = 0; /* EXEC mask */
2200 pos_args[1].done = 0; /* last export? */
2201 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2202 pos_args[1].compr = 0; /* COMPR flag */
2203 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2204 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2205 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2206 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2207
2208 if (shader->selector->info.writes_psize)
2209 pos_args[1].out[0] = psize_value;
2210
2211 if (pos_writes_edgeflag) {
2212 /* The output is a float, but the hw expects an integer
2213 * with the first bit containing the edge flag. */
2214 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2215 edgeflag_value,
2216 ctx->i32, "");
2217 edgeflag_value = ac_build_umin(&ctx->ac,
2218 edgeflag_value,
2219 ctx->i32_1);
2220
2221 /* The LLVM intrinsic expects a float. */
2222 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2223 }
2224
2225 if (ctx->screen->info.chip_class >= GFX9) {
2226 /* GFX9 has the layer in out.z[10:0] and the viewport
2227 * index in out.z[19:16].
2228 */
2229 if (shader->selector->info.writes_layer)
2230 pos_args[1].out[2] = layer_value;
2231
2232 if (shader->selector->info.writes_viewport_index) {
2233 LLVMValueRef v = viewport_index_value;
2234
2235 v = ac_to_integer(&ctx->ac, v);
2236 v = LLVMBuildShl(ctx->ac.builder, v,
2237 LLVMConstInt(ctx->i32, 16, 0), "");
2238 v = LLVMBuildOr(ctx->ac.builder, v,
2239 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2240 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2241 pos_args[1].enabled_channels |= 1 << 2;
2242 }
2243 } else {
2244 if (shader->selector->info.writes_layer)
2245 pos_args[1].out[2] = layer_value;
2246
2247 if (shader->selector->info.writes_viewport_index) {
2248 pos_args[1].out[3] = viewport_index_value;
2249 pos_args[1].enabled_channels |= 1 << 3;
2250 }
2251 }
2252 }
2253
2254 for (i = 0; i < 4; i++)
2255 if (pos_args[i].out[0])
2256 shader->info.nr_pos_exports++;
2257
2258 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2259 * Setting valid_mask=1 prevents it and has no other effect.
2260 */
2261 if (ctx->screen->info.family == CHIP_NAVI10 ||
2262 ctx->screen->info.family == CHIP_NAVI12 ||
2263 ctx->screen->info.family == CHIP_NAVI14)
2264 pos_args[0].valid_mask = 1;
2265
2266 pos_idx = 0;
2267 for (i = 0; i < 4; i++) {
2268 if (!pos_args[i].out[0])
2269 continue;
2270
2271 /* Specify the target we are exporting */
2272 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2273
2274 if (pos_idx == shader->info.nr_pos_exports)
2275 /* Specify that this is the last export */
2276 pos_args[i].done = 1;
2277
2278 ac_build_export(&ctx->ac, &pos_args[i]);
2279 }
2280
2281 /* Build parameter exports. */
2282 si_build_param_exports(ctx, outputs, noutput);
2283 }
2284
2285 /**
2286 * Forward all outputs from the vertex shader to the TES. This is only used
2287 * for the fixed function TCS.
2288 */
2289 static void si_copy_tcs_inputs(struct si_shader_context *ctx)
2290 {
2291 LLVMValueRef invocation_id, buffer, buffer_offset;
2292 LLVMValueRef lds_vertex_stride, lds_base;
2293 uint64_t inputs;
2294
2295 invocation_id = si_unpack_param(ctx, ctx->args.tcs_rel_ids, 8, 5);
2296 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
2297 buffer_offset = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
2298
2299 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2300 lds_base = get_tcs_in_current_patch_offset(ctx);
2301 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
2302 lds_base);
2303
2304 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2305 while (inputs) {
2306 unsigned i = u_bit_scan64(&inputs);
2307
2308 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2309 LLVMConstInt(ctx->i32, 4 * i, 0),
2310 "");
2311
2312 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2313 get_rel_patch_id(ctx),
2314 invocation_id,
2315 LLVMConstInt(ctx->i32, i, 0));
2316
2317 LLVMValueRef value = lshs_lds_load(ctx, ctx->ac.i32, ~0, lds_ptr);
2318
2319 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2320 buffer_offset, 0, ac_glc);
2321 }
2322 }
2323
2324 static void si_write_tess_factors(struct si_shader_context *ctx,
2325 LLVMValueRef rel_patch_id,
2326 LLVMValueRef invocation_id,
2327 LLVMValueRef tcs_out_current_patch_data_offset,
2328 LLVMValueRef invoc0_tf_outer[4],
2329 LLVMValueRef invoc0_tf_inner[2])
2330 {
2331 struct si_shader *shader = ctx->shader;
2332 unsigned tess_inner_index, tess_outer_index;
2333 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2334 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2335 unsigned stride, outer_comps, inner_comps, i, offset;
2336
2337 /* Add a barrier before loading tess factors from LDS. */
2338 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2339 si_llvm_emit_barrier(ctx);
2340
2341 /* Do this only for invocation 0, because the tess levels are per-patch,
2342 * not per-vertex.
2343 *
2344 * This can't jump, because invocation 0 executes this. It should
2345 * at least mask out the loads and stores for other invocations.
2346 */
2347 ac_build_ifcc(&ctx->ac,
2348 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2349 invocation_id, ctx->i32_0, ""), 6503);
2350
2351 /* Determine the layout of one tess factor element in the buffer. */
2352 switch (shader->key.part.tcs.epilog.prim_mode) {
2353 case PIPE_PRIM_LINES:
2354 stride = 2; /* 2 dwords, 1 vec2 store */
2355 outer_comps = 2;
2356 inner_comps = 0;
2357 break;
2358 case PIPE_PRIM_TRIANGLES:
2359 stride = 4; /* 4 dwords, 1 vec4 store */
2360 outer_comps = 3;
2361 inner_comps = 1;
2362 break;
2363 case PIPE_PRIM_QUADS:
2364 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2365 outer_comps = 4;
2366 inner_comps = 2;
2367 break;
2368 default:
2369 assert(0);
2370 return;
2371 }
2372
2373 for (i = 0; i < 4; i++) {
2374 inner[i] = LLVMGetUndef(ctx->i32);
2375 outer[i] = LLVMGetUndef(ctx->i32);
2376 }
2377
2378 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2379 /* Tess factors are in VGPRs. */
2380 for (i = 0; i < outer_comps; i++)
2381 outer[i] = out[i] = invoc0_tf_outer[i];
2382 for (i = 0; i < inner_comps; i++)
2383 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2384 } else {
2385 /* Load tess_inner and tess_outer from LDS.
2386 * Any invocation can write them, so we can't get them from a temporary.
2387 */
2388 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2389 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2390
2391 lds_base = tcs_out_current_patch_data_offset;
2392 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2393 LLVMConstInt(ctx->i32,
2394 tess_inner_index * 4, 0), "");
2395 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2396 LLVMConstInt(ctx->i32,
2397 tess_outer_index * 4, 0), "");
2398
2399 for (i = 0; i < outer_comps; i++) {
2400 outer[i] = out[i] =
2401 lshs_lds_load(ctx, ctx->ac.i32, i, lds_outer);
2402 }
2403 for (i = 0; i < inner_comps; i++) {
2404 inner[i] = out[outer_comps+i] =
2405 lshs_lds_load(ctx, ctx->ac.i32, i, lds_inner);
2406 }
2407 }
2408
2409 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2410 /* For isolines, the hardware expects tess factors in the
2411 * reverse order from what NIR specifies.
2412 */
2413 LLVMValueRef tmp = out[0];
2414 out[0] = out[1];
2415 out[1] = tmp;
2416 }
2417
2418 /* Convert the outputs to vectors for stores. */
2419 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2420 vec1 = NULL;
2421
2422 if (stride > 4)
2423 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
2424
2425 /* Get the buffer. */
2426 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
2427
2428 /* Get the offset. */
2429 tf_base = ac_get_arg(&ctx->ac,
2430 ctx->tcs_factor_offset);
2431 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2432 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2433
2434 ac_build_ifcc(&ctx->ac,
2435 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2436 rel_patch_id, ctx->i32_0, ""), 6504);
2437
2438 /* Store the dynamic HS control word. */
2439 offset = 0;
2440 if (ctx->screen->info.chip_class <= GFX8) {
2441 ac_build_buffer_store_dword(&ctx->ac, buffer,
2442 LLVMConstInt(ctx->i32, 0x80000000, 0),
2443 1, ctx->i32_0, tf_base,
2444 offset, ac_glc);
2445 offset += 4;
2446 }
2447
2448 ac_build_endif(&ctx->ac, 6504);
2449
2450 /* Store the tessellation factors. */
2451 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2452 MIN2(stride, 4), byteoffset, tf_base,
2453 offset, ac_glc);
2454 offset += 16;
2455 if (vec1)
2456 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2457 stride - 4, byteoffset, tf_base,
2458 offset, ac_glc);
2459
2460 /* Store the tess factors into the offchip buffer if TES reads them. */
2461 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2462 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2463 LLVMValueRef tf_inner_offset;
2464 unsigned param_outer, param_inner;
2465
2466 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
2467 base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
2468
2469 param_outer = si_shader_io_get_unique_index_patch(
2470 TGSI_SEMANTIC_TESSOUTER, 0);
2471 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2472 LLVMConstInt(ctx->i32, param_outer, 0));
2473
2474 unsigned outer_vec_size =
2475 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
2476 outer_comps : util_next_power_of_two(outer_comps);
2477 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
2478
2479 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2480 outer_comps, tf_outer_offset,
2481 base, 0, ac_glc);
2482 if (inner_comps) {
2483 param_inner = si_shader_io_get_unique_index_patch(
2484 TGSI_SEMANTIC_TESSINNER, 0);
2485 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2486 LLVMConstInt(ctx->i32, param_inner, 0));
2487
2488 inner_vec = inner_comps == 1 ? inner[0] :
2489 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2490 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2491 inner_comps, tf_inner_offset,
2492 base, 0, ac_glc);
2493 }
2494 }
2495
2496 ac_build_endif(&ctx->ac, 6503);
2497 }
2498
2499 static LLVMValueRef
2500 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2501 struct ac_arg param, unsigned return_index)
2502 {
2503 return LLVMBuildInsertValue(ctx->ac.builder, ret,
2504 ac_get_arg(&ctx->ac, param),
2505 return_index, "");
2506 }
2507
2508 static LLVMValueRef
2509 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2510 struct ac_arg param, unsigned return_index)
2511 {
2512 LLVMBuilderRef builder = ctx->ac.builder;
2513 LLVMValueRef p = ac_get_arg(&ctx->ac, param);
2514
2515 return LLVMBuildInsertValue(builder, ret,
2516 ac_to_float(&ctx->ac, p),
2517 return_index, "");
2518 }
2519
2520 static LLVMValueRef
2521 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
2522 struct ac_arg param, unsigned return_index)
2523 {
2524 LLVMBuilderRef builder = ctx->ac.builder;
2525 LLVMValueRef ptr = ac_get_arg(&ctx->ac, param);
2526 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
2527 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
2528 }
2529
2530 /* This only writes the tessellation factor levels. */
2531 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
2532 unsigned max_outputs,
2533 LLVMValueRef *addrs)
2534 {
2535 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2536 LLVMBuilderRef builder = ctx->ac.builder;
2537 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2538
2539 si_copy_tcs_inputs(ctx);
2540
2541 rel_patch_id = get_rel_patch_id(ctx);
2542 invocation_id = si_unpack_param(ctx, ctx->args.tcs_rel_ids, 8, 5);
2543 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2544
2545 if (ctx->screen->info.chip_class >= GFX9) {
2546 LLVMBasicBlockRef blocks[2] = {
2547 LLVMGetInsertBlock(builder),
2548 ctx->merged_wrap_if_entry_block
2549 };
2550 LLVMValueRef values[2];
2551
2552 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
2553
2554 values[0] = rel_patch_id;
2555 values[1] = LLVMGetUndef(ctx->i32);
2556 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2557
2558 values[0] = tf_lds_offset;
2559 values[1] = LLVMGetUndef(ctx->i32);
2560 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2561
2562 values[0] = invocation_id;
2563 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
2564 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2565 }
2566
2567 /* Return epilog parameters from this function. */
2568 LLVMValueRef ret = ctx->return_value;
2569 unsigned vgpr;
2570
2571 if (ctx->screen->info.chip_class >= GFX9) {
2572 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout,
2573 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2574 ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout,
2575 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
2576 /* Tess offchip and tess factor offsets are at the beginning. */
2577 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_offset, 2);
2578 ret = si_insert_input_ret(ctx, ret, ctx->tcs_factor_offset, 4);
2579 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
2580 } else {
2581 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout,
2582 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
2583 ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout,
2584 GFX6_SGPR_TCS_OUT_LAYOUT);
2585 /* Tess offchip and tess factor offsets are after user SGPRs. */
2586 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_offset,
2587 GFX6_TCS_NUM_USER_SGPR);
2588 ret = si_insert_input_ret(ctx, ret, ctx->tcs_factor_offset,
2589 GFX6_TCS_NUM_USER_SGPR + 1);
2590 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
2591 }
2592
2593 /* VGPRs */
2594 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
2595 invocation_id = ac_to_float(&ctx->ac, invocation_id);
2596 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
2597
2598 /* Leave a hole corresponding to the two input VGPRs. This ensures that
2599 * the invocation_id output does not alias the tcs_rel_ids input,
2600 * which saves a V_MOV on gfx9.
2601 */
2602 vgpr += 2;
2603
2604 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2605 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2606
2607 if (ctx->shader->selector->info.tessfactors_are_def_in_all_invocs) {
2608 vgpr++; /* skip the tess factor LDS offset */
2609 for (unsigned i = 0; i < 6; i++) {
2610 LLVMValueRef value =
2611 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
2612 value = ac_to_float(&ctx->ac, value);
2613 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
2614 }
2615 } else {
2616 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2617 }
2618 ctx->return_value = ret;
2619 }
2620
2621 /* Pass TCS inputs from LS to TCS on GFX9. */
2622 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
2623 {
2624 LLVMValueRef ret = ctx->return_value;
2625
2626 ret = si_insert_input_ptr(ctx, ret, ctx->other_const_and_shader_buffers, 0);
2627 ret = si_insert_input_ptr(ctx, ret, ctx->other_samplers_and_images, 1);
2628 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_offset, 2);
2629 ret = si_insert_input_ret(ctx, ret, ctx->merged_wave_info, 3);
2630 ret = si_insert_input_ret(ctx, ret, ctx->tcs_factor_offset, 4);
2631 ret = si_insert_input_ret(ctx, ret, ctx->merged_scratch_offset, 5);
2632
2633 ret = si_insert_input_ptr(ctx, ret, ctx->rw_buffers,
2634 8 + SI_SGPR_RW_BUFFERS);
2635 ret = si_insert_input_ptr(ctx, ret,
2636 ctx->bindless_samplers_and_images,
2637 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
2638
2639 ret = si_insert_input_ret(ctx, ret, ctx->vs_state_bits,
2640 8 + SI_SGPR_VS_STATE_BITS);
2641
2642 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout,
2643 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2644 ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_offsets,
2645 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
2646 ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout,
2647 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
2648
2649 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
2650 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
2651 ac_to_float(&ctx->ac,
2652 ac_get_arg(&ctx->ac, ctx->args.tcs_patch_id)),
2653 vgpr++, "");
2654 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
2655 ac_to_float(&ctx->ac,
2656 ac_get_arg(&ctx->ac, ctx->args.tcs_rel_ids)),
2657 vgpr++, "");
2658 ctx->return_value = ret;
2659 }
2660
2661 /* Pass GS inputs from ES to GS on GFX9. */
2662 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
2663 {
2664 LLVMValueRef ret = ctx->return_value;
2665
2666 ret = si_insert_input_ptr(ctx, ret, ctx->other_const_and_shader_buffers, 0);
2667 ret = si_insert_input_ptr(ctx, ret, ctx->other_samplers_and_images, 1);
2668 if (ctx->shader->key.as_ngg)
2669 ret = si_insert_input_ptr(ctx, ret, ctx->gs_tg_info, 2);
2670 else
2671 ret = si_insert_input_ret(ctx, ret, ctx->gs2vs_offset, 2);
2672 ret = si_insert_input_ret(ctx, ret, ctx->merged_wave_info, 3);
2673 ret = si_insert_input_ret(ctx, ret, ctx->merged_scratch_offset, 5);
2674
2675 ret = si_insert_input_ptr(ctx, ret, ctx->rw_buffers,
2676 8 + SI_SGPR_RW_BUFFERS);
2677 ret = si_insert_input_ptr(ctx, ret,
2678 ctx->bindless_samplers_and_images,
2679 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
2680 if (ctx->screen->use_ngg) {
2681 ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits,
2682 8 + SI_SGPR_VS_STATE_BITS);
2683 }
2684
2685 unsigned vgpr;
2686 if (ctx->type == PIPE_SHADER_VERTEX)
2687 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
2688 else
2689 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
2690
2691 ret = si_insert_input_ret_float(ctx, ret, ctx->gs_vtx01_offset, vgpr++);
2692 ret = si_insert_input_ret_float(ctx, ret, ctx->gs_vtx23_offset, vgpr++);
2693 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_prim_id, vgpr++);
2694 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_invocation_id, vgpr++);
2695 ret = si_insert_input_ret_float(ctx, ret, ctx->gs_vtx45_offset, vgpr++);
2696 ctx->return_value = ret;
2697 }
2698
2699 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
2700 unsigned max_outputs,
2701 LLVMValueRef *addrs)
2702 {
2703 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2704 struct si_shader *shader = ctx->shader;
2705 struct si_shader_info *info = &shader->selector->info;
2706 unsigned i, chan;
2707 LLVMValueRef vertex_id = ac_get_arg(&ctx->ac, ctx->rel_auto_id);
2708 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
2709 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2710 vertex_dw_stride, "");
2711
2712 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2713 * its inputs from it. */
2714 for (i = 0; i < info->num_outputs; i++) {
2715 unsigned name = info->output_semantic_name[i];
2716 unsigned index = info->output_semantic_index[i];
2717
2718 /* The ARB_shader_viewport_layer_array spec contains the
2719 * following issue:
2720 *
2721 * 2) What happens if gl_ViewportIndex or gl_Layer is
2722 * written in the vertex shader and a geometry shader is
2723 * present?
2724 *
2725 * RESOLVED: The value written by the last vertex processing
2726 * stage is used. If the last vertex processing stage
2727 * (vertex, tessellation evaluation or geometry) does not
2728 * statically assign to gl_ViewportIndex or gl_Layer, index
2729 * or layer zero is assumed.
2730 *
2731 * So writes to those outputs in VS-as-LS are simply ignored.
2732 */
2733 if (name == TGSI_SEMANTIC_LAYER ||
2734 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
2735 continue;
2736
2737 int param = si_shader_io_get_unique_index(name, index, false);
2738 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2739 LLVMConstInt(ctx->i32, param * 4, 0), "");
2740
2741 for (chan = 0; chan < 4; chan++) {
2742 if (!(info->output_usagemask[i] & (1 << chan)))
2743 continue;
2744
2745 lshs_lds_store(ctx, chan, dw_addr,
2746 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
2747 }
2748 }
2749
2750 if (ctx->screen->info.chip_class >= GFX9)
2751 si_set_ls_return_value_for_tcs(ctx);
2752 }
2753
2754 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
2755 unsigned max_outputs,
2756 LLVMValueRef *addrs)
2757 {
2758 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2759 struct si_shader *es = ctx->shader;
2760 struct si_shader_info *info = &es->selector->info;
2761 LLVMValueRef lds_base = NULL;
2762 unsigned chan;
2763 int i;
2764
2765 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
2766 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
2767 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2768 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->merged_wave_info, 24, 4);
2769 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2770 LLVMBuildMul(ctx->ac.builder, wave_idx,
2771 LLVMConstInt(ctx->i32, ctx->ac.wave_size, false), ""), "");
2772 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2773 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
2774 }
2775
2776 for (i = 0; i < info->num_outputs; i++) {
2777 int param;
2778
2779 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2780 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2781 continue;
2782
2783 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
2784 info->output_semantic_index[i], false);
2785
2786 for (chan = 0; chan < 4; chan++) {
2787 if (!(info->output_usagemask[i] & (1 << chan)))
2788 continue;
2789
2790 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
2791 out_val = ac_to_integer(&ctx->ac, out_val);
2792
2793 /* GFX9 has the ESGS ring in LDS. */
2794 if (ctx->screen->info.chip_class >= GFX9) {
2795 LLVMValueRef idx = LLVMConstInt(ctx->i32, param * 4 + chan, false);
2796 idx = LLVMBuildAdd(ctx->ac.builder, lds_base, idx, "");
2797 ac_build_indexed_store(&ctx->ac, ctx->esgs_ring, idx, out_val);
2798 continue;
2799 }
2800
2801 ac_build_buffer_store_dword(&ctx->ac,
2802 ctx->esgs_ring,
2803 out_val, 1, NULL,
2804 ac_get_arg(&ctx->ac, ctx->es2gs_offset),
2805 (4 * param + chan) * 4,
2806 ac_glc | ac_slc | ac_swizzled);
2807 }
2808 }
2809
2810 if (ctx->screen->info.chip_class >= GFX9)
2811 si_set_es_return_value_for_gs(ctx);
2812 }
2813
2814 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
2815 {
2816 if (ctx->screen->info.chip_class >= GFX9)
2817 return si_unpack_param(ctx, ctx->merged_wave_info, 16, 8);
2818 else
2819 return ac_get_arg(&ctx->ac, ctx->gs_wave_id);
2820 }
2821
2822 static void emit_gs_epilogue(struct si_shader_context *ctx)
2823 {
2824 if (ctx->shader->key.as_ngg) {
2825 gfx10_ngg_gs_emit_epilogue(ctx);
2826 return;
2827 }
2828
2829 if (ctx->screen->info.chip_class >= GFX10)
2830 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
2831
2832 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2833 si_get_gs_wave_id(ctx));
2834
2835 if (ctx->screen->info.chip_class >= GFX9)
2836 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
2837 }
2838
2839 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
2840 unsigned max_outputs,
2841 LLVMValueRef *addrs)
2842 {
2843 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2844 struct si_shader_info UNUSED *info = &ctx->shader->selector->info;
2845
2846 assert(info->num_outputs <= max_outputs);
2847
2848 emit_gs_epilogue(ctx);
2849 }
2850
2851 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
2852 unsigned max_outputs,
2853 LLVMValueRef *addrs)
2854 {
2855 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2856 struct si_shader_info *info = &ctx->shader->selector->info;
2857 struct si_shader_output_values *outputs = NULL;
2858 int i,j;
2859
2860 assert(!ctx->shader->is_gs_copy_shader);
2861 assert(info->num_outputs <= max_outputs);
2862
2863 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2864
2865 for (i = 0; i < info->num_outputs; i++) {
2866 outputs[i].semantic_name = info->output_semantic_name[i];
2867 outputs[i].semantic_index = info->output_semantic_index[i];
2868
2869 for (j = 0; j < 4; j++) {
2870 outputs[i].values[j] =
2871 LLVMBuildLoad(ctx->ac.builder,
2872