ea749becdde2aaddb6739f1cabcffcf3daaf9ec8
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_from_mesa.h"
32
33 #include "ac_binary.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
36 #include "ac_rtld.h"
37 #include "ac_llvm_util.h"
38 #include "si_shader_internal.h"
39 #include "si_pipe.h"
40 #include "sid.h"
41
42 #include "compiler/nir/nir.h"
43
44 static const char scratch_rsrc_dword0_symbol[] =
45 "SCRATCH_RSRC_DWORD0";
46
47 static const char scratch_rsrc_dword1_symbol[] =
48 "SCRATCH_RSRC_DWORD1";
49
50 static void si_init_shader_ctx(struct si_shader_context *ctx,
51 struct si_screen *sscreen,
52 struct ac_llvm_compiler *compiler,
53 unsigned wave_size);
54
55 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
56 struct lp_build_tgsi_context *bld_base,
57 struct lp_build_emit_data *emit_data);
58
59 static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
60
61 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
62 union si_shader_part_key *key);
63 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
64 union si_shader_part_key *key);
65 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
66 union si_shader_part_key *key);
67 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
68 union si_shader_part_key *key);
69 static void si_fix_resource_usage(struct si_screen *sscreen,
70 struct si_shader *shader);
71
72 /* Ideally pass the sample mask input to the PS epilog as v14, which
73 * is its usual location, so that the shader doesn't have to add v_mov.
74 */
75 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
76
77 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
78 LLVMTypeRef type)
79 {
80 if (type == ctx->ac.i64 || type == ctx->ac.f64)
81 return true;
82
83 return false;
84 }
85
86 /** Whether the shader runs as a combination of multiple API shaders */
87 static bool is_multi_part_shader(struct si_shader_context *ctx)
88 {
89 if (ctx->screen->info.chip_class <= GFX8)
90 return false;
91
92 return ctx->shader->key.as_ls ||
93 ctx->shader->key.as_es ||
94 ctx->type == PIPE_SHADER_TESS_CTRL ||
95 ctx->type == PIPE_SHADER_GEOMETRY;
96 }
97
98 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
99 static bool is_merged_shader(struct si_shader_context *ctx)
100 {
101 return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
102 }
103
104 void si_init_function_info(struct si_function_info *fninfo)
105 {
106 fninfo->num_params = 0;
107 fninfo->num_sgpr_params = 0;
108 }
109
110 unsigned add_arg_assign(struct si_function_info *fninfo,
111 enum si_arg_regfile regfile, LLVMTypeRef type,
112 LLVMValueRef *assign)
113 {
114 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
115
116 unsigned idx = fninfo->num_params++;
117 assert(idx < ARRAY_SIZE(fninfo->types));
118
119 if (regfile == ARG_SGPR)
120 fninfo->num_sgpr_params = fninfo->num_params;
121
122 fninfo->types[idx] = type;
123 fninfo->assign[idx] = assign;
124 return idx;
125 }
126
127 static unsigned add_arg(struct si_function_info *fninfo,
128 enum si_arg_regfile regfile, LLVMTypeRef type)
129 {
130 return add_arg_assign(fninfo, regfile, type, NULL);
131 }
132
133 static void add_arg_assign_checked(struct si_function_info *fninfo,
134 enum si_arg_regfile regfile, LLVMTypeRef type,
135 LLVMValueRef *assign, unsigned idx)
136 {
137 ASSERTED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
138 assert(actual == idx);
139 }
140
141 static void add_arg_checked(struct si_function_info *fninfo,
142 enum si_arg_regfile regfile, LLVMTypeRef type,
143 unsigned idx)
144 {
145 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
146 }
147
148 /**
149 * Returns a unique index for a per-patch semantic name and index. The index
150 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
151 * can be calculated.
152 */
153 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
154 {
155 switch (semantic_name) {
156 case TGSI_SEMANTIC_TESSOUTER:
157 return 0;
158 case TGSI_SEMANTIC_TESSINNER:
159 return 1;
160 case TGSI_SEMANTIC_PATCH:
161 assert(index < 30);
162 return 2 + index;
163
164 default:
165 assert(!"invalid semantic name");
166 return 0;
167 }
168 }
169
170 /**
171 * Returns a unique index for a semantic name and index. The index must be
172 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
173 * calculated.
174 */
175 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
176 unsigned is_varying)
177 {
178 switch (semantic_name) {
179 case TGSI_SEMANTIC_POSITION:
180 return 0;
181 case TGSI_SEMANTIC_GENERIC:
182 /* Since some shader stages use the the highest used IO index
183 * to determine the size to allocate for inputs/outputs
184 * (in LDS, tess and GS rings). GENERIC should be placed right
185 * after POSITION to make that size as small as possible.
186 */
187 if (index < SI_MAX_IO_GENERIC)
188 return 1 + index;
189
190 assert(!"invalid generic index");
191 return 0;
192 case TGSI_SEMANTIC_FOG:
193 return SI_MAX_IO_GENERIC + 1;
194 case TGSI_SEMANTIC_COLOR:
195 assert(index < 2);
196 return SI_MAX_IO_GENERIC + 2 + index;
197 case TGSI_SEMANTIC_BCOLOR:
198 assert(index < 2);
199 /* If it's a varying, COLOR and BCOLOR alias. */
200 if (is_varying)
201 return SI_MAX_IO_GENERIC + 2 + index;
202 else
203 return SI_MAX_IO_GENERIC + 4 + index;
204 case TGSI_SEMANTIC_TEXCOORD:
205 assert(index < 8);
206 return SI_MAX_IO_GENERIC + 6 + index;
207
208 /* These are rarely used between LS and HS or ES and GS. */
209 case TGSI_SEMANTIC_CLIPDIST:
210 assert(index < 2);
211 return SI_MAX_IO_GENERIC + 6 + 8 + index;
212 case TGSI_SEMANTIC_CLIPVERTEX:
213 return SI_MAX_IO_GENERIC + 6 + 8 + 2;
214 case TGSI_SEMANTIC_PSIZE:
215 return SI_MAX_IO_GENERIC + 6 + 8 + 3;
216
217 /* These can't be written by LS, HS, and ES. */
218 case TGSI_SEMANTIC_LAYER:
219 return SI_MAX_IO_GENERIC + 6 + 8 + 4;
220 case TGSI_SEMANTIC_VIEWPORT_INDEX:
221 return SI_MAX_IO_GENERIC + 6 + 8 + 5;
222 case TGSI_SEMANTIC_PRIMID:
223 STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
224 return SI_MAX_IO_GENERIC + 6 + 8 + 6;
225 default:
226 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
227 assert(!"invalid semantic name");
228 return 0;
229 }
230 }
231
232 /**
233 * Get the value of a shader input parameter and extract a bitfield.
234 */
235 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
236 LLVMValueRef value, unsigned rshift,
237 unsigned bitwidth)
238 {
239 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
240 value = ac_to_integer(&ctx->ac, value);
241
242 if (rshift)
243 value = LLVMBuildLShr(ctx->ac.builder, value,
244 LLVMConstInt(ctx->i32, rshift, 0), "");
245
246 if (rshift + bitwidth < 32) {
247 unsigned mask = (1 << bitwidth) - 1;
248 value = LLVMBuildAnd(ctx->ac.builder, value,
249 LLVMConstInt(ctx->i32, mask, 0), "");
250 }
251
252 return value;
253 }
254
255 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
256 unsigned param, unsigned rshift,
257 unsigned bitwidth)
258 {
259 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
260
261 return unpack_llvm_param(ctx, value, rshift, bitwidth);
262 }
263
264 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
265 {
266 switch (ctx->type) {
267 case PIPE_SHADER_TESS_CTRL:
268 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
269
270 case PIPE_SHADER_TESS_EVAL:
271 return LLVMGetParam(ctx->main_fn,
272 ctx->param_tes_rel_patch_id);
273
274 default:
275 assert(0);
276 return NULL;
277 }
278 }
279
280 /* Tessellation shaders pass outputs to the next shader using LDS.
281 *
282 * LS outputs = TCS inputs
283 * TCS outputs = TES inputs
284 *
285 * The LDS layout is:
286 * - TCS inputs for patch 0
287 * - TCS inputs for patch 1
288 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
289 * - ...
290 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
291 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
292 * - TCS outputs for patch 1
293 * - Per-patch TCS outputs for patch 1
294 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
295 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
296 * - ...
297 *
298 * All three shaders VS(LS), TCS, TES share the same LDS space.
299 */
300
301 static LLVMValueRef
302 get_tcs_in_patch_stride(struct si_shader_context *ctx)
303 {
304 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
305 }
306
307 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
308 {
309 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
310
311 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
312 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
313
314 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
315 }
316
317 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
318 {
319 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
320
321 return LLVMConstInt(ctx->i32, stride, 0);
322 }
323
324 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
325 {
326 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
327 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
328
329 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
330 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
331 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
332 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
333 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
334 num_patch_outputs * 4;
335 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
336 }
337
338 static LLVMValueRef
339 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
340 {
341 return LLVMBuildMul(ctx->ac.builder,
342 si_unpack_param(ctx,
343 ctx->param_tcs_out_lds_offsets,
344 0, 16),
345 LLVMConstInt(ctx->i32, 4, 0), "");
346 }
347
348 static LLVMValueRef
349 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
350 {
351 return LLVMBuildMul(ctx->ac.builder,
352 si_unpack_param(ctx,
353 ctx->param_tcs_out_lds_offsets,
354 16, 16),
355 LLVMConstInt(ctx->i32, 4, 0), "");
356 }
357
358 static LLVMValueRef
359 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
360 {
361 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
362 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
363
364 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
365 }
366
367 static LLVMValueRef
368 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
369 {
370 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
371 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
372 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
373
374 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
375 }
376
377 static LLVMValueRef
378 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
379 {
380 LLVMValueRef patch0_patch_data_offset =
381 get_tcs_out_patch0_patch_data_offset(ctx);
382 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
383 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
384
385 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
386 }
387
388 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
389 {
390 unsigned tcs_out_vertices =
391 ctx->shader->selector ?
392 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
393
394 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
395 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
396 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
397
398 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
399 }
400
401 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
402 {
403 unsigned stride;
404
405 switch (ctx->type) {
406 case PIPE_SHADER_VERTEX:
407 stride = ctx->shader->selector->lshs_vertex_stride / 4;
408 return LLVMConstInt(ctx->i32, stride, 0);
409
410 case PIPE_SHADER_TESS_CTRL:
411 if (ctx->screen->info.chip_class >= GFX9 &&
412 ctx->shader->is_monolithic) {
413 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
414 return LLVMConstInt(ctx->i32, stride, 0);
415 }
416 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
417
418 default:
419 assert(0);
420 return NULL;
421 }
422 }
423
424 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
425 LLVMValueRef i32, unsigned index)
426 {
427 assert(index <= 1);
428
429 if (index == 1)
430 return LLVMBuildAShr(ctx->ac.builder, i32,
431 LLVMConstInt(ctx->i32, 16, 0), "");
432
433 return LLVMBuildSExt(ctx->ac.builder,
434 LLVMBuildTrunc(ctx->ac.builder, i32,
435 ctx->ac.i16, ""),
436 ctx->i32, "");
437 }
438
439 void si_llvm_load_input_vs(
440 struct si_shader_context *ctx,
441 unsigned input_index,
442 LLVMValueRef out[4])
443 {
444 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
445 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
446
447 if (vs_blit_property) {
448 LLVMValueRef vertex_id = ctx->abi.vertex_id;
449 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
450 LLVMIntULE, vertex_id,
451 ctx->i32_1, "");
452 /* Use LLVMIntNE, because we have 3 vertices and only
453 * the middle one should use y2.
454 */
455 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
456 LLVMIntNE, vertex_id,
457 ctx->i32_1, "");
458
459 if (input_index == 0) {
460 /* Position: */
461 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
462 ctx->param_vs_blit_inputs);
463 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
464 ctx->param_vs_blit_inputs + 1);
465
466 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
467 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
468 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
469 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
470
471 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
472 x1, x2, "");
473 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
474 y1, y2, "");
475
476 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
477 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
478 out[2] = LLVMGetParam(ctx->main_fn,
479 ctx->param_vs_blit_inputs + 2);
480 out[3] = ctx->ac.f32_1;
481 return;
482 }
483
484 /* Color or texture coordinates: */
485 assert(input_index == 1);
486
487 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
488 for (int i = 0; i < 4; i++) {
489 out[i] = LLVMGetParam(ctx->main_fn,
490 ctx->param_vs_blit_inputs + 3 + i);
491 }
492 } else {
493 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
494 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
495 ctx->param_vs_blit_inputs + 3);
496 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
497 ctx->param_vs_blit_inputs + 4);
498 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
499 ctx->param_vs_blit_inputs + 5);
500 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs + 6);
502
503 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
504 x1, x2, "");
505 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
506 y1, y2, "");
507 out[2] = LLVMGetParam(ctx->main_fn,
508 ctx->param_vs_blit_inputs + 7);
509 out[3] = LLVMGetParam(ctx->main_fn,
510 ctx->param_vs_blit_inputs + 8);
511 }
512 return;
513 }
514
515 union si_vs_fix_fetch fix_fetch;
516 LLVMValueRef t_list_ptr;
517 LLVMValueRef t_offset;
518 LLVMValueRef t_list;
519 LLVMValueRef vertex_index;
520 LLVMValueRef tmp;
521
522 /* Load the T list */
523 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
524
525 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
526
527 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
528
529 vertex_index = LLVMGetParam(ctx->main_fn,
530 ctx->param_vertex_index0 +
531 input_index);
532
533 /* Use the open-coded implementation for all loads of doubles and
534 * of dword-sized data that needs fixups. We need to insert conversion
535 * code anyway, and the amd/common code does it for us.
536 *
537 * Note: On LLVM <= 8, we can only open-code formats with
538 * channel size >= 4 bytes.
539 */
540 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
541 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
542 if (opencode ||
543 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
544 (fix_fetch.u.log_size == 2)) {
545 tmp = ac_build_opencoded_load_format(
546 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
547 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
548 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
549 for (unsigned i = 0; i < 4; ++i)
550 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
551 return;
552 }
553
554 /* Do multiple loads for special formats. */
555 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
556 LLVMValueRef fetches[4];
557 unsigned num_fetches;
558 unsigned fetch_stride;
559 unsigned channels_per_fetch;
560
561 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
562 num_fetches = MIN2(required_channels, 3);
563 fetch_stride = 1 << fix_fetch.u.log_size;
564 channels_per_fetch = 1;
565 } else {
566 num_fetches = 1;
567 fetch_stride = 0;
568 channels_per_fetch = required_channels;
569 }
570
571 for (unsigned i = 0; i < num_fetches; ++i) {
572 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
573 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
574 channels_per_fetch, 0, true);
575 }
576
577 if (num_fetches == 1 && channels_per_fetch > 1) {
578 LLVMValueRef fetch = fetches[0];
579 for (unsigned i = 0; i < channels_per_fetch; ++i) {
580 tmp = LLVMConstInt(ctx->i32, i, false);
581 fetches[i] = LLVMBuildExtractElement(
582 ctx->ac.builder, fetch, tmp, "");
583 }
584 num_fetches = channels_per_fetch;
585 channels_per_fetch = 1;
586 }
587
588 for (unsigned i = num_fetches; i < 4; ++i)
589 fetches[i] = LLVMGetUndef(ctx->f32);
590
591 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
592 required_channels == 4) {
593 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
594 fetches[3] = ctx->ac.i32_1;
595 else
596 fetches[3] = ctx->ac.f32_1;
597 } else if (fix_fetch.u.log_size == 3 &&
598 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
599 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
600 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
601 required_channels == 4) {
602 /* For 2_10_10_10, the hardware returns an unsigned value;
603 * convert it to a signed one.
604 */
605 LLVMValueRef tmp = fetches[3];
606 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
607
608 /* First, recover the sign-extended signed integer value. */
609 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
610 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
611 else
612 tmp = ac_to_integer(&ctx->ac, tmp);
613
614 /* For the integer-like cases, do a natural sign extension.
615 *
616 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
617 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
618 * exponent.
619 */
620 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
621 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
622 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
623 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
624
625 /* Convert back to the right type. */
626 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
627 LLVMValueRef clamp;
628 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
629 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
630 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
631 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
632 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
633 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
634 }
635
636 fetches[3] = tmp;
637 }
638
639 for (unsigned i = 0; i < 4; ++i)
640 out[i] = ac_to_float(&ctx->ac, fetches[i]);
641 }
642
643 static void declare_input_vs(
644 struct si_shader_context *ctx,
645 unsigned input_index,
646 const struct tgsi_full_declaration *decl,
647 LLVMValueRef out[4])
648 {
649 si_llvm_load_input_vs(ctx, input_index, out);
650 }
651
652 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
653 unsigned swizzle)
654 {
655 if (swizzle > 0)
656 return ctx->i32_0;
657
658 switch (ctx->type) {
659 case PIPE_SHADER_VERTEX:
660 return LLVMGetParam(ctx->main_fn,
661 ctx->param_vs_prim_id);
662 case PIPE_SHADER_TESS_CTRL:
663 return ctx->abi.tcs_patch_id;
664 case PIPE_SHADER_TESS_EVAL:
665 return ctx->abi.tes_patch_id;
666 case PIPE_SHADER_GEOMETRY:
667 return ctx->abi.gs_prim_id;
668 default:
669 assert(0);
670 return ctx->i32_0;
671 }
672 }
673
674 /**
675 * Return the value of tgsi_ind_register for indexing.
676 * This is the indirect index with the constant offset added to it.
677 */
678 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
679 const struct tgsi_ind_register *ind,
680 unsigned addr_mul,
681 int rel_index)
682 {
683 LLVMValueRef result;
684
685 if (ind->File == TGSI_FILE_ADDRESS) {
686 result = ctx->addrs[ind->Index][ind->Swizzle];
687 result = LLVMBuildLoad(ctx->ac.builder, result, "");
688 } else {
689 struct tgsi_full_src_register src = {};
690
691 src.Register.File = ind->File;
692 src.Register.Index = ind->Index;
693
694 /* Set the second index to 0 for constants. */
695 if (ind->File == TGSI_FILE_CONSTANT)
696 src.Register.Dimension = 1;
697
698 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
699 TGSI_TYPE_SIGNED,
700 ind->Swizzle);
701 result = ac_to_integer(&ctx->ac, result);
702 }
703
704 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
705 LLVMConstInt(ctx->i32, rel_index, 0));
706 }
707
708 /**
709 * Like si_get_indirect_index, but restricts the return value to a (possibly
710 * undefined) value inside [0..num).
711 */
712 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
713 const struct tgsi_ind_register *ind,
714 int rel_index, unsigned num)
715 {
716 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
717
718 return si_llvm_bound_index(ctx, result, num);
719 }
720
721 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
722 LLVMValueRef vertex_dw_stride,
723 LLVMValueRef base_addr,
724 LLVMValueRef vertex_index,
725 LLVMValueRef param_index,
726 unsigned input_index,
727 ubyte *name,
728 ubyte *index,
729 bool is_patch)
730 {
731 if (vertex_dw_stride) {
732 base_addr = ac_build_imad(&ctx->ac, vertex_index,
733 vertex_dw_stride, base_addr);
734 }
735
736 if (param_index) {
737 base_addr = ac_build_imad(&ctx->ac, param_index,
738 LLVMConstInt(ctx->i32, 4, 0), base_addr);
739 }
740
741 int param = is_patch ?
742 si_shader_io_get_unique_index_patch(name[input_index],
743 index[input_index]) :
744 si_shader_io_get_unique_index(name[input_index],
745 index[input_index], false);
746
747 /* Add the base address of the element. */
748 return LLVMBuildAdd(ctx->ac.builder, base_addr,
749 LLVMConstInt(ctx->i32, param * 4, 0), "");
750 }
751
752 /**
753 * Calculate a dword address given an input or output register and a stride.
754 */
755 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
756 const struct tgsi_full_dst_register *dst,
757 const struct tgsi_full_src_register *src,
758 LLVMValueRef vertex_dw_stride,
759 LLVMValueRef base_addr)
760 {
761 struct tgsi_shader_info *info = &ctx->shader->selector->info;
762 ubyte *name, *index, *array_first;
763 int input_index;
764 struct tgsi_full_dst_register reg;
765 LLVMValueRef vertex_index = NULL;
766 LLVMValueRef ind_index = NULL;
767
768 /* Set the register description. The address computation is the same
769 * for sources and destinations. */
770 if (src) {
771 reg.Register.File = src->Register.File;
772 reg.Register.Index = src->Register.Index;
773 reg.Register.Indirect = src->Register.Indirect;
774 reg.Register.Dimension = src->Register.Dimension;
775 reg.Indirect = src->Indirect;
776 reg.Dimension = src->Dimension;
777 reg.DimIndirect = src->DimIndirect;
778 } else
779 reg = *dst;
780
781 /* If the register is 2-dimensional (e.g. an array of vertices
782 * in a primitive), calculate the base address of the vertex. */
783 if (reg.Register.Dimension) {
784 if (reg.Dimension.Indirect)
785 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
786 1, reg.Dimension.Index);
787 else
788 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
789 }
790
791 /* Get information about the register. */
792 if (reg.Register.File == TGSI_FILE_INPUT) {
793 name = info->input_semantic_name;
794 index = info->input_semantic_index;
795 array_first = info->input_array_first;
796 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
797 name = info->output_semantic_name;
798 index = info->output_semantic_index;
799 array_first = info->output_array_first;
800 } else {
801 assert(0);
802 return NULL;
803 }
804
805 if (reg.Register.Indirect) {
806 /* Add the relative address of the element. */
807 if (reg.Indirect.ArrayID)
808 input_index = array_first[reg.Indirect.ArrayID];
809 else
810 input_index = reg.Register.Index;
811
812 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
813 1, reg.Register.Index - input_index);
814 } else {
815 input_index = reg.Register.Index;
816 }
817
818 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
819 base_addr, vertex_index,
820 ind_index, input_index,
821 name, index,
822 !reg.Register.Dimension);
823 }
824
825 /* The offchip buffer layout for TCS->TES is
826 *
827 * - attribute 0 of patch 0 vertex 0
828 * - attribute 0 of patch 0 vertex 1
829 * - attribute 0 of patch 0 vertex 2
830 * ...
831 * - attribute 0 of patch 1 vertex 0
832 * - attribute 0 of patch 1 vertex 1
833 * ...
834 * - attribute 1 of patch 0 vertex 0
835 * - attribute 1 of patch 0 vertex 1
836 * ...
837 * - per patch attribute 0 of patch 0
838 * - per patch attribute 0 of patch 1
839 * ...
840 *
841 * Note that every attribute has 4 components.
842 */
843 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
844 LLVMValueRef rel_patch_id,
845 LLVMValueRef vertex_index,
846 LLVMValueRef param_index)
847 {
848 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
849 LLVMValueRef param_stride, constant16;
850
851 vertices_per_patch = get_num_tcs_out_vertices(ctx);
852 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
853 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
854 num_patches, "");
855
856 constant16 = LLVMConstInt(ctx->i32, 16, 0);
857 if (vertex_index) {
858 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
859 vertices_per_patch, vertex_index);
860 param_stride = total_vertices;
861 } else {
862 base_addr = rel_patch_id;
863 param_stride = num_patches;
864 }
865
866 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
867 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
868
869 if (!vertex_index) {
870 LLVMValueRef patch_data_offset =
871 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
872
873 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
874 patch_data_offset, "");
875 }
876 return base_addr;
877 }
878
879 /* This is a generic helper that can be shared by the NIR and TGSI backends */
880 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
881 struct si_shader_context *ctx,
882 LLVMValueRef vertex_index,
883 LLVMValueRef param_index,
884 unsigned param_base,
885 ubyte *name,
886 ubyte *index,
887 bool is_patch)
888 {
889 unsigned param_index_base;
890
891 param_index_base = is_patch ?
892 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
893 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
894
895 if (param_index) {
896 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
897 LLVMConstInt(ctx->i32, param_index_base, 0),
898 "");
899 } else {
900 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
901 }
902
903 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
904 vertex_index, param_index);
905 }
906
907 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
908 struct si_shader_context *ctx,
909 const struct tgsi_full_dst_register *dst,
910 const struct tgsi_full_src_register *src)
911 {
912 struct tgsi_shader_info *info = &ctx->shader->selector->info;
913 ubyte *name, *index, *array_first;
914 struct tgsi_full_src_register reg;
915 LLVMValueRef vertex_index = NULL;
916 LLVMValueRef param_index = NULL;
917 unsigned param_base;
918
919 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
920
921 if (reg.Register.Dimension) {
922
923 if (reg.Dimension.Indirect)
924 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
925 1, reg.Dimension.Index);
926 else
927 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
928 }
929
930 /* Get information about the register. */
931 if (reg.Register.File == TGSI_FILE_INPUT) {
932 name = info->input_semantic_name;
933 index = info->input_semantic_index;
934 array_first = info->input_array_first;
935 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
936 name = info->output_semantic_name;
937 index = info->output_semantic_index;
938 array_first = info->output_array_first;
939 } else {
940 assert(0);
941 return NULL;
942 }
943
944 if (reg.Register.Indirect) {
945 if (reg.Indirect.ArrayID)
946 param_base = array_first[reg.Indirect.ArrayID];
947 else
948 param_base = reg.Register.Index;
949
950 param_index = si_get_indirect_index(ctx, &reg.Indirect,
951 1, reg.Register.Index - param_base);
952
953 } else {
954 param_base = reg.Register.Index;
955 }
956
957 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
958 param_index, param_base,
959 name, index, !reg.Register.Dimension);
960 }
961
962 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
963 LLVMTypeRef type, unsigned swizzle,
964 LLVMValueRef buffer, LLVMValueRef offset,
965 LLVMValueRef base, bool can_speculate)
966 {
967 struct si_shader_context *ctx = si_shader_context(bld_base);
968 LLVMValueRef value, value2;
969 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
970
971 if (swizzle == ~0) {
972 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
973 0, ac_glc, can_speculate, false);
974
975 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
976 }
977
978 if (!llvm_type_is_64bit(ctx, type)) {
979 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
980 0, ac_glc, can_speculate, false);
981
982 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
983 return LLVMBuildExtractElement(ctx->ac.builder, value,
984 LLVMConstInt(ctx->i32, swizzle, 0), "");
985 }
986
987 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
988 swizzle * 4, ac_glc, can_speculate, false);
989
990 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
991 swizzle * 4 + 4, ac_glc, can_speculate, false);
992
993 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
994 }
995
996 /**
997 * Load from LSHS LDS storage.
998 *
999 * \param type output value type
1000 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1001 * \param dw_addr address in dwords
1002 */
1003 static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
1004 LLVMTypeRef type, unsigned swizzle,
1005 LLVMValueRef dw_addr)
1006 {
1007 struct si_shader_context *ctx = si_shader_context(bld_base);
1008 LLVMValueRef value;
1009
1010 if (swizzle == ~0) {
1011 LLVMValueRef values[TGSI_NUM_CHANNELS];
1012
1013 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1014 values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);
1015
1016 return ac_build_gather_values(&ctx->ac, values,
1017 TGSI_NUM_CHANNELS);
1018 }
1019
1020 /* Split 64-bit loads. */
1021 if (llvm_type_is_64bit(ctx, type)) {
1022 LLVMValueRef lo, hi;
1023
1024 lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1025 hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1026 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1027 }
1028
1029 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1030 LLVMConstInt(ctx->i32, swizzle, 0), "");
1031
1032 value = ac_lds_load(&ctx->ac, dw_addr);
1033
1034 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1035 }
1036
1037 /**
1038 * Store to LSHS LDS storage.
1039 *
1040 * \param swizzle offset (typically 0..3)
1041 * \param dw_addr address in dwords
1042 * \param value value to store
1043 */
1044 static void lshs_lds_store(struct si_shader_context *ctx,
1045 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1046 LLVMValueRef value)
1047 {
1048 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1049 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1050
1051 ac_lds_store(&ctx->ac, dw_addr, value);
1052 }
1053
1054 enum si_tess_ring {
1055 TCS_FACTOR_RING,
1056 TESS_OFFCHIP_RING_TCS,
1057 TESS_OFFCHIP_RING_TES,
1058 };
1059
1060 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1061 enum si_tess_ring ring)
1062 {
1063 LLVMBuilderRef builder = ctx->ac.builder;
1064 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1065 ctx->param_tcs_out_lds_layout;
1066 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1067
1068 /* TCS only receives high 13 bits of the address. */
1069 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1070 addr = LLVMBuildAnd(builder, addr,
1071 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1072 }
1073
1074 if (ring == TCS_FACTOR_RING) {
1075 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1076 addr = LLVMBuildAdd(builder, addr,
1077 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1078 }
1079
1080 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1081 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1082 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1083 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1084
1085 if (ctx->screen->info.chip_class >= GFX10)
1086 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1087 S_008F0C_OOB_SELECT(3) |
1088 S_008F0C_RESOURCE_LEVEL(1);
1089 else
1090 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1091 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1092
1093 LLVMValueRef desc[4];
1094 desc[0] = addr;
1095 desc[1] = LLVMConstInt(ctx->i32,
1096 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1097 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1098 desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);
1099
1100 return ac_build_gather_values(&ctx->ac, desc, 4);
1101 }
1102
1103 static LLVMValueRef fetch_input_tcs(
1104 struct lp_build_tgsi_context *bld_base,
1105 const struct tgsi_full_src_register *reg,
1106 enum tgsi_opcode_type type, unsigned swizzle_in)
1107 {
1108 struct si_shader_context *ctx = si_shader_context(bld_base);
1109 LLVMValueRef dw_addr, stride;
1110 unsigned swizzle = swizzle_in & 0xffff;
1111 stride = get_tcs_in_vertex_dw_stride(ctx);
1112 dw_addr = get_tcs_in_current_patch_offset(ctx);
1113 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1114
1115 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1116 }
1117
1118 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1119 LLVMTypeRef type,
1120 LLVMValueRef vertex_index,
1121 LLVMValueRef param_index,
1122 unsigned const_index,
1123 unsigned location,
1124 unsigned driver_location,
1125 unsigned component,
1126 unsigned num_components,
1127 bool is_patch,
1128 bool is_compact,
1129 bool load_input)
1130 {
1131 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1132 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1133 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1134 LLVMValueRef dw_addr, stride;
1135
1136 driver_location = driver_location / 4;
1137
1138 if (load_input) {
1139 stride = get_tcs_in_vertex_dw_stride(ctx);
1140 dw_addr = get_tcs_in_current_patch_offset(ctx);
1141 } else {
1142 if (is_patch) {
1143 stride = NULL;
1144 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1145 } else {
1146 stride = get_tcs_out_vertex_dw_stride(ctx);
1147 dw_addr = get_tcs_out_current_patch_offset(ctx);
1148 }
1149 }
1150
1151 if (param_index) {
1152 /* Add the constant index to the indirect index */
1153 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1154 LLVMConstInt(ctx->i32, const_index, 0), "");
1155 } else {
1156 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1157 }
1158
1159 ubyte *names;
1160 ubyte *indices;
1161 if (load_input) {
1162 names = info->input_semantic_name;
1163 indices = info->input_semantic_index;
1164 } else {
1165 names = info->output_semantic_name;
1166 indices = info->output_semantic_index;
1167 }
1168
1169 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1170 vertex_index, param_index,
1171 driver_location,
1172 names, indices,
1173 is_patch);
1174
1175 LLVMValueRef value[4];
1176 for (unsigned i = 0; i < num_components; i++) {
1177 unsigned offset = i;
1178 if (llvm_type_is_64bit(ctx, type))
1179 offset *= 2;
1180
1181 offset += component;
1182 value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
1183 }
1184
1185 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1186 }
1187
1188 static LLVMValueRef fetch_output_tcs(
1189 struct lp_build_tgsi_context *bld_base,
1190 const struct tgsi_full_src_register *reg,
1191 enum tgsi_opcode_type type, unsigned swizzle_in)
1192 {
1193 struct si_shader_context *ctx = si_shader_context(bld_base);
1194 LLVMValueRef dw_addr, stride;
1195 unsigned swizzle = (swizzle_in & 0xffff);
1196
1197 if (reg->Register.Dimension) {
1198 stride = get_tcs_out_vertex_dw_stride(ctx);
1199 dw_addr = get_tcs_out_current_patch_offset(ctx);
1200 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1201 } else {
1202 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1203 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1204 }
1205
1206 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1207 }
1208
1209 static LLVMValueRef fetch_input_tes(
1210 struct lp_build_tgsi_context *bld_base,
1211 const struct tgsi_full_src_register *reg,
1212 enum tgsi_opcode_type type, unsigned swizzle_in)
1213 {
1214 struct si_shader_context *ctx = si_shader_context(bld_base);
1215 LLVMValueRef base, addr;
1216 unsigned swizzle = (swizzle_in & 0xffff);
1217
1218 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1219 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1220
1221 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1222 ctx->tess_offchip_ring, base, addr, true);
1223 }
1224
1225 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1226 LLVMTypeRef type,
1227 LLVMValueRef vertex_index,
1228 LLVMValueRef param_index,
1229 unsigned const_index,
1230 unsigned location,
1231 unsigned driver_location,
1232 unsigned component,
1233 unsigned num_components,
1234 bool is_patch,
1235 bool is_compact,
1236 bool load_input)
1237 {
1238 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1239 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1240 LLVMValueRef base, addr;
1241
1242 driver_location = driver_location / 4;
1243
1244 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1245
1246 if (param_index) {
1247 /* Add the constant index to the indirect index */
1248 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1249 LLVMConstInt(ctx->i32, const_index, 0), "");
1250 } else {
1251 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1252 }
1253
1254 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1255 param_index, driver_location,
1256 info->input_semantic_name,
1257 info->input_semantic_index,
1258 is_patch);
1259
1260 /* TODO: This will generate rather ordinary llvm code, although it
1261 * should be easy for the optimiser to fix up. In future we might want
1262 * to refactor buffer_load(), but for now this maximises code sharing
1263 * between the NIR and TGSI backends.
1264 */
1265 LLVMValueRef value[4];
1266 for (unsigned i = 0; i < num_components; i++) {
1267 unsigned offset = i;
1268 if (llvm_type_is_64bit(ctx, type)) {
1269 offset *= 2;
1270 if (offset == 4) {
1271 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1272 vertex_index,
1273 param_index,
1274 driver_location + 1,
1275 info->input_semantic_name,
1276 info->input_semantic_index,
1277 is_patch);
1278 }
1279
1280 offset = offset % 4;
1281 }
1282
1283 offset += component;
1284 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1285 ctx->tess_offchip_ring, base, addr, true);
1286 }
1287
1288 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1289 }
1290
1291 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1292 const struct tgsi_full_instruction *inst,
1293 const struct tgsi_opcode_info *info,
1294 unsigned index,
1295 LLVMValueRef dst[4])
1296 {
1297 struct si_shader_context *ctx = si_shader_context(bld_base);
1298 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1299 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1300 unsigned chan_index;
1301 LLVMValueRef dw_addr, stride;
1302 LLVMValueRef buffer, base, buf_addr;
1303 LLVMValueRef values[4];
1304 bool skip_lds_store;
1305 bool is_tess_factor = false, is_tess_inner = false;
1306
1307 /* Only handle per-patch and per-vertex outputs here.
1308 * Vectors will be lowered to scalars and this function will be called again.
1309 */
1310 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1311 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1312 si_llvm_emit_store(bld_base, inst, info, index, dst);
1313 return;
1314 }
1315
1316 if (reg->Register.Dimension) {
1317 stride = get_tcs_out_vertex_dw_stride(ctx);
1318 dw_addr = get_tcs_out_current_patch_offset(ctx);
1319 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1320 skip_lds_store = !sh_info->reads_pervertex_outputs;
1321 } else {
1322 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1323 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1324 skip_lds_store = !sh_info->reads_perpatch_outputs;
1325
1326 if (!reg->Register.Indirect) {
1327 int name = sh_info->output_semantic_name[reg->Register.Index];
1328
1329 /* Always write tess factors into LDS for the TCS epilog. */
1330 if (name == TGSI_SEMANTIC_TESSINNER ||
1331 name == TGSI_SEMANTIC_TESSOUTER) {
1332 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1333 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1334 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1335 is_tess_factor = true;
1336 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1337 }
1338 }
1339 }
1340
1341 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1342
1343 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1344 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1345
1346 uint32_t writemask = reg->Register.WriteMask;
1347 while (writemask) {
1348 chan_index = u_bit_scan(&writemask);
1349 LLVMValueRef value = dst[chan_index];
1350
1351 if (inst->Instruction.Saturate)
1352 value = ac_build_clamp(&ctx->ac, value);
1353
1354 /* Skip LDS stores if there is no LDS read of this output. */
1355 if (!skip_lds_store)
1356 lshs_lds_store(ctx, chan_index, dw_addr, value);
1357
1358 value = ac_to_integer(&ctx->ac, value);
1359 values[chan_index] = value;
1360
1361 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1362 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1363 buf_addr, base,
1364 4 * chan_index, ac_glc, false);
1365 }
1366
1367 /* Write tess factors into VGPRs for the epilog. */
1368 if (is_tess_factor &&
1369 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1370 if (!is_tess_inner) {
1371 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1372 ctx->invoc0_tess_factors[chan_index]);
1373 } else if (chan_index < 2) {
1374 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1375 ctx->invoc0_tess_factors[4 + chan_index]);
1376 }
1377 }
1378 }
1379
1380 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1381 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1382 values, 4);
1383 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1384 base, 0, ac_glc, false);
1385 }
1386 }
1387
1388 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1389 const struct nir_variable *var,
1390 LLVMValueRef vertex_index,
1391 LLVMValueRef param_index,
1392 unsigned const_index,
1393 LLVMValueRef src,
1394 unsigned writemask)
1395 {
1396 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1397 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1398 const unsigned component = var->data.location_frac;
1399 const bool is_patch = var->data.patch;
1400 unsigned driver_location = var->data.driver_location;
1401 LLVMValueRef dw_addr, stride;
1402 LLVMValueRef buffer, base, addr;
1403 LLVMValueRef values[8];
1404 bool skip_lds_store;
1405 bool is_tess_factor = false, is_tess_inner = false;
1406
1407 driver_location = driver_location / 4;
1408
1409 if (param_index) {
1410 /* Add the constant index to the indirect index */
1411 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1412 LLVMConstInt(ctx->i32, const_index, 0), "");
1413 } else {
1414 if (const_index != 0)
1415 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1416 }
1417
1418 if (!is_patch) {
1419 stride = get_tcs_out_vertex_dw_stride(ctx);
1420 dw_addr = get_tcs_out_current_patch_offset(ctx);
1421 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1422 vertex_index, param_index,
1423 driver_location,
1424 info->output_semantic_name,
1425 info->output_semantic_index,
1426 is_patch);
1427
1428 skip_lds_store = !info->reads_pervertex_outputs;
1429 } else {
1430 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1431 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1432 vertex_index, param_index,
1433 driver_location,
1434 info->output_semantic_name,
1435 info->output_semantic_index,
1436 is_patch);
1437
1438 skip_lds_store = !info->reads_perpatch_outputs;
1439
1440 if (!param_index) {
1441 int name = info->output_semantic_name[driver_location];
1442
1443 /* Always write tess factors into LDS for the TCS epilog. */
1444 if (name == TGSI_SEMANTIC_TESSINNER ||
1445 name == TGSI_SEMANTIC_TESSOUTER) {
1446 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1447 skip_lds_store = !info->reads_tessfactor_outputs &&
1448 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1449 is_tess_factor = true;
1450 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1451 }
1452 }
1453 }
1454
1455 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1456
1457 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1458
1459 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1460 param_index, driver_location,
1461 info->output_semantic_name,
1462 info->output_semantic_index,
1463 is_patch);
1464
1465 for (unsigned chan = 0; chan < 8; chan++) {
1466 if (!(writemask & (1 << chan)))
1467 continue;
1468 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1469
1470 unsigned buffer_store_offset = chan % 4;
1471 if (chan == 4) {
1472 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1473 vertex_index,
1474 param_index,
1475 driver_location + 1,
1476 info->output_semantic_name,
1477 info->output_semantic_index,
1478 is_patch);
1479 }
1480
1481 /* Skip LDS stores if there is no LDS read of this output. */
1482 if (!skip_lds_store)
1483 lshs_lds_store(ctx, chan, dw_addr, value);
1484
1485 value = ac_to_integer(&ctx->ac, value);
1486 values[chan] = value;
1487
1488 if (writemask != 0xF && !is_tess_factor) {
1489 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1490 addr, base,
1491 4 * buffer_store_offset,
1492 ac_glc, false);
1493 }
1494
1495 /* Write tess factors into VGPRs for the epilog. */
1496 if (is_tess_factor &&
1497 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1498 if (!is_tess_inner) {
1499 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1500 ctx->invoc0_tess_factors[chan]);
1501 } else if (chan < 2) {
1502 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1503 ctx->invoc0_tess_factors[4 + chan]);
1504 }
1505 }
1506 }
1507
1508 if (writemask == 0xF && !is_tess_factor) {
1509 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1510 values, 4);
1511 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1512 base, 0, ac_glc, false);
1513 }
1514 }
1515
1516 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1517 unsigned input_index,
1518 unsigned vtx_offset_param,
1519 LLVMTypeRef type,
1520 unsigned swizzle)
1521 {
1522 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1523 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1524 struct si_shader *shader = ctx->shader;
1525 LLVMValueRef vtx_offset, soffset;
1526 struct tgsi_shader_info *info = &shader->selector->info;
1527 unsigned semantic_name = info->input_semantic_name[input_index];
1528 unsigned semantic_index = info->input_semantic_index[input_index];
1529 unsigned param;
1530 LLVMValueRef value;
1531
1532 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1533
1534 /* GFX9 has the ESGS ring in LDS. */
1535 if (ctx->screen->info.chip_class >= GFX9) {
1536 unsigned index = vtx_offset_param;
1537
1538 switch (index / 2) {
1539 case 0:
1540 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1541 index % 2 ? 16 : 0, 16);
1542 break;
1543 case 1:
1544 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1545 index % 2 ? 16 : 0, 16);
1546 break;
1547 case 2:
1548 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1549 index % 2 ? 16 : 0, 16);
1550 break;
1551 default:
1552 assert(0);
1553 return NULL;
1554 }
1555
1556 unsigned offset = param * 4 + swizzle;
1557 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1558 LLVMConstInt(ctx->i32, offset, false), "");
1559
1560 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1561 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1562 if (llvm_type_is_64bit(ctx, type)) {
1563 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1564 &ctx->ac.i32_1, 1, "");
1565 LLVMValueRef values[2] = {
1566 value,
1567 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1568 };
1569 value = ac_build_gather_values(&ctx->ac, values, 2);
1570 }
1571 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1572 }
1573
1574 /* GFX6: input load from the ESGS ring in memory. */
1575 if (swizzle == ~0) {
1576 LLVMValueRef values[TGSI_NUM_CHANNELS];
1577 unsigned chan;
1578 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1579 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1580 type, chan);
1581 }
1582 return ac_build_gather_values(&ctx->ac, values,
1583 TGSI_NUM_CHANNELS);
1584 }
1585
1586 /* Get the vertex offset parameter on GFX6. */
1587 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1588
1589 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1590 LLVMConstInt(ctx->i32, 4, 0), "");
1591
1592 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1593
1594 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1595 vtx_offset, soffset, 0, ac_glc, true, false);
1596 if (llvm_type_is_64bit(ctx, type)) {
1597 LLVMValueRef value2;
1598 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1599
1600 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1601 ctx->i32_0, vtx_offset, soffset,
1602 0, ac_glc, true, false);
1603 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1604 }
1605 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1606 }
1607
1608 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1609 unsigned location,
1610 unsigned driver_location,
1611 unsigned component,
1612 unsigned num_components,
1613 unsigned vertex_index,
1614 unsigned const_index,
1615 LLVMTypeRef type)
1616 {
1617 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1618
1619 LLVMValueRef value[4];
1620 for (unsigned i = 0; i < num_components; i++) {
1621 unsigned offset = i;
1622 if (llvm_type_is_64bit(ctx, type))
1623 offset *= 2;
1624
1625 offset += component;
1626 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1627 vertex_index, type, offset);
1628 }
1629
1630 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1631 }
1632
1633 static LLVMValueRef fetch_input_gs(
1634 struct lp_build_tgsi_context *bld_base,
1635 const struct tgsi_full_src_register *reg,
1636 enum tgsi_opcode_type type,
1637 unsigned swizzle_in)
1638 {
1639 struct si_shader_context *ctx = si_shader_context(bld_base);
1640 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1641 unsigned swizzle = swizzle_in & 0xffff;
1642
1643 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1644 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1645 return si_get_primitive_id(ctx, swizzle);
1646
1647 if (!reg->Register.Dimension)
1648 return NULL;
1649
1650 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1651 reg->Dimension.Index,
1652 tgsi2llvmtype(bld_base, type),
1653 swizzle);
1654 }
1655
1656 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1657 {
1658 switch (interpolate) {
1659 case TGSI_INTERPOLATE_CONSTANT:
1660 return 0;
1661
1662 case TGSI_INTERPOLATE_LINEAR:
1663 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1664 return SI_PARAM_LINEAR_SAMPLE;
1665 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1666 return SI_PARAM_LINEAR_CENTROID;
1667 else
1668 return SI_PARAM_LINEAR_CENTER;
1669 break;
1670 case TGSI_INTERPOLATE_COLOR:
1671 case TGSI_INTERPOLATE_PERSPECTIVE:
1672 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1673 return SI_PARAM_PERSP_SAMPLE;
1674 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1675 return SI_PARAM_PERSP_CENTROID;
1676 else
1677 return SI_PARAM_PERSP_CENTER;
1678 break;
1679 default:
1680 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1681 return -1;
1682 }
1683 }
1684
1685 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1686 unsigned attr_index, unsigned chan,
1687 LLVMValueRef prim_mask,
1688 LLVMValueRef i, LLVMValueRef j)
1689 {
1690 if (i || j) {
1691 return ac_build_fs_interp(&ctx->ac,
1692 LLVMConstInt(ctx->i32, chan, 0),
1693 LLVMConstInt(ctx->i32, attr_index, 0),
1694 prim_mask, i, j);
1695 }
1696 return ac_build_fs_interp_mov(&ctx->ac,
1697 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1698 LLVMConstInt(ctx->i32, chan, 0),
1699 LLVMConstInt(ctx->i32, attr_index, 0),
1700 prim_mask);
1701 }
1702
1703 /**
1704 * Interpolate a fragment shader input.
1705 *
1706 * @param ctx context
1707 * @param input_index index of the input in hardware
1708 * @param semantic_name TGSI_SEMANTIC_*
1709 * @param semantic_index semantic index
1710 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1711 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1712 * @param interp_param interpolation weights (i,j)
1713 * @param prim_mask SI_PARAM_PRIM_MASK
1714 * @param face SI_PARAM_FRONT_FACE
1715 * @param result the return value (4 components)
1716 */
1717 static void interp_fs_input(struct si_shader_context *ctx,
1718 unsigned input_index,
1719 unsigned semantic_name,
1720 unsigned semantic_index,
1721 unsigned num_interp_inputs,
1722 unsigned colors_read_mask,
1723 LLVMValueRef interp_param,
1724 LLVMValueRef prim_mask,
1725 LLVMValueRef face,
1726 LLVMValueRef result[4])
1727 {
1728 LLVMValueRef i = NULL, j = NULL;
1729 unsigned chan;
1730
1731 /* fs.constant returns the param from the middle vertex, so it's not
1732 * really useful for flat shading. It's meant to be used for custom
1733 * interpolation (but the intrinsic can't fetch from the other two
1734 * vertices).
1735 *
1736 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1737 * to do the right thing. The only reason we use fs.constant is that
1738 * fs.interp cannot be used on integers, because they can be equal
1739 * to NaN.
1740 *
1741 * When interp is false we will use fs.constant or for newer llvm,
1742 * amdgcn.interp.mov.
1743 */
1744 bool interp = interp_param != NULL;
1745
1746 if (interp) {
1747 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1748 LLVMVectorType(ctx->f32, 2), "");
1749
1750 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1751 ctx->i32_0, "");
1752 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1753 ctx->i32_1, "");
1754 }
1755
1756 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1757 ctx->shader->key.part.ps.prolog.color_two_side) {
1758 LLVMValueRef is_face_positive;
1759
1760 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1761 * otherwise it's at offset "num_inputs".
1762 */
1763 unsigned back_attr_offset = num_interp_inputs;
1764 if (semantic_index == 1 && colors_read_mask & 0xf)
1765 back_attr_offset += 1;
1766
1767 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1768 face, ctx->i32_0, "");
1769
1770 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1771 LLVMValueRef front, back;
1772
1773 front = si_build_fs_interp(ctx,
1774 input_index, chan,
1775 prim_mask, i, j);
1776 back = si_build_fs_interp(ctx,
1777 back_attr_offset, chan,
1778 prim_mask, i, j);
1779
1780 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1781 is_face_positive,
1782 front,
1783 back,
1784 "");
1785 }
1786 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1787 result[0] = si_build_fs_interp(ctx, input_index,
1788 0, prim_mask, i, j);
1789 result[1] =
1790 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1791 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1792 } else {
1793 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1794 result[chan] = si_build_fs_interp(ctx,
1795 input_index, chan,
1796 prim_mask, i, j);
1797 }
1798 }
1799 }
1800
1801 void si_llvm_load_input_fs(
1802 struct si_shader_context *ctx,
1803 unsigned input_index,
1804 LLVMValueRef out[4])
1805 {
1806 struct si_shader *shader = ctx->shader;
1807 struct tgsi_shader_info *info = &shader->selector->info;
1808 LLVMValueRef main_fn = ctx->main_fn;
1809 LLVMValueRef interp_param = NULL;
1810 int interp_param_idx;
1811 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1812 unsigned semantic_index = info->input_semantic_index[input_index];
1813 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1814 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1815
1816 /* Get colors from input VGPRs (set by the prolog). */
1817 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1818 unsigned colors_read = shader->selector->info.colors_read;
1819 unsigned mask = colors_read >> (semantic_index * 4);
1820 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1821 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1822 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1823
1824 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1825 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1826 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1827 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1828 return;
1829 }
1830
1831 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1832 if (interp_param_idx == -1)
1833 return;
1834 else if (interp_param_idx) {
1835 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1836 }
1837
1838 interp_fs_input(ctx, input_index, semantic_name,
1839 semantic_index, 0, /* this param is unused */
1840 shader->selector->info.colors_read, interp_param,
1841 ctx->abi.prim_mask,
1842 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1843 &out[0]);
1844 }
1845
1846 static void declare_input_fs(
1847 struct si_shader_context *ctx,
1848 unsigned input_index,
1849 const struct tgsi_full_declaration *decl,
1850 LLVMValueRef out[4])
1851 {
1852 si_llvm_load_input_fs(ctx, input_index, out);
1853 }
1854
1855 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1856 {
1857 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1858 }
1859
1860 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1861 {
1862 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1863
1864 /* For non-indexed draws, the base vertex set by the driver
1865 * (for direct draws) or the CP (for indirect draws) is the
1866 * first vertex ID, but GLSL expects 0 to be returned.
1867 */
1868 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1869 ctx->param_vs_state_bits);
1870 LLVMValueRef indexed;
1871
1872 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1873 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1874
1875 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1876 ctx->i32_0, "");
1877 }
1878
1879 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1880 {
1881 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1882
1883 LLVMValueRef values[3];
1884 LLVMValueRef result;
1885 unsigned i;
1886 unsigned *properties = ctx->shader->selector->info.properties;
1887
1888 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1889 unsigned sizes[3] = {
1890 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1891 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1892 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1893 };
1894
1895 for (i = 0; i < 3; ++i)
1896 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1897
1898 result = ac_build_gather_values(&ctx->ac, values, 3);
1899 } else {
1900 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1901 }
1902
1903 return result;
1904 }
1905
1906 /**
1907 * Load a dword from a constant buffer.
1908 */
1909 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1910 LLVMValueRef resource,
1911 LLVMValueRef offset)
1912 {
1913 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1914 0, 0, true, true);
1915 }
1916
1917 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1918 {
1919 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1920 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1921 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1922 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1923
1924 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1925 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1926 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1927
1928 LLVMValueRef pos[4] = {
1929 buffer_load_const(ctx, resource, offset0),
1930 buffer_load_const(ctx, resource, offset1),
1931 LLVMConstReal(ctx->f32, 0),
1932 LLVMConstReal(ctx->f32, 0)
1933 };
1934
1935 return ac_build_gather_values(&ctx->ac, pos, 4);
1936 }
1937
1938 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1939 {
1940 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1941 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1942 }
1943
1944 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1945 {
1946 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1947 LLVMValueRef coord[4] = {
1948 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1949 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1950 ctx->ac.f32_0,
1951 ctx->ac.f32_0
1952 };
1953
1954 /* For triangles, the vector should be (u, v, 1-u-v). */
1955 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1956 PIPE_PRIM_TRIANGLES) {
1957 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1958 LLVMBuildFAdd(ctx->ac.builder,
1959 coord[0], coord[1], ""), "");
1960 }
1961 return ac_build_gather_values(&ctx->ac, coord, 4);
1962 }
1963
1964 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1965 unsigned semantic_name)
1966 {
1967 LLVMValueRef base, addr;
1968
1969 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1970
1971 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1972 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1973 LLVMConstInt(ctx->i32, param, 0));
1974
1975 return buffer_load(&ctx->bld_base, ctx->f32,
1976 ~0, ctx->tess_offchip_ring, base, addr, true);
1977
1978 }
1979
1980 static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx,
1981 unsigned semantic_name)
1982 {
1983 LLVMValueRef buf, slot, val[4];
1984 int i, offset;
1985
1986 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1987 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1988 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1989 offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;
1990
1991 for (i = 0; i < 4; i++)
1992 val[i] = buffer_load_const(ctx, buf,
1993 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1994 return ac_build_gather_values(&ctx->ac, val, 4);
1995 }
1996
1997 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1998 unsigned varying_id,
1999 bool load_default_state)
2000 {
2001 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2002 unsigned semantic_name;
2003
2004 if (load_default_state) {
2005 switch (varying_id) {
2006 case VARYING_SLOT_TESS_LEVEL_INNER:
2007 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
2008 break;
2009 case VARYING_SLOT_TESS_LEVEL_OUTER:
2010 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
2011 break;
2012 default:
2013 unreachable("unknown tess level");
2014 }
2015 return load_tess_level_default(ctx, semantic_name);
2016 }
2017
2018 switch (varying_id) {
2019 case VARYING_SLOT_TESS_LEVEL_INNER:
2020 semantic_name = TGSI_SEMANTIC_TESSINNER;
2021 break;
2022 case VARYING_SLOT_TESS_LEVEL_OUTER:
2023 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2024 break;
2025 default:
2026 unreachable("unknown tess level");
2027 }
2028
2029 return load_tess_level(ctx, semantic_name);
2030
2031 }
2032
2033 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2034 {
2035 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2036 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2037 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2038 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2039 return get_num_tcs_out_vertices(ctx);
2040 else
2041 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2042 }
2043
2044 void si_load_system_value(struct si_shader_context *ctx,
2045 unsigned index,
2046 const struct tgsi_full_declaration *decl)
2047 {
2048 LLVMValueRef value = 0;
2049
2050 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2051
2052 switch (decl->Semantic.Name) {
2053 case TGSI_SEMANTIC_INSTANCEID:
2054 value = ctx->abi.instance_id;
2055 break;
2056
2057 case TGSI_SEMANTIC_VERTEXID:
2058 value = LLVMBuildAdd(ctx->ac.builder,
2059 ctx->abi.vertex_id,
2060 ctx->abi.base_vertex, "");
2061 break;
2062
2063 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2064 /* Unused. Clarify the meaning in indexed vs. non-indexed
2065 * draws if this is ever used again. */
2066 assert(false);
2067 break;
2068
2069 case TGSI_SEMANTIC_BASEVERTEX:
2070 value = get_base_vertex(&ctx->abi);
2071 break;
2072
2073 case TGSI_SEMANTIC_BASEINSTANCE:
2074 value = ctx->abi.start_instance;
2075 break;
2076
2077 case TGSI_SEMANTIC_DRAWID:
2078 value = ctx->abi.draw_id;
2079 break;
2080
2081 case TGSI_SEMANTIC_INVOCATIONID:
2082 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
2083 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2084 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
2085 if (ctx->screen->info.chip_class >= GFX10) {
2086 value = LLVMBuildAnd(ctx->ac.builder,
2087 ctx->abi.gs_invocation_id,
2088 LLVMConstInt(ctx->i32, 127, 0), "");
2089 } else {
2090 value = ctx->abi.gs_invocation_id;
2091 }
2092 } else {
2093 assert(!"INVOCATIONID not implemented");
2094 }
2095 break;
2096
2097 case TGSI_SEMANTIC_POSITION:
2098 {
2099 LLVMValueRef pos[4] = {
2100 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2101 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2102 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2103 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2104 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2105 };
2106 value = ac_build_gather_values(&ctx->ac, pos, 4);
2107 break;
2108 }
2109
2110 case TGSI_SEMANTIC_FACE:
2111 value = ctx->abi.front_face;
2112 break;
2113
2114 case TGSI_SEMANTIC_SAMPLEID:
2115 value = si_get_sample_id(ctx);
2116 break;
2117
2118 case TGSI_SEMANTIC_SAMPLEPOS: {
2119 LLVMValueRef pos[4] = {
2120 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2121 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2122 LLVMConstReal(ctx->f32, 0),
2123 LLVMConstReal(ctx->f32, 0)
2124 };
2125 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2126 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2127 value = ac_build_gather_values(&ctx->ac, pos, 4);
2128 break;
2129 }
2130
2131 case TGSI_SEMANTIC_SAMPLEMASK:
2132 /* This can only occur with the OpenGL Core profile, which
2133 * doesn't support smoothing.
2134 */
2135 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2136 break;
2137
2138 case TGSI_SEMANTIC_TESSCOORD:
2139 value = si_load_tess_coord(&ctx->abi);
2140 break;
2141
2142 case TGSI_SEMANTIC_VERTICESIN:
2143 value = si_load_patch_vertices_in(&ctx->abi);
2144 break;
2145
2146 case TGSI_SEMANTIC_TESSINNER:
2147 case TGSI_SEMANTIC_TESSOUTER:
2148 value = load_tess_level(ctx, decl->Semantic.Name);
2149 break;
2150
2151 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
2152 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
2153 value = load_tess_level_default(ctx, decl->Semantic.Name);
2154 break;
2155
2156 case TGSI_SEMANTIC_PRIMID:
2157 value = si_get_primitive_id(ctx, 0);
2158 break;
2159
2160 case TGSI_SEMANTIC_GRID_SIZE:
2161 value = ctx->abi.num_work_groups;
2162 break;
2163
2164 case TGSI_SEMANTIC_BLOCK_SIZE:
2165 value = get_block_size(&ctx->abi);
2166 break;
2167
2168 case TGSI_SEMANTIC_BLOCK_ID:
2169 {
2170 LLVMValueRef values[3];
2171
2172 for (int i = 0; i < 3; i++) {
2173 values[i] = ctx->i32_0;
2174 if (ctx->abi.workgroup_ids[i]) {
2175 values[i] = ctx->abi.workgroup_ids[i];
2176 }
2177 }
2178 value = ac_build_gather_values(&ctx->ac, values, 3);
2179 break;
2180 }
2181
2182 case TGSI_SEMANTIC_THREAD_ID:
2183 value = ctx->abi.local_invocation_ids;
2184 break;
2185
2186 case TGSI_SEMANTIC_HELPER_INVOCATION:
2187 value = ac_build_load_helper_invocation(&ctx->ac);
2188 break;
2189
2190 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2191 value = LLVMConstInt(ctx->i32, ctx->ac.wave_size, 0);
2192 break;
2193
2194 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2195 value = ac_get_thread_id(&ctx->ac);
2196 break;
2197
2198 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2199 {
2200 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2201 if (ctx->ac.wave_size == 64)
2202 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2203 value = LLVMBuildShl(ctx->ac.builder,
2204 LLVMConstInt(ctx->ac.iN_wavemask, 1, 0), id, "");
2205 if (ctx->ac.wave_size == 32)
2206 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2207 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2208 break;
2209 }
2210
2211 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2212 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2213 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2214 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2215 {
2216 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2217 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2218 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2219 /* All bits set except LSB */
2220 value = LLVMConstInt(ctx->ac.iN_wavemask, -2, 0);
2221 } else {
2222 /* All bits set */
2223 value = LLVMConstInt(ctx->ac.iN_wavemask, -1, 0);
2224 }
2225 if (ctx->ac.wave_size == 64)
2226 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2227 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2228 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2229 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2230 value = LLVMBuildNot(ctx->ac.builder, value, "");
2231 if (ctx->ac.wave_size == 32)
2232 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2233 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2234 break;
2235 }
2236
2237 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
2238 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2239 break;
2240
2241 default:
2242 assert(!"unknown system value");
2243 return;
2244 }
2245
2246 ctx->system_values[index] = value;
2247 }
2248
2249 void si_declare_compute_memory(struct si_shader_context *ctx)
2250 {
2251 struct si_shader_selector *sel = ctx->shader->selector;
2252 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2253
2254 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2255 LLVMValueRef var;
2256
2257 assert(!ctx->ac.lds);
2258
2259 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2260 LLVMArrayType(ctx->i8, lds_size),
2261 "compute_lds",
2262 AC_ADDR_SPACE_LDS);
2263 LLVMSetAlignment(var, 64 * 1024);
2264
2265 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2266 }
2267
2268 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2269 const struct tgsi_full_declaration *decl)
2270 {
2271 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2272 assert(decl->Range.First == decl->Range.Last);
2273
2274 si_declare_compute_memory(ctx);
2275 }
2276
2277 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2278 {
2279 LLVMValueRef ptr =
2280 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2281 struct si_shader_selector *sel = ctx->shader->selector;
2282
2283 /* Do the bounds checking with a descriptor, because
2284 * doing computation and manual bounds checking of 64-bit
2285 * addresses generates horrible VALU code with very high
2286 * VGPR usage and very low SIMD occupancy.
2287 */
2288 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2289
2290 LLVMValueRef desc0, desc1;
2291 desc0 = ptr;
2292 desc1 = LLVMConstInt(ctx->i32,
2293 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2294
2295 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2296 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2297 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2298 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2299
2300 if (ctx->screen->info.chip_class >= GFX10)
2301 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2302 S_008F0C_OOB_SELECT(3) |
2303 S_008F0C_RESOURCE_LEVEL(1);
2304 else
2305 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2306 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2307
2308 LLVMValueRef desc_elems[] = {
2309 desc0,
2310 desc1,
2311 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2312 LLVMConstInt(ctx->i32, rsrc3, false)
2313 };
2314
2315 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2316 }
2317
2318 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2319 {
2320 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2321 ctx->param_const_and_shader_buffers);
2322
2323 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2324 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2325 }
2326
2327 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2328 {
2329 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2330 struct si_shader_selector *sel = ctx->shader->selector;
2331
2332 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2333
2334 if (sel->info.const_buffers_declared == 1 &&
2335 sel->info.shader_buffers_declared == 0) {
2336 return load_const_buffer_desc_fast_path(ctx);
2337 }
2338
2339 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2340 index = LLVMBuildAdd(ctx->ac.builder, index,
2341 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2342
2343 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2344 }
2345
2346 static LLVMValueRef
2347 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2348 {
2349 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2350 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2351 ctx->param_const_and_shader_buffers);
2352
2353 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2354 index = LLVMBuildSub(ctx->ac.builder,
2355 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2356 index, "");
2357
2358 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2359 }
2360
2361 static LLVMValueRef fetch_constant(
2362 struct lp_build_tgsi_context *bld_base,
2363 const struct tgsi_full_src_register *reg,
2364 enum tgsi_opcode_type type,
2365 unsigned swizzle_in)
2366 {
2367 struct si_shader_context *ctx = si_shader_context(bld_base);
2368 struct si_shader_selector *sel = ctx->shader->selector;
2369 const struct tgsi_ind_register *ireg = &reg->Indirect;
2370 unsigned buf, idx;
2371 unsigned swizzle = swizzle_in & 0xffff;
2372
2373 LLVMValueRef addr, bufp;
2374
2375 if (swizzle_in == LP_CHAN_ALL) {
2376 unsigned chan;
2377 LLVMValueRef values[4];
2378 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2379 values[chan] = fetch_constant(bld_base, reg, type, chan);
2380
2381 return ac_build_gather_values(&ctx->ac, values, 4);
2382 }
2383
2384 /* Split 64-bit loads. */
2385 if (tgsi_type_is_64bit(type)) {
2386 LLVMValueRef lo, hi;
2387
2388 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2389 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2390 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2391 lo, hi);
2392 }
2393
2394 idx = reg->Register.Index * 4 + swizzle;
2395 if (reg->Register.Indirect) {
2396 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2397 } else {
2398 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2399 }
2400
2401 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2402 if (sel->info.const_buffers_declared == 1 &&
2403 sel->info.shader_buffers_declared == 0) {
2404 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2405 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2406 return bitcast(bld_base, type, result);
2407 }
2408
2409 assert(reg->Register.Dimension);
2410 buf = reg->Dimension.Index;
2411
2412 if (reg->Dimension.Indirect) {
2413 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2414 LLVMValueRef index;
2415 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2416 reg->Dimension.Index,
2417 ctx->num_const_buffers);
2418 index = LLVMBuildAdd(ctx->ac.builder, index,
2419 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2420 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2421 } else
2422 bufp = load_const_buffer_desc(ctx, buf);
2423
2424 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2425 }
2426
2427 /* Initialize arguments for the shader export intrinsic */
2428 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2429 LLVMValueRef *values,
2430 unsigned target,
2431 struct ac_export_args *args)
2432 {
2433 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2434 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2435 unsigned chan;
2436 bool is_int8, is_int10;
2437
2438 /* Default is 0xf. Adjusted below depending on the format. */
2439 args->enabled_channels = 0xf; /* writemask */
2440
2441 /* Specify whether the EXEC mask represents the valid mask */
2442 args->valid_mask = 0;
2443
2444 /* Specify whether this is the last export */
2445 args->done = 0;
2446
2447 /* Specify the target we are exporting */
2448 args->target = target;
2449
2450 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2451 const struct si_shader_key *key = &ctx->shader->key;
2452 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2453 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2454
2455 assert(cbuf >= 0 && cbuf < 8);
2456 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2457 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2458 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2459 }
2460
2461 args->compr = false;
2462 args->out[0] = f32undef;
2463 args->out[1] = f32undef;
2464 args->out[2] = f32undef;
2465 args->out[3] = f32undef;
2466
2467 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2468 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2469 unsigned bits, bool hi) = NULL;
2470
2471 switch (spi_shader_col_format) {
2472 case V_028714_SPI_SHADER_ZERO:
2473 args->enabled_channels = 0; /* writemask */
2474 args->target = V_008DFC_SQ_EXP_NULL;
2475 break;
2476
2477 case V_028714_SPI_SHADER_32_R:
2478 args->enabled_channels = 1; /* writemask */
2479 args->out[0] = values[0];
2480 break;
2481
2482 case V_028714_SPI_SHADER_32_GR:
2483 args->enabled_channels = 0x3; /* writemask */
2484 args->out[0] = values[0];
2485 args->out[1] = values[1];
2486 break;
2487
2488 case V_028714_SPI_SHADER_32_AR:
2489 if (ctx->screen->info.chip_class >= GFX10) {
2490 args->enabled_channels = 0x3; /* writemask */
2491 args->out[0] = values[0];
2492 args->out[1] = values[3];
2493 } else {
2494 args->enabled_channels = 0x9; /* writemask */
2495 args->out[0] = values[0];
2496 args->out[3] = values[3];
2497 }
2498 break;
2499
2500 case V_028714_SPI_SHADER_FP16_ABGR:
2501 packf = ac_build_cvt_pkrtz_f16;
2502 break;
2503
2504 case V_028714_SPI_SHADER_UNORM16_ABGR:
2505 packf = ac_build_cvt_pknorm_u16;
2506 break;
2507
2508 case V_028714_SPI_SHADER_SNORM16_ABGR:
2509 packf = ac_build_cvt_pknorm_i16;
2510 break;
2511
2512 case V_028714_SPI_SHADER_UINT16_ABGR:
2513 packi = ac_build_cvt_pk_u16;
2514 break;
2515
2516 case V_028714_SPI_SHADER_SINT16_ABGR:
2517 packi = ac_build_cvt_pk_i16;
2518 break;
2519
2520 case V_028714_SPI_SHADER_32_ABGR:
2521 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2522 break;
2523 }
2524
2525 /* Pack f16 or norm_i16/u16. */
2526 if (packf) {
2527 for (chan = 0; chan < 2; chan++) {
2528 LLVMValueRef pack_args[2] = {
2529 values[2 * chan],
2530 values[2 * chan + 1]
2531 };
2532 LLVMValueRef packed;
2533
2534 packed = packf(&ctx->ac, pack_args);
2535 args->out[chan] = ac_to_float(&ctx->ac, packed);
2536 }
2537 args->compr = 1; /* COMPR flag */
2538 }
2539 /* Pack i16/u16. */
2540 if (packi) {
2541 for (chan = 0; chan < 2; chan++) {
2542 LLVMValueRef pack_args[2] = {
2543 ac_to_integer(&ctx->ac, values[2 * chan]),
2544 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2545 };
2546 LLVMValueRef packed;
2547
2548 packed = packi(&ctx->ac, pack_args,
2549 is_int8 ? 8 : is_int10 ? 10 : 16,
2550 chan == 1);
2551 args->out[chan] = ac_to_float(&ctx->ac, packed);
2552 }
2553 args->compr = 1; /* COMPR flag */
2554 }
2555 }
2556
2557 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2558 LLVMValueRef alpha)
2559 {
2560 struct si_shader_context *ctx = si_shader_context(bld_base);
2561
2562 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2563 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2564 [PIPE_FUNC_LESS] = LLVMRealOLT,
2565 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2566 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2567 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2568 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2569 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2570 };
2571 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2572 assert(cond);
2573
2574 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2575 SI_PARAM_ALPHA_REF);
2576 LLVMValueRef alpha_pass =
2577 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2578 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2579 } else {
2580 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2581 }
2582 }
2583
2584 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2585 LLVMValueRef alpha,
2586 unsigned samplemask_param)
2587 {
2588 struct si_shader_context *ctx = si_shader_context(bld_base);
2589 LLVMValueRef coverage;
2590
2591 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2592 coverage = LLVMGetParam(ctx->main_fn,
2593 samplemask_param);
2594 coverage = ac_to_integer(&ctx->ac, coverage);
2595
2596 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2597 ctx->i32,
2598 &coverage, 1, AC_FUNC_ATTR_READNONE);
2599
2600 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2601 ctx->f32, "");
2602
2603 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2604 LLVMConstReal(ctx->f32,
2605 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2606
2607 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2608 }
2609
2610 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2611 struct ac_export_args *pos, LLVMValueRef *out_elts)
2612 {
2613 unsigned reg_index;
2614 unsigned chan;
2615 unsigned const_chan;
2616 LLVMValueRef base_elt;
2617 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2618 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2619 SI_VS_CONST_CLIP_PLANES, 0);
2620 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2621
2622 for (reg_index = 0; reg_index < 2; reg_index ++) {
2623 struct ac_export_args *args = &pos[2 + reg_index];
2624
2625 args->out[0] =
2626 args->out[1] =
2627 args->out[2] =
2628 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2629
2630 /* Compute dot products of position and user clip plane vectors */
2631 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2632 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2633 LLVMValueRef addr =
2634 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2635 const_chan) * 4, 0);
2636 base_elt = buffer_load_const(ctx, const_resource,
2637 addr);
2638 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2639 out_elts[const_chan], args->out[chan]);
2640 }
2641 }
2642
2643 args->enabled_channels = 0xf;
2644 args->valid_mask = 0;
2645 args->done = 0;
2646 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2647 args->compr = 0;
2648 }
2649 }
2650
2651 static void si_dump_streamout(struct pipe_stream_output_info *so)
2652 {
2653 unsigned i;
2654
2655 if (so->num_outputs)
2656 fprintf(stderr, "STREAMOUT\n");
2657
2658 for (i = 0; i < so->num_outputs; i++) {
2659 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2660 so->output[i].start_component;
2661 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2662 i, so->output[i].output_buffer,
2663 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2664 so->output[i].register_index,
2665 mask & 1 ? "x" : "",
2666 mask & 2 ? "y" : "",
2667 mask & 4 ? "z" : "",
2668 mask & 8 ? "w" : "");
2669 }
2670 }
2671
2672 void si_emit_streamout_output(struct si_shader_context *ctx,
2673 LLVMValueRef const *so_buffers,
2674 LLVMValueRef const *so_write_offsets,
2675 struct pipe_stream_output *stream_out,
2676 struct si_shader_output_values *shader_out)
2677 {
2678 unsigned buf_idx = stream_out->output_buffer;
2679 unsigned start = stream_out->start_component;
2680 unsigned num_comps = stream_out->num_components;
2681 LLVMValueRef out[4];
2682
2683 assert(num_comps && num_comps <= 4);
2684 if (!num_comps || num_comps > 4)
2685 return;
2686
2687 /* Load the output as int. */
2688 for (int j = 0; j < num_comps; j++) {
2689 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2690
2691 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2692 }
2693
2694 /* Pack the output. */
2695 LLVMValueRef vdata = NULL;
2696
2697 switch (num_comps) {
2698 case 1: /* as i32 */
2699 vdata = out[0];
2700 break;
2701 case 2: /* as v2i32 */
2702 case 3: /* as v3i32 */
2703 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2704 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2705 break;
2706 }
2707 /* as v4i32 (aligned to 4) */
2708 out[3] = LLVMGetUndef(ctx->i32);
2709 /* fall through */
2710 case 4: /* as v4i32 */
2711 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2712 break;
2713 }
2714
2715 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2716 vdata, num_comps,
2717 so_write_offsets[buf_idx],
2718 ctx->i32_0,
2719 stream_out->dst_offset * 4, ac_glc | ac_slc, false);
2720 }
2721
2722 /**
2723 * Write streamout data to buffers for vertex stream @p stream (different
2724 * vertex streams can occur for GS copy shaders).
2725 */
2726 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2727 struct si_shader_output_values *outputs,
2728 unsigned noutput, unsigned stream)
2729 {
2730 struct si_shader_selector *sel = ctx->shader->selector;
2731 struct pipe_stream_output_info *so = &sel->so;
2732 LLVMBuilderRef builder = ctx->ac.builder;
2733 int i;
2734
2735 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2736 LLVMValueRef so_vtx_count =
2737 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2738
2739 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2740
2741 /* can_emit = tid < so_vtx_count; */
2742 LLVMValueRef can_emit =
2743 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2744
2745 /* Emit the streamout code conditionally. This actually avoids
2746 * out-of-bounds buffer access. The hw tells us via the SGPR
2747 * (so_vtx_count) which threads are allowed to emit streamout data. */
2748 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2749 {
2750 /* The buffer offset is computed as follows:
2751 * ByteOffset = streamout_offset[buffer_id]*4 +
2752 * (streamout_write_index + thread_id)*stride[buffer_id] +
2753 * attrib_offset
2754 */
2755
2756 LLVMValueRef so_write_index =
2757 LLVMGetParam(ctx->main_fn,
2758 ctx->param_streamout_write_index);
2759
2760 /* Compute (streamout_write_index + thread_id). */
2761 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2762
2763 /* Load the descriptor and compute the write offset for each
2764 * enabled buffer. */
2765 LLVMValueRef so_write_offset[4] = {};
2766 LLVMValueRef so_buffers[4];
2767 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2768 ctx->param_rw_buffers);
2769
2770 for (i = 0; i < 4; i++) {
2771 if (!so->stride[i])
2772 continue;
2773
2774 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2775 SI_VS_STREAMOUT_BUF0 + i, 0);
2776
2777 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2778
2779 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2780 ctx->param_streamout_offset[i]);
2781 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2782
2783 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2784 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2785 so_offset);
2786 }
2787
2788 /* Write streamout data. */
2789 for (i = 0; i < so->num_outputs; i++) {
2790 unsigned reg = so->output[i].register_index;
2791
2792 if (reg >= noutput)
2793 continue;
2794
2795 if (stream != so->output[i].stream)
2796 continue;
2797
2798 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
2799 &so->output[i], &outputs[reg]);
2800 }
2801 }
2802 ac_build_endif(&ctx->ac, 6501);
2803 }
2804
2805 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2806 LLVMValueRef *values)
2807 {
2808 struct ac_export_args args;
2809
2810 si_llvm_init_export_args(ctx, values,
2811 V_008DFC_SQ_EXP_PARAM + index, &args);
2812 ac_build_export(&ctx->ac, &args);
2813 }
2814
2815 static void si_build_param_exports(struct si_shader_context *ctx,
2816 struct si_shader_output_values *outputs,
2817 unsigned noutput)
2818 {
2819 struct si_shader *shader = ctx->shader;
2820 unsigned param_count = 0;
2821
2822 for (unsigned i = 0; i < noutput; i++) {
2823 unsigned semantic_name = outputs[i].semantic_name;
2824 unsigned semantic_index = outputs[i].semantic_index;
2825
2826 if (outputs[i].vertex_stream[0] != 0 &&
2827 outputs[i].vertex_stream[1] != 0 &&
2828 outputs[i].vertex_stream[2] != 0 &&
2829 outputs[i].vertex_stream[3] != 0)
2830 continue;
2831
2832 switch (semantic_name) {
2833 case TGSI_SEMANTIC_LAYER:
2834 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2835 case TGSI_SEMANTIC_CLIPDIST:
2836 case TGSI_SEMANTIC_COLOR:
2837 case TGSI_SEMANTIC_BCOLOR:
2838 case TGSI_SEMANTIC_PRIMID:
2839 case TGSI_SEMANTIC_FOG:
2840 case TGSI_SEMANTIC_TEXCOORD:
2841 case TGSI_SEMANTIC_GENERIC:
2842 break;
2843 default:
2844 continue;
2845 }
2846
2847 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2848 semantic_index < SI_MAX_IO_GENERIC) &&
2849 shader->key.opt.kill_outputs &
2850 (1ull << si_shader_io_get_unique_index(semantic_name,
2851 semantic_index, true)))
2852 continue;
2853
2854 si_export_param(ctx, param_count, outputs[i].values);
2855
2856 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2857 shader->info.vs_output_param_offset[i] = param_count++;
2858 }
2859
2860 shader->info.nr_param_exports = param_count;
2861 }
2862
2863 /**
2864 * Vertex color clamping.
2865 *
2866 * This uses a state constant loaded in a user data SGPR and
2867 * an IF statement is added that clamps all colors if the constant
2868 * is true.
2869 */
2870 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2871 struct si_shader_output_values *outputs,
2872 unsigned noutput)
2873 {
2874 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2875 bool has_colors = false;
2876
2877 /* Store original colors to alloca variables. */
2878 for (unsigned i = 0; i < noutput; i++) {
2879 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2880 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2881 continue;
2882
2883 for (unsigned j = 0; j < 4; j++) {
2884 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2885 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2886 }
2887 has_colors = true;
2888 }
2889
2890 if (!has_colors)
2891 return;
2892
2893 /* The state is in the first bit of the user SGPR. */
2894 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2895 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2896
2897 ac_build_ifcc(&ctx->ac, cond, 6502);
2898
2899 /* Store clamped colors to alloca variables within the conditional block. */
2900 for (unsigned i = 0; i < noutput; i++) {
2901 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2902 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2903 continue;
2904
2905 for (unsigned j = 0; j < 4; j++) {
2906 LLVMBuildStore(ctx->ac.builder,
2907 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2908 addr[i][j]);
2909 }
2910 }
2911 ac_build_endif(&ctx->ac, 6502);
2912
2913 /* Load clamped colors */
2914 for (unsigned i = 0; i < noutput; i++) {
2915 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2916 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2917 continue;
2918
2919 for (unsigned j = 0; j < 4; j++) {
2920 outputs[i].values[j] =
2921 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2922 }
2923 }
2924 }
2925
2926 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2927 * (position and parameter data only).
2928 */
2929 void si_llvm_export_vs(struct si_shader_context *ctx,
2930 struct si_shader_output_values *outputs,
2931 unsigned noutput)
2932 {
2933 struct si_shader *shader = ctx->shader;
2934 struct ac_export_args pos_args[4] = {};
2935 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2936 unsigned pos_idx;
2937 int i;
2938
2939 si_vertex_color_clamping(ctx, outputs, noutput);
2940
2941 /* Build position exports. */
2942 for (i = 0; i < noutput; i++) {
2943 switch (outputs[i].semantic_name) {
2944 case TGSI_SEMANTIC_POSITION:
2945 si_llvm_init_export_args(ctx, outputs[i].values,
2946 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2947 break;
2948 case TGSI_SEMANTIC_PSIZE:
2949 psize_value = outputs[i].values[0];
2950 break;
2951 case TGSI_SEMANTIC_LAYER:
2952 layer_value = outputs[i].values[0];
2953 break;
2954 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2955 viewport_index_value = outputs[i].values[0];
2956 break;
2957 case TGSI_SEMANTIC_EDGEFLAG:
2958 edgeflag_value = outputs[i].values[0];
2959 break;
2960 case TGSI_SEMANTIC_CLIPDIST:
2961 if (!shader->key.opt.clip_disable) {
2962 unsigned index = 2 + outputs[i].semantic_index;
2963 si_llvm_init_export_args(ctx, outputs[i].values,
2964 V_008DFC_SQ_EXP_POS + index,
2965 &pos_args[index]);
2966 }
2967 break;
2968 case TGSI_SEMANTIC_CLIPVERTEX:
2969 if (!shader->key.opt.clip_disable) {
2970 si_llvm_emit_clipvertex(ctx, pos_args,
2971 outputs[i].values);
2972 }
2973 break;
2974 }
2975 }
2976
2977 /* We need to add the position output manually if it's missing. */
2978 if (!pos_args[0].out[0]) {
2979 pos_args[0].enabled_channels = 0xf; /* writemask */
2980 pos_args[0].valid_mask = 0; /* EXEC mask */
2981 pos_args[0].done = 0; /* last export? */
2982 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2983 pos_args[0].compr = 0; /* COMPR flag */
2984 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2985 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2986 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2987 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2988 }
2989
2990 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2991 if (shader->selector->info.writes_psize ||
2992 shader->selector->pos_writes_edgeflag ||
2993 shader->selector->info.writes_viewport_index ||
2994 shader->selector->info.writes_layer) {
2995 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2996 (shader->selector->pos_writes_edgeflag << 1) |
2997 (shader->selector->info.writes_layer << 2);
2998
2999 pos_args[1].valid_mask = 0; /* EXEC mask */
3000 pos_args[1].done = 0; /* last export? */
3001 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
3002 pos_args[1].compr = 0; /* COMPR flag */
3003 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
3004 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
3005 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
3006 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
3007
3008 if (shader->selector->info.writes_psize)
3009 pos_args[1].out[0] = psize_value;
3010
3011 if (shader->selector->pos_writes_edgeflag) {
3012 /* The output is a float, but the hw expects an integer
3013 * with the first bit containing the edge flag. */
3014 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
3015 edgeflag_value,
3016 ctx->i32, "");
3017 edgeflag_value = ac_build_umin(&ctx->ac,
3018 edgeflag_value,
3019 ctx->i32_1);
3020
3021 /* The LLVM intrinsic expects a float. */
3022 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
3023 }
3024
3025 if (ctx->screen->info.chip_class >= GFX9) {
3026 /* GFX9 has the layer in out.z[10:0] and the viewport
3027 * index in out.z[19:16].
3028 */
3029 if (shader->selector->info.writes_layer)
3030 pos_args[1].out[2] = layer_value;
3031
3032 if (shader->selector->info.writes_viewport_index) {
3033 LLVMValueRef v = viewport_index_value;
3034
3035 v = ac_to_integer(&ctx->ac, v);
3036 v = LLVMBuildShl(ctx->ac.builder, v,
3037 LLVMConstInt(ctx->i32, 16, 0), "");
3038 v = LLVMBuildOr(ctx->ac.builder, v,
3039 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3040 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3041 pos_args[1].enabled_channels |= 1 << 2;
3042 }
3043 } else {
3044 if (shader->selector->info.writes_layer)
3045 pos_args[1].out[2] = layer_value;
3046
3047 if (shader->selector->info.writes_viewport_index) {
3048 pos_args[1].out[3] = viewport_index_value;
3049 pos_args[1].enabled_channels |= 1 << 3;
3050 }
3051 }
3052 }
3053
3054 for (i = 0; i < 4; i++)
3055 if (pos_args[i].out[0])
3056 shader->info.nr_pos_exports++;
3057
3058 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
3059 * Setting valid_mask=1 prevents it and has no other effect.
3060 */
3061 if (ctx->screen->info.family == CHIP_NAVI10 ||
3062 ctx->screen->info.family == CHIP_NAVI12 ||
3063 ctx->screen->info.family == CHIP_NAVI14)
3064 pos_args[0].valid_mask = 1;
3065
3066 pos_idx = 0;
3067 for (i = 0; i < 4; i++) {
3068 if (!pos_args[i].out[0])
3069 continue;
3070
3071 /* Specify the target we are exporting */
3072 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3073
3074 if (pos_idx == shader->info.nr_pos_exports)
3075 /* Specify that this is the last export */
3076 pos_args[i].done = 1;
3077
3078 ac_build_export(&ctx->ac, &pos_args[i]);
3079 }
3080
3081 /* Build parameter exports. */
3082 si_build_param_exports(ctx, outputs, noutput);
3083 }
3084
3085 /**
3086 * Forward all outputs from the vertex shader to the TES. This is only used
3087 * for the fixed function TCS.
3088 */
3089 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3090 {
3091 struct si_shader_context *ctx = si_shader_context(bld_base);
3092 LLVMValueRef invocation_id, buffer, buffer_offset;
3093 LLVMValueRef lds_vertex_stride, lds_base;
3094 uint64_t inputs;
3095
3096 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3097 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3098 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3099
3100 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3101 lds_base = get_tcs_in_current_patch_offset(ctx);
3102 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3103 lds_base);
3104
3105 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3106 while (inputs) {
3107 unsigned i = u_bit_scan64(&inputs);
3108
3109 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3110 LLVMConstInt(ctx->i32, 4 * i, 0),
3111 "");
3112
3113 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3114 get_rel_patch_id(ctx),
3115 invocation_id,
3116 LLVMConstInt(ctx->i32, i, 0));
3117
3118 LLVMValueRef value = lshs_lds_load(bld_base, ctx->ac.i32, ~0, lds_ptr);
3119
3120 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3121 buffer_offset, 0, ac_glc, false);
3122 }
3123 }
3124
3125 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3126 LLVMValueRef rel_patch_id,
3127 LLVMValueRef invocation_id,
3128 LLVMValueRef tcs_out_current_patch_data_offset,
3129 LLVMValueRef invoc0_tf_outer[4],
3130 LLVMValueRef invoc0_tf_inner[2])
3131 {
3132 struct si_shader_context *ctx = si_shader_context(bld_base);
3133 struct si_shader *shader = ctx->shader;
3134 unsigned tess_inner_index, tess_outer_index;
3135 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3136 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3137 unsigned stride, outer_comps, inner_comps, i, offset;
3138
3139 /* Add a barrier before loading tess factors from LDS. */
3140 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3141 si_llvm_emit_barrier(NULL, bld_base, NULL);
3142
3143 /* Do this only for invocation 0, because the tess levels are per-patch,
3144 * not per-vertex.
3145 *
3146 * This can't jump, because invocation 0 executes this. It should
3147 * at least mask out the loads and stores for other invocations.
3148 */
3149 ac_build_ifcc(&ctx->ac,
3150 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3151 invocation_id, ctx->i32_0, ""), 6503);
3152
3153 /* Determine the layout of one tess factor element in the buffer. */
3154 switch (shader->key.part.tcs.epilog.prim_mode) {
3155 case PIPE_PRIM_LINES:
3156 stride = 2; /* 2 dwords, 1 vec2 store */
3157 outer_comps = 2;
3158 inner_comps = 0;
3159 break;
3160 case PIPE_PRIM_TRIANGLES:
3161 stride = 4; /* 4 dwords, 1 vec4 store */
3162 outer_comps = 3;
3163 inner_comps = 1;
3164 break;
3165 case PIPE_PRIM_QUADS:
3166 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3167 outer_comps = 4;
3168 inner_comps = 2;
3169 break;
3170 default:
3171 assert(0);
3172 return;
3173 }
3174
3175 for (i = 0; i < 4; i++) {
3176 inner[i] = LLVMGetUndef(ctx->i32);
3177 outer[i] = LLVMGetUndef(ctx->i32);
3178 }
3179
3180 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3181 /* Tess factors are in VGPRs. */
3182 for (i = 0; i < outer_comps; i++)
3183 outer[i] = out[i] = invoc0_tf_outer[i];
3184 for (i = 0; i < inner_comps; i++)
3185 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3186 } else {
3187 /* Load tess_inner and tess_outer from LDS.
3188 * Any invocation can write them, so we can't get them from a temporary.
3189 */
3190 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3191 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3192
3193 lds_base = tcs_out_current_patch_data_offset;
3194 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3195 LLVMConstInt(ctx->i32,
3196 tess_inner_index * 4, 0), "");
3197 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3198 LLVMConstInt(ctx->i32,
3199 tess_outer_index * 4, 0), "");
3200
3201 for (i = 0; i < outer_comps; i++) {
3202 outer[i] = out[i] =
3203 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3204 }
3205 for (i = 0; i < inner_comps; i++) {
3206 inner[i] = out[outer_comps+i] =
3207 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3208 }
3209 }
3210
3211 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3212 /* For isolines, the hardware expects tess factors in the
3213 * reverse order from what GLSL / TGSI specify.
3214 */
3215 LLVMValueRef tmp = out[0];
3216 out[0] = out[1];
3217 out[1] = tmp;
3218 }
3219
3220 /* Convert the outputs to vectors for stores. */
3221 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3222 vec1 = NULL;
3223
3224 if (stride > 4)
3225 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3226
3227 /* Get the buffer. */
3228 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3229
3230 /* Get the offset. */
3231 tf_base = LLVMGetParam(ctx->main_fn,
3232 ctx->param_tcs_factor_offset);
3233 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3234 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3235
3236 ac_build_ifcc(&ctx->ac,
3237 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3238 rel_patch_id, ctx->i32_0, ""), 6504);
3239
3240 /* Store the dynamic HS control word. */
3241 offset = 0;
3242 if (ctx->screen->info.chip_class <= GFX8) {
3243 ac_build_buffer_store_dword(&ctx->ac, buffer,
3244 LLVMConstInt(ctx->i32, 0x80000000, 0),
3245 1, ctx->i32_0, tf_base,
3246 offset, ac_glc, false);
3247 offset += 4;
3248 }
3249
3250 ac_build_endif(&ctx->ac, 6504);
3251
3252 /* Store the tessellation factors. */
3253 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3254 MIN2(stride, 4), byteoffset, tf_base,
3255 offset, ac_glc, false);
3256 offset += 16;
3257 if (vec1)
3258 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3259 stride - 4, byteoffset, tf_base,
3260 offset, ac_glc, false);
3261
3262 /* Store the tess factors into the offchip buffer if TES reads them. */
3263 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3264 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3265 LLVMValueRef tf_inner_offset;
3266 unsigned param_outer, param_inner;
3267
3268 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3269 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3270
3271 param_outer = si_shader_io_get_unique_index_patch(
3272 TGSI_SEMANTIC_TESSOUTER, 0);
3273 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3274 LLVMConstInt(ctx->i32, param_outer, 0));
3275
3276 unsigned outer_vec_size =
3277 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
3278 outer_comps : util_next_power_of_two(outer_comps);
3279 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
3280
3281 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3282 outer_comps, tf_outer_offset,
3283 base, 0, ac_glc, false);
3284 if (inner_comps) {
3285 param_inner = si_shader_io_get_unique_index_patch(
3286 TGSI_SEMANTIC_TESSINNER, 0);
3287 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3288 LLVMConstInt(ctx->i32, param_inner, 0));
3289
3290 inner_vec = inner_comps == 1 ? inner[0] :
3291 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3292 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3293 inner_comps, tf_inner_offset,
3294 base, 0, ac_glc, false);
3295 }
3296 }
3297
3298 ac_build_endif(&ctx->ac, 6503);
3299 }
3300
3301 static LLVMValueRef
3302 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,