projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: don't use lp_build_if for the wrapping if block in merged shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_from_mesa.h"
32
33 #include "ac_binary.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
36 #include "ac_rtld.h"
37 #include "ac_llvm_util.h"
38 #include "si_shader_internal.h"
39 #include "si_pipe.h"
40 #include "sid.h"
41
42 #include "compiler/nir/nir.h"
43
44 static const char scratch_rsrc_dword0_symbol[] =
45 "SCRATCH_RSRC_DWORD0";
46
47 static const char scratch_rsrc_dword1_symbol[] =
48 "SCRATCH_RSRC_DWORD1";
49
50 static void si_init_shader_ctx(struct si_shader_context *ctx,
51 struct si_screen *sscreen,
52 struct ac_llvm_compiler *compiler,
53 unsigned wave_size);
54
55 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
56 struct lp_build_tgsi_context *bld_base,
57 struct lp_build_emit_data *emit_data);
58
59 static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
60
61 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
62 union si_shader_part_key *key);
63 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
64 union si_shader_part_key *key);
65 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
66 union si_shader_part_key *key);
67 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
68 union si_shader_part_key *key);
69 static void si_fix_resource_usage(struct si_screen *sscreen,
70 struct si_shader *shader);
71
72 /* Ideally pass the sample mask input to the PS epilog as v14, which
73 * is its usual location, so that the shader doesn't have to add v_mov.
74 */
75 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
76
77 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
78 LLVMTypeRef type)
79 {
80 if (type == ctx->ac.i64 || type == ctx->ac.f64)
81 return true;
82
83 return false;
84 }
85
86 /** Whether the shader runs as a combination of multiple API shaders */
87 static bool is_multi_part_shader(struct si_shader_context *ctx)
88 {
89 if (ctx->screen->info.chip_class <= GFX8)
90 return false;
91
92 return ctx->shader->key.as_ls ||
93 ctx->shader->key.as_es ||
94 ctx->type == PIPE_SHADER_TESS_CTRL ||
95 ctx->type == PIPE_SHADER_GEOMETRY;
96 }
97
98 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
99 static bool is_merged_shader(struct si_shader_context *ctx)
100 {
101 return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
102 }
103
104 void si_init_function_info(struct si_function_info *fninfo)
105 {
106 fninfo->num_params = 0;
107 fninfo->num_sgpr_params = 0;
108 }
109
110 unsigned add_arg_assign(struct si_function_info *fninfo,
111 enum si_arg_regfile regfile, LLVMTypeRef type,
112 LLVMValueRef *assign)
113 {
114 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
115
116 unsigned idx = fninfo->num_params++;
117 assert(idx < ARRAY_SIZE(fninfo->types));
118
119 if (regfile == ARG_SGPR)
120 fninfo->num_sgpr_params = fninfo->num_params;
121
122 fninfo->types[idx] = type;
123 fninfo->assign[idx] = assign;
124 return idx;
125 }
126
127 static unsigned add_arg(struct si_function_info *fninfo,
128 enum si_arg_regfile regfile, LLVMTypeRef type)
129 {
130 return add_arg_assign(fninfo, regfile, type, NULL);
131 }
132
133 static void add_arg_assign_checked(struct si_function_info *fninfo,
134 enum si_arg_regfile regfile, LLVMTypeRef type,
135 LLVMValueRef *assign, unsigned idx)
136 {
137 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
138 assert(actual == idx);
139 }
140
141 static void add_arg_checked(struct si_function_info *fninfo,
142 enum si_arg_regfile regfile, LLVMTypeRef type,
143 unsigned idx)
144 {
145 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
146 }
147
148 /**
149 * Returns a unique index for a per-patch semantic name and index. The index
150 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
151 * can be calculated.
152 */
153 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
154 {
155 switch (semantic_name) {
156 case TGSI_SEMANTIC_TESSOUTER:
157 return 0;
158 case TGSI_SEMANTIC_TESSINNER:
159 return 1;
160 case TGSI_SEMANTIC_PATCH:
161 assert(index < 30);
162 return 2 + index;
163
164 default:
165 assert(!"invalid semantic name");
166 return 0;
167 }
168 }
169
170 /**
171 * Returns a unique index for a semantic name and index. The index must be
172 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
173 * calculated.
174 */
175 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
176 unsigned is_varying)
177 {
178 switch (semantic_name) {
179 case TGSI_SEMANTIC_POSITION:
180 return 0;
181 case TGSI_SEMANTIC_GENERIC:
182 /* Since some shader stages use the the highest used IO index
183 * to determine the size to allocate for inputs/outputs
184 * (in LDS, tess and GS rings). GENERIC should be placed right
185 * after POSITION to make that size as small as possible.
186 */
187 if (index < SI_MAX_IO_GENERIC)
188 return 1 + index;
189
190 assert(!"invalid generic index");
191 return 0;
192 case TGSI_SEMANTIC_FOG:
193 return SI_MAX_IO_GENERIC + 1;
194 case TGSI_SEMANTIC_COLOR:
195 assert(index < 2);
196 return SI_MAX_IO_GENERIC + 2 + index;
197 case TGSI_SEMANTIC_BCOLOR:
198 assert(index < 2);
199 /* If it's a varying, COLOR and BCOLOR alias. */
200 if (is_varying)
201 return SI_MAX_IO_GENERIC + 2 + index;
202 else
203 return SI_MAX_IO_GENERIC + 4 + index;
204 case TGSI_SEMANTIC_TEXCOORD:
205 assert(index < 8);
206 return SI_MAX_IO_GENERIC + 6 + index;
207
208 /* These are rarely used between LS and HS or ES and GS. */
209 case TGSI_SEMANTIC_CLIPDIST:
210 assert(index < 2);
211 return SI_MAX_IO_GENERIC + 6 + 8 + index;
212 case TGSI_SEMANTIC_CLIPVERTEX:
213 return SI_MAX_IO_GENERIC + 6 + 8 + 2;
214 case TGSI_SEMANTIC_PSIZE:
215 return SI_MAX_IO_GENERIC + 6 + 8 + 3;
216
217 /* These can't be written by LS, HS, and ES. */
218 case TGSI_SEMANTIC_LAYER:
219 return SI_MAX_IO_GENERIC + 6 + 8 + 4;
220 case TGSI_SEMANTIC_VIEWPORT_INDEX:
221 return SI_MAX_IO_GENERIC + 6 + 8 + 5;
222 case TGSI_SEMANTIC_PRIMID:
223 STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
224 return SI_MAX_IO_GENERIC + 6 + 8 + 6;
225 default:
226 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
227 assert(!"invalid semantic name");
228 return 0;
229 }
230 }
231
232 /**
233 * Get the value of a shader input parameter and extract a bitfield.
234 */
235 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
236 LLVMValueRef value, unsigned rshift,
237 unsigned bitwidth)
238 {
239 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
240 value = ac_to_integer(&ctx->ac, value);
241
242 if (rshift)
243 value = LLVMBuildLShr(ctx->ac.builder, value,
244 LLVMConstInt(ctx->i32, rshift, 0), "");
245
246 if (rshift + bitwidth < 32) {
247 unsigned mask = (1 << bitwidth) - 1;
248 value = LLVMBuildAnd(ctx->ac.builder, value,
249 LLVMConstInt(ctx->i32, mask, 0), "");
250 }
251
252 return value;
253 }
254
255 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
256 unsigned param, unsigned rshift,
257 unsigned bitwidth)
258 {
259 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
260
261 return unpack_llvm_param(ctx, value, rshift, bitwidth);
262 }
263
264 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
265 {
266 switch (ctx->type) {
267 case PIPE_SHADER_TESS_CTRL:
268 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
269
270 case PIPE_SHADER_TESS_EVAL:
271 return LLVMGetParam(ctx->main_fn,
272 ctx->param_tes_rel_patch_id);
273
274 default:
275 assert(0);
276 return NULL;
277 }
278 }
279
280 /* Tessellation shaders pass outputs to the next shader using LDS.
281 *
282 * LS outputs = TCS inputs
283 * TCS outputs = TES inputs
284 *
285 * The LDS layout is:
286 * - TCS inputs for patch 0
287 * - TCS inputs for patch 1
288 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
289 * - ...
290 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
291 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
292 * - TCS outputs for patch 1
293 * - Per-patch TCS outputs for patch 1
294 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
295 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
296 * - ...
297 *
298 * All three shaders VS(LS), TCS, TES share the same LDS space.
299 */
300
301 static LLVMValueRef
302 get_tcs_in_patch_stride(struct si_shader_context *ctx)
303 {
304 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
305 }
306
307 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
308 {
309 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
310
311 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
312 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
313
314 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
315 }
316
317 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
318 {
319 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
320
321 return LLVMConstInt(ctx->i32, stride, 0);
322 }
323
324 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
325 {
326 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
327 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
328
329 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
330 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
331 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
332 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
333 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
334 num_patch_outputs * 4;
335 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
336 }
337
338 static LLVMValueRef
339 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
340 {
341 return LLVMBuildMul(ctx->ac.builder,
342 si_unpack_param(ctx,
343 ctx->param_tcs_out_lds_offsets,
344 0, 16),
345 LLVMConstInt(ctx->i32, 4, 0), "");
346 }
347
348 static LLVMValueRef
349 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
350 {
351 return LLVMBuildMul(ctx->ac.builder,
352 si_unpack_param(ctx,
353 ctx->param_tcs_out_lds_offsets,
354 16, 16),
355 LLVMConstInt(ctx->i32, 4, 0), "");
356 }
357
358 static LLVMValueRef
359 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
360 {
361 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
362 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
363
364 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
365 }
366
367 static LLVMValueRef
368 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
369 {
370 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
371 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
372 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
373
374 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
375 }
376
377 static LLVMValueRef
378 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
379 {
380 LLVMValueRef patch0_patch_data_offset =
381 get_tcs_out_patch0_patch_data_offset(ctx);
382 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
383 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
384
385 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
386 }
387
388 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
389 {
390 unsigned tcs_out_vertices =
391 ctx->shader->selector ?
392 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
393
394 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
395 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
396 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
397
398 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
399 }
400
401 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
402 {
403 unsigned stride;
404
405 switch (ctx->type) {
406 case PIPE_SHADER_VERTEX:
407 stride = ctx->shader->selector->lshs_vertex_stride / 4;
408 return LLVMConstInt(ctx->i32, stride, 0);
409
410 case PIPE_SHADER_TESS_CTRL:
411 if (ctx->screen->info.chip_class >= GFX9 &&
412 ctx->shader->is_monolithic) {
413 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
414 return LLVMConstInt(ctx->i32, stride, 0);
415 }
416 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
417
418 default:
419 assert(0);
420 return NULL;
421 }
422 }
423
424 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
425 LLVMValueRef i32, unsigned index)
426 {
427 assert(index <= 1);
428
429 if (index == 1)
430 return LLVMBuildAShr(ctx->ac.builder, i32,
431 LLVMConstInt(ctx->i32, 16, 0), "");
432
433 return LLVMBuildSExt(ctx->ac.builder,
434 LLVMBuildTrunc(ctx->ac.builder, i32,
435 ctx->ac.i16, ""),
436 ctx->i32, "");
437 }
438
439 void si_llvm_load_input_vs(
440 struct si_shader_context *ctx,
441 unsigned input_index,
442 LLVMValueRef out[4])
443 {
444 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
445 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
446
447 if (vs_blit_property) {
448 LLVMValueRef vertex_id = ctx->abi.vertex_id;
449 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
450 LLVMIntULE, vertex_id,
451 ctx->i32_1, "");
452 /* Use LLVMIntNE, because we have 3 vertices and only
453 * the middle one should use y2.
454 */
455 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
456 LLVMIntNE, vertex_id,
457 ctx->i32_1, "");
458
459 if (input_index == 0) {
460 /* Position: */
461 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
462 ctx->param_vs_blit_inputs);
463 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
464 ctx->param_vs_blit_inputs + 1);
465
466 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
467 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
468 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
469 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
470
471 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
472 x1, x2, "");
473 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
474 y1, y2, "");
475
476 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
477 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
478 out[2] = LLVMGetParam(ctx->main_fn,
479 ctx->param_vs_blit_inputs + 2);
480 out[3] = ctx->ac.f32_1;
481 return;
482 }
483
484 /* Color or texture coordinates: */
485 assert(input_index == 1);
486
487 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
488 for (int i = 0; i < 4; i++) {
489 out[i] = LLVMGetParam(ctx->main_fn,
490 ctx->param_vs_blit_inputs + 3 + i);
491 }
492 } else {
493 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
494 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
495 ctx->param_vs_blit_inputs + 3);
496 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
497 ctx->param_vs_blit_inputs + 4);
498 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
499 ctx->param_vs_blit_inputs + 5);
500 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs + 6);
502
503 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
504 x1, x2, "");
505 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
506 y1, y2, "");
507 out[2] = LLVMGetParam(ctx->main_fn,
508 ctx->param_vs_blit_inputs + 7);
509 out[3] = LLVMGetParam(ctx->main_fn,
510 ctx->param_vs_blit_inputs + 8);
511 }
512 return;
513 }
514
515 union si_vs_fix_fetch fix_fetch;
516 LLVMValueRef t_list_ptr;
517 LLVMValueRef t_offset;
518 LLVMValueRef t_list;
519 LLVMValueRef vertex_index;
520 LLVMValueRef tmp;
521
522 /* Load the T list */
523 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
524
525 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
526
527 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
528
529 vertex_index = LLVMGetParam(ctx->main_fn,
530 ctx->param_vertex_index0 +
531 input_index);
532
533 /* Use the open-coded implementation for all loads of doubles and
534 * of dword-sized data that needs fixups. We need to insert conversion
535 * code anyway, and the amd/common code does it for us.
536 *
537 * Note: On LLVM <= 8, we can only open-code formats with
538 * channel size >= 4 bytes.
539 */
540 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
541 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
542 if (opencode ||
543 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
544 (fix_fetch.u.log_size == 2)) {
545 tmp = ac_build_opencoded_load_format(
546 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
547 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
548 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
549 for (unsigned i = 0; i < 4; ++i)
550 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
551 return;
552 }
553
554 /* Do multiple loads for special formats. */
555 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
556 LLVMValueRef fetches[4];
557 unsigned num_fetches;
558 unsigned fetch_stride;
559 unsigned channels_per_fetch;
560
561 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
562 num_fetches = MIN2(required_channels, 3);
563 fetch_stride = 1 << fix_fetch.u.log_size;
564 channels_per_fetch = 1;
565 } else {
566 num_fetches = 1;
567 fetch_stride = 0;
568 channels_per_fetch = required_channels;
569 }
570
571 for (unsigned i = 0; i < num_fetches; ++i) {
572 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
573 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
574 channels_per_fetch, 0, true);
575 }
576
577 if (num_fetches == 1 && channels_per_fetch > 1) {
578 LLVMValueRef fetch = fetches[0];
579 for (unsigned i = 0; i < channels_per_fetch; ++i) {
580 tmp = LLVMConstInt(ctx->i32, i, false);
581 fetches[i] = LLVMBuildExtractElement(
582 ctx->ac.builder, fetch, tmp, "");
583 }
584 num_fetches = channels_per_fetch;
585 channels_per_fetch = 1;
586 }
587
588 for (unsigned i = num_fetches; i < 4; ++i)
589 fetches[i] = LLVMGetUndef(ctx->f32);
590
591 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
592 required_channels == 4) {
593 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
594 fetches[3] = ctx->ac.i32_1;
595 else
596 fetches[3] = ctx->ac.f32_1;
597 } else if (fix_fetch.u.log_size == 3 &&
598 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
599 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
600 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
601 required_channels == 4) {
602 /* For 2_10_10_10, the hardware returns an unsigned value;
603 * convert it to a signed one.
604 */
605 LLVMValueRef tmp = fetches[3];
606 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
607
608 /* First, recover the sign-extended signed integer value. */
609 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
610 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
611 else
612 tmp = ac_to_integer(&ctx->ac, tmp);
613
614 /* For the integer-like cases, do a natural sign extension.
615 *
616 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
617 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
618 * exponent.
619 */
620 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
621 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
622 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
623 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
624
625 /* Convert back to the right type. */
626 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
627 LLVMValueRef clamp;
628 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
629 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
630 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
631 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
632 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
633 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
634 }
635
636 fetches[3] = tmp;
637 }
638
639 for (unsigned i = 0; i < 4; ++i)
640 out[i] = ac_to_float(&ctx->ac, fetches[i]);
641 }
642
643 static void declare_input_vs(
644 struct si_shader_context *ctx,
645 unsigned input_index,
646 const struct tgsi_full_declaration *decl,
647 LLVMValueRef out[4])
648 {
649 si_llvm_load_input_vs(ctx, input_index, out);
650 }
651
652 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
653 unsigned swizzle)
654 {
655 if (swizzle > 0)
656 return ctx->i32_0;
657
658 switch (ctx->type) {
659 case PIPE_SHADER_VERTEX:
660 return LLVMGetParam(ctx->main_fn,
661 ctx->param_vs_prim_id);
662 case PIPE_SHADER_TESS_CTRL:
663 return ctx->abi.tcs_patch_id;
664 case PIPE_SHADER_TESS_EVAL:
665 return ctx->abi.tes_patch_id;
666 case PIPE_SHADER_GEOMETRY:
667 return ctx->abi.gs_prim_id;
668 default:
669 assert(0);
670 return ctx->i32_0;
671 }
672 }
673
674 /**
675 * Return the value of tgsi_ind_register for indexing.
676 * This is the indirect index with the constant offset added to it.
677 */
678 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
679 const struct tgsi_ind_register *ind,
680 unsigned addr_mul,
681 int rel_index)
682 {
683 LLVMValueRef result;
684
685 if (ind->File == TGSI_FILE_ADDRESS) {
686 result = ctx->addrs[ind->Index][ind->Swizzle];
687 result = LLVMBuildLoad(ctx->ac.builder, result, "");
688 } else {
689 struct tgsi_full_src_register src = {};
690
691 src.Register.File = ind->File;
692 src.Register.Index = ind->Index;
693
694 /* Set the second index to 0 for constants. */
695 if (ind->File == TGSI_FILE_CONSTANT)
696 src.Register.Dimension = 1;
697
698 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
699 TGSI_TYPE_SIGNED,
700 ind->Swizzle);
701 result = ac_to_integer(&ctx->ac, result);
702 }
703
704 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
705 LLVMConstInt(ctx->i32, rel_index, 0));
706 }
707
708 /**
709 * Like si_get_indirect_index, but restricts the return value to a (possibly
710 * undefined) value inside [0..num).
711 */
712 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
713 const struct tgsi_ind_register *ind,
714 int rel_index, unsigned num)
715 {
716 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
717
718 return si_llvm_bound_index(ctx, result, num);
719 }
720
721 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
722 LLVMValueRef vertex_dw_stride,
723 LLVMValueRef base_addr,
724 LLVMValueRef vertex_index,
725 LLVMValueRef param_index,
726 unsigned input_index,
727 ubyte *name,
728 ubyte *index,
729 bool is_patch)
730 {
731 if (vertex_dw_stride) {
732 base_addr = ac_build_imad(&ctx->ac, vertex_index,
733 vertex_dw_stride, base_addr);
734 }
735
736 if (param_index) {
737 base_addr = ac_build_imad(&ctx->ac, param_index,
738 LLVMConstInt(ctx->i32, 4, 0), base_addr);
739 }
740
741 int param = is_patch ?
742 si_shader_io_get_unique_index_patch(name[input_index],
743 index[input_index]) :
744 si_shader_io_get_unique_index(name[input_index],
745 index[input_index], false);
746
747 /* Add the base address of the element. */
748 return LLVMBuildAdd(ctx->ac.builder, base_addr,
749 LLVMConstInt(ctx->i32, param * 4, 0), "");
750 }
751
752 /**
753 * Calculate a dword address given an input or output register and a stride.
754 */
755 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
756 const struct tgsi_full_dst_register *dst,
757 const struct tgsi_full_src_register *src,
758 LLVMValueRef vertex_dw_stride,
759 LLVMValueRef base_addr)
760 {
761 struct tgsi_shader_info *info = &ctx->shader->selector->info;
762 ubyte *name, *index, *array_first;
763 int input_index;
764 struct tgsi_full_dst_register reg;
765 LLVMValueRef vertex_index = NULL;
766 LLVMValueRef ind_index = NULL;
767
768 /* Set the register description. The address computation is the same
769 * for sources and destinations. */
770 if (src) {
771 reg.Register.File = src->Register.File;
772 reg.Register.Index = src->Register.Index;
773 reg.Register.Indirect = src->Register.Indirect;
774 reg.Register.Dimension = src->Register.Dimension;
775 reg.Indirect = src->Indirect;
776 reg.Dimension = src->Dimension;
777 reg.DimIndirect = src->DimIndirect;
778 } else
779 reg = *dst;
780
781 /* If the register is 2-dimensional (e.g. an array of vertices
782 * in a primitive), calculate the base address of the vertex. */
783 if (reg.Register.Dimension) {
784 if (reg.Dimension.Indirect)
785 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
786 1, reg.Dimension.Index);
787 else
788 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
789 }
790
791 /* Get information about the register. */
792 if (reg.Register.File == TGSI_FILE_INPUT) {
793 name = info->input_semantic_name;
794 index = info->input_semantic_index;
795 array_first = info->input_array_first;
796 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
797 name = info->output_semantic_name;
798 index = info->output_semantic_index;
799 array_first = info->output_array_first;
800 } else {
801 assert(0);
802 return NULL;
803 }
804
805 if (reg.Register.Indirect) {
806 /* Add the relative address of the element. */
807 if (reg.Indirect.ArrayID)
808 input_index = array_first[reg.Indirect.ArrayID];
809 else
810 input_index = reg.Register.Index;
811
812 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
813 1, reg.Register.Index - input_index);
814 } else {
815 input_index = reg.Register.Index;
816 }
817
818 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
819 base_addr, vertex_index,
820 ind_index, input_index,
821 name, index,
822 !reg.Register.Dimension);
823 }
824
825 /* The offchip buffer layout for TCS->TES is
826 *
827 * - attribute 0 of patch 0 vertex 0
828 * - attribute 0 of patch 0 vertex 1
829 * - attribute 0 of patch 0 vertex 2
830 * ...
831 * - attribute 0 of patch 1 vertex 0
832 * - attribute 0 of patch 1 vertex 1
833 * ...
834 * - attribute 1 of patch 0 vertex 0
835 * - attribute 1 of patch 0 vertex 1
836 * ...
837 * - per patch attribute 0 of patch 0
838 * - per patch attribute 0 of patch 1
839 * ...
840 *
841 * Note that every attribute has 4 components.
842 */
843 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
844 LLVMValueRef rel_patch_id,
845 LLVMValueRef vertex_index,
846 LLVMValueRef param_index)
847 {
848 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
849 LLVMValueRef param_stride, constant16;
850
851 vertices_per_patch = get_num_tcs_out_vertices(ctx);
852 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
853 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
854 num_patches, "");
855
856 constant16 = LLVMConstInt(ctx->i32, 16, 0);
857 if (vertex_index) {
858 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
859 vertices_per_patch, vertex_index);
860 param_stride = total_vertices;
861 } else {
862 base_addr = rel_patch_id;
863 param_stride = num_patches;
864 }
865
866 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
867 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
868
869 if (!vertex_index) {
870 LLVMValueRef patch_data_offset =
871 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
872
873 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
874 patch_data_offset, "");
875 }
876 return base_addr;
877 }
878
879 /* This is a generic helper that can be shared by the NIR and TGSI backends */
880 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
881 struct si_shader_context *ctx,
882 LLVMValueRef vertex_index,
883 LLVMValueRef param_index,
884 unsigned param_base,
885 ubyte *name,
886 ubyte *index,
887 bool is_patch)
888 {
889 unsigned param_index_base;
890
891 param_index_base = is_patch ?
892 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
893 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
894
895 if (param_index) {
896 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
897 LLVMConstInt(ctx->i32, param_index_base, 0),
898 "");
899 } else {
900 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
901 }
902
903 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
904 vertex_index, param_index);
905 }
906
907 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
908 struct si_shader_context *ctx,
909 const struct tgsi_full_dst_register *dst,
910 const struct tgsi_full_src_register *src)
911 {
912 struct tgsi_shader_info *info = &ctx->shader->selector->info;
913 ubyte *name, *index, *array_first;
914 struct tgsi_full_src_register reg;
915 LLVMValueRef vertex_index = NULL;
916 LLVMValueRef param_index = NULL;
917 unsigned param_base;
918
919 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
920
921 if (reg.Register.Dimension) {
922
923 if (reg.Dimension.Indirect)
924 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
925 1, reg.Dimension.Index);
926 else
927 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
928 }
929
930 /* Get information about the register. */
931 if (reg.Register.File == TGSI_FILE_INPUT) {
932 name = info->input_semantic_name;
933 index = info->input_semantic_index;
934 array_first = info->input_array_first;
935 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
936 name = info->output_semantic_name;
937 index = info->output_semantic_index;
938 array_first = info->output_array_first;
939 } else {
940 assert(0);
941 return NULL;
942 }
943
944 if (reg.Register.Indirect) {
945 if (reg.Indirect.ArrayID)
946 param_base = array_first[reg.Indirect.ArrayID];
947 else
948 param_base = reg.Register.Index;
949
950 param_index = si_get_indirect_index(ctx, &reg.Indirect,
951 1, reg.Register.Index - param_base);
952
953 } else {
954 param_base = reg.Register.Index;
955 }
956
957 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
958 param_index, param_base,
959 name, index, !reg.Register.Dimension);
960 }
961
962 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
963 LLVMTypeRef type, unsigned swizzle,
964 LLVMValueRef buffer, LLVMValueRef offset,
965 LLVMValueRef base, bool can_speculate)
966 {
967 struct si_shader_context *ctx = si_shader_context(bld_base);
968 LLVMValueRef value, value2;
969 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
970
971 if (swizzle == ~0) {
972 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
973 0, ac_glc, can_speculate, false);
974
975 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
976 }
977
978 if (!llvm_type_is_64bit(ctx, type)) {
979 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
980 0, ac_glc, can_speculate, false);
981
982 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
983 return LLVMBuildExtractElement(ctx->ac.builder, value,
984 LLVMConstInt(ctx->i32, swizzle, 0), "");
985 }
986
987 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
988 swizzle * 4, ac_glc, can_speculate, false);
989
990 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
991 swizzle * 4 + 4, ac_glc, can_speculate, false);
992
993 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
994 }
995
996 /**
997 * Load from LSHS LDS storage.
998 *
999 * \param type output value type
1000 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1001 * \param dw_addr address in dwords
1002 */
1003 static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
1004 LLVMTypeRef type, unsigned swizzle,
1005 LLVMValueRef dw_addr)
1006 {
1007 struct si_shader_context *ctx = si_shader_context(bld_base);
1008 LLVMValueRef value;
1009
1010 if (swizzle == ~0) {
1011 LLVMValueRef values[TGSI_NUM_CHANNELS];
1012
1013 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1014 values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);
1015
1016 return ac_build_gather_values(&ctx->ac, values,
1017 TGSI_NUM_CHANNELS);
1018 }
1019
1020 /* Split 64-bit loads. */
1021 if (llvm_type_is_64bit(ctx, type)) {
1022 LLVMValueRef lo, hi;
1023
1024 lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1025 hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1026 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1027 }
1028
1029 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1030 LLVMConstInt(ctx->i32, swizzle, 0), "");
1031
1032 value = ac_lds_load(&ctx->ac, dw_addr);
1033
1034 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1035 }
1036
1037 /**
1038 * Store to LSHS LDS storage.
1039 *
1040 * \param swizzle offset (typically 0..3)
1041 * \param dw_addr address in dwords
1042 * \param value value to store
1043 */
1044 static void lshs_lds_store(struct si_shader_context *ctx,
1045 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1046 LLVMValueRef value)
1047 {
1048 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1049 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1050
1051 ac_lds_store(&ctx->ac, dw_addr, value);
1052 }
1053
1054 enum si_tess_ring {
1055 TCS_FACTOR_RING,
1056 TESS_OFFCHIP_RING_TCS,
1057 TESS_OFFCHIP_RING_TES,
1058 };
1059
1060 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1061 enum si_tess_ring ring)
1062 {
1063 LLVMBuilderRef builder = ctx->ac.builder;
1064 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1065 ctx->param_tcs_out_lds_layout;
1066 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1067
1068 /* TCS only receives high 13 bits of the address. */
1069 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1070 addr = LLVMBuildAnd(builder, addr,
1071 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1072 }
1073
1074 if (ring == TCS_FACTOR_RING) {
1075 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1076 addr = LLVMBuildAdd(builder, addr,
1077 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1078 }
1079
1080 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1081 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1082 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1083 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1084
1085 if (ctx->screen->info.chip_class >= GFX10)
1086 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1087 S_008F0C_OOB_SELECT(3) |
1088 S_008F0C_RESOURCE_LEVEL(1);
1089 else
1090 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1091 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1092
1093 LLVMValueRef desc[4];
1094 desc[0] = addr;
1095 desc[1] = LLVMConstInt(ctx->i32,
1096 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1097 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1098 desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);
1099
1100 return ac_build_gather_values(&ctx->ac, desc, 4);
1101 }
1102
1103 static LLVMValueRef fetch_input_tcs(
1104 struct lp_build_tgsi_context *bld_base,
1105 const struct tgsi_full_src_register *reg,
1106 enum tgsi_opcode_type type, unsigned swizzle_in)
1107 {
1108 struct si_shader_context *ctx = si_shader_context(bld_base);
1109 LLVMValueRef dw_addr, stride;
1110 unsigned swizzle = swizzle_in & 0xffff;
1111 stride = get_tcs_in_vertex_dw_stride(ctx);
1112 dw_addr = get_tcs_in_current_patch_offset(ctx);
1113 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1114
1115 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1116 }
1117
1118 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1119 LLVMTypeRef type,
1120 LLVMValueRef vertex_index,
1121 LLVMValueRef param_index,
1122 unsigned const_index,
1123 unsigned location,
1124 unsigned driver_location,
1125 unsigned component,
1126 unsigned num_components,
1127 bool is_patch,
1128 bool is_compact,
1129 bool load_input)
1130 {
1131 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1132 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1133 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1134 LLVMValueRef dw_addr, stride;
1135
1136 driver_location = driver_location / 4;
1137
1138 if (load_input) {
1139 stride = get_tcs_in_vertex_dw_stride(ctx);
1140 dw_addr = get_tcs_in_current_patch_offset(ctx);
1141 } else {
1142 if (is_patch) {
1143 stride = NULL;
1144 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1145 } else {
1146 stride = get_tcs_out_vertex_dw_stride(ctx);
1147 dw_addr = get_tcs_out_current_patch_offset(ctx);
1148 }
1149 }
1150
1151 if (param_index) {
1152 /* Add the constant index to the indirect index */
1153 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1154 LLVMConstInt(ctx->i32, const_index, 0), "");
1155 } else {
1156 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1157 }
1158
1159 ubyte *names;
1160 ubyte *indices;
1161 if (load_input) {
1162 names = info->input_semantic_name;
1163 indices = info->input_semantic_index;
1164 } else {
1165 names = info->output_semantic_name;
1166 indices = info->output_semantic_index;
1167 }
1168
1169 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1170 vertex_index, param_index,
1171 driver_location,
1172 names, indices,
1173 is_patch);
1174
1175 LLVMValueRef value[4];
1176 for (unsigned i = 0; i < num_components; i++) {
1177 unsigned offset = i;
1178 if (llvm_type_is_64bit(ctx, type))
1179 offset *= 2;
1180
1181 offset += component;
1182 value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
1183 }
1184
1185 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1186 }
1187
1188 static LLVMValueRef fetch_output_tcs(
1189 struct lp_build_tgsi_context *bld_base,
1190 const struct tgsi_full_src_register *reg,
1191 enum tgsi_opcode_type type, unsigned swizzle_in)
1192 {
1193 struct si_shader_context *ctx = si_shader_context(bld_base);
1194 LLVMValueRef dw_addr, stride;
1195 unsigned swizzle = (swizzle_in & 0xffff);
1196
1197 if (reg->Register.Dimension) {
1198 stride = get_tcs_out_vertex_dw_stride(ctx);
1199 dw_addr = get_tcs_out_current_patch_offset(ctx);
1200 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1201 } else {
1202 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1203 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1204 }
1205
1206 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1207 }
1208
1209 static LLVMValueRef fetch_input_tes(
1210 struct lp_build_tgsi_context *bld_base,
1211 const struct tgsi_full_src_register *reg,
1212 enum tgsi_opcode_type type, unsigned swizzle_in)
1213 {
1214 struct si_shader_context *ctx = si_shader_context(bld_base);
1215 LLVMValueRef base, addr;
1216 unsigned swizzle = (swizzle_in & 0xffff);
1217
1218 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1219 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1220
1221 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1222 ctx->tess_offchip_ring, base, addr, true);
1223 }
1224
1225 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1226 LLVMTypeRef type,
1227 LLVMValueRef vertex_index,
1228 LLVMValueRef param_index,
1229 unsigned const_index,
1230 unsigned location,
1231 unsigned driver_location,
1232 unsigned component,
1233 unsigned num_components,
1234 bool is_patch,
1235 bool is_compact,
1236 bool load_input)
1237 {
1238 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1239 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1240 LLVMValueRef base, addr;
1241
1242 driver_location = driver_location / 4;
1243
1244 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1245
1246 if (param_index) {
1247 /* Add the constant index to the indirect index */
1248 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1249 LLVMConstInt(ctx->i32, const_index, 0), "");
1250 } else {
1251 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1252 }
1253
1254 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1255 param_index, driver_location,
1256 info->input_semantic_name,
1257 info->input_semantic_index,
1258 is_patch);
1259
1260 /* TODO: This will generate rather ordinary llvm code, although it
1261 * should be easy for the optimiser to fix up. In future we might want
1262 * to refactor buffer_load(), but for now this maximises code sharing
1263 * between the NIR and TGSI backends.
1264 */
1265 LLVMValueRef value[4];
1266 for (unsigned i = 0; i < num_components; i++) {
1267 unsigned offset = i;
1268 if (llvm_type_is_64bit(ctx, type)) {
1269 offset *= 2;
1270 if (offset == 4) {
1271 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1272 vertex_index,
1273 param_index,
1274 driver_location + 1,
1275 info->input_semantic_name,
1276 info->input_semantic_index,
1277 is_patch);
1278 }
1279
1280 offset = offset % 4;
1281 }
1282
1283 offset += component;
1284 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1285 ctx->tess_offchip_ring, base, addr, true);
1286 }
1287
1288 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1289 }
1290
1291 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1292 const struct tgsi_full_instruction *inst,
1293 const struct tgsi_opcode_info *info,
1294 unsigned index,
1295 LLVMValueRef dst[4])
1296 {
1297 struct si_shader_context *ctx = si_shader_context(bld_base);
1298 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1299 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1300 unsigned chan_index;
1301 LLVMValueRef dw_addr, stride;
1302 LLVMValueRef buffer, base, buf_addr;
1303 LLVMValueRef values[4];
1304 bool skip_lds_store;
1305 bool is_tess_factor = false, is_tess_inner = false;
1306
1307 /* Only handle per-patch and per-vertex outputs here.
1308 * Vectors will be lowered to scalars and this function will be called again.
1309 */
1310 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1311 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1312 si_llvm_emit_store(bld_base, inst, info, index, dst);
1313 return;
1314 }
1315
1316 if (reg->Register.Dimension) {
1317 stride = get_tcs_out_vertex_dw_stride(ctx);
1318 dw_addr = get_tcs_out_current_patch_offset(ctx);
1319 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1320 skip_lds_store = !sh_info->reads_pervertex_outputs;
1321 } else {
1322 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1323 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1324 skip_lds_store = !sh_info->reads_perpatch_outputs;
1325
1326 if (!reg->Register.Indirect) {
1327 int name = sh_info->output_semantic_name[reg->Register.Index];
1328
1329 /* Always write tess factors into LDS for the TCS epilog. */
1330 if (name == TGSI_SEMANTIC_TESSINNER ||
1331 name == TGSI_SEMANTIC_TESSOUTER) {
1332 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1333 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1334 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1335 is_tess_factor = true;
1336 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1337 }
1338 }
1339 }
1340
1341 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1342
1343 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1344 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1345
1346 uint32_t writemask = reg->Register.WriteMask;
1347 while (writemask) {
1348 chan_index = u_bit_scan(&writemask);
1349 LLVMValueRef value = dst[chan_index];
1350
1351 if (inst->Instruction.Saturate)
1352 value = ac_build_clamp(&ctx->ac, value);
1353
1354 /* Skip LDS stores if there is no LDS read of this output. */
1355 if (!skip_lds_store)
1356 lshs_lds_store(ctx, chan_index, dw_addr, value);
1357
1358 value = ac_to_integer(&ctx->ac, value);
1359 values[chan_index] = value;
1360
1361 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1362 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1363 buf_addr, base,
1364 4 * chan_index, ac_glc, false);
1365 }
1366
1367 /* Write tess factors into VGPRs for the epilog. */
1368 if (is_tess_factor &&
1369 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1370 if (!is_tess_inner) {
1371 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1372 ctx->invoc0_tess_factors[chan_index]);
1373 } else if (chan_index < 2) {
1374 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1375 ctx->invoc0_tess_factors[4 + chan_index]);
1376 }
1377 }
1378 }
1379
1380 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1381 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1382 values, 4);
1383 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1384 base, 0, ac_glc, false);
1385 }
1386 }
1387
1388 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1389 const struct nir_variable *var,
1390 LLVMValueRef vertex_index,
1391 LLVMValueRef param_index,
1392 unsigned const_index,
1393 LLVMValueRef src,
1394 unsigned writemask)
1395 {
1396 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1397 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1398 const unsigned component = var->data.location_frac;
1399 const bool is_patch = var->data.patch;
1400 unsigned driver_location = var->data.driver_location;
1401 LLVMValueRef dw_addr, stride;
1402 LLVMValueRef buffer, base, addr;
1403 LLVMValueRef values[8];
1404 bool skip_lds_store;
1405 bool is_tess_factor = false, is_tess_inner = false;
1406
1407 driver_location = driver_location / 4;
1408
1409 if (param_index) {
1410 /* Add the constant index to the indirect index */
1411 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1412 LLVMConstInt(ctx->i32, const_index, 0), "");
1413 } else {
1414 if (const_index != 0)
1415 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1416 }
1417
1418 if (!is_patch) {
1419 stride = get_tcs_out_vertex_dw_stride(ctx);
1420 dw_addr = get_tcs_out_current_patch_offset(ctx);
1421 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1422 vertex_index, param_index,
1423 driver_location,
1424 info->output_semantic_name,
1425 info->output_semantic_index,
1426 is_patch);
1427
1428 skip_lds_store = !info->reads_pervertex_outputs;
1429 } else {
1430 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1431 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1432 vertex_index, param_index,
1433 driver_location,
1434 info->output_semantic_name,
1435 info->output_semantic_index,
1436 is_patch);
1437
1438 skip_lds_store = !info->reads_perpatch_outputs;
1439
1440 if (!param_index) {
1441 int name = info->output_semantic_name[driver_location];
1442
1443 /* Always write tess factors into LDS for the TCS epilog. */
1444 if (name == TGSI_SEMANTIC_TESSINNER ||
1445 name == TGSI_SEMANTIC_TESSOUTER) {
1446 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1447 skip_lds_store = !info->reads_tessfactor_outputs &&
1448 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1449 is_tess_factor = true;
1450 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1451 }
1452 }
1453 }
1454
1455 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1456
1457 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1458
1459 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1460 param_index, driver_location,
1461 info->output_semantic_name,
1462 info->output_semantic_index,
1463 is_patch);
1464
1465 for (unsigned chan = 0; chan < 8; chan++) {
1466 if (!(writemask & (1 << chan)))
1467 continue;
1468 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1469
1470 unsigned buffer_store_offset = chan % 4;
1471 if (chan == 4) {
1472 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1473 vertex_index,
1474 param_index,
1475 driver_location + 1,
1476 info->output_semantic_name,
1477 info->output_semantic_index,
1478 is_patch);
1479 }
1480
1481 /* Skip LDS stores if there is no LDS read of this output. */
1482 if (!skip_lds_store)
1483 lshs_lds_store(ctx, chan, dw_addr, value);
1484
1485 value = ac_to_integer(&ctx->ac, value);
1486 values[chan] = value;
1487
1488 if (writemask != 0xF && !is_tess_factor) {
1489 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1490 addr, base,
1491 4 * buffer_store_offset,
1492 ac_glc, false);
1493 }
1494
1495 /* Write tess factors into VGPRs for the epilog. */
1496 if (is_tess_factor &&
1497 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1498 if (!is_tess_inner) {
1499 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1500 ctx->invoc0_tess_factors[chan]);
1501 } else if (chan < 2) {
1502 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1503 ctx->invoc0_tess_factors[4 + chan]);
1504 }
1505 }
1506 }
1507
1508 if (writemask == 0xF && !is_tess_factor) {
1509 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1510 values, 4);
1511 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1512 base, 0, ac_glc, false);
1513 }
1514 }
1515
1516 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1517 unsigned input_index,
1518 unsigned vtx_offset_param,
1519 LLVMTypeRef type,
1520 unsigned swizzle)
1521 {
1522 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1523 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1524 struct si_shader *shader = ctx->shader;
1525 LLVMValueRef vtx_offset, soffset;
1526 struct tgsi_shader_info *info = &shader->selector->info;
1527 unsigned semantic_name = info->input_semantic_name[input_index];
1528 unsigned semantic_index = info->input_semantic_index[input_index];
1529 unsigned param;
1530 LLVMValueRef value;
1531
1532 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1533
1534 /* GFX9 has the ESGS ring in LDS. */
1535 if (ctx->screen->info.chip_class >= GFX9) {
1536 unsigned index = vtx_offset_param;
1537
1538 switch (index / 2) {
1539 case 0:
1540 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1541 index % 2 ? 16 : 0, 16);
1542 break;
1543 case 1:
1544 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1545 index % 2 ? 16 : 0, 16);
1546 break;
1547 case 2:
1548 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1549 index % 2 ? 16 : 0, 16);
1550 break;
1551 default:
1552 assert(0);
1553 return NULL;
1554 }
1555
1556 unsigned offset = param * 4 + swizzle;
1557 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1558 LLVMConstInt(ctx->i32, offset, false), "");
1559
1560 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1561 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1562 if (llvm_type_is_64bit(ctx, type)) {
1563 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1564 &ctx->ac.i32_1, 1, "");
1565 LLVMValueRef values[2] = {
1566 value,
1567 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1568 };
1569 value = ac_build_gather_values(&ctx->ac, values, 2);
1570 }
1571 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1572 }
1573
1574 /* GFX6: input load from the ESGS ring in memory. */
1575 if (swizzle == ~0) {
1576 LLVMValueRef values[TGSI_NUM_CHANNELS];
1577 unsigned chan;
1578 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1579 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1580 type, chan);
1581 }
1582 return ac_build_gather_values(&ctx->ac, values,
1583 TGSI_NUM_CHANNELS);
1584 }
1585
1586 /* Get the vertex offset parameter on GFX6. */
1587 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1588
1589 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1590 LLVMConstInt(ctx->i32, 4, 0), "");
1591
1592 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1593
1594 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1595 vtx_offset, soffset, 0, ac_glc, true, false);
1596 if (llvm_type_is_64bit(ctx, type)) {
1597 LLVMValueRef value2;
1598 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1599
1600 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1601 ctx->i32_0, vtx_offset, soffset,
1602 0, ac_glc, true, false);
1603 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1604 }
1605 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1606 }
1607
1608 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1609 unsigned location,
1610 unsigned driver_location,
1611 unsigned component,
1612 unsigned num_components,
1613 unsigned vertex_index,
1614 unsigned const_index,
1615 LLVMTypeRef type)
1616 {
1617 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1618
1619 LLVMValueRef value[4];
1620 for (unsigned i = 0; i < num_components; i++) {
1621 unsigned offset = i;
1622 if (llvm_type_is_64bit(ctx, type))
1623 offset *= 2;
1624
1625 offset += component;
1626 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1627 vertex_index, type, offset);
1628 }
1629
1630 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1631 }
1632
1633 static LLVMValueRef fetch_input_gs(
1634 struct lp_build_tgsi_context *bld_base,
1635 const struct tgsi_full_src_register *reg,
1636 enum tgsi_opcode_type type,
1637 unsigned swizzle_in)
1638 {
1639 struct si_shader_context *ctx = si_shader_context(bld_base);
1640 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1641 unsigned swizzle = swizzle_in & 0xffff;
1642
1643 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1644 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1645 return si_get_primitive_id(ctx, swizzle);
1646
1647 if (!reg->Register.Dimension)
1648 return NULL;
1649
1650 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1651 reg->Dimension.Index,
1652 tgsi2llvmtype(bld_base, type),
1653 swizzle);
1654 }
1655
1656 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1657 {
1658 switch (interpolate) {
1659 case TGSI_INTERPOLATE_CONSTANT:
1660 return 0;
1661
1662 case TGSI_INTERPOLATE_LINEAR:
1663 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1664 return SI_PARAM_LINEAR_SAMPLE;
1665 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1666 return SI_PARAM_LINEAR_CENTROID;
1667 else
1668 return SI_PARAM_LINEAR_CENTER;
1669 break;
1670 case TGSI_INTERPOLATE_COLOR:
1671 case TGSI_INTERPOLATE_PERSPECTIVE:
1672 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1673 return SI_PARAM_PERSP_SAMPLE;
1674 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1675 return SI_PARAM_PERSP_CENTROID;
1676 else
1677 return SI_PARAM_PERSP_CENTER;
1678 break;
1679 default:
1680 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1681 return -1;
1682 }
1683 }
1684
1685 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1686 unsigned attr_index, unsigned chan,
1687 LLVMValueRef prim_mask,
1688 LLVMValueRef i, LLVMValueRef j)
1689 {
1690 if (i || j) {
1691 return ac_build_fs_interp(&ctx->ac,
1692 LLVMConstInt(ctx->i32, chan, 0),
1693 LLVMConstInt(ctx->i32, attr_index, 0),
1694 prim_mask, i, j);
1695 }
1696 return ac_build_fs_interp_mov(&ctx->ac,
1697 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1698 LLVMConstInt(ctx->i32, chan, 0),
1699 LLVMConstInt(ctx->i32, attr_index, 0),
1700 prim_mask);
1701 }
1702
1703 /**
1704 * Interpolate a fragment shader input.
1705 *
1706 * @param ctx context
1707 * @param input_index index of the input in hardware
1708 * @param semantic_name TGSI_SEMANTIC_*
1709 * @param semantic_index semantic index
1710 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1711 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1712 * @param interp_param interpolation weights (i,j)
1713 * @param prim_mask SI_PARAM_PRIM_MASK
1714 * @param face SI_PARAM_FRONT_FACE
1715 * @param result the return value (4 components)
1716 */
1717 static void interp_fs_input(struct si_shader_context *ctx,
1718 unsigned input_index,
1719 unsigned semantic_name,
1720 unsigned semantic_index,
1721 unsigned num_interp_inputs,
1722 unsigned colors_read_mask,
1723 LLVMValueRef interp_param,
1724 LLVMValueRef prim_mask,
1725 LLVMValueRef face,
1726 LLVMValueRef result[4])
1727 {
1728 LLVMValueRef i = NULL, j = NULL;
1729 unsigned chan;
1730
1731 /* fs.constant returns the param from the middle vertex, so it's not
1732 * really useful for flat shading. It's meant to be used for custom
1733 * interpolation (but the intrinsic can't fetch from the other two
1734 * vertices).
1735 *
1736 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1737 * to do the right thing. The only reason we use fs.constant is that
1738 * fs.interp cannot be used on integers, because they can be equal
1739 * to NaN.
1740 *
1741 * When interp is false we will use fs.constant or for newer llvm,
1742 * amdgcn.interp.mov.
1743 */
1744 bool interp = interp_param != NULL;
1745
1746 if (interp) {
1747 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1748 LLVMVectorType(ctx->f32, 2), "");
1749
1750 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1751 ctx->i32_0, "");
1752 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1753 ctx->i32_1, "");
1754 }
1755
1756 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1757 ctx->shader->key.part.ps.prolog.color_two_side) {
1758 LLVMValueRef is_face_positive;
1759
1760 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1761 * otherwise it's at offset "num_inputs".
1762 */
1763 unsigned back_attr_offset = num_interp_inputs;
1764 if (semantic_index == 1 && colors_read_mask & 0xf)
1765 back_attr_offset += 1;
1766
1767 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1768 face, ctx->i32_0, "");
1769
1770 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1771 LLVMValueRef front, back;
1772
1773 front = si_build_fs_interp(ctx,
1774 input_index, chan,
1775 prim_mask, i, j);
1776 back = si_build_fs_interp(ctx,
1777 back_attr_offset, chan,
1778 prim_mask, i, j);
1779
1780 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1781 is_face_positive,
1782 front,
1783 back,
1784 "");
1785 }
1786 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1787 result[0] = si_build_fs_interp(ctx, input_index,
1788 0, prim_mask, i, j);
1789 result[1] =
1790 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1791 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1792 } else {
1793 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1794 result[chan] = si_build_fs_interp(ctx,
1795 input_index, chan,
1796 prim_mask, i, j);
1797 }
1798 }
1799 }
1800
1801 void si_llvm_load_input_fs(
1802 struct si_shader_context *ctx,
1803 unsigned input_index,
1804 LLVMValueRef out[4])
1805 {
1806 struct si_shader *shader = ctx->shader;
1807 struct tgsi_shader_info *info = &shader->selector->info;
1808 LLVMValueRef main_fn = ctx->main_fn;
1809 LLVMValueRef interp_param = NULL;
1810 int interp_param_idx;
1811 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1812 unsigned semantic_index = info->input_semantic_index[input_index];
1813 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1814 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1815
1816 /* Get colors from input VGPRs (set by the prolog). */
1817 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1818 unsigned colors_read = shader->selector->info.colors_read;
1819 unsigned mask = colors_read >> (semantic_index * 4);
1820 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1821 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1822 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1823
1824 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1825 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1826 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1827 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1828 return;
1829 }
1830
1831 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1832 if (interp_param_idx == -1)
1833 return;
1834 else if (interp_param_idx) {
1835 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1836 }
1837
1838 interp_fs_input(ctx, input_index, semantic_name,
1839 semantic_index, 0, /* this param is unused */
1840 shader->selector->info.colors_read, interp_param,
1841 ctx->abi.prim_mask,
1842 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1843 &out[0]);
1844 }
1845
1846 static void declare_input_fs(
1847 struct si_shader_context *ctx,
1848 unsigned input_index,
1849 const struct tgsi_full_declaration *decl,
1850 LLVMValueRef out[4])
1851 {
1852 si_llvm_load_input_fs(ctx, input_index, out);
1853 }
1854
1855 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1856 {
1857 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1858 }
1859
1860 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1861 {
1862 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1863
1864 /* For non-indexed draws, the base vertex set by the driver
1865 * (for direct draws) or the CP (for indirect draws) is the
1866 * first vertex ID, but GLSL expects 0 to be returned.
1867 */
1868 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1869 ctx->param_vs_state_bits);
1870 LLVMValueRef indexed;
1871
1872 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1873 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1874
1875 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1876 ctx->i32_0, "");
1877 }
1878
1879 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1880 {
1881 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1882
1883 LLVMValueRef values[3];
1884 LLVMValueRef result;
1885 unsigned i;
1886 unsigned *properties = ctx->shader->selector->info.properties;
1887
1888 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1889 unsigned sizes[3] = {
1890 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1891 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1892 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1893 };
1894
1895 for (i = 0; i < 3; ++i)
1896 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1897
1898 result = ac_build_gather_values(&ctx->ac, values, 3);
1899 } else {
1900 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1901 }
1902
1903 return result;
1904 }
1905
1906 /**
1907 * Load a dword from a constant buffer.
1908 */
1909 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1910 LLVMValueRef resource,
1911 LLVMValueRef offset)
1912 {
1913 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1914 0, 0, true, true);
1915 }
1916
1917 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1918 {
1919 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1920 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1921 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1922 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1923
1924 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1925 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1926 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1927
1928 LLVMValueRef pos[4] = {
1929 buffer_load_const(ctx, resource, offset0),
1930 buffer_load_const(ctx, resource, offset1),
1931 LLVMConstReal(ctx->f32, 0),
1932 LLVMConstReal(ctx->f32, 0)
1933 };
1934
1935 return ac_build_gather_values(&ctx->ac, pos, 4);
1936 }
1937
1938 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1939 {
1940 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1941 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1942 }
1943
1944 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1945 {
1946 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1947 LLVMValueRef coord[4] = {
1948 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1949 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1950 ctx->ac.f32_0,
1951 ctx->ac.f32_0
1952 };
1953
1954 /* For triangles, the vector should be (u, v, 1-u-v). */
1955 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1956 PIPE_PRIM_TRIANGLES) {
1957 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1958 LLVMBuildFAdd(ctx->ac.builder,
1959 coord[0], coord[1], ""), "");
1960 }
1961 return ac_build_gather_values(&ctx->ac, coord, 4);
1962 }
1963
1964 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1965 unsigned semantic_name)
1966 {
1967 LLVMValueRef base, addr;
1968
1969 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1970
1971 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1972 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1973 LLVMConstInt(ctx->i32, param, 0));
1974
1975 return buffer_load(&ctx->bld_base, ctx->f32,
1976 ~0, ctx->tess_offchip_ring, base, addr, true);
1977
1978 }
1979
1980 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1981 unsigned varying_id)
1982 {
1983 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1984 unsigned semantic_name;
1985
1986 switch (varying_id) {
1987 case VARYING_SLOT_TESS_LEVEL_INNER:
1988 semantic_name = TGSI_SEMANTIC_TESSINNER;
1989 break;
1990 case VARYING_SLOT_TESS_LEVEL_OUTER:
1991 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1992 break;
1993 default:
1994 unreachable("unknown tess level");
1995 }
1996
1997 return load_tess_level(ctx, semantic_name);
1998
1999 }
2000
2001 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2002 {
2003 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2004 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2005 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2006 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2007 return get_num_tcs_out_vertices(ctx);
2008 else
2009 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2010 }
2011
2012 void si_load_system_value(struct si_shader_context *ctx,
2013 unsigned index,
2014 const struct tgsi_full_declaration *decl)
2015 {
2016 LLVMValueRef value = 0;
2017
2018 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2019
2020 switch (decl->Semantic.Name) {
2021 case TGSI_SEMANTIC_INSTANCEID:
2022 value = ctx->abi.instance_id;
2023 break;
2024
2025 case TGSI_SEMANTIC_VERTEXID:
2026 value = LLVMBuildAdd(ctx->ac.builder,
2027 ctx->abi.vertex_id,
2028 ctx->abi.base_vertex, "");
2029 break;
2030
2031 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2032 /* Unused. Clarify the meaning in indexed vs. non-indexed
2033 * draws if this is ever used again. */
2034 assert(false);
2035 break;
2036
2037 case TGSI_SEMANTIC_BASEVERTEX:
2038 value = get_base_vertex(&ctx->abi);
2039 break;
2040
2041 case TGSI_SEMANTIC_BASEINSTANCE:
2042 value = ctx->abi.start_instance;
2043 break;
2044
2045 case TGSI_SEMANTIC_DRAWID:
2046 value = ctx->abi.draw_id;
2047 break;
2048
2049 case TGSI_SEMANTIC_INVOCATIONID:
2050 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
2051 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2052 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
2053 if (ctx->screen->info.chip_class >= GFX10) {
2054 value = LLVMBuildAnd(ctx->ac.builder,
2055 ctx->abi.gs_invocation_id,
2056 LLVMConstInt(ctx->i32, 127, 0), "");
2057 } else {
2058 value = ctx->abi.gs_invocation_id;
2059 }
2060 } else {
2061 assert(!"INVOCATIONID not implemented");
2062 }
2063 break;
2064
2065 case TGSI_SEMANTIC_POSITION:
2066 {
2067 LLVMValueRef pos[4] = {
2068 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2069 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2070 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2071 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2072 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2073 };
2074 value = ac_build_gather_values(&ctx->ac, pos, 4);
2075 break;
2076 }
2077
2078 case TGSI_SEMANTIC_FACE:
2079 value = ctx->abi.front_face;
2080 break;
2081
2082 case TGSI_SEMANTIC_SAMPLEID:
2083 value = si_get_sample_id(ctx);
2084 break;
2085
2086 case TGSI_SEMANTIC_SAMPLEPOS: {
2087 LLVMValueRef pos[4] = {
2088 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2089 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2090 LLVMConstReal(ctx->f32, 0),
2091 LLVMConstReal(ctx->f32, 0)
2092 };
2093 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2094 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2095 value = ac_build_gather_values(&ctx->ac, pos, 4);
2096 break;
2097 }
2098
2099 case TGSI_SEMANTIC_SAMPLEMASK:
2100 /* This can only occur with the OpenGL Core profile, which
2101 * doesn't support smoothing.
2102 */
2103 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2104 break;
2105
2106 case TGSI_SEMANTIC_TESSCOORD:
2107 value = si_load_tess_coord(&ctx->abi);
2108 break;
2109
2110 case TGSI_SEMANTIC_VERTICESIN:
2111 value = si_load_patch_vertices_in(&ctx->abi);
2112 break;
2113
2114 case TGSI_SEMANTIC_TESSINNER:
2115 case TGSI_SEMANTIC_TESSOUTER:
2116 value = load_tess_level(ctx, decl->Semantic.Name);
2117 break;
2118
2119 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2120 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2121 {
2122 LLVMValueRef buf, slot, val[4];
2123 int i, offset;
2124
2125 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2126 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2127 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2128 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2129
2130 for (i = 0; i < 4; i++)
2131 val[i] = buffer_load_const(ctx, buf,
2132 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2133 value = ac_build_gather_values(&ctx->ac, val, 4);
2134 break;
2135 }
2136
2137 case TGSI_SEMANTIC_PRIMID:
2138 value = si_get_primitive_id(ctx, 0);
2139 break;
2140
2141 case TGSI_SEMANTIC_GRID_SIZE:
2142 value = ctx->abi.num_work_groups;
2143 break;
2144
2145 case TGSI_SEMANTIC_BLOCK_SIZE:
2146 value = get_block_size(&ctx->abi);
2147 break;
2148
2149 case TGSI_SEMANTIC_BLOCK_ID:
2150 {
2151 LLVMValueRef values[3];
2152
2153 for (int i = 0; i < 3; i++) {
2154 values[i] = ctx->i32_0;
2155 if (ctx->abi.workgroup_ids[i]) {
2156 values[i] = ctx->abi.workgroup_ids[i];
2157 }
2158 }
2159 value = ac_build_gather_values(&ctx->ac, values, 3);
2160 break;
2161 }
2162
2163 case TGSI_SEMANTIC_THREAD_ID:
2164 value = ctx->abi.local_invocation_ids;
2165 break;
2166
2167 case TGSI_SEMANTIC_HELPER_INVOCATION:
2168 value = ac_build_load_helper_invocation(&ctx->ac);
2169 break;
2170
2171 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2172 value = LLVMConstInt(ctx->i32, ctx->ac.wave_size, 0);
2173 break;
2174
2175 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2176 value = ac_get_thread_id(&ctx->ac);
2177 break;
2178
2179 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2180 {
2181 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2182 if (ctx->ac.wave_size == 64)
2183 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2184 value = LLVMBuildShl(ctx->ac.builder,
2185 LLVMConstInt(ctx->ac.iN_wavemask, 1, 0), id, "");
2186 if (ctx->ac.wave_size == 32)
2187 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2188 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2189 break;
2190 }
2191
2192 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2193 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2194 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2195 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2196 {
2197 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2198 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2199 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2200 /* All bits set except LSB */
2201 value = LLVMConstInt(ctx->ac.iN_wavemask, -2, 0);
2202 } else {
2203 /* All bits set */
2204 value = LLVMConstInt(ctx->ac.iN_wavemask, -1, 0);
2205 }
2206 if (ctx->ac.wave_size == 64)
2207 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2208 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2209 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2210 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2211 value = LLVMBuildNot(ctx->ac.builder, value, "");
2212 if (ctx->ac.wave_size == 32)
2213 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2214 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2215 break;
2216 }
2217
2218 case TGSI_SEMANTIC_CS_USER_DATA:
2219 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2220 break;
2221
2222 default:
2223 assert(!"unknown system value");
2224 return;
2225 }
2226
2227 ctx->system_values[index] = value;
2228 }
2229
2230 void si_declare_compute_memory(struct si_shader_context *ctx)
2231 {
2232 struct si_shader_selector *sel = ctx->shader->selector;
2233 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2234
2235 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2236 LLVMValueRef var;
2237
2238 assert(!ctx->ac.lds);
2239
2240 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2241 LLVMArrayType(ctx->i8, lds_size),
2242 "compute_lds",
2243 AC_ADDR_SPACE_LDS);
2244 LLVMSetAlignment(var, 64 * 1024);
2245
2246 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2247 }
2248
2249 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2250 const struct tgsi_full_declaration *decl)
2251 {
2252 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2253 assert(decl->Range.First == decl->Range.Last);
2254
2255 si_declare_compute_memory(ctx);
2256 }
2257
2258 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2259 {
2260 LLVMValueRef ptr =
2261 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2262 struct si_shader_selector *sel = ctx->shader->selector;
2263
2264 /* Do the bounds checking with a descriptor, because
2265 * doing computation and manual bounds checking of 64-bit
2266 * addresses generates horrible VALU code with very high
2267 * VGPR usage and very low SIMD occupancy.
2268 */
2269 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2270
2271 LLVMValueRef desc0, desc1;
2272 desc0 = ptr;
2273 desc1 = LLVMConstInt(ctx->i32,
2274 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2275
2276 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2277 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2278 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2279 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2280
2281 if (ctx->screen->info.chip_class >= GFX10)
2282 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2283 S_008F0C_OOB_SELECT(3) |
2284 S_008F0C_RESOURCE_LEVEL(1);
2285 else
2286 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2287 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2288
2289 LLVMValueRef desc_elems[] = {
2290 desc0,
2291 desc1,
2292 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2293 LLVMConstInt(ctx->i32, rsrc3, false)
2294 };
2295
2296 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2297 }
2298
2299 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2300 {
2301 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2302 ctx->param_const_and_shader_buffers);
2303
2304 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2305 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2306 }
2307
2308 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2309 {
2310 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2311 struct si_shader_selector *sel = ctx->shader->selector;
2312
2313 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2314
2315 if (sel->info.const_buffers_declared == 1 &&
2316 sel->info.shader_buffers_declared == 0) {
2317 return load_const_buffer_desc_fast_path(ctx);
2318 }
2319
2320 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2321 index = LLVMBuildAdd(ctx->ac.builder, index,
2322 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2323
2324 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2325 }
2326
2327 static LLVMValueRef
2328 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2329 {
2330 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2331 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2332 ctx->param_const_and_shader_buffers);
2333
2334 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2335 index = LLVMBuildSub(ctx->ac.builder,
2336 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2337 index, "");
2338
2339 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2340 }
2341
2342 static LLVMValueRef fetch_constant(
2343 struct lp_build_tgsi_context *bld_base,
2344 const struct tgsi_full_src_register *reg,
2345 enum tgsi_opcode_type type,
2346 unsigned swizzle_in)
2347 {
2348 struct si_shader_context *ctx = si_shader_context(bld_base);
2349 struct si_shader_selector *sel = ctx->shader->selector;
2350 const struct tgsi_ind_register *ireg = &reg->Indirect;
2351 unsigned buf, idx;
2352 unsigned swizzle = swizzle_in & 0xffff;
2353
2354 LLVMValueRef addr, bufp;
2355
2356 if (swizzle_in == LP_CHAN_ALL) {
2357 unsigned chan;
2358 LLVMValueRef values[4];
2359 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2360 values[chan] = fetch_constant(bld_base, reg, type, chan);
2361
2362 return ac_build_gather_values(&ctx->ac, values, 4);
2363 }
2364
2365 /* Split 64-bit loads. */
2366 if (tgsi_type_is_64bit(type)) {
2367 LLVMValueRef lo, hi;
2368
2369 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2370 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2371 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2372 lo, hi);
2373 }
2374
2375 idx = reg->Register.Index * 4 + swizzle;
2376 if (reg->Register.Indirect) {
2377 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2378 } else {
2379 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2380 }
2381
2382 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2383 if (sel->info.const_buffers_declared == 1 &&
2384 sel->info.shader_buffers_declared == 0) {
2385 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2386 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2387 return bitcast(bld_base, type, result);
2388 }
2389
2390 assert(reg->Register.Dimension);
2391 buf = reg->Dimension.Index;
2392
2393 if (reg->Dimension.Indirect) {
2394 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2395 LLVMValueRef index;
2396 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2397 reg->Dimension.Index,
2398 ctx->num_const_buffers);
2399 index = LLVMBuildAdd(ctx->ac.builder, index,
2400 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2401 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2402 } else
2403 bufp = load_const_buffer_desc(ctx, buf);
2404
2405 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2406 }
2407
2408 /* Initialize arguments for the shader export intrinsic */
2409 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2410 LLVMValueRef *values,
2411 unsigned target,
2412 struct ac_export_args *args)
2413 {
2414 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2415 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2416 unsigned chan;
2417 bool is_int8, is_int10;
2418
2419 /* Default is 0xf. Adjusted below depending on the format. */
2420 args->enabled_channels = 0xf; /* writemask */
2421
2422 /* Specify whether the EXEC mask represents the valid mask */
2423 args->valid_mask = 0;
2424
2425 /* Specify whether this is the last export */
2426 args->done = 0;
2427
2428 /* Specify the target we are exporting */
2429 args->target = target;
2430
2431 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2432 const struct si_shader_key *key = &ctx->shader->key;
2433 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2434 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2435
2436 assert(cbuf >= 0 && cbuf < 8);
2437 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2438 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2439 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2440 }
2441
2442 args->compr = false;
2443 args->out[0] = f32undef;
2444 args->out[1] = f32undef;
2445 args->out[2] = f32undef;
2446 args->out[3] = f32undef;
2447
2448 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2449 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2450 unsigned bits, bool hi) = NULL;
2451
2452 switch (spi_shader_col_format) {
2453 case V_028714_SPI_SHADER_ZERO:
2454 args->enabled_channels = 0; /* writemask */
2455 args->target = V_008DFC_SQ_EXP_NULL;
2456 break;
2457
2458 case V_028714_SPI_SHADER_32_R:
2459 args->enabled_channels = 1; /* writemask */
2460 args->out[0] = values[0];
2461 break;
2462
2463 case V_028714_SPI_SHADER_32_GR:
2464 args->enabled_channels = 0x3; /* writemask */
2465 args->out[0] = values[0];
2466 args->out[1] = values[1];
2467 break;
2468
2469 case V_028714_SPI_SHADER_32_AR:
2470 if (ctx->screen->info.chip_class >= GFX10) {
2471 args->enabled_channels = 0x3; /* writemask */
2472 args->out[0] = values[0];
2473 args->out[1] = values[3];
2474 } else {
2475 args->enabled_channels = 0x9; /* writemask */
2476 args->out[0] = values[0];
2477 args->out[3] = values[3];
2478 }
2479 break;
2480
2481 case V_028714_SPI_SHADER_FP16_ABGR:
2482 packf = ac_build_cvt_pkrtz_f16;
2483 break;
2484
2485 case V_028714_SPI_SHADER_UNORM16_ABGR:
2486 packf = ac_build_cvt_pknorm_u16;
2487 break;
2488
2489 case V_028714_SPI_SHADER_SNORM16_ABGR:
2490 packf = ac_build_cvt_pknorm_i16;
2491 break;
2492
2493 case V_028714_SPI_SHADER_UINT16_ABGR:
2494 packi = ac_build_cvt_pk_u16;
2495 break;
2496
2497 case V_028714_SPI_SHADER_SINT16_ABGR:
2498 packi = ac_build_cvt_pk_i16;
2499 break;
2500
2501 case V_028714_SPI_SHADER_32_ABGR:
2502 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2503 break;
2504 }
2505
2506 /* Pack f16 or norm_i16/u16. */
2507 if (packf) {
2508 for (chan = 0; chan < 2; chan++) {
2509 LLVMValueRef pack_args[2] = {
2510 values[2 * chan],
2511 values[2 * chan + 1]
2512 };
2513 LLVMValueRef packed;
2514
2515 packed = packf(&ctx->ac, pack_args);
2516 args->out[chan] = ac_to_float(&ctx->ac, packed);
2517 }
2518 args->compr = 1; /* COMPR flag */
2519 }
2520 /* Pack i16/u16. */
2521 if (packi) {
2522 for (chan = 0; chan < 2; chan++) {
2523 LLVMValueRef pack_args[2] = {
2524 ac_to_integer(&ctx->ac, values[2 * chan]),
2525 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2526 };
2527 LLVMValueRef packed;
2528
2529 packed = packi(&ctx->ac, pack_args,
2530 is_int8 ? 8 : is_int10 ? 10 : 16,
2531 chan == 1);
2532 args->out[chan] = ac_to_float(&ctx->ac, packed);
2533 }
2534 args->compr = 1; /* COMPR flag */
2535 }
2536 }
2537
2538 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2539 LLVMValueRef alpha)
2540 {
2541 struct si_shader_context *ctx = si_shader_context(bld_base);
2542
2543 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2544 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2545 [PIPE_FUNC_LESS] = LLVMRealOLT,
2546 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2547 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2548 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2549 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2550 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2551 };
2552 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2553 assert(cond);
2554
2555 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2556 SI_PARAM_ALPHA_REF);
2557 LLVMValueRef alpha_pass =
2558 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2559 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2560 } else {
2561 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2562 }
2563 }
2564
2565 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2566 LLVMValueRef alpha,
2567 unsigned samplemask_param)
2568 {
2569 struct si_shader_context *ctx = si_shader_context(bld_base);
2570 LLVMValueRef coverage;
2571
2572 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2573 coverage = LLVMGetParam(ctx->main_fn,
2574 samplemask_param);
2575 coverage = ac_to_integer(&ctx->ac, coverage);
2576
2577 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2578 ctx->i32,
2579 &coverage, 1, AC_FUNC_ATTR_READNONE);
2580
2581 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2582 ctx->f32, "");
2583
2584 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2585 LLVMConstReal(ctx->f32,
2586 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2587
2588 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2589 }
2590
2591 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2592 struct ac_export_args *pos, LLVMValueRef *out_elts)
2593 {
2594 unsigned reg_index;
2595 unsigned chan;
2596 unsigned const_chan;
2597 LLVMValueRef base_elt;
2598 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2599 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2600 SI_VS_CONST_CLIP_PLANES, 0);
2601 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2602
2603 for (reg_index = 0; reg_index < 2; reg_index ++) {
2604 struct ac_export_args *args = &pos[2 + reg_index];
2605
2606 args->out[0] =
2607 args->out[1] =
2608 args->out[2] =
2609 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2610
2611 /* Compute dot products of position and user clip plane vectors */
2612 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2613 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2614 LLVMValueRef addr =
2615 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2616 const_chan) * 4, 0);
2617 base_elt = buffer_load_const(ctx, const_resource,
2618 addr);
2619 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2620 out_elts[const_chan], args->out[chan]);
2621 }
2622 }
2623
2624 args->enabled_channels = 0xf;
2625 args->valid_mask = 0;
2626 args->done = 0;
2627 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2628 args->compr = 0;
2629 }
2630 }
2631
2632 static void si_dump_streamout(struct pipe_stream_output_info *so)
2633 {
2634 unsigned i;
2635
2636 if (so->num_outputs)
2637 fprintf(stderr, "STREAMOUT\n");
2638
2639 for (i = 0; i < so->num_outputs; i++) {
2640 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2641 so->output[i].start_component;
2642 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2643 i, so->output[i].output_buffer,
2644 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2645 so->output[i].register_index,
2646 mask & 1 ? "x" : "",
2647 mask & 2 ? "y" : "",
2648 mask & 4 ? "z" : "",
2649 mask & 8 ? "w" : "");
2650 }
2651 }
2652
2653 void si_emit_streamout_output(struct si_shader_context *ctx,
2654 LLVMValueRef const *so_buffers,
2655 LLVMValueRef const *so_write_offsets,
2656 struct pipe_stream_output *stream_out,
2657 struct si_shader_output_values *shader_out)
2658 {
2659 unsigned buf_idx = stream_out->output_buffer;
2660 unsigned start = stream_out->start_component;
2661 unsigned num_comps = stream_out->num_components;
2662 LLVMValueRef out[4];
2663
2664 assert(num_comps && num_comps <= 4);
2665 if (!num_comps || num_comps > 4)
2666 return;
2667
2668 /* Load the output as int. */
2669 for (int j = 0; j < num_comps; j++) {
2670 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2671
2672 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2673 }
2674
2675 /* Pack the output. */
2676 LLVMValueRef vdata = NULL;
2677
2678 switch (num_comps) {
2679 case 1: /* as i32 */
2680 vdata = out[0];
2681 break;
2682 case 2: /* as v2i32 */
2683 case 3: /* as v3i32 */
2684 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2685 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2686 break;
2687 }
2688 /* as v4i32 (aligned to 4) */
2689 out[3] = LLVMGetUndef(ctx->i32);
2690 /* fall through */
2691 case 4: /* as v4i32 */
2692 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2693 break;
2694 }
2695
2696 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2697 vdata, num_comps,
2698 so_write_offsets[buf_idx],
2699 ctx->i32_0,
2700 stream_out->dst_offset * 4, ac_glc | ac_slc, false);
2701 }
2702
2703 /**
2704 * Write streamout data to buffers for vertex stream @p stream (different
2705 * vertex streams can occur for GS copy shaders).
2706 */
2707 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2708 struct si_shader_output_values *outputs,
2709 unsigned noutput, unsigned stream)
2710 {
2711 struct si_shader_selector *sel = ctx->shader->selector;
2712 struct pipe_stream_output_info *so = &sel->so;
2713 LLVMBuilderRef builder = ctx->ac.builder;
2714 int i;
2715
2716 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2717 LLVMValueRef so_vtx_count =
2718 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2719
2720 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2721
2722 /* can_emit = tid < so_vtx_count; */
2723 LLVMValueRef can_emit =
2724 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2725
2726 /* Emit the streamout code conditionally. This actually avoids
2727 * out-of-bounds buffer access. The hw tells us via the SGPR
2728 * (so_vtx_count) which threads are allowed to emit streamout data. */
2729 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2730 {
2731 /* The buffer offset is computed as follows:
2732 * ByteOffset = streamout_offset[buffer_id]*4 +
2733 * (streamout_write_index + thread_id)*stride[buffer_id] +
2734 * attrib_offset
2735 */
2736
2737 LLVMValueRef so_write_index =
2738 LLVMGetParam(ctx->main_fn,
2739 ctx->param_streamout_write_index);
2740
2741 /* Compute (streamout_write_index + thread_id). */
2742 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2743
2744 /* Load the descriptor and compute the write offset for each
2745 * enabled buffer. */
2746 LLVMValueRef so_write_offset[4] = {};
2747 LLVMValueRef so_buffers[4];
2748 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2749 ctx->param_rw_buffers);
2750
2751 for (i = 0; i < 4; i++) {
2752 if (!so->stride[i])
2753 continue;
2754
2755 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2756 SI_VS_STREAMOUT_BUF0 + i, 0);
2757
2758 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2759
2760 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2761 ctx->param_streamout_offset[i]);
2762 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2763
2764 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2765 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2766 so_offset);
2767 }
2768
2769 /* Write streamout data. */
2770 for (i = 0; i < so->num_outputs; i++) {
2771 unsigned reg = so->output[i].register_index;
2772
2773 if (reg >= noutput)
2774 continue;
2775
2776 if (stream != so->output[i].stream)
2777 continue;
2778
2779 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
2780 &so->output[i], &outputs[reg]);
2781 }
2782 }
2783 ac_build_endif(&ctx->ac, 6501);
2784 }
2785
2786 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2787 LLVMValueRef *values)
2788 {
2789 struct ac_export_args args;
2790
2791 si_llvm_init_export_args(ctx, values,
2792 V_008DFC_SQ_EXP_PARAM + index, &args);
2793 ac_build_export(&ctx->ac, &args);
2794 }
2795
2796 static void si_build_param_exports(struct si_shader_context *ctx,
2797 struct si_shader_output_values *outputs,
2798 unsigned noutput)
2799 {
2800 struct si_shader *shader = ctx->shader;
2801 unsigned param_count = 0;
2802
2803 for (unsigned i = 0; i < noutput; i++) {
2804 unsigned semantic_name = outputs[i].semantic_name;
2805 unsigned semantic_index = outputs[i].semantic_index;
2806
2807 if (outputs[i].vertex_stream[0] != 0 &&
2808 outputs[i].vertex_stream[1] != 0 &&
2809 outputs[i].vertex_stream[2] != 0 &&
2810 outputs[i].vertex_stream[3] != 0)
2811 continue;
2812
2813 switch (semantic_name) {
2814 case TGSI_SEMANTIC_LAYER:
2815 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2816 case TGSI_SEMANTIC_CLIPDIST:
2817 case TGSI_SEMANTIC_COLOR:
2818 case TGSI_SEMANTIC_BCOLOR:
2819 case TGSI_SEMANTIC_PRIMID:
2820 case TGSI_SEMANTIC_FOG:
2821 case TGSI_SEMANTIC_TEXCOORD:
2822 case TGSI_SEMANTIC_GENERIC:
2823 break;
2824 default:
2825 continue;
2826 }
2827
2828 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2829 semantic_index < SI_MAX_IO_GENERIC) &&
2830 shader->key.opt.kill_outputs &
2831 (1ull << si_shader_io_get_unique_index(semantic_name,
2832 semantic_index, true)))
2833 continue;
2834
2835 si_export_param(ctx, param_count, outputs[i].values);
2836
2837 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2838 shader->info.vs_output_param_offset[i] = param_count++;
2839 }
2840
2841 shader->info.nr_param_exports = param_count;
2842 }
2843
2844 /**
2845 * Vertex color clamping.
2846 *
2847 * This uses a state constant loaded in a user data SGPR and
2848 * an IF statement is added that clamps all colors if the constant
2849 * is true.
2850 */
2851 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2852 struct si_shader_output_values *outputs,
2853 unsigned noutput)
2854 {
2855 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2856 bool has_colors = false;
2857
2858 /* Store original colors to alloca variables. */
2859 for (unsigned i = 0; i < noutput; i++) {
2860 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2861 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2862 continue;
2863
2864 for (unsigned j = 0; j < 4; j++) {
2865 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2866 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2867 }
2868 has_colors = true;
2869 }
2870
2871 if (!has_colors)
2872 return;
2873
2874 /* The state is in the first bit of the user SGPR. */
2875 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2876 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2877
2878 ac_build_ifcc(&ctx->ac, cond, 6502);
2879
2880 /* Store clamped colors to alloca variables within the conditional block. */
2881 for (unsigned i = 0; i < noutput; i++) {
2882 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2883 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2884 continue;
2885
2886 for (unsigned j = 0; j < 4; j++) {
2887 LLVMBuildStore(ctx->ac.builder,
2888 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2889 addr[i][j]);
2890 }
2891 }
2892 ac_build_endif(&ctx->ac, 6502);
2893
2894 /* Load clamped colors */
2895 for (unsigned i = 0; i < noutput; i++) {
2896 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2897 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2898 continue;
2899
2900 for (unsigned j = 0; j < 4; j++) {
2901 outputs[i].values[j] =
2902 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2903 }
2904 }
2905 }
2906
2907 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2908 * (position and parameter data only).
2909 */
2910 void si_llvm_export_vs(struct si_shader_context *ctx,
2911 struct si_shader_output_values *outputs,
2912 unsigned noutput)
2913 {
2914 struct si_shader *shader = ctx->shader;
2915 struct ac_export_args pos_args[4] = {};
2916 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2917 unsigned pos_idx;
2918 int i;
2919
2920 si_vertex_color_clamping(ctx, outputs, noutput);
2921
2922 /* Build position exports. */
2923 for (i = 0; i < noutput; i++) {
2924 switch (outputs[i].semantic_name) {
2925 case TGSI_SEMANTIC_POSITION:
2926 si_llvm_init_export_args(ctx, outputs[i].values,
2927 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2928 break;
2929 case TGSI_SEMANTIC_PSIZE:
2930 psize_value = outputs[i].values[0];
2931 break;
2932 case TGSI_SEMANTIC_LAYER:
2933 layer_value = outputs[i].values[0];
2934 break;
2935 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2936 viewport_index_value = outputs[i].values[0];
2937 break;
2938 case TGSI_SEMANTIC_EDGEFLAG:
2939 edgeflag_value = outputs[i].values[0];
2940 break;
2941 case TGSI_SEMANTIC_CLIPDIST:
2942 if (!shader->key.opt.clip_disable) {
2943 unsigned index = 2 + outputs[i].semantic_index;
2944 si_llvm_init_export_args(ctx, outputs[i].values,
2945 V_008DFC_SQ_EXP_POS + index,
2946 &pos_args[index]);
2947 }
2948 break;
2949 case TGSI_SEMANTIC_CLIPVERTEX:
2950 if (!shader->key.opt.clip_disable) {
2951 si_llvm_emit_clipvertex(ctx, pos_args,
2952 outputs[i].values);
2953 }
2954 break;
2955 }
2956 }
2957
2958 /* We need to add the position output manually if it's missing. */
2959 if (!pos_args[0].out[0]) {
2960 pos_args[0].enabled_channels = 0xf; /* writemask */
2961 pos_args[0].valid_mask = 0; /* EXEC mask */
2962 pos_args[0].done = 0; /* last export? */
2963 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2964 pos_args[0].compr = 0; /* COMPR flag */
2965 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2966 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2967 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2968 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2969 }
2970
2971 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2972 if (shader->selector->info.writes_psize ||
2973 shader->selector->pos_writes_edgeflag ||
2974 shader->selector->info.writes_viewport_index ||
2975 shader->selector->info.writes_layer) {
2976 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2977 (shader->selector->pos_writes_edgeflag << 1) |
2978 (shader->selector->info.writes_layer << 2);
2979
2980 pos_args[1].valid_mask = 0; /* EXEC mask */
2981 pos_args[1].done = 0; /* last export? */
2982 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2983 pos_args[1].compr = 0; /* COMPR flag */
2984 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2985 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2986 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2987 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2988
2989 if (shader->selector->info.writes_psize)
2990 pos_args[1].out[0] = psize_value;
2991
2992 if (shader->selector->pos_writes_edgeflag) {
2993 /* The output is a float, but the hw expects an integer
2994 * with the first bit containing the edge flag. */
2995 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2996 edgeflag_value,
2997 ctx->i32, "");
2998 edgeflag_value = ac_build_umin(&ctx->ac,
2999 edgeflag_value,
3000 ctx->i32_1);
3001
3002 /* The LLVM intrinsic expects a float. */
3003 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
3004 }
3005
3006 if (ctx->screen->info.chip_class >= GFX9) {
3007 /* GFX9 has the layer in out.z[10:0] and the viewport
3008 * index in out.z[19:16].
3009 */
3010 if (shader->selector->info.writes_layer)
3011 pos_args[1].out[2] = layer_value;
3012
3013 if (shader->selector->info.writes_viewport_index) {
3014 LLVMValueRef v = viewport_index_value;
3015
3016 v = ac_to_integer(&ctx->ac, v);
3017 v = LLVMBuildShl(ctx->ac.builder, v,
3018 LLVMConstInt(ctx->i32, 16, 0), "");
3019 v = LLVMBuildOr(ctx->ac.builder, v,
3020 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3021 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3022 pos_args[1].enabled_channels |= 1 << 2;
3023 }
3024 } else {
3025 if (shader->selector->info.writes_layer)
3026 pos_args[1].out[2] = layer_value;
3027
3028 if (shader->selector->info.writes_viewport_index) {
3029 pos_args[1].out[3] = viewport_index_value;
3030 pos_args[1].enabled_channels |= 1 << 3;
3031 }
3032 }
3033 }
3034
3035 for (i = 0; i < 4; i++)
3036 if (pos_args[i].out[0])
3037 shader->info.nr_pos_exports++;
3038
3039 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
3040 * Setting valid_mask=1 prevents it and has no other effect.
3041 */
3042 if (ctx->screen->info.family == CHIP_NAVI10 ||
3043 ctx->screen->info.family == CHIP_NAVI12 ||
3044 ctx->screen->info.family == CHIP_NAVI14)
3045 pos_args[0].valid_mask = 1;
3046
3047 pos_idx = 0;
3048 for (i = 0; i < 4; i++) {
3049 if (!pos_args[i].out[0])
3050 continue;
3051
3052 /* Specify the target we are exporting */
3053 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3054
3055 if (pos_idx == shader->info.nr_pos_exports)
3056 /* Specify that this is the last export */
3057 pos_args[i].done = 1;
3058
3059 ac_build_export(&ctx->ac, &pos_args[i]);
3060 }
3061
3062 /* Build parameter exports. */
3063 si_build_param_exports(ctx, outputs, noutput);
3064 }
3065
3066 /**
3067 * Forward all outputs from the vertex shader to the TES. This is only used
3068 * for the fixed function TCS.
3069 */
3070 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3071 {
3072 struct si_shader_context *ctx = si_shader_context(bld_base);
3073 LLVMValueRef invocation_id, buffer, buffer_offset;
3074 LLVMValueRef lds_vertex_stride, lds_base;
3075 uint64_t inputs;
3076
3077 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3078 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3079 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3080
3081 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3082 lds_base = get_tcs_in_current_patch_offset(ctx);
3083 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3084 lds_base);
3085
3086 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3087 while (inputs) {
3088 unsigned i = u_bit_scan64(&inputs);
3089
3090 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3091 LLVMConstInt(ctx->i32, 4 * i, 0),
3092 "");
3093
3094 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3095 get_rel_patch_id(ctx),
3096 invocation_id,
3097 LLVMConstInt(ctx->i32, i, 0));
3098
3099 LLVMValueRef value = lshs_lds_load(bld_base, ctx->ac.i32, ~0, lds_ptr);
3100
3101 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3102 buffer_offset, 0, ac_glc, false);
3103 }
3104 }
3105
3106 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3107 LLVMValueRef rel_patch_id,
3108 LLVMValueRef invocation_id,
3109 LLVMValueRef tcs_out_current_patch_data_offset,
3110 LLVMValueRef invoc0_tf_outer[4],
3111 LLVMValueRef invoc0_tf_inner[2])
3112 {
3113 struct si_shader_context *ctx = si_shader_context(bld_base);
3114 struct si_shader *shader = ctx->shader;
3115 unsigned tess_inner_index, tess_outer_index;
3116 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3117 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3118 unsigned stride, outer_comps, inner_comps, i, offset;
3119
3120 /* Add a barrier before loading tess factors from LDS. */
3121 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3122 si_llvm_emit_barrier(NULL, bld_base, NULL);
3123
3124 /* Do this only for invocation 0, because the tess levels are per-patch,
3125 * not per-vertex.
3126 *
3127 * This can't jump, because invocation 0 executes this. It should
3128 * at least mask out the loads and stores for other invocations.
3129 */
3130 ac_build_ifcc(&ctx->ac,
3131 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3132 invocation_id, ctx->i32_0, ""), 6503);
3133
3134 /* Determine the layout of one tess factor element in the buffer. */
3135 switch (shader->key.part.tcs.epilog.prim_mode) {
3136 case PIPE_PRIM_LINES:
3137 stride = 2; /* 2 dwords, 1 vec2 store */
3138 outer_comps = 2;
3139 inner_comps = 0;
3140 break;
3141 case PIPE_PRIM_TRIANGLES:
3142 stride = 4; /* 4 dwords, 1 vec4 store */
3143 outer_comps = 3;
3144 inner_comps = 1;
3145 break;
3146 case PIPE_PRIM_QUADS:
3147 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3148 outer_comps = 4;
3149 inner_comps = 2;
3150 break;
3151 default:
3152 assert(0);
3153 return;
3154 }
3155
3156 for (i = 0; i < 4; i++) {
3157 inner[i] = LLVMGetUndef(ctx->i32);
3158 outer[i] = LLVMGetUndef(ctx->i32);
3159 }
3160
3161 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3162 /* Tess factors are in VGPRs. */
3163 for (i = 0; i < outer_comps; i++)
3164 outer[i] = out[i] = invoc0_tf_outer[i];
3165 for (i = 0; i < inner_comps; i++)
3166 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3167 } else {
3168 /* Load tess_inner and tess_outer from LDS.
3169 * Any invocation can write them, so we can't get them from a temporary.
3170 */
3171 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3172 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3173
3174 lds_base = tcs_out_current_patch_data_offset;
3175 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3176 LLVMConstInt(ctx->i32,
3177 tess_inner_index * 4, 0), "");
3178 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3179 LLVMConstInt(ctx->i32,
3180 tess_outer_index * 4, 0), "");
3181
3182 for (i = 0; i < outer_comps; i++) {
3183 outer[i] = out[i] =
3184 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3185 }
3186 for (i = 0; i < inner_comps; i++) {
3187 inner[i] = out[outer_comps+i] =
3188 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3189 }
3190 }
3191
3192 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3193 /* For isolines, the hardware expects tess factors in the
3194 * reverse order from what GLSL / TGSI specify.
3195 */
3196 LLVMValueRef tmp = out[0];
3197 out[0] = out[1];
3198 out[1] = tmp;
3199 }
3200
3201 /* Convert the outputs to vectors for stores. */
3202 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3203 vec1 = NULL;
3204
3205 if (stride > 4)
3206 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3207
3208 /* Get the buffer. */
3209 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3210
3211 /* Get the offset. */
3212 tf_base = LLVMGetParam(ctx->main_fn,
3213 ctx->param_tcs_factor_offset);
3214 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3215 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3216
3217 ac_build_ifcc(&ctx->ac,
3218 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3219 rel_patch_id, ctx->i32_0, ""), 6504);
3220
3221 /* Store the dynamic HS control word. */
3222 offset = 0;
3223 if (ctx->screen->info.chip_class <= GFX8) {
3224 ac_build_buffer_store_dword(&ctx->ac, buffer,
3225 LLVMConstInt(ctx->i32, 0x80000000, 0),
3226 1, ctx->i32_0, tf_base,
3227 offset, ac_glc, false);
3228 offset += 4;
3229 }
3230
3231 ac_build_endif(&ctx->ac, 6504);
3232
3233 /* Store the tessellation factors. */
3234 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3235 MIN2(stride, 4), byteoffset, tf_base,
3236 offset, ac_glc, false);
3237 offset += 16;
3238 if (vec1)
3239 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3240 stride - 4, byteoffset, tf_base,
3241 offset, ac_glc, false);
3242
3243 /* Store the tess factors into the offchip buffer if TES reads them. */
3244 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3245 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3246 LLVMValueRef tf_inner_offset;
3247 unsigned param_outer, param_inner;
3248
3249 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3250 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3251
3252 param_outer = si_shader_io_get_unique_index_patch(
3253 TGSI_SEMANTIC_TESSOUTER, 0);
3254 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3255 LLVMConstInt(ctx->i32, param_outer, 0));
3256
3257 unsigned outer_vec_size =
3258 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
3259 outer_comps : util_next_power_of_two(outer_comps);
3260 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
3261
3262 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3263 outer_comps, tf_outer_offset,
3264 base, 0, ac_glc, false);
3265 if (inner_comps) {
3266 param_inner = si_shader_io_get_unique_index_patch(
3267 TGSI_SEMANTIC_TESSINNER, 0);
3268 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3269 LLVMConstInt(ctx->i32, param_inner, 0));
3270
3271 inner_vec = inner_comps == 1 ? inner[0] :
3272 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3273 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3274 inner_comps, tf_inner_offset,
3275 base, 0, ac_glc, false);
3276 }
3277 }
3278
3279 ac_build_endif(&ctx->ac, 6503);
3280 }
3281
3282 static LLVMValueRef
3283 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3284 unsigned param, unsigned return_index)
3285 {
3286 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3287 LLVMGetParam(ctx->main_fn, param),
3288 return_index, "");
3289 }
3290
3291 static LLVMValueRef
3292 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3293 unsigned param, unsigned return_index)
3294 {
3295 LLVMBuilderRef builder = ctx->ac.builder;
3296 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3297
3298 return LLVMBuildInsertValue(builder, ret,
3299 ac_to_float(&ctx->ac, p),
3300 return_index, "");
3301 }
3302
3303 static LLVMValueRef
3304 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3305 unsigned param, unsigned return_index)
3306 {
3307 LLVMBuilderRef builder = ctx->ac.builder;
3308 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, param);
3309 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3310 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3311 }
3312
3313 /* This only writes the tessellation factor levels. */
3314 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3315 unsigned max_outputs,
3316 LLVMValueRef *addrs)
3317 {
3318 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3319 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3320 LLVMBuilderRef builder = ctx->ac.builder;
3321 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3322
3323 si_copy_tcs_inputs(bld_base);
3324
3325 rel_patch_id = get_rel_patch_id(ctx);
3326 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3327 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3328
3329 if (ctx->screen->info.chip_class >= GFX9) {
3330 LLVMBasicBlockRef blocks[2] = {
3331 LLVMGetInsertBlock(builder),
3332 ctx->merged_wrap_if_entry_block
3333 };
3334 LLVMValueRef values[2];
3335
3336 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
3337
3338 values[0] = rel_patch_id;
3339 values[1] = LLVMGetUndef(ctx->i32);
3340 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3341
3342 values[0] = tf_lds_offset;
3343 values[1] = LLVMGetUndef(ctx->i32);
3344 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3345
3346 values[0] = invocation_id;
3347 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3348 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3349 }
3350
3351 /* Return epilog parameters from this function. */
3352 LLVMValueRef ret = ctx->return_value;
3353 unsigned vgpr;
3354
3355 if (ctx->screen->info.chip_class >= GFX9) {
3356 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3357 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3358 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3359 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3360 /* Tess offchip and tess factor offsets are at the beginning. */
3361 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3362 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3363 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3364 } else {
3365 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3366 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3367 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3368 GFX6_SGPR_TCS_OUT_LAYOUT);
3369 /* Tess offchip and tess factor offsets are after user SGPRs. */
3370 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3371 GFX6_TCS_NUM_USER_SGPR);
3372 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3373 GFX6_TCS_NUM_USER_SGPR + 1);
3374 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3375 }
3376
3377 /* VGPRs */
3378 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3379 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3380 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3381
3382 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3383 * the invocation_id output does not alias the tcs_rel_ids input,
3384 * which saves a V_MOV on gfx9.
3385 */
3386 vgpr += 2;
3387
3388 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3389 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3390
3391 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3392 vgpr++; /* skip the tess factor LDS offset */
3393 for (unsigned i = 0; i < 6; i++) {
3394 LLVMValueRef value =
3395 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3396 value = ac_to_float(&ctx->ac, value);
3397 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3398 }
3399 } else {
3400 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3401 }
3402 ctx->return_value = ret;
3403 }
3404
3405 /* Pass TCS inputs from LS to TCS on GFX9. */
3406 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3407 {
3408 LLVMValueRef ret = ctx->return_value;
3409
3410 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3411 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3412 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3413 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3414 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3415 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3416
3417 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3418 8 + SI_SGPR_RW_BUFFERS);
3419 ret = si_insert_input_ptr(ctx, ret,
3420 ctx->param_bindless_samplers_and_images,
3421 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3422
3423 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3424 8 + SI_SGPR_VS_STATE_BITS);
3425
3426 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3427 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3428 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3429 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3430 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3431 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3432
3433 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3434 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3435 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3436 vgpr++, "");
3437 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3438 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3439 vgpr++, "");
3440 ctx->return_value = ret;
3441 }
3442
3443 /* Pass GS inputs from ES to GS on GFX9. */
3444 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3445 {
3446 LLVMBuilderRef builder = ctx->ac.builder;
3447 LLVMValueRef ret = ctx->return_value;
3448
3449 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3450 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3451 if (ctx->shader->key.as_ngg)
3452 ret = LLVMBuildInsertValue(builder, ret, ctx->gs_tg_info, 2, "");
3453 else
3454 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3455 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3456 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3457
3458 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3459 8 + SI_SGPR_RW_BUFFERS);
3460 ret = si_insert_input_ptr(ctx, ret,
3461 ctx->param_bindless_samplers_and_images,
3462 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3463 if (ctx->screen->info.chip_class >= GFX10) {
3464 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits,
3465 8 + SI_SGPR_VS_STATE_BITS);
3466 }
3467
3468 unsigned vgpr;
3469 if (ctx->type == PIPE_SHADER_VERTEX)
3470 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3471 else
3472 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3473
3474 for (unsigned i = 0; i < 5; i++) {
3475 unsigned param = ctx->param_gs_vtx01_offset + i;
3476 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3477 }
3478 ctx->return_value = ret;
3479 }
3480
3481 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3482 unsigned max_outputs,
3483 LLVMValueRef *addrs)
3484 {
3485 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3486 struct si_shader *shader = ctx->shader;
3487 struct tgsi_shader_info *info = &shader->selector->info;
3488 unsigned i, chan;
3489 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3490 ctx->param_rel_auto_id);
3491 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3492 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3493 vertex_dw_stride, "");
3494
3495 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3496 * its inputs from it. */
3497 for (i = 0; i < info->num_outputs; i++) {
3498 unsigned name = info->output_semantic_name[i];
3499 unsigned index = info->output_semantic_index[i];
3500
3501 /* The ARB_shader_viewport_layer_array spec contains the
3502 * following issue:
3503 *
3504 * 2) What happens if gl_ViewportIndex or gl_Layer is
3505 * written in the vertex shader and a geometry shader is
3506 * present?
3507 *
3508 * RESOLVED: The value written by the last vertex processing
3509 * stage is used. If the last vertex processing stage
3510 * (vertex, tessellation evaluation or geometry) does not
3511 * statically assign to gl_ViewportIndex or gl_Layer, index
3512 * or layer zero is assumed.
3513 *
3514 * So writes to those outputs in VS-as-LS are simply ignored.
3515 */
3516 if (name == TGSI_SEMANTIC_LAYER ||
3517 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3518 continue;
3519
3520 int param = si_shader_io_get_unique_index(name, index, false);
3521 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3522 LLVMConstInt(ctx->i32, param * 4, 0), "");
3523
3524 for (chan = 0; chan < 4; chan++) {
3525 if (!(info->output_usagemask[i] & (1 << chan)))
3526 continue;
3527
3528 lshs_lds_store(ctx, chan, dw_addr,
3529 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3530 }
3531 }
3532
3533 if (ctx->screen->info.chip_class >= GFX9)
3534 si_set_ls_return_value_for_tcs(ctx);
3535 }
3536
3537 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3538 unsigned max_outputs,
3539 LLVMValueRef *addrs)
3540 {
3541 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3542 struct si_shader *es = ctx->shader;
3543 struct tgsi_shader_info *info = &es->selector->info;
3544 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3545 ctx->param_es2gs_offset);
3546 LLVMValueRef lds_base = NULL;
3547 unsigned chan;
3548 int i;
3549
3550 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3551 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3552 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3553 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3554 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3555 LLVMBuildMul(ctx->ac.builder, wave_idx,
3556 LLVMConstInt(ctx->i32, ctx->ac.wave_size, false), ""), "");
3557 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3558 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3559 }
3560
3561 for (i = 0; i < info->num_outputs; i++) {
3562 int param;
3563
3564 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3565 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3566 continue;
3567
3568 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3569 info->output_semantic_index[i], false);
3570
3571 for (chan = 0; chan < 4; chan++) {
3572 if (!(info->output_usagemask[i] & (1 << chan)))
3573 continue;
3574
3575 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3576 out_val = ac_to_integer(&ctx->ac, out_val);
3577
3578 /* GFX9 has the ESGS ring in LDS. */
3579 if (ctx->screen->info.chip_class >= GFX9) {
3580 LLVMValueRef idx = LLVMConstInt(ctx->i32, param * 4 + chan, false);
3581 idx = LLVMBuildAdd(ctx->ac.builder, lds_base, idx, "");
3582 ac_build_indexed_store(&ctx->ac, ctx->esgs_ring, idx, out_val);
3583 continue;
3584 }
3585
3586 ac_build_buffer_store_dword(&ctx->ac,
3587 ctx->esgs_ring,
3588 out_val, 1, NULL, soffset,
3589 (4 * param + chan) * 4,
3590 ac_glc | ac_slc, true);
3591 }
3592 }
3593
3594 if (ctx->screen->info.chip_class >= GFX9)
3595 si_set_es_return_value_for_gs(ctx);
3596 }
3597
3598 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3599 {
3600 if (ctx->screen->info.chip_class >= GFX9)
3601 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3602 else
3603 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3604 }
3605
3606 static void emit_gs_epilogue(struct si_shader_context *ctx)
3607 {
3608 if (ctx->shader->key.as_ngg) {
3609 gfx10_ngg_gs_emit_epilogue(ctx);
3610 return;
3611 }
3612
3613 if (ctx->screen->info.chip_class >= GFX10)
3614 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3615
3616 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3617 si_get_gs_wave_id(ctx));
3618
3619 if (ctx->screen->info.chip_class >= GFX9)
3620 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
3621 }
3622
3623 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3624 unsigned max_outputs,
3625 LLVMValueRef *addrs)
3626 {
3627 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3628 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3629
3630 assert(info->num_outputs <= max_outputs);
3631
3632 emit_gs_epilogue(ctx);
3633 }
3634
3635 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3636 {
3637 struct si_shader_context *ctx = si_shader_context(bld_base);
3638 emit_gs_epilogue(ctx);
3639 }
3640
3641 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3642 unsigned max_outputs,
3643 LLVMValueRef *addrs)
3644 {
3645 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3646 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3647 struct si_shader_output_values *outputs = NULL;
3648 int i,j;
3649
3650 assert(!ctx->shader->is_gs_copy_shader);
3651 assert(info->num_outputs <= max_outputs);
3652
3653 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3654
3655 for (i = 0; i < info->num_outputs; i++) {
3656 outputs[i].semantic_name = info->output_semantic_name[i];
3657 outputs[i].semantic_index = info->output_semantic_index[i];
3658
3659 for (j = 0; j < 4; j++) {
3660 outputs[i].values[j] =
3661 LLVMBuildLoad(ctx->ac.builder,
3662 addrs[4 * i + j],
3663 "");
3664 outputs[i].vertex_stream[j] =
3665 (info->output_streams[i] >> (2 * j)) & 3;
3666 }
3667 }
3668
3669 if (ctx->ac.chip_class <= GFX9 &&
3670 ctx->shader->selector->so.num_outputs)
3671 si_llvm_emit_streamout(ctx, outputs, i, 0);
3672
3673 /* Export PrimitiveID. */
3674 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3675 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3676 outputs[i].semantic_index = 0;
3677 outputs[i].values[0] = ac_to_float(&ctx->ac, si_get_primitive_id(ctx, 0));
3678 for (j = 1; j < 4; j++)
3679 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3680
3681 memset(outputs[i].vertex_stream, 0,
3682 sizeof(outputs[i].vertex_stream));
3683 i++;
3684 }
3685
3686 si_llvm_export_vs(ctx, outputs, i);
3687 FREE(outputs);
3688 }
3689
3690 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
3691 unsigned max_outputs,
3692 LLVMValueRef *addrs)
3693 {
3694 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3695 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3696 LLVMValueRef pos[4] = {};
3697
3698 assert(info->num_outputs <= max_outputs);
3699
3700 for (unsigned i = 0; i < info->num_outputs; i++) {
3701 if (info->output_semantic_name[i] != TGSI_SEMANTIC_POSITION)
3702 continue;
3703
3704 for (unsigned chan = 0; chan < 4; chan++)
3705 pos[chan] = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3706 break;
3707 }
3708 assert(pos[0] != NULL);
3709
3710 /* Return the position output. */
3711 LLVMValueRef ret = ctx->return_value;
3712 for (unsigned chan = 0; chan < 4; chan++)
3713 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, pos[chan], chan, "");
3714 ctx->return_value = ret;
3715 }
3716
3717 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3718 {
3719 struct si_shader_context *ctx = si_shader_context(bld_base);
3720
3721 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3722 &ctx->outputs[0][0]);
3723 }
3724
3725 struct si_ps_exports {
3726 unsigned num;
3727 struct ac_export_args args[10];
3728 };
3729
3730 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3731 LLVMValueRef depth, LLVMValueRef stencil,
3732 LLVMValueRef samplemask, struct si_ps_exports *exp)
3733 {
3734 struct si_shader_context *ctx = si_shader_context(bld_base);
3735 struct ac_export_args args;
3736
3737 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3738
3739 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3740 }
3741
3742 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3743 LLVMValueRef *color, unsigned index,
3744 unsigned samplemask_param,
3745 bool is_last, struct si_ps_exports *exp)
3746 {
3747 struct si_shader_context *ctx = si_shader_context(bld_base);
3748 int i;
3749
3750 /* Clamp color */
3751 if (ctx->shader->key.part.ps.epilog.clamp_color)
3752 for (i = 0; i < 4; i++)
3753 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3754
3755 /* Alpha to one */
3756 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3757 color[3] = ctx->ac.f32_1;
3758
3759 /* Alpha test */
3760 if (index == 0 &&
3761 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3762 si_alpha_test(bld_base, color[3]);
3763
3764 /* Line & polygon smoothing */
3765 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3766 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3767 samplemask_param);
3768
3769 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3770 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3771 struct ac_export_args args[8];
3772 int c, last = -1;
3773
3774 /* Get the export arguments, also find out what the last one is. */
3775 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3776 si_llvm_init_export_args(ctx, color,
3777 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3778 if (args[c].enabled_channels)
3779 last = c;
3780 }
3781
3782 /* Emit all exports. */
3783 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3784 if (is_last && last == c) {
3785 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3786 args[c].done = 1; /* DONE bit */
3787 } else if (!args[c].enabled_channels)
3788 continue; /* unnecessary NULL export */
3789
3790 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3791 }
3792 } else {
3793 struct ac_export_args args;
3794
3795 /* Export */
3796 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3797 &args);
3798 if (is_last) {
3799 args.valid_mask = 1; /* whether the EXEC mask is valid */
3800 args.done = 1; /* DONE bit */
3801 } else if (!args.enabled_channels)
3802 return; /* unnecessary NULL export */
3803
3804 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3805 }
3806 }
3807
3808 static void si_emit_ps_exports(struct si_shader_context *ctx,
3809 struct si_ps_exports *exp)
3810 {
3811 for (unsigned i = 0; i < exp->num; i++)
3812 ac_build_export(&ctx->ac, &exp->args[i]);
3813 }
3814
3815 /**
3816 * Return PS outputs in this order:
3817 *
3818 * v[0:3] = color0.xyzw
3819 * v[4:7] = color1.xyzw
3820 * ...
3821 * vN+0 = Depth
3822 * vN+1 = Stencil
3823 * vN+2 = SampleMask
3824 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3825 *
3826 * The alpha-ref SGPR is returned via its original location.
3827 */
3828 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3829 unsigned max_outputs,
3830 LLVMValueRef *addrs)
3831 {
3832 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3833 struct si_shader *shader = ctx->shader;
3834 struct tgsi_shader_info *info = &shader->selector->info;
3835 LLVMBuilderRef builder = ctx->ac.builder;
3836 unsigned i, j, first_vgpr, vgpr;
3837
3838 LLVMValueRef color[8][4] = {};
3839 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3840 LLVMValueRef ret;
3841
3842 if (ctx->postponed_kill)
3843 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3844
3845 /* Read the output values. */
3846 for (i = 0; i < info->num_outputs; i++) {
3847 unsigned semantic_name = info->output_semantic_name[i];
3848 unsigned semantic_index = info->output_semantic_index[i];
3849
3850 switch (semantic_name) {
3851 case TGSI_SEMANTIC_COLOR:
3852 assert(semantic_index < 8);
3853 for (j = 0; j < 4; j++) {
3854 LLVMValueRef ptr = addrs[4 * i + j];
3855 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3856 color[semantic_index][j] = result;
3857 }
3858 break;
3859 case TGSI_SEMANTIC_POSITION:
3860 depth = LLVMBuildLoad(builder,
3861 addrs[4 * i + 2], "");
3862 break;
3863 case TGSI_SEMANTIC_STENCIL:
3864 stencil = LLVMBuildLoad(builder,
3865 addrs[4 * i + 1], "");
3866 break;
3867 case TGSI_SEMANTIC_SAMPLEMASK:
3868 samplemask = LLVMBuildLoad(builder,
3869 addrs[4 * i + 0], "");
3870 break;
3871 default:
3872 fprintf(stderr, "Warning: GFX6 unhandled fs output type:%d\n",
3873 semantic_name);
3874 }
3875 }
3876
3877 /* Fill the return structure. */
3878 ret = ctx->return_value;
3879
3880 /* Set SGPRs. */
3881 ret = LLVMBuildInsertValue(builder, ret,
3882 ac_to_integer(&ctx->ac,
3883 LLVMGetParam(ctx->main_fn,
3884 SI_PARAM_ALPHA_REF)),
3885 SI_SGPR_ALPHA_REF, "");
3886
3887 /* Set VGPRs */
3888 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3889 for (i = 0; i < ARRAY_SIZE(color); i++) {
3890 if (!color[i][0])
3891 continue;
3892
3893 for (j = 0; j < 4; j++)
3894 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3895 }
3896 if (depth)
3897 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3898 if (stencil)
3899 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3900 if (samplemask)
3901 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3902
3903 /* Add the input sample mask for smoothing at the end. */
3904 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3905 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3906 ret = LLVMBuildInsertValue(builder, ret,
3907 LLVMGetParam(ctx->main_fn,
3908 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3909
3910 ctx->return_value = ret;
3911 }
3912
3913 static void membar_emit(
3914 const struct lp_build_tgsi_action *action,
3915 struct lp_build_tgsi_context *bld_base,
3916 struct lp_build_emit_data *emit_data)
3917 {
3918 struct si_shader_context *ctx = si_shader_context(bld_base);
3919 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3920 unsigned flags = LLVMConstIntGetZExtValue(src0);
3921 unsigned wait_flags = 0;
3922
3923 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3924 wait_flags |= AC_WAIT_LGKM | AC_WAIT_VLOAD | AC_WAIT_VSTORE;
3925
3926 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3927 TGSI_MEMBAR_SHADER_BUFFER |
3928 TGSI_MEMBAR_SHADER_IMAGE))
3929 wait_flags |= AC_WAIT_VLOAD | AC_WAIT_VSTORE;
3930
3931 if (flags & TGSI_MEMBAR_SHARED)
3932 wait_flags |= AC_WAIT_LGKM;
3933
3934 ac_build_waitcnt(&ctx->ac, wait_flags);
3935 }
3936
3937 static void clock_emit(
3938 const struct lp_build_tgsi_action *action,
3939 struct lp_build_tgsi_context *bld_base,
3940 struct lp_build_emit_data *emit_data)
3941 {
3942 struct si_shader_context *ctx = si_shader_context(bld_base);
3943 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3944
3945 emit_data->output[0] =
3946 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3947 emit_data->output[1] =
3948 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3949 }
3950
3951 static void si_llvm_emit_ddxy(
3952 const struct lp_build_tgsi_action *action,
3953 struct lp_build_tgsi_context *bld_base,
3954 struct lp_build_emit_data *emit_data)
3955 {
3956 struct si_shader_context *ctx = si_shader_context(bld_base);
3957 unsigned opcode = emit_data->info->opcode;
3958 LLVMValueRef val;
3959 int idx;
3960 unsigned mask;
3961
3962 if (opcode == TGSI_OPCODE_DDX_FINE)
3963 mask = AC_TID_MASK_LEFT;
3964 else if (opcode == TGSI_OPCODE_DDY_FINE)
3965 mask = AC_TID_MASK_TOP;
3966 else
3967 mask = AC_TID_MASK_TOP_LEFT;
3968
3969 /* for DDX we want to next X pixel, DDY next Y pixel. */
3970 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3971
3972 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3973 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3974 emit_data->output[emit_data->chan] = val;
3975 }
3976
3977 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3978 struct lp_build_tgsi_context *bld_base,
3979 struct lp_build_emit_data *emit_data)
3980 {
3981 struct si_shader_context *ctx = si_shader_context(bld_base);
3982 struct si_shader *shader = ctx->shader;
3983 const struct tgsi_shader_info *info = &shader->selector->info;
3984 LLVMValueRef interp_param;
3985 const struct tgsi_full_instruction *inst = emit_data->inst;
3986 const struct tgsi_full_src_register *input = &inst->Src[0];
3987 int input_base, input_array_size;
3988 int chan;
3989 int i;
3990 LLVMValueRef prim_mask = ctx->abi.prim_mask;
3991 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
3992 int interp_param_idx;
3993 unsigned interp;
3994 unsigned location;
3995
3996 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3997 /* offset is in second src, first two channels */
3998 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3999 TGSI_CHAN_X);
4000 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
4001 TGSI_CHAN_Y);
4002 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4003 LLVMValueRef sample_position;
4004 LLVMValueRef sample_id;
4005 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4006
4007 /* fetch sample ID, then fetch its sample position,
4008 * and place into first two channels.
4009 */
4010 sample_id = lp_build_emit_fetch(bld_base,
4011 emit_data->inst, 1, TGSI_CHAN_X);
4012 sample_id = ac_to_integer(&ctx->ac, sample_id);
4013
4014 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4015 * Language 4.50 spec says about interpolateAtSample:
4016 *
4017 * "Returns the value of the input interpolant variable at
4018 * the location of sample number sample. If multisample
4019 * buffers are not available, the input variable will be
4020 * evaluated at the center of the pixel. If sample sample
4021 * does not exist, the position used to interpolate the
4022 * input variable is undefined."
4023 *
4024 * This means that sample_id values outside of the valid are
4025 * in fact valid input, and the usual mechanism for loading the
4026 * sample position doesn't work.
4027 */
4028 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4029 LLVMValueRef center[4] = {
4030 LLVMConstReal(ctx->f32, 0.5),
4031 LLVMConstReal(ctx->f32, 0.5),
4032 ctx->ac.f32_0,
4033 ctx->ac.f32_0,
4034 };
4035
4036 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
4037 } else {
4038 sample_position = load_sample_position(&ctx->abi, sample_id);
4039 }
4040
4041 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4042 ctx->i32_0, "");
4043
4044 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
4045 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4046 ctx->i32_1, "");
4047 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
4048 }
4049
4050 assert(input->Register.File == TGSI_FILE_INPUT);
4051
4052 if (input->Register.Indirect) {
4053 unsigned array_id = input->Indirect.ArrayID;
4054
4055 if (array_id) {
4056 input_base = info->input_array_first[array_id];
4057 input_array_size = info->input_array_last[array_id] - input_base + 1;
4058 } else {
4059 input_base = inst->Src[0].Register.Index;
4060 input_array_size = info->num_inputs - input_base;
4061 }
4062
4063 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4064 1, input->Register.Index - input_base);
4065 } else {
4066 input_base = inst->Src[0].Register.Index;
4067 input_array_size = 1;
4068 array_idx = ctx->i32_0;
4069 }
4070
4071 interp = shader->selector->info.input_interpolate[input_base];
4072
4073 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4074 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4075 location = TGSI_INTERPOLATE_LOC_CENTER;
4076 else
4077 location = TGSI_INTERPOLATE_LOC_CENTROID;
4078
4079 interp_param_idx = lookup_interp_param_index(interp, location);
4080 if (interp_param_idx == -1)
4081 return;
4082 else if (interp_param_idx)
4083 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4084 else
4085 interp_param = NULL;
4086
4087 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4088 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4089 LLVMValueRef ij_out[2];
4090 LLVMValueRef ddxy_out = ac_build_ddxy_interp(&ctx->ac, interp_param);
4091
4092 /*
4093 * take the I then J parameters, and the DDX/Y for it, and
4094 * calculate the IJ inputs for the interpolator.
4095 * temp1 = ddx * offset/sample.x + I;
4096 * interp_param.I = ddy * offset/sample.y + temp1;
4097 * temp1 = ddx * offset/sample.x + J;
4098 * interp_param.J = ddy * offset/sample.y + temp1;
4099 */
4100 for (i = 0; i < 2; i++) {
4101 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4102 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4103 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4104 ddxy_out, ix_ll, "");
4105 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4106 ddxy_out, iy_ll, "");
4107 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4108 interp_param, ix_ll, "");
4109 LLVMValueRef temp;
4110
4111 interp_el = ac_to_float(&ctx->ac, interp_el);
4112
4113 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4114 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4115 }
4116 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4117 }
4118
4119 if (interp_param)
4120 interp_param = ac_to_float(&ctx->ac, interp_param);
4121
4122 for (chan = 0; chan < 4; chan++) {
4123 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4124 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4125
4126 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4127 LLVMValueRef v, i = NULL, j = NULL;
4128
4129 if (interp_param) {
4130 i = LLVMBuildExtractElement(
4131 ctx->ac.builder, interp_param, ctx->i32_0, "");
4132 j = LLVMBuildExtractElement(
4133 ctx->ac.builder, interp_param, ctx->i32_1, "");
4134 }
4135 v = si_build_fs_interp(ctx, input_base + idx, schan,
4136 prim_mask, i, j);
4137
4138 gather = LLVMBuildInsertElement(ctx->ac.builder,
4139 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4140 }
4141
4142 emit_data->output[chan] = LLVMBuildExtractElement(
4143 ctx->ac.builder, gather, array_idx, "");
4144 }
4145 }
4146
4147 static void vote_all_emit(
4148 const struct lp_build_tgsi_action *action,
4149 struct lp_build_tgsi_context *bld_base,
4150 struct lp_build_emit_data *emit_data)
4151 {
4152 struct si_shader_context *ctx = si_shader_context(bld_base);
4153
4154 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4155 emit_data->output[emit_data->chan] =
4156 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4157 }
4158
4159 static void vote_any_emit(
4160 const struct lp_build_tgsi_action *action,
4161 struct lp_build_tgsi_context *bld_base,
4162 struct lp_build_emit_data *emit_data)
4163 {
4164 struct si_shader_context *ctx = si_shader_context(bld_base);
4165
4166 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4167 emit_data->output[emit_data->chan] =
4168 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4169 }
4170
4171 static void vote_eq_emit(
4172 const struct lp_build_tgsi_action *action,
4173 struct lp_build_tgsi_context *bld_base,
4174 struct lp_build_emit_data *emit_data)
4175 {
4176 struct si_shader_context *ctx = si_shader_context(bld_base);
4177
4178 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4179 emit_data->output[emit_data->chan] =
4180 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4181 }
4182
4183 static void ballot_emit(
4184 const struct lp_build_tgsi_action *action,
4185 struct lp_build_tgsi_context *bld_base,
4186 struct lp_build_emit_data *emit_data)
4187 {
4188 struct si_shader_context *ctx = si_shader_context(bld_base);
4189 LLVMBuilderRef builder = ctx->ac.builder;
4190 LLVMValueRef tmp;
4191
4192 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4193 tmp = ac_build_ballot(&ctx->ac, tmp);
4194
4195 emit_data->output[0] = LLVMBuildTrunc(builder, tmp, ctx->i32, "");
4196
4197 if (ctx->ac.wave_size == 32) {
4198 emit_data->output[1] = ctx->i32_0;
4199 } else {
4200 tmp = LLVMBuildLShr(builder, tmp, LLVMConstInt(ctx->i64, 32, 0), "");
4201 emit_data->output[1] = LLVMBuildTrunc(builder, tmp, ctx->i32, "");
4202 }
4203 }
4204
4205 static void read_lane_emit(
4206 const struct lp_build_tgsi_action *action,
4207 struct lp_build_tgsi_context *bld_base,
4208 struct lp_build_emit_data *emit_data)
4209 {
4210 struct si_shader_context *ctx = si_shader_context(bld_base);
4211
4212 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4213 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4214 0, emit_data->src_chan);
4215
4216 /* Always read the source invocation (= lane) from the X channel. */
4217 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4218 1, TGSI_CHAN_X);
4219 emit_data->arg_count = 2;
4220 }
4221
4222 /* We currently have no other way to prevent LLVM from lifting the icmp
4223 * calls to a dominating basic block.
4224 */
4225 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4226
4227 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4228 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4229
4230 emit_data->output[emit_data->chan] =
4231 ac_build_intrinsic(&ctx->ac, action->intr_name,
4232 ctx->i32, emit_data->args, emit_data->arg_count,
4233 AC_FUNC_ATTR_READNONE |
4234 AC_FUNC_ATTR_CONVERGENT);
4235 }
4236
4237 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4238 struct lp_build_emit_data *emit_data)
4239 {
4240 struct si_shader_context *ctx = si_shader_context(bld_base);
4241 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4242 LLVMValueRef imm;
4243 unsigned stream;
4244
4245 assert(src0.File == TGSI_FILE_IMMEDIATE);
4246
4247 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4248 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4249 return stream;
4250 }
4251
4252 /* Emit one vertex from the geometry shader */
4253 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4254 unsigned stream,
4255 LLVMValueRef *addrs)
4256 {
4257 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4258
4259 if (ctx->shader->key.as_ngg) {
4260 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
4261 return;
4262 }
4263
4264 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4265 struct si_shader *shader = ctx->shader;
4266 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4267 ctx->param_gs2vs_offset);
4268 LLVMValueRef gs_next_vertex;
4269 LLVMValueRef can_emit;
4270 unsigned chan, offset;
4271 int i;
4272
4273 /* Write vertex attribute values to GSVS ring */
4274 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4275 ctx->gs_next_vertex[stream],
4276 "");
4277
4278 /* If this thread has already emitted the declared maximum number of
4279 * vertices, skip the write: excessive vertex emissions are not
4280 * supposed to have any effect.
4281 *
4282 * If the shader has no writes to memory, kill it instead. This skips
4283 * further memory loads and may allow LLVM to skip to the end
4284 * altogether.
4285 */
4286 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4287 LLVMConstInt(ctx->i32,
4288 shader->selector->gs_max_out_vertices, 0), "");
4289
4290 bool use_kill = !info->writes_memory;
4291 if (use_kill) {
4292 ac_build_kill_if_false(&ctx->ac, can_emit);
4293 } else {
4294 ac_build_ifcc(&ctx->ac, can_emit, 6505);
4295 }
4296
4297 offset = 0;
4298 for (i = 0; i < info->num_outputs; i++) {
4299 for (chan = 0; chan < 4; chan++) {
4300 if (!(info->output_usagemask[i] & (1 << chan)) ||
4301 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4302 continue;
4303
4304 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4305 LLVMValueRef voffset =
4306 LLVMConstInt(ctx->i32, offset *
4307 shader->selector->gs_max_out_vertices, 0);
4308 offset++;
4309
4310 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4311 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4312 LLVMConstInt(ctx->i32, 4, 0), "");
4313
4314 out_val = ac_to_integer(&ctx->ac, out_val);
4315
4316 ac_build_buffer_store_dword(&ctx->ac,
4317 ctx->gsvs_ring[stream],
4318 out_val, 1,
4319 voffset, soffset, 0,
4320 ac_glc | ac_slc, true);
4321 }
4322 }
4323
4324 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4325 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4326
4327 /* Signal vertex emission if vertex data was written. */
4328 if (offset) {
4329 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4330 si_get_gs_wave_id(ctx));
4331 }
4332
4333 if (!use_kill)
4334 ac_build_endif(&ctx->ac, 6505);
4335 }
4336
4337 /* Emit one vertex from the geometry shader */
4338 static void si_tgsi_emit_vertex(
4339 const struct lp_build_tgsi_action *action,
4340 struct lp_build_tgsi_context *bld_base,
4341 struct lp_build_emit_data *emit_data)
4342 {
4343 struct si_shader_context *ctx = si_shader_context(bld_base);
4344 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4345
4346 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4347 }
4348
4349 /* Cut one primitive from the geometry shader */
4350 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4351 unsigned stream)
4352 {
4353 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4354
4355 if (ctx->shader->key.as_ngg) {
4356 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
4357 return;
4358 }
4359
4360 /* Signal primitive cut */
4361 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4362 si_get_gs_wave_id(ctx));
4363 }
4364
4365 /* Cut one primitive from the geometry shader */
4366 static void si_tgsi_emit_primitive(
4367 const struct lp_build_tgsi_action *action,
4368 struct lp_build_tgsi_context *bld_base,
4369 struct lp_build_emit_data *emit_data)
4370 {
4371 struct si_shader_context *ctx = si_shader_context(bld_base);
4372
4373 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4374 }
4375
4376 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4377 struct lp_build_tgsi_context *bld_base,
4378 struct lp_build_emit_data *emit_data)
4379 {
4380 struct si_shader_context *ctx = si_shader_context(bld_base);
4381
4382 /* GFX6 only (thanks to a hw bug workaround):
4383 * The real barrier instruction isn’t needed, because an entire patch
4384 * always fits into a single wave.
4385 */
4386 if (ctx->screen->info.chip_class == GFX6 &&
4387 ctx->type == PIPE_SHADER_TESS_CTRL) {
4388 ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM | AC_WAIT_VLOAD | AC_WAIT_VSTORE);
4389 return;
4390 }
4391
4392 ac_build_s_barrier(&ctx->ac);
4393 }
4394
4395 void si_create_function(struct si_shader_context *ctx,
4396 const char *name,
4397 LLVMTypeRef *returns, unsigned num_returns,
4398 struct si_function_info *fninfo,
4399 unsigned max_workgroup_size)
4400 {
4401 int i;
4402
4403 si_llvm_create_func(ctx, name, returns, num_returns,
4404 fninfo->types, fninfo->num_params);
4405 ctx->return_value = LLVMGetUndef(ctx->return_type);
4406
4407 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4408 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4409
4410 /* The combination of:
4411 * - noalias
4412 * - dereferenceable
4413 * - invariant.load
4414 * allows the optimization passes to move loads and reduces
4415 * SGPR spilling significantly.
4416 */
4417 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4418 AC_FUNC_ATTR_INREG);
4419
4420 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4421 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4422 AC_FUNC_ATTR_NOALIAS);
4423 ac_add_attr_dereferenceable(P, UINT64_MAX);
4424 }
4425 }
4426
4427 for (i = 0; i < fninfo->num_params; ++i) {
4428 if (fninfo->assign[i])
4429 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4430 }
4431
4432 if (ctx->screen->info.address32_hi) {
4433 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4434 "amdgpu-32bit-address-high-bits",
4435 ctx->screen->info.address32_hi);
4436 }
4437
4438 ac_llvm_set_workgroup_size(ctx->main_fn, max_workgroup_size);
4439
4440 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4441 "no-signed-zeros-fp-math",
4442 "true");
4443
4444 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4445 /* These were copied from some LLVM test. */
4446 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4447 "less-precise-fpmad",
4448 "true");
4449 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4450 "no-infs-fp-math",
4451 "true");
4452 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4453 "no-nans-fp-math",
4454 "true");
4455 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4456 "unsafe-fp-math",
4457 "true");
4458 }
4459 }
4460
4461 static void declare_streamout_params(struct si_shader_context *ctx,
4462 struct pipe_stream_output_info *so,
4463 struct si_function_info *fninfo)
4464 {
4465 if (ctx->ac.chip_class >= GFX10)
4466 return;
4467
4468 /* Streamout SGPRs. */
4469 if (so->num_outputs) {
4470 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4471 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4472 else
4473 ctx->param_streamout_config = fninfo->num_params - 1;
4474
4475 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4476 }
4477 /* A streamout buffer offset is loaded if the stride is non-zero. */
4478 for (int i = 0; i < 4; i++) {
4479 if (!so->stride[i])
4480 continue;
4481
4482 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4483 }
4484 }
4485
4486 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4487 {
4488 switch (shader->selector->type) {
4489 case PIPE_SHADER_VERTEX:
4490 case PIPE_SHADER_TESS_EVAL:
4491 return shader->key.as_ngg ? 128 : 0;
4492
4493 case PIPE_SHADER_TESS_CTRL:
4494 /* Return this so that LLVM doesn't remove s_barrier
4495 * instructions on chips where we use s_barrier. */
4496 return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 0;
4497
4498 case PIPE_SHADER_GEOMETRY:
4499 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 0;
4500
4501 case PIPE_SHADER_COMPUTE:
4502 break; /* see below */
4503
4504 default:
4505 return 0;
4506 }
4507
4508 const unsigned *properties = shader->selector->info.properties;
4509 unsigned max_work_group_size =
4510 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4511 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4512 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4513
4514 if (!max_work_group_size) {
4515 /* This is a variable group size compute shader,
4516 * compile it for the maximum possible group size.
4517 */
4518 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4519 }
4520 return max_work_group_size;
4521 }
4522
4523 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4524 struct si_function_info *fninfo,
4525 bool assign_params)
4526 {
4527 LLVMTypeRef const_shader_buf_type;
4528
4529 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4530 ctx->shader->selector->info.shader_buffers_declared == 0)
4531 const_shader_buf_type = ctx->f32;
4532 else
4533 const_shader_buf_type = ctx->v4i32;
4534
4535 unsigned const_and_shader_buffers =
4536 add_arg(fninfo, ARG_SGPR,
4537 ac_array_in_const32_addr_space(const_shader_buf_type));
4538
4539 if (assign_params)
4540 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4541 }
4542
4543 static void declare_samplers_and_images(struct si_shader_context *ctx,
4544 struct si_function_info *fninfo,
4545 bool assign_params)
4546 {
4547 unsigned samplers_and_images =
4548 add_arg(fninfo, ARG_SGPR,
4549 ac_array_in_const32_addr_space(ctx->v8i32));
4550
4551 if (assign_params)
4552 ctx->param_samplers_and_images = samplers_and_images;
4553 }
4554
4555 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4556 struct si_function_info *fninfo,
4557 bool assign_params)
4558 {
4559 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4560 declare_samplers_and_images(ctx, fninfo, assign_params);
4561 }
4562
4563 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4564 struct si_function_info *fninfo)
4565 {
4566 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4567 ac_array_in_const32_addr_space(ctx->v4i32));
4568 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4569 ac_array_in_const32_addr_space(ctx->v8i32));
4570 }
4571
4572 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4573 struct si_function_info *fninfo)
4574 {
4575 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4576 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4577 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4578 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4579 }
4580
4581 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4582 struct si_function_info *fninfo,
4583 unsigned *num_prolog_vgprs)
4584 {
4585 struct si_shader *shader = ctx->shader;
4586
4587 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4588 if (shader->key.as_ls) {
4589 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4590 if (ctx->screen->info.chip_class >= GFX10) {
4591 add_arg(fninfo, ARG_VGPR, ctx->i32); /* user VGPR */
4592 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4593 } else {
4594 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4595 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4596 }
4597 } else if (ctx->screen->info.chip_class == GFX10 &&
4598 !shader->is_gs_copy_shader) {
4599 add_arg(fninfo, ARG_VGPR, ctx->i32); /* user vgpr */
4600 add_arg(fninfo, ARG_VGPR, ctx->i32); /* user vgpr */
4601 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4602 } else {
4603 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4604 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4605 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4606 }
4607
4608 if (!shader->is_gs_copy_shader) {
4609 /* Vertex load indices. */
4610 ctx->param_vertex_index0 = fninfo->num_params;
4611 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4612 add_arg(fninfo, ARG_VGPR, ctx->i32);
4613 *num_prolog_vgprs += shader->selector->info.num_inputs;
4614 }
4615 }
4616
4617 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
4618 struct si_function_info *fninfo,
4619 unsigned vs_blit_property)
4620 {
4621 ctx->param_vs_blit_inputs = fninfo->num_params;
4622 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4623 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4624 add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
4625
4626 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4627 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
4628 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
4629 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
4630 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
4631 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4632 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4633 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4634 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4635 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4636 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4637 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4638 }
4639 }
4640
4641 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4642 struct si_function_info *fninfo)
4643 {
4644 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4645 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4646 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4647 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4648 }
4649
4650 enum {
4651 /* Convenient merged shader definitions. */
4652 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4653 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4654 };
4655
4656 static void create_function(struct si_shader_context *ctx)
4657 {
4658 struct si_shader *shader = ctx->shader;
4659 struct si_function_info fninfo;
4660 LLVMTypeRef returns[16+32*4];
4661 unsigned i, num_return_sgprs;
4662 unsigned num_returns = 0;
4663 unsigned num_prolog_vgprs = 0;
4664 unsigned type = ctx->type;
4665 unsigned vs_blit_property =
4666 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4667
4668 si_init_function_info(&fninfo);
4669
4670 /* Set MERGED shaders. */
4671 if (ctx->screen->info.chip_class >= GFX9) {
4672 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4673 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4674 else if (shader->key.as_es || shader->key.as_ngg || type == PIPE_SHADER_GEOMETRY)
4675 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4676 }
4677
4678 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4679
4680 switch (type) {
4681 case PIPE_SHADER_VERTEX:
4682 declare_global_desc_pointers(ctx, &fninfo);
4683
4684 if (vs_blit_property) {
4685 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4686
4687 /* VGPRs */
4688 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4689 break;
4690 }
4691
4692 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4693 declare_vs_specific_input_sgprs(ctx, &fninfo);
4694 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4695 ac_array_in_const32_addr_space(ctx->v4i32));
4696
4697 if (shader->key.as_es) {
4698 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4699 } else if (shader->key.as_ls) {
4700 /* no extra parameters */
4701 } else {
4702 if (shader->is_gs_copy_shader) {
4703 fninfo.num_params = ctx->param_vs_state_bits + 1;
4704 fninfo.num_sgpr_params = fninfo.num_params;
4705 }
4706
4707 /* The locations of the other parameters are assigned dynamically. */
4708 declare_streamout_params(ctx, &shader->selector->so,
4709 &fninfo);
4710 }
4711
4712 /* VGPRs */
4713 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4714
4715 /* Return values */
4716 if (shader->key.opt.vs_as_prim_discard_cs) {
4717 for (i = 0; i < 4; i++)
4718 returns[num_returns++] = ctx->f32; /* VGPRs */
4719 }
4720 break;
4721
4722 case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */
4723 declare_global_desc_pointers(ctx, &fninfo);
4724 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4725 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4726 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4727 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4728 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4729 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4730 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4731
4732 /* VGPRs */
4733 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4734 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4735
4736 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4737 * placed after the user SGPRs.
4738 */
4739 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4740 returns[num_returns++] = ctx->i32; /* SGPRs */
4741 for (i = 0; i < 11; i++)
4742 returns[num_returns++] = ctx->f32; /* VGPRs */
4743 break;
4744
4745 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4746 /* Merged stages have 8 system SGPRs at the beginning. */
4747 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4748 declare_per_stage_desc_pointers(ctx, &fninfo,
4749 ctx->type == PIPE_SHADER_TESS_CTRL);
4750 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4751 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4752 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4753 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4754 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4755 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4756
4757 declare_global_desc_pointers(ctx, &fninfo);
4758 declare_per_stage_desc_pointers(ctx, &fninfo,
4759 ctx->type == PIPE_SHADER_VERTEX);
4760 declare_vs_specific_input_sgprs(ctx, &fninfo);
4761
4762 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4763 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4764 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4765 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4766 ac_array_in_const32_addr_space(ctx->v4i32));
4767
4768 /* VGPRs (first TCS, then VS) */
4769 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4770 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4771
4772 if (ctx->type == PIPE_SHADER_VERTEX) {
4773 declare_vs_input_vgprs(ctx, &fninfo,
4774 &num_prolog_vgprs);
4775
4776 /* LS return values are inputs to the TCS main shader part. */
4777 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4778 returns[num_returns++] = ctx->i32; /* SGPRs */
4779 for (i = 0; i < 2; i++)
4780 returns[num_returns++] = ctx->f32; /* VGPRs */
4781 } else {
4782 /* TCS return values are inputs to the TCS epilog.
4783 *
4784 * param_tcs_offchip_offset, param_tcs_factor_offset,
4785 * param_tcs_offchip_layout, and param_rw_buffers
4786 * should be passed to the epilog.
4787 */
4788 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4789 returns[num_returns++] = ctx->i32; /* SGPRs */
4790 for (i = 0; i < 11; i++)
4791 returns[num_returns++] = ctx->f32; /* VGPRs */
4792 }
4793 break;
4794
4795 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4796 /* Merged stages have 8 system SGPRs at the beginning. */
4797 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4798 declare_per_stage_desc_pointers(ctx, &fninfo,
4799 ctx->type == PIPE_SHADER_GEOMETRY);
4800
4801 if (ctx->shader->key.as_ngg)
4802 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->gs_tg_info);
4803 else
4804 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4805
4806 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4807 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4808 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4809 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4810 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4811
4812 declare_global_desc_pointers(ctx, &fninfo);
4813 if (ctx->type != PIPE_SHADER_VERTEX || !vs_blit_property) {
4814 declare_per_stage_desc_pointers(ctx, &fninfo,
4815 (ctx->type == PIPE_SHADER_VERTEX ||
4816 ctx->type == PIPE_SHADER_TESS_EVAL));
4817 }
4818
4819 if (ctx->type == PIPE_SHADER_VERTEX) {
4820 if (vs_blit_property)
4821 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4822 else
4823 declare_vs_specific_input_sgprs(ctx, &fninfo);
4824 } else {
4825 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4826 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4827 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4828 /* Declare as many input SGPRs as the VS has. */
4829 }
4830
4831 if (ctx->type == PIPE_SHADER_VERTEX) {
4832 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4833 ac_array_in_const32_addr_space(ctx->v4i32));
4834 }
4835
4836 /* VGPRs (first GS, then VS/TES) */
4837 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4838 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4839 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4840 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4841 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4842
4843 if (ctx->type == PIPE_SHADER_VERTEX) {
4844 declare_vs_input_vgprs(ctx, &fninfo,
4845 &num_prolog_vgprs);
4846 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4847 declare_tes_input_vgprs(ctx, &fninfo);
4848 }
4849
4850 if (ctx->shader->key.as_es &&
4851 (ctx->type == PIPE_SHADER_VERTEX ||
4852 ctx->type == PIPE_SHADER_TESS_EVAL)) {
4853 unsigned num_user_sgprs;
4854
4855 if (ctx->type == PIPE_SHADER_VERTEX)
4856 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4857 else
4858 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4859
4860 /* ES return values are inputs to GS. */
4861 for (i = 0; i < 8 + num_user_sgprs; i++)
4862 returns[num_returns++] = ctx->i32; /* SGPRs */
4863 for (i = 0; i < 5; i++)
4864 returns[num_returns++] = ctx->f32; /* VGPRs */
4865 }
4866 break;
4867
4868 case PIPE_SHADER_TESS_EVAL:
4869 declare_global_desc_pointers(ctx, &fninfo);
4870 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4871 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4872 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4873 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4874
4875 if (shader->key.as_es) {
4876 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4877 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4878 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4879 } else {
4880 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4881 declare_streamout_params(ctx, &shader->selector->so,
4882 &fninfo);
4883 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4884 }
4885
4886 /* VGPRs */
4887 declare_tes_input_vgprs(ctx, &fninfo);
4888 break;
4889
4890 case PIPE_SHADER_GEOMETRY:
4891 declare_global_desc_pointers(ctx, &fninfo);
4892 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4893 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4894 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4895
4896 /* VGPRs */
4897 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4898 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4899 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4900 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4901 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4902 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4903 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4904 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4905 break;
4906
4907 case PIPE_SHADER_FRAGMENT:
4908 declare_global_desc_pointers(ctx, &fninfo);
4909 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4910 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4911 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4912 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4913
4914 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4915 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4916 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4917 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4918 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4919 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4920 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4921 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4922 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4923 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4924 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4925 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4926 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4927 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4928 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4929 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4930 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4931 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4932 shader->info.face_vgpr_index = 20;
4933 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4934 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4935 shader->info.ancillary_vgpr_index = 21;
4936 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4937 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4938 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4939
4940 /* Color inputs from the prolog. */
4941 if (shader->selector->info.colors_read) {
4942 unsigned num_color_elements =
4943 util_bitcount(shader->selector->info.colors_read);
4944
4945 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4946 for (i = 0; i < num_color_elements; i++)
4947 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4948
4949 num_prolog_vgprs += num_color_elements;
4950 }
4951
4952 /* Outputs for the epilog. */
4953 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4954 num_returns =
4955 num_return_sgprs +
4956 util_bitcount(shader->selector->info.colors_written) * 4 +
4957 shader->selector->info.writes_z +
4958 shader->selector->info.writes_stencil +
4959 shader->selector->info.writes_samplemask +
4960 1 /* SampleMaskIn */;
4961
4962 num_returns = MAX2(num_returns,
4963 num_return_sgprs +
4964 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4965
4966 for (i = 0; i < num_return_sgprs; i++)
4967 returns[i] = ctx->i32;
4968 for (; i < num_returns; i++)
4969 returns[i] = ctx->f32;
4970 break;
4971
4972 case PIPE_SHADER_COMPUTE:
4973 declare_global_desc_pointers(ctx, &fninfo);
4974 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4975 if (shader->selector->info.uses_grid_size)
4976 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4977 if (shader->selector->info.uses_block_size &&
4978 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4979 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4980
4981 unsigned cs_user_data_dwords =
4982 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4983 if (cs_user_data_dwords) {
4984 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4985 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4986 }
4987
4988 for (i = 0; i < 3; i++) {
4989 ctx->abi.workgroup_ids[i] = NULL;
4990 if (shader->selector->info.uses_block_id[i])
4991 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4992 }
4993
4994 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4995 break;
4996 default:
4997 assert(0 && "unimplemented shader");
4998 return;
4999 }
5000
5001 si_create_function(ctx, "main", returns, num_returns, &fninfo,
5002 si_get_max_workgroup_size(shader));
5003
5004 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5005 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
5006 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
5007 "InitialPSInputAddr",
5008 S_0286D0_PERSP_SAMPLE_ENA(1) |
5009 S_0286D0_PERSP_CENTER_ENA(1) |
5010 S_0286D0_PERSP_CENTROID_ENA(1) |
5011 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5012 S_0286D0_LINEAR_CENTER_ENA(1) |
5013 S_0286D0_LINEAR_CENTROID_ENA(1) |
5014 S_0286D0_FRONT_FACE_ENA(1) |
5015 S_0286D0_ANCILLARY_ENA(1) |
5016 S_0286D0_POS_FIXED_PT_ENA(1));
5017 }
5018
5019 shader->info.num_input_sgprs = 0;
5020 shader->info.num_input_vgprs = 0;
5021
5022 for (i = 0; i < fninfo.num_sgpr_params; ++i)
5023 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
5024
5025 for (; i < fninfo.num_params; ++i)
5026 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
5027
5028 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5029 shader->info.num_input_vgprs -= num_prolog_vgprs;
5030
5031 if (shader->key.as_ls || ctx->type == PIPE_SHADER_TESS_CTRL) {
5032 if (USE_LDS_SYMBOLS && HAVE_LLVM >= 0x0900) {
5033 /* The LSHS size is not known until draw time, so we append it
5034 * at the end of whatever LDS use there may be in the rest of
5035 * the shader (currently none, unless LLVM decides to do its
5036 * own LDS-based lowering).
5037 */
5038 ctx->ac.lds = LLVMAddGlobalInAddressSpace(
5039 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
5040 "__lds_end", AC_ADDR_SPACE_LDS);
5041 LLVMSetAlignment(ctx->ac.lds, 256);
5042 } else {
5043 ac_declare_lds_as_pointer(&ctx->ac);
5044 }
5045 }
5046 }
5047
5048 /* Ensure that the esgs ring is declared.
5049 *
5050 * We declare it with 64KB alignment as a hint that the
5051 * pointer value will always be 0.
5052 */
5053 static void declare_esgs_ring(struct si_shader_context *ctx)
5054 {
5055 if (ctx->esgs_ring)
5056 return;
5057
5058 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
5059
5060 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
5061 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
5062 "esgs_ring",
5063 AC_ADDR_SPACE_LDS);
5064 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
5065 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
5066 }
5067
5068 /**
5069 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5070 * for later use.
5071 */
5072 static void preload_ring_buffers(struct si_shader_context *ctx)
5073 {
5074 LLVMBuilderRef builder = ctx->ac.builder;
5075
5076 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5077 ctx->param_rw_buffers);
5078
5079 if (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY) {
5080 if (ctx->screen->info.chip_class <= GFX8) {
5081 unsigned ring =
5082 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5083 : SI_ES_RING_ESGS;
5084 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5085
5086 ctx->esgs_ring =
5087 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5088 } else {
5089 if (USE_LDS_SYMBOLS && HAVE_LLVM >= 0x0900) {
5090 /* Declare the ESGS ring as an explicit LDS symbol. */
5091 declare_esgs_ring(ctx);
5092 } else {
5093 ac_declare_lds_as_pointer(&ctx->ac);
5094 ctx->esgs_ring = ctx->ac.lds;
5095 }
5096 }
5097 }
5098
5099 if (ctx->shader->is_gs_copy_shader) {
5100 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5101
5102 ctx->gsvs_ring[0] =
5103 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5104 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5105 const struct si_shader_selector *sel = ctx->shader->selector;
5106 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5107 LLVMValueRef base_ring;
5108
5109 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5110
5111 /* The conceptual layout of the GSVS ring is
5112 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5113 * but the real memory layout is swizzled across
5114 * threads:
5115 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5116 * t16v0c0 ..
5117 * Override the buffer descriptor accordingly.
5118 */
5119 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5120 uint64_t stream_offset = 0;
5121
5122 for (unsigned stream = 0; stream < 4; ++stream) {
5123 unsigned num_components;
5124 unsigned stride;
5125 unsigned num_records;
5126 LLVMValueRef ring, tmp;
5127
5128 num_components = sel->info.num_stream_output_components[stream];
5129 if (!num_components)
5130 continue;
5131
5132 stride = 4 * num_components * sel->gs_max_out_vertices;
5133
5134 /* Limit on the stride field for <= GFX7. */
5135 assert(stride < (1 << 14));
5136
5137 num_records = ctx->ac.wave_size;
5138
5139 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5140 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5141 tmp = LLVMBuildAdd(builder, tmp,
5142 LLVMConstInt(ctx->i64,
5143 stream_offset, 0), "");
5144 stream_offset += stride * ctx->ac.wave_size;
5145
5146 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5147 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5148 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5149 tmp = LLVMBuildOr(builder, tmp,
5150 LLVMConstInt(ctx->i32,
5151 S_008F04_STRIDE(stride) |
5152 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5153 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5154 ring = LLVMBuildInsertElement(builder, ring,
5155 LLVMConstInt(ctx->i32, num_records, 0),
5156 LLVMConstInt(ctx->i32, 2, 0), "");
5157
5158 uint32_t rsrc3 =
5159 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5160 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5161 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5162 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5163 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5164 S_008F0C_ADD_TID_ENABLE(1);
5165
5166 if (ctx->ac.chip_class >= GFX10) {
5167 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5168 S_008F0C_OOB_SELECT(2) |
5169 S_008F0C_RESOURCE_LEVEL(1);
5170 } else {
5171 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5173 S_008F0C_ELEMENT_SIZE(1); /* element_size = 4 (bytes) */
5174 }
5175
5176 ring = LLVMBuildInsertElement(builder, ring,
5177 LLVMConstInt(ctx->i32, rsrc3, false),
5178 LLVMConstInt(ctx->i32, 3, 0), "");
5179
5180 ctx->gsvs_ring[stream] = ring;
5181 }
5182 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5183 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5184 }
5185 }
5186
5187 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5188 LLVMValueRef param_rw_buffers,
5189 unsigned param_pos_fixed_pt)
5190 {
5191 LLVMBuilderRef builder = ctx->ac.builder;
5192 LLVMValueRef slot, desc, offset, row, bit, address[2];
5193
5194 /* Use the fixed-point gl_FragCoord input.
5195 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5196 * per coordinate to get the repeating effect.
5197 */
5198 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5199 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5200
5201 /* Load the buffer descriptor. */
5202 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5203 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5204
5205 /* The stipple pattern is 32x32, each row has 32 bits. */
5206 offset = LLVMBuildMul(builder, address[1],
5207 LLVMConstInt(ctx->i32, 4, 0), "");
5208 row = buffer_load_const(ctx, desc, offset);
5209 row = ac_to_integer(&ctx->ac, row);
5210 bit = LLVMBuildLShr(builder, row, address[0], "");
5211 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5212 ac_build_kill_if_false(&ctx->ac, bit);
5213 }
5214
5215 /* For the UMR disassembler. */
5216 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5217 #define DEBUGGER_NUM_MARKERS 5
5218
5219 static bool si_shader_binary_open(struct si_screen *screen,
5220 struct si_shader *shader,
5221 struct ac_rtld_binary *rtld)
5222 {
5223 const struct si_shader_selector *sel = shader->selector;
5224 const char *part_elfs[5];
5225 size_t part_sizes[5];
5226 unsigned num_parts = 0;
5227
5228 #define add_part(shader_or_part) \
5229 if (shader_or_part) { \
5230 part_elfs[num_parts] = (shader_or_part)->binary.elf_buffer; \
5231 part_sizes[num_parts] = (shader_or_part)->binary.elf_size; \
5232 num_parts++; \
5233 }
5234
5235 add_part(shader->prolog);
5236 add_part(shader->previous_stage);
5237 add_part(shader->prolog2);
5238 add_part(shader);
5239 add_part(shader->epilog);
5240
5241 #undef add_part
5242
5243 struct ac_rtld_symbol lds_symbols[2];
5244 unsigned num_lds_symbols = 0;
5245
5246 if (sel && screen->info.chip_class >= GFX9 && !shader->is_gs_copy_shader &&
5247 (sel->type == PIPE_SHADER_GEOMETRY || shader->key.as_ngg)) {
5248 /* We add this symbol even on LLVM <= 8 to ensure that
5249 * shader->config.lds_size is set correctly below.
5250 */
5251 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
5252 sym->name = "esgs_ring";
5253 sym->size = shader->gs_info.esgs_ring_size;
5254 sym->align = 64 * 1024;
5255 }
5256
5257 if (shader->key.as_ngg && sel->type == PIPE_SHADER_GEOMETRY) {
5258 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
5259 sym->name = "ngg_emit";
5260 sym->size = shader->ngg.ngg_emit_size * 4;
5261 sym->align = 4;
5262 }
5263
5264 bool ok = ac_rtld_open(rtld, (struct ac_rtld_open_info){
5265 .info = &screen->info,
5266 .options = {
5267 .halt_at_entry = screen->options.halt_shaders,
5268 },
5269 .shader_type = tgsi_processor_to_shader_stage(sel->type),
5270 .wave_size = si_get_shader_wave_size(shader),
5271 .num_parts = num_parts,
5272 .elf_ptrs = part_elfs,
5273 .elf_sizes = part_sizes,
5274 .num_shared_lds_symbols = num_lds_symbols,
5275 .shared_lds_symbols = lds_symbols });
5276
5277 if (rtld->lds_size > 0) {
5278 unsigned alloc_granularity = screen->info.chip_class >= GFX7 ? 512 : 256;
5279 shader->config.lds_size =
5280 align(rtld->lds_size, alloc_granularity) / alloc_granularity;
5281 }
5282
5283 return ok;
5284 }
5285
5286 static unsigned si_get_shader_binary_size(struct si_screen *screen, struct si_shader *shader)
5287 {
5288 struct ac_rtld_binary rtld;
5289 si_shader_binary_open(screen, shader, &rtld);
5290 return rtld.rx_size;
5291 }
5292
5293 static bool si_get_external_symbol(void *data, const char *name, uint64_t *value)
5294 {
5295 uint64_t *scratch_va = data;
5296
5297 if (!strcmp(scratch_rsrc_dword0_symbol, name)) {
5298 *value = (uint32_t)*scratch_va;
5299 return true;
5300 }
5301 if (!strcmp(scratch_rsrc_dword1_symbol, name)) {
5302 /* Enable scratch coalescing. */
5303 *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32) |
5304 S_008F04_SWIZZLE_ENABLE(1);
5305 if (HAVE_LLVM < 0x0800) {
5306 /* Old LLVM created an R_ABS32_HI relocation for
5307 * this symbol. */
5308 *value <<= 32;
5309 }
5310 return true;
5311 }
5312
5313 return false;
5314 }
5315
5316 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
5317 uint64_t scratch_va)
5318 {
5319 struct ac_rtld_binary binary;
5320 if (!si_shader_binary_open(sscreen, shader, &binary))
5321 return false;
5322
5323 si_resource_reference(&shader->bo, NULL);
5324 shader->bo = si_aligned_buffer_create(&sscreen->b,
5325 sscreen->cpdma_prefetch_writes_memory ?
5326 0 : SI_RESOURCE_FLAG_READ_ONLY,
5327 PIPE_USAGE_IMMUTABLE,
5328 align(binary.rx_size, SI_CPDMA_ALIGNMENT),
5329 256);
5330 if (!shader->bo)
5331 return false;
5332
5333 /* Upload. */
5334 struct ac_rtld_upload_info u = {};
5335 u.binary = &binary;
5336 u.get_external_symbol = si_get_external_symbol;
5337 u.cb_data = &scratch_va;
5338 u.rx_va = shader->bo->gpu_address;
5339 u.rx_ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5340 PIPE_TRANSFER_READ_WRITE |
5341 PIPE_TRANSFER_UNSYNCHRONIZED |
5342 RADEON_TRANSFER_TEMPORARY);
5343 if (!u.rx_ptr)
5344 return false;
5345
5346 bool ok = ac_rtld_upload(&u);
5347
5348 sscreen->ws->buffer_unmap(shader->bo->buf);
5349 ac_rtld_close(&binary);
5350
5351 return ok;
5352 }
5353
5354 static void si_shader_dump_disassembly(struct si_screen *screen,
5355 const struct si_shader_binary *binary,
5356 enum pipe_shader_type shader_type,
5357 unsigned wave_size,
5358 struct pipe_debug_callback *debug,
5359 const char *name, FILE *file)
5360 {
5361 struct ac_rtld_binary rtld_binary;
5362
5363 if (!ac_rtld_open(&rtld_binary, (struct ac_rtld_open_info){
5364 .info = &screen->info,
5365 .shader_type = tgsi_processor_to_shader_stage(shader_type),
5366 .wave_size = wave_size,
5367 .num_parts = 1,
5368 .elf_ptrs = &binary->elf_buffer,
5369 .elf_sizes = &binary->elf_size }))
5370 return;
5371
5372 const char *disasm;
5373 size_t nbytes;
5374
5375 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm, &nbytes))
5376 goto out;
5377
5378 if (nbytes > INT_MAX)
5379 goto out;
5380
5381 if (debug && debug->debug_message) {
5382 /* Very long debug messages are cut off, so send the
5383 * disassembly one line at a time. This causes more
5384 * overhead, but on the plus side it simplifies
5385 * parsing of resulting logs.
5386 */
5387 pipe_debug_message(debug, SHADER_INFO,
5388 "Shader Disassembly Begin");
5389
5390 uint64_t line = 0;
5391 while (line < nbytes) {
5392 int count = nbytes - line;
5393 const char *nl = memchr(disasm + line, '\n', nbytes - line);
5394 if (nl)
5395 count = nl - (disasm + line);
5396
5397 if (count) {
5398 pipe_debug_message(debug, SHADER_INFO,
5399 "%.*s", count, disasm + line);
5400 }
5401
5402 line += count + 1;
5403 }
5404
5405 pipe_debug_message(debug, SHADER_INFO,
5406 "Shader Disassembly End");
5407 }
5408
5409 if (file) {
5410 fprintf(file, "Shader %s disassembly:\n", name);
5411 fprintf(file, "%*s", (int)nbytes, disasm);
5412 }
5413
5414 out:
5415 ac_rtld_close(&rtld_binary);
5416 }
5417
5418 static void si_calculate_max_simd_waves(struct si_shader *shader)
5419 {
5420 struct si_screen *sscreen = shader->selector->screen;
5421 struct ac_shader_config *conf = &shader->config;
5422 unsigned num_inputs = shader->selector->info.num_inputs;
5423 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256;
5424 unsigned lds_per_wave = 0;
5425 unsigned max_simd_waves;
5426
5427 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5428
5429 /* Compute LDS usage for PS. */
5430 switch (shader->selector->type) {
5431 case PIPE_SHADER_FRAGMENT:
5432 /* The minimum usage per wave is (num_inputs * 48). The maximum
5433 * usage is (num_inputs * 48 * 16).
5434 * We can get anything in between and it varies between waves.
5435 *
5436 * The 48 bytes per input for a single primitive is equal to
5437 * 4 bytes/component * 4 components/input * 3 points.
5438 *
5439 * Other stages don't know the size at compile time or don't
5440 * allocate LDS per wave, but instead they do it per thread group.
5441 */
5442 lds_per_wave = conf->lds_size * lds_increment +
5443 align(num_inputs * 48, lds_increment);
5444 break;
5445 case PIPE_SHADER_COMPUTE:
5446 if (shader->selector) {
5447 unsigned max_workgroup_size =
5448 si_get_max_workgroup_size(shader);
5449 lds_per_wave = (conf->lds_size * lds_increment) /
5450 DIV_ROUND_UP(max_workgroup_size,
5451 sscreen->compute_wave_size);
5452 }
5453 break;
5454 default:;
5455 }
5456
5457 /* Compute the per-SIMD wave counts. */
5458 if (conf->num_sgprs) {
5459 max_simd_waves =
5460 MIN2(max_simd_waves,
5461 ac_get_num_physical_sgprs(sscreen->info.chip_class) / conf->num_sgprs);
5462 }
5463
5464 if (conf->num_vgprs)
5465 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5466
5467 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5468 * 16KB makes some SIMDs unoccupied). */
5469 if (lds_per_wave)
5470 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5471
5472 shader->info.max_simd_waves = max_simd_waves;
5473 }
5474
5475 void si_shader_dump_stats_for_shader_db(struct si_screen *screen,
5476 struct si_shader *shader,
5477 struct pipe_debug_callback *debug)
5478 {
5479 const struct ac_shader_config *conf = &shader->config;
5480
5481 if (screen->options.debug_disassembly)
5482 si_shader_dump_disassembly(screen, &shader->binary,
5483 shader->selector->type,
5484 si_get_shader_wave_size(shader),
5485 debug, "main", NULL);
5486
5487 pipe_debug_message(debug, SHADER_INFO,
5488 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5489 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5490 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5491 conf->num_sgprs, conf->num_vgprs,
5492 si_get_shader_binary_size(screen, shader),
5493 conf->lds_size, conf->scratch_bytes_per_wave,
5494 shader->info.max_simd_waves, conf->spilled_sgprs,
5495 conf->spilled_vgprs, shader->info.private_mem_vgprs);
5496 }
5497
5498 static void si_shader_dump_stats(struct si_screen *sscreen,
5499 struct si_shader *shader,
5500 FILE *file,
5501 bool check_debug_option)
5502 {
5503 const struct ac_shader_config *conf = &shader->config;
5504
5505 if (!check_debug_option ||
5506 si_can_dump_shader(sscreen, shader->selector->type)) {
5507 if (shader->selector->type == PIPE_SHADER_FRAGMENT) {
5508 fprintf(file, "*** SHADER CONFIG ***\n"
5509 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5510 "SPI_PS_INPUT_ENA = 0x%04x\n",
5511 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5512 }
5513
5514 fprintf(file, "*** SHADER STATS ***\n"
5515 "SGPRS: %d\n"
5516 "VGPRS: %d\n"
5517 "Spilled SGPRs: %d\n"
5518 "Spilled VGPRs: %d\n"
5519 "Private memory VGPRs: %d\n"
5520 "Code Size: %d bytes\n"
5521 "LDS: %d blocks\n"
5522 "Scratch: %d bytes per wave\n"
5523 "Max Waves: %d\n"
5524 "********************\n\n\n",
5525 conf->num_sgprs, conf->num_vgprs,
5526 conf->spilled_sgprs, conf->spilled_vgprs,
5527 shader->info.private_mem_vgprs,
5528 si_get_shader_binary_size(sscreen, shader),
5529 conf->lds_size, conf->scratch_bytes_per_wave,
5530 shader->info.max_simd_waves);
5531 }
5532 }
5533
5534 const char *si_get_shader_name(const struct si_shader *shader)
5535 {
5536 switch (shader->selector->type) {
5537 case PIPE_SHADER_VERTEX:
5538 if (shader->key.as_es)
5539 return "Vertex Shader as ES";
5540 else if (shader->key.as_ls)
5541 return "Vertex Shader as LS";
5542 else if (shader->key.opt.vs_as_prim_discard_cs)
5543 return "Vertex Shader as Primitive Discard CS";
5544 else if (shader->key.as_ngg)
5545 return "Vertex Shader as ESGS";
5546 else
5547 return "Vertex Shader as VS";
5548 case PIPE_SHADER_TESS_CTRL:
5549 return "Tessellation Control Shader";
5550 case PIPE_SHADER_TESS_EVAL:
5551 if (shader->key.as_es)
5552 return "Tessellation Evaluation Shader as ES";
5553 else if (shader->key.as_ngg)
5554 return "Tessellation Evaluation Shader as ESGS";
5555 else
5556 return "Tessellation Evaluation Shader as VS";
5557 case PIPE_SHADER_GEOMETRY:
5558 if (shader->is_gs_copy_shader)
5559 return "GS Copy Shader as VS";
5560 else
5561 return "Geometry Shader";
5562 case PIPE_SHADER_FRAGMENT:
5563 return "Pixel Shader";
5564 case PIPE_SHADER_COMPUTE:
5565 return "Compute Shader";
5566 default:
5567 return "Unknown Shader";
5568 }
5569 }
5570
5571 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5572 struct pipe_debug_callback *debug,
5573 FILE *file, bool check_debug_option)
5574 {
5575 enum pipe_shader_type shader_type = shader->selector->type;
5576
5577 if (!check_debug_option ||
5578 si_can_dump_shader(sscreen, shader_type))
5579 si_dump_shader_key(shader, file);
5580
5581 if (!check_debug_option && shader->binary.llvm_ir_string) {
5582 if (shader->previous_stage &&
5583 shader->previous_stage->binary.llvm_ir_string) {
5584 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5585 si_get_shader_name(shader));
5586 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5587 }
5588
5589 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5590 si_get_shader_name(shader));
5591 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5592 }
5593
5594 if (!check_debug_option ||
5595 (si_can_dump_shader(sscreen, shader_type) &&
5596 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5597 unsigned wave_size = si_get_shader_wave_size(shader);
5598
5599 fprintf(file, "\n%s:\n", si_get_shader_name(shader));
5600
5601 if (shader->prolog)
5602 si_shader_dump_disassembly(sscreen, &shader->prolog->binary,
5603 shader_type, wave_size, debug, "prolog", file);
5604 if (shader->previous_stage)
5605 si_shader_dump_disassembly(sscreen, &shader->previous_stage->binary,
5606 shader_type, wave_size, debug, "previous stage", file);
5607 if (shader->prolog2)
5608 si_shader_dump_disassembly(sscreen, &shader->prolog2->binary,
5609 shader_type, wave_size, debug, "prolog2", file);
5610
5611 si_shader_dump_disassembly(sscreen, &shader->binary, shader_type,
5612 wave_size, debug, "main", file);
5613
5614 if (shader->epilog)
5615 si_shader_dump_disassembly(sscreen, &shader->epilog->binary,
5616 shader_type, wave_size, debug, "epilog", file);
5617 fprintf(file, "\n");
5618 }
5619
5620 si_shader_dump_stats(sscreen, shader, file, check_debug_option);
5621 }
5622
5623 static int si_compile_llvm(struct si_screen *sscreen,
5624 struct si_shader_binary *binary,
5625 struct ac_shader_config *conf,
5626 struct ac_llvm_compiler *compiler,
5627 LLVMModuleRef mod,
5628 struct pipe_debug_callback *debug,
5629 enum pipe_shader_type shader_type,
5630 unsigned wave_size,
5631 const char *name,
5632 bool less_optimized)
5633 {
5634 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5635
5636 if (si_can_dump_shader(sscreen, shader_type)) {
5637 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5638
5639 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5640 fprintf(stderr, "%s LLVM IR:\n\n", name);
5641 ac_dump_module(mod);
5642 fprintf(stderr, "\n");
5643 }
5644 }
5645
5646 if (sscreen->record_llvm_ir) {
5647 char *ir = LLVMPrintModuleToString(mod);
5648 binary->llvm_ir_string = strdup(ir);
5649 LLVMDisposeMessage(ir);
5650 }
5651
5652 if (!si_replace_shader(count, binary)) {
5653 unsigned r = si_llvm_compile(mod, binary, compiler, debug,
5654 less_optimized, wave_size);
5655 if (r)
5656 return r;
5657 }
5658
5659 struct ac_rtld_binary rtld;
5660 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
5661 .info = &sscreen->info,
5662 .shader_type = tgsi_processor_to_shader_stage(shader_type),
5663 .wave_size = wave_size,
5664 .num_parts = 1,
5665 .elf_ptrs = &binary->elf_buffer,
5666 .elf_sizes = &binary->elf_size }))
5667 return -1;
5668
5669 bool ok = ac_rtld_read_config(&rtld, conf);
5670 ac_rtld_close(&rtld);
5671 if (!ok)
5672 return -1;
5673
5674 /* Enable 64-bit and 16-bit denormals, because there is no performance
5675 * cost.
5676 *
5677 * If denormals are enabled, all floating-point output modifiers are
5678 * ignored.
5679 *
5680 * Don't enable denormals for 32-bit floats, because:
5681 * - Floating-point output modifiers would be ignored by the hw.
5682 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5683 * have to stop using those.
5684 * - GFX6 & GFX7 would be very slow.
5685 */
5686 conf->float_mode |= V_00B028_FP_64_DENORMS;
5687
5688 return 0;
5689 }
5690
5691 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5692 {
5693 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5694 LLVMBuildRetVoid(ctx->ac.builder);
5695 else
5696 LLVMBuildRet(ctx->ac.builder, ret);
5697 }
5698
5699 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5700 struct si_shader *
5701 si_generate_gs_copy_shader(struct si_screen *sscreen,
5702 struct ac_llvm_compiler *compiler,
5703 struct si_shader_selector *gs_selector,
5704 struct pipe_debug_callback *debug)
5705 {
5706 struct si_shader_context ctx;
5707 struct si_shader *shader;
5708 LLVMBuilderRef builder;
5709 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5710 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5711 int i;
5712
5713
5714 shader = CALLOC_STRUCT(si_shader);
5715 if (!shader)
5716 return NULL;
5717
5718 /* We can leave the fence as permanently signaled because the GS copy
5719 * shader only becomes visible globally after it has been compiled. */
5720 util_queue_fence_init(&shader->ready);
5721
5722 shader->selector = gs_selector;
5723 shader->is_gs_copy_shader = true;
5724
5725 si_init_shader_ctx(&ctx, sscreen, compiler,
5726 si_get_wave_size(sscreen, PIPE_SHADER_VERTEX, false, false));
5727 ctx.shader = shader;
5728 ctx.type = PIPE_SHADER_VERTEX;
5729
5730 builder = ctx.ac.builder;
5731
5732 create_function(&ctx);
5733 preload_ring_buffers(&ctx);
5734
5735 LLVMValueRef voffset =
5736 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5737 LLVMConstInt(ctx.i32, 4, 0), "");
5738
5739 /* Fetch the vertex stream ID.*/
5740 LLVMValueRef stream_id;
5741
5742 if (ctx.ac.chip_class <= GFX9 && gs_selector->so.num_outputs)
5743 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5744 else
5745 stream_id = ctx.i32_0;
5746
5747 /* Fill in output information. */
5748 for (i = 0; i < gsinfo->num_outputs; ++i) {
5749 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5750 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5751
5752 for (int chan = 0; chan < 4; chan++) {
5753 outputs[i].vertex_stream[chan] =
5754 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5755 }
5756 }
5757
5758 LLVMBasicBlockRef end_bb;
5759 LLVMValueRef switch_inst;
5760
5761 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5762 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5763
5764 for (int stream = 0; stream < 4; stream++) {
5765 LLVMBasicBlockRef bb;
5766 unsigned offset;
5767
5768 if (!gsinfo->num_stream_output_components[stream])
5769 continue;
5770
5771 if (stream > 0 && !gs_selector->so.num_outputs)
5772 continue;
5773
5774 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5775 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5776 LLVMPositionBuilderAtEnd(builder, bb);
5777
5778 /* Fetch vertex data from GSVS ring */
5779 offset = 0;
5780 for (i = 0; i < gsinfo->num_outputs; ++i) {
5781 for (unsigned chan = 0; chan < 4; chan++) {
5782 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5783 outputs[i].vertex_stream[chan] != stream) {
5784 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5785 continue;
5786 }
5787
5788 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5789 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5790 offset++;
5791
5792 outputs[i].values[chan] =
5793 ac_build_buffer_load(&ctx.ac,
5794 ctx.gsvs_ring[0], 1,
5795 ctx.i32_0, voffset,
5796 soffset, 0, ac_glc | ac_slc,
5797 true, false);
5798 }
5799 }
5800
5801 /* Streamout and exports. */
5802 if (ctx.ac.chip_class <= GFX9 && gs_selector->so.num_outputs) {
5803 si_llvm_emit_streamout(&ctx, outputs,
5804 gsinfo->num_outputs,
5805 stream);
5806 }
5807
5808 if (stream == 0)
5809 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5810
5811 LLVMBuildBr(builder, end_bb);
5812 }
5813
5814 LLVMPositionBuilderAtEnd(builder, end_bb);
5815
5816 LLVMBuildRetVoid(ctx.ac.builder);
5817
5818 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5819 si_llvm_optimize_module(&ctx);
5820
5821 bool ok = false;
5822 if (si_compile_llvm(sscreen, &ctx.shader->binary,
5823 &ctx.shader->config, ctx.compiler,
5824 ctx.ac.module,
5825 debug, PIPE_SHADER_GEOMETRY, ctx.ac.wave_size,
5826 "GS Copy Shader", false) == 0) {
5827 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5828 fprintf(stderr, "GS Copy Shader:\n");
5829 si_shader_dump(sscreen, ctx.shader, debug, stderr, true);
5830
5831 if (!ctx.shader->config.scratch_bytes_per_wave)
5832 ok = si_shader_binary_upload(sscreen, ctx.shader, 0);
5833 else
5834 ok = true;
5835 }
5836
5837 si_llvm_dispose(&ctx);
5838
5839 if (!ok) {
5840 FREE(shader);
5841 shader = NULL;
5842 } else {
5843 si_fix_resource_usage(sscreen, shader);
5844 }
5845 return shader;
5846 }
5847
5848 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5849 const struct si_vs_prolog_bits *prolog,
5850 const char *prefix, FILE *f)
5851 {
5852 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5853 prefix, prolog->instance_divisor_is_one);
5854 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5855 prefix, prolog->instance_divisor_is_fetched);
5856 fprintf(f, " %s.unpack_instance_id_from_vertex_id = %u\n",
5857 prefix, prolog->unpack_instance_id_from_vertex_id);
5858 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5859 prefix, prolog->ls_vgpr_fix);
5860
5861 fprintf(f, " mono.vs.fetch_opencode = %x\n", key->mono.vs_fetch_opencode);
5862 fprintf(f, " mono.vs.fix_fetch = {");
5863 for (int i = 0; i < SI_MAX_ATTRIBS; i++) {
5864 union si_vs_fix_fetch fix = key->mono.vs_fix_fetch[i];
5865 if (i)
5866 fprintf(f, ", ");
5867 if (!fix.bits)
5868 fprintf(f, "0");
5869 else
5870 fprintf(f, "%u.%u.%u.%u", fix.u.reverse, fix.u.log_size,
5871 fix.u.num_channels_m1, fix.u.format);
5872 }
5873 fprintf(f, "}\n");
5874 }
5875
5876 static void si_dump_shader_key(const struct si_shader *shader, FILE *f)
5877 {
5878 const struct si_shader_key *key = &shader->key;
5879 enum pipe_shader_type shader_type = shader->selector->type;
5880
5881 fprintf(f, "SHADER KEY\n");
5882
5883 switch (shader_type) {
5884 case PIPE_SHADER_VERTEX:
5885 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5886 "part.vs.prolog", f);
5887 fprintf(f, " as_es = %u\n", key->as_es);
5888 fprintf(f, " as_ls = %u\n", key->as_ls);
5889 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5890 key->mono.u.vs_export_prim_id);
5891 fprintf(f, " opt.vs_as_prim_discard_cs = %u\n",
5892 key->opt.vs_as_prim_discard_cs);
5893 fprintf(f, " opt.cs_prim_type = %s\n",
5894 tgsi_primitive_names[key->opt.cs_prim_type]);
5895 fprintf(f, " opt.cs_indexed = %u\n",
5896 key->opt.cs_indexed);
5897 fprintf(f, " opt.cs_instancing = %u\n",
5898 key->opt.cs_instancing);
5899 fprintf(f, " opt.cs_primitive_restart = %u\n",
5900 key->opt.cs_primitive_restart);
5901 fprintf(f, " opt.cs_provoking_vertex_first = %u\n",
5902 key->opt.cs_provoking_vertex_first);
5903 fprintf(f, " opt.cs_need_correct_orientation = %u\n",
5904 key->opt.cs_need_correct_orientation);
5905 fprintf(f, " opt.cs_cull_front = %u\n",
5906 key->opt.cs_cull_front);
5907 fprintf(f, " opt.cs_cull_back = %u\n",
5908 key->opt.cs_cull_back);
5909 fprintf(f, " opt.cs_cull_z = %u\n",
5910 key->opt.cs_cull_z);
5911 fprintf(f, " opt.cs_halfz_clip_space = %u\n",
5912 key->opt.cs_halfz_clip_space);
5913 break;
5914
5915 case PIPE_SHADER_TESS_CTRL:
5916 if (shader->selector->screen->info.chip_class >= GFX9) {
5917 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5918 "part.tcs.ls_prolog", f);
5919 }
5920 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5921 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5922 break;
5923
5924 case PIPE_SHADER_TESS_EVAL:
5925 fprintf(f, " as_es = %u\n", key->as_es);
5926 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5927 key->mono.u.vs_export_prim_id);
5928 break;
5929
5930 case PIPE_SHADER_GEOMETRY:
5931 if (shader->is_gs_copy_shader)
5932 break;
5933
5934 if (shader->selector->screen->info.chip_class >= GFX9 &&
5935 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5936 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5937 "part.gs.vs_prolog", f);
5938 }
5939 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5940 break;
5941
5942 case PIPE_SHADER_COMPUTE:
5943 break;
5944
5945 case PIPE_SHADER_FRAGMENT:
5946 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5947 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5948 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5949 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5950 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5951 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5952 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5953 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5954 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5955 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5956 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5957 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5958 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5959 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5960 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5961 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5962 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5963 break;
5964
5965 default:
5966 assert(0);
5967 }
5968
5969 if ((shader_type == PIPE_SHADER_GEOMETRY ||
5970 shader_type == PIPE_SHADER_TESS_EVAL ||
5971 shader_type == PIPE_SHADER_VERTEX) &&
5972 !key->as_es && !key->as_ls) {
5973 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5974 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5975 }
5976 }
5977
5978 static void si_init_shader_ctx(struct si_shader_context *ctx,
5979 struct si_screen *sscreen,
5980 struct ac_llvm_compiler *compiler,
5981 unsigned wave_size)
5982 {
5983 struct lp_build_tgsi_context *bld_base;
5984
5985 si_llvm_context_init(ctx, sscreen, compiler, wave_size);
5986
5987 bld_base = &ctx->bld_base;
5988 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5989
5990 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5991 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5992 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5993
5994 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5995
5996 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5997
5998 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5999 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6000 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6001 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6002
6003 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
6004 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
6005 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
6006 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
6007 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
6008 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
6009 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
6010 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
6011
6012 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
6013 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
6014 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6015 }
6016
6017 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
6018 {
6019 struct si_shader *shader = ctx->shader;
6020 struct tgsi_shader_info *info = &shader->selector->info;
6021
6022 if ((ctx->type != PIPE_SHADER_VERTEX &&
6023 ctx->type != PIPE_SHADER_TESS_EVAL) ||
6024 shader->key.as_ls ||
6025 shader->key.as_es)
6026 return;
6027
6028 ac_optimize_vs_outputs(&ctx->ac,
6029 ctx->main_fn,
6030 shader->info.vs_output_param_offset,
6031 info->num_outputs,
6032 &shader->info.nr_param_exports);
6033 }
6034
6035 static void si_init_exec_from_input(struct si_shader_context *ctx,
6036 unsigned param, unsigned bitoffset)
6037 {
6038 LLVMValueRef args[] = {
6039 LLVMGetParam(ctx->main_fn, param),
6040 LLVMConstInt(ctx->i32, bitoffset, 0),
6041 };
6042 ac_build_intrinsic(&ctx->ac,
6043 "llvm.amdgcn.init.exec.from.input",
6044 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
6045 }
6046
6047 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6048 const struct si_vs_prolog_bits *key)
6049 {
6050 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6051 * VS prolog. */
6052 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6053 }
6054
6055 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
6056 {
6057 struct si_shader *shader = ctx->shader;
6058 struct si_shader_selector *sel = shader->selector;
6059 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6060
6061 // TODO clean all this up!
6062 switch (ctx->type) {
6063 case PIPE_SHADER_VERTEX:
6064 ctx->load_input = declare_input_vs;
6065 if (shader->key.as_ls)
6066 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6067 else if (shader->key.as_es)
6068 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6069 else if (shader->key.opt.vs_as_prim_discard_cs)
6070 ctx->abi.emit_outputs = si_llvm_emit_prim_discard_cs_epilogue;
6071 else if (shader->key.as_ngg)
6072 ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue;
6073 else
6074 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6075 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6076 ctx->abi.load_base_vertex = get_base_vertex;
6077 break;
6078 case PIPE_SHADER_TESS_CTRL:
6079 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6080 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6081 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6082 bld_base->emit_store = store_output_tcs;
6083 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6084 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6085 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6086 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6087 break;
6088 case PIPE_SHADER_TESS_EVAL:
6089 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6090 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6091 ctx->abi.load_tess_coord = si_load_tess_coord;
6092 ctx->abi.load_tess_level = si_load_tess_level;
6093 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6094 if (shader->key.as_es)
6095 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6096 else if (shader->key.as_ngg)
6097 ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue;
6098 else
6099 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6100 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6101 break;
6102 case PIPE_SHADER_GEOMETRY:
6103 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6104 ctx->abi.load_inputs = si_nir_load_input_gs;
6105 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6106 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6107 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6108 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6109 break;
6110 case PIPE_SHADER_FRAGMENT:
6111 ctx->load_input = declare_input_fs;
6112 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6113 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6114 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6115 ctx->abi.load_sample_position = load_sample_position;
6116 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6117 ctx->abi.emit_fbfetch = si_nir_emit_fbfetch;
6118 ctx->abi.emit_kill = si_llvm_emit_kill;
6119 break;
6120 case PIPE_SHADER_COMPUTE:
6121 ctx->abi.load_local_group_size = get_block_size;
6122 break;
6123 default:
6124 assert(!"Unsupported shader type");
6125 return false;
6126 }
6127
6128 ctx->abi.load_ubo = load_ubo;
6129 ctx->abi.load_ssbo = load_ssbo;
6130
6131 create_function(ctx);
6132 preload_ring_buffers(ctx);
6133
6134 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6135 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6136 for (unsigned i = 0; i < 6; i++) {
6137 ctx->invoc0_tess_factors[i] =
6138 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6139 }
6140 }
6141
6142 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6143 for (unsigned i = 0; i < 4; i++) {
6144 ctx->gs_next_vertex[i] =
6145 ac_build_alloca(&ctx->ac, ctx->i32, "");
6146 }
6147 if (shader->key.as_ngg) {
6148 for (unsigned i = 0; i < 4; ++i) {
6149 ctx->gs_curprim_verts[i] =
6150 ac_build_alloca(&ctx->ac, ctx->ac.i32, "");
6151 ctx->gs_generated_prims[i] =
6152 ac_build_alloca(&ctx->ac, ctx->ac.i32, "");
6153 }
6154
6155 unsigned scratch_size = 8;
6156 if (sel->so.num_outputs)
6157 scratch_size = 44;
6158
6159 LLVMTypeRef ai32 = LLVMArrayType(ctx->i32, scratch_size);
6160 ctx->gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6161 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
6162 LLVMSetInitializer(ctx->gs_ngg_scratch, LLVMGetUndef(ai32));
6163 LLVMSetAlignment(ctx->gs_ngg_scratch, 4);
6164
6165 ctx->gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6166 LLVMArrayType(ctx->i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
6167 LLVMSetLinkage(ctx->gs_ngg_emit, LLVMExternalLinkage);
6168 LLVMSetAlignment(ctx->gs_ngg_emit, 4);
6169 }
6170 }
6171
6172 if (ctx->type != PIPE_SHADER_GEOMETRY &&
6173 (shader->key.as_ngg && !shader->key.as_es)) {
6174 /* Unconditionally declare scratch space base for streamout and
6175 * vertex compaction. Whether space is actually allocated is
6176 * determined during linking / PM4 creation.
6177 *
6178 * Add an extra dword per vertex to ensure an odd stride, which
6179 * avoids bank conflicts for SoA accesses.
6180 */
6181 declare_esgs_ring(ctx);
6182
6183 /* This is really only needed when streamout and / or vertex
6184 * compaction is enabled.
6185 */
6186 LLVMTypeRef asi32 = LLVMArrayType(ctx->i32, 8);
6187 ctx->gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6188 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
6189 LLVMSetInitializer(ctx->gs_ngg_scratch, LLVMGetUndef(asi32));
6190 LLVMSetAlignment(ctx->gs_ngg_scratch, 4);
6191 }
6192
6193 /* For GFX9 merged shaders:
6194 * - Set EXEC for the first shader. If the prolog is present, set
6195 * EXEC there instead.
6196 * - Add a barrier before the second shader.
6197 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6198 * an if-statement. This is required for correctness in geometry
6199 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6200 * GS_CUT messages.
6201 *
6202 * For monolithic merged shaders, the first shader is wrapped in an
6203 * if-block together with its prolog in si_build_wrapper_function.
6204 *
6205 * NGG vertex and tess eval shaders running as the last
6206 * vertex/geometry stage handle execution explicitly using
6207 * if-statements.
6208 */
6209 if (ctx->screen->info.chip_class >= GFX9) {
6210 if (!shader->is_monolithic &&
6211 sel->info.num_instructions > 1 && /* not empty shader */
6212 (shader->key.as_es || shader->key.as_ls) &&
6213 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6214 (ctx->type == PIPE_SHADER_VERTEX &&
6215 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6216 si_init_exec_from_input(ctx,
6217 ctx->param_merged_wave_info, 0);
6218 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6219 ctx->type == PIPE_SHADER_GEOMETRY ||
6220 (shader->key.as_ngg && !shader->key.as_es)) {
6221 LLVMValueRef num_threads;
6222 bool nested_barrier;
6223
6224 if (!shader->is_monolithic ||
6225 (ctx->type == PIPE_SHADER_TESS_EVAL &&
6226 (shader->key.as_ngg && !shader->key.as_es)))
6227 ac_init_exec_full_mask(&ctx->ac);
6228
6229 if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6230 ctx->type == PIPE_SHADER_GEOMETRY) {
6231 if (ctx->type == PIPE_SHADER_GEOMETRY && shader->key.as_ngg) {
6232 gfx10_ngg_gs_emit_prologue(ctx);
6233 nested_barrier = false;
6234 } else {
6235 nested_barrier = true;
6236 }
6237
6238 /* Number of patches / primitives */
6239 num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6240 } else {
6241 /* Number of vertices */
6242 num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 0, 8);
6243 nested_barrier = false;
6244 }
6245
6246 LLVMValueRef ena =
6247 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6248 ac_get_thread_id(&ctx->ac), num_threads, "");
6249
6250 ctx->merged_wrap_if_entry_block = LLVMGetInsertBlock(ctx->ac.builder);
6251 ctx->merged_wrap_if_label = 11500;
6252 ac_build_ifcc(&ctx->ac, ena, ctx->merged_wrap_if_label);
6253
6254 if (nested_barrier) {
6255 /* Execute a barrier before the second shader in
6256 * a merged shader.
6257 *
6258 * Execute the barrier inside the conditional block,
6259 * so that empty waves can jump directly to s_endpgm,
6260 * which will also signal the barrier.
6261 *
6262 * This is possible in gfx9, because an empty wave
6263 * for the second shader does not participate in
6264 * the epilogue. With NGG, empty waves may still
6265 * be required to export data (e.g. GS output vertices),
6266 * so we cannot let them exit early.
6267 *
6268 * If the shader is TCS and the TCS epilog is present
6269 * and contains a barrier, it will wait there and then
6270 * reach s_endpgm.
6271 */
6272 si_llvm_emit_barrier(NULL, bld_base, NULL);
6273 }
6274 }
6275 }
6276
6277 if (sel->force_correct_derivs_after_kill) {
6278 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6279 /* true = don't kill. */
6280 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6281 ctx->postponed_kill);
6282 }
6283
6284 if (sel->tokens) {
6285 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6286 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6287 return false;
6288 }
6289 } else {
6290 if (!si_nir_build_llvm(ctx, sel->nir)) {
6291 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6292 return false;
6293 }
6294 }
6295
6296 si_llvm_build_ret(ctx, ctx->return_value);
6297 return true;
6298 }
6299
6300 /**
6301 * Compute the VS prolog key, which contains all the information needed to
6302 * build the VS prolog function, and set shader->info bits where needed.
6303 *
6304 * \param info Shader info of the vertex shader.
6305 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6306 * \param prolog_key Key of the VS prolog
6307 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6308 * \param key Output shader part key.
6309 */
6310 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6311 unsigned num_input_sgprs,
6312 const struct si_vs_prolog_bits *prolog_key,
6313 struct si_shader *shader_out,
6314 union si_shader_part_key *key)
6315 {
6316 memset(key, 0, sizeof(*key));
6317 key->vs_prolog.states = *prolog_key;
6318 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6319 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6320 key->vs_prolog.as_ls = shader_out->key.as_ls;
6321 key->vs_prolog.as_es = shader_out->key.as_es;
6322 key->vs_prolog.as_ngg = shader_out->key.as_ngg;
6323
6324 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6325 key->vs_prolog.as_ls = 1;
6326 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6327 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6328 key->vs_prolog.as_es = 1;
6329 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6330 } else if (shader_out->key.as_ngg) {
6331 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6332 }
6333
6334 /* Enable loading the InstanceID VGPR. */
6335 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6336
6337 if ((key->vs_prolog.states.instance_divisor_is_one |
6338 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6339 shader_out->info.uses_instanceid = true;
6340 }
6341
6342 /**
6343 * Compute the PS prolog key, which contains all the information needed to
6344 * build the PS prolog function, and set related bits in shader->config.
6345 */
6346 static void si_get_ps_prolog_key(struct si_shader *shader,
6347 union si_shader_part_key *key,
6348 bool separate_prolog)
6349 {
6350 struct tgsi_shader_info *info = &shader->selector->info;
6351
6352 memset(key, 0, sizeof(*key));
6353 key->ps_prolog.states = shader->key.part.ps.prolog;
6354 key->ps_prolog.colors_read = info->colors_read;
6355 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6356 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6357 key->ps_prolog.wqm = info->uses_derivatives &&
6358 (key->ps_prolog.colors_read ||
6359 key->ps_prolog.states.force_persp_sample_interp ||
6360 key->ps_prolog.states.force_linear_sample_interp ||
6361 key->ps_prolog.states.force_persp_center_interp ||
6362 key->ps_prolog.states.force_linear_center_interp ||
6363 key->ps_prolog.states.bc_optimize_for_persp ||
6364 key->ps_prolog.states.bc_optimize_for_linear);
6365 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6366
6367 if (info->colors_read) {
6368 unsigned *color = shader->selector->color_attr_index;
6369
6370 if (shader->key.part.ps.prolog.color_two_side) {
6371 /* BCOLORs are stored after the last input. */
6372 key->ps_prolog.num_interp_inputs = info->num_inputs;
6373 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6374 if (separate_prolog)
6375 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6376 }
6377
6378 for (unsigned i = 0; i < 2; i++) {
6379 unsigned interp = info->input_interpolate[color[i]];
6380 unsigned location = info->input_interpolate_loc[color[i]];
6381
6382 if (!(info->colors_read & (0xf << i*4)))
6383 continue;
6384
6385 key->ps_prolog.color_attr_index[i] = color[i];
6386
6387 if (shader->key.part.ps.prolog.flatshade_colors &&
6388 interp == TGSI_INTERPOLATE_COLOR)
6389 interp = TGSI_INTERPOLATE_CONSTANT;
6390
6391 switch (interp) {
6392 case TGSI_INTERPOLATE_CONSTANT:
6393 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6394 break;
6395 case TGSI_INTERPOLATE_PERSPECTIVE:
6396 case TGSI_INTERPOLATE_COLOR:
6397 /* Force the interpolation location for colors here. */
6398 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6399 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6400 if (shader->key.part.ps.prolog.force_persp_center_interp)
6401 location = TGSI_INTERPOLATE_LOC_CENTER;
6402
6403 switch (location) {
6404 case TGSI_INTERPOLATE_LOC_SAMPLE:
6405 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6406 if (separate_prolog) {
6407 shader->config.spi_ps_input_ena |=
6408 S_0286CC_PERSP_SAMPLE_ENA(1);
6409 }
6410 break;
6411 case TGSI_INTERPOLATE_LOC_CENTER:
6412 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6413 if (separate_prolog) {
6414 shader->config.spi_ps_input_ena |=
6415 S_0286CC_PERSP_CENTER_ENA(1);
6416 }
6417 break;
6418 case TGSI_INTERPOLATE_LOC_CENTROID:
6419 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6420 if (separate_prolog) {
6421 shader->config.spi_ps_input_ena |=
6422 S_0286CC_PERSP_CENTROID_ENA(1);
6423 }
6424 break;
6425 default:
6426 assert(0);
6427 }
6428 break;
6429 case TGSI_INTERPOLATE_LINEAR:
6430 /* Force the interpolation location for colors here. */
6431 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6432 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6433 if (shader->key.part.ps.prolog.force_linear_center_interp)
6434 location = TGSI_INTERPOLATE_LOC_CENTER;
6435
6436 /* The VGPR assignment for non-monolithic shaders
6437 * works because InitialPSInputAddr is set on the
6438 * main shader and PERSP_PULL_MODEL is never used.
6439 */
6440 switch (location) {
6441 case TGSI_INTERPOLATE_LOC_SAMPLE:
6442 key->ps_prolog.color_interp_vgpr_index[i] =
6443 separate_prolog ? 6 : 9;
6444 if (separate_prolog) {
6445 shader->config.spi_ps_input_ena |=
6446 S_0286CC_LINEAR_SAMPLE_ENA(1);
6447 }
6448 break;
6449 case TGSI_INTERPOLATE_LOC_CENTER:
6450 key->ps_prolog.color_interp_vgpr_index[i] =
6451 separate_prolog ? 8 : 11;
6452 if (separate_prolog) {
6453 shader->config.spi_ps_input_ena |=
6454 S_0286CC_LINEAR_CENTER_ENA(1);
6455 }
6456 break;
6457 case TGSI_INTERPOLATE_LOC_CENTROID:
6458 key->ps_prolog.color_interp_vgpr_index[i] =
6459 separate_prolog ? 10 : 13;
6460 if (separate_prolog) {
6461 shader->config.spi_ps_input_ena |=
6462 S_0286CC_LINEAR_CENTROID_ENA(1);
6463 }
6464 break;
6465 default:
6466 assert(0);
6467 }
6468 break;
6469 default:
6470 assert(0);
6471 }
6472 }
6473 }
6474 }
6475
6476 /**
6477 * Check whether a PS prolog is required based on the key.
6478 */
6479 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6480 {
6481 return key->ps_prolog.colors_read ||
6482 key->ps_prolog.states.force_persp_sample_interp ||
6483 key->ps_prolog.states.force_linear_sample_interp ||
6484 key->ps_prolog.states.force_persp_center_interp ||
6485 key->ps_prolog.states.force_linear_center_interp ||
6486 key->ps_prolog.states.bc_optimize_for_persp ||
6487 key->ps_prolog.states.bc_optimize_for_linear ||
6488 key->ps_prolog.states.poly_stipple ||
6489 key->ps_prolog.states.samplemask_log_ps_iter;
6490 }
6491
6492 /**
6493 * Compute the PS epilog key, which contains all the information needed to
6494 * build the PS epilog function.
6495 */
6496 static void si_get_ps_epilog_key(struct si_shader *shader,
6497 union si_shader_part_key *key)
6498 {
6499 struct tgsi_shader_info *info = &shader->selector->info;
6500 memset(key, 0, sizeof(*key));
6501 key->ps_epilog.colors_written = info->colors_written;
6502 key->ps_epilog.writes_z = info->writes_z;
6503 key->ps_epilog.writes_stencil = info->writes_stencil;
6504 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6505 key->ps_epilog.states = shader->key.part.ps.epilog;
6506 }
6507
6508 /**
6509 * Build the GS prolog function. Rotate the input vertices for triangle strips
6510 * with adjacency.
6511 */
6512 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6513 union si_shader_part_key *key)
6514 {
6515 unsigned num_sgprs, num_vgprs;
6516 struct si_function_info fninfo;
6517 LLVMBuilderRef builder = ctx->ac.builder;
6518 LLVMTypeRef returns[48];
6519 LLVMValueRef func, ret;
6520
6521 si_init_function_info(&fninfo);
6522
6523 if (ctx->screen->info.chip_class >= GFX9) {
6524 if (key->gs_prolog.states.gfx9_prev_is_vs)
6525 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6526 else
6527 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6528 num_vgprs = 5; /* ES inputs are not needed by GS */
6529 } else {
6530 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6531 num_vgprs = 8;
6532 }
6533
6534 for (unsigned i = 0; i < num_sgprs; ++i) {
6535 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6536 returns[i] = ctx->i32;
6537 }
6538
6539 for (unsigned i = 0; i < num_vgprs; ++i) {
6540 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6541 returns[num_sgprs + i] = ctx->f32;
6542 }
6543
6544 /* Create the function. */
6545 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6546 &fninfo, 0);
6547 func = ctx->main_fn;
6548
6549 /* Set the full EXEC mask for the prolog, because we are only fiddling
6550 * with registers here. The main shader part will set the correct EXEC
6551 * mask.
6552 */
6553 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6554 ac_init_exec_full_mask(&ctx->ac);
6555
6556 /* Copy inputs to outputs. This should be no-op, as the registers match,
6557 * but it will prevent the compiler from overwriting them unintentionally.
6558 */
6559 ret = ctx->return_value;
6560 for (unsigned i = 0; i < num_sgprs; i++) {
6561 LLVMValueRef p = LLVMGetParam(func, i);
6562 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6563 }
6564 for (unsigned i = 0; i < num_vgprs; i++) {
6565 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6566 p = ac_to_float(&ctx->ac, p);
6567 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6568 }
6569
6570 if (key->gs_prolog.states.tri_strip_adj_fix) {
6571 /* Remap the input vertices for every other primitive. */
6572 const unsigned gfx6_vtx_params[6] = {
6573 num_sgprs,
6574 num_sgprs + 1,
6575 num_sgprs + 3,
6576 num_sgprs + 4,
6577 num_sgprs + 5,
6578 num_sgprs + 6
6579 };
6580 const unsigned gfx9_vtx_params[3] = {
6581 num_sgprs,
6582 num_sgprs + 1,
6583 num_sgprs + 4,
6584 };
6585 LLVMValueRef vtx_in[6], vtx_out[6];
6586 LLVMValueRef prim_id, rotate;
6587
6588 if (ctx->screen->info.chip_class >= GFX9) {
6589 for (unsigned i = 0; i < 3; i++) {
6590 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6591 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6592 }
6593 } else {
6594 for (unsigned i = 0; i < 6; i++)
6595 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6596 }
6597
6598 prim_id = LLVMGetParam(func, num_sgprs + 2);
6599 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6600
6601 for (unsigned i = 0; i < 6; ++i) {
6602 LLVMValueRef base, rotated;
6603 base = vtx_in[i];
6604 rotated = vtx_in[(i + 4) % 6];
6605 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6606 }
6607
6608 if (ctx->screen->info.chip_class >= GFX9) {
6609 for (unsigned i = 0; i < 3; i++) {
6610 LLVMValueRef hi, out;
6611
6612 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6613 LLVMConstInt(ctx->i32, 16, 0), "");
6614 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6615 out = ac_to_float(&ctx->ac, out);
6616 ret = LLVMBuildInsertValue(builder, ret, out,
6617 gfx9_vtx_params[i], "");
6618 }
6619 } else {
6620 for (unsigned i = 0; i < 6; i++) {
6621 LLVMValueRef out;
6622
6623 out = ac_to_float(&ctx->ac, vtx_out[i]);
6624 ret = LLVMBuildInsertValue(builder, ret, out,
6625 gfx6_vtx_params[i], "");
6626 }
6627 }
6628 }
6629
6630 LLVMBuildRet(builder, ret);
6631 }
6632
6633 /**
6634 * Given a list of shader part functions, build a wrapper function that
6635 * runs them in sequence to form a monolithic shader.
6636 */
6637 static void si_build_wrapper_function(struct si_shader_context *ctx,
6638 LLVMValueRef *parts,
6639 unsigned num_parts,
6640 unsigned main_part,
6641 unsigned next_shader_first_part)
6642 {
6643 LLVMBuilderRef builder = ctx->ac.builder;
6644 /* PS epilog has one arg per color component; gfx9 merged shader
6645 * prologs need to forward 32 user SGPRs.
6646 */
6647 struct si_function_info fninfo;
6648 LLVMValueRef initial[64], out[64];
6649 LLVMTypeRef function_type;
6650 unsigned num_first_params;
6651 unsigned num_out, initial_num_out;
6652 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6653 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6654 unsigned num_sgprs, num_vgprs;
6655 unsigned gprs;
6656
6657 si_init_function_info(&fninfo);
6658
6659 for (unsigned i = 0; i < num_parts; ++i) {
6660 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6661 AC_FUNC_ATTR_ALWAYSINLINE);
6662 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6663 }
6664
6665 /* The parameters of the wrapper function correspond to those of the
6666 * first part in terms of SGPRs and VGPRs, but we use the types of the
6667 * main part to get the right types. This is relevant for the
6668 * dereferenceable attribute on descriptor table pointers.
6669 */
6670 num_sgprs = 0;
6671 num_vgprs = 0;
6672
6673 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6674 num_first_params = LLVMCountParamTypes(function_type);
6675
6676 for (unsigned i = 0; i < num_first_params; ++i) {
6677 LLVMValueRef param = LLVMGetParam(parts[0], i);
6678
6679 if (ac_is_sgpr_param(param)) {
6680 assert(num_vgprs == 0);
6681 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6682 } else {
6683 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6684 }
6685 }
6686
6687 gprs = 0;
6688 while (gprs < num_sgprs + num_vgprs) {
6689 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6690 LLVMTypeRef type = LLVMTypeOf(param);
6691 unsigned size = ac_get_type_size(type) / 4;
6692
6693 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6694
6695 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6696 assert(gprs + size <= num_sgprs + num_vgprs &&
6697 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6698
6699 gprs += size;
6700 }
6701
6702 /* Prepare the return type. */
6703 unsigned num_returns = 0;
6704 LLVMTypeRef returns[32], last_func_type, return_type;
6705
6706 last_func_type = LLVMGetElementType(LLVMTypeOf(parts[num_parts - 1]));
6707 return_type = LLVMGetReturnType(last_func_type);
6708
6709 switch (LLVMGetTypeKind(return_type)) {
6710 case LLVMStructTypeKind:
6711 num_returns = LLVMCountStructElementTypes(return_type);
6712 assert(num_returns <= ARRAY_SIZE(returns));
6713 LLVMGetStructElementTypes(return_type, returns);
6714 break;
6715 case LLVMVoidTypeKind:
6716 break;
6717 default:
6718 unreachable("unexpected type");
6719 }
6720
6721 si_create_function(ctx, "wrapper", returns, num_returns, &fninfo,
6722 si_get_max_workgroup_size(ctx->shader));
6723
6724 if (is_merged_shader(ctx))
6725 ac_init_exec_full_mask(&ctx->ac);
6726
6727 /* Record the arguments of the function as if they were an output of
6728 * a previous part.
6729 */
6730 num_out = 0;
6731 num_out_sgpr = 0;
6732
6733 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6734 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6735 LLVMTypeRef param_type = LLVMTypeOf(param);
6736 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6737 unsigned size = ac_get_type_size(param_type) / 4;
6738
6739 if (size == 1) {
6740 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6741 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6742 param_type = ctx->i32;
6743 }
6744
6745 if (param_type != out_type)
6746 param = LLVMBuildBitCast(builder, param, out_type, "");
6747 out[num_out++] = param;
6748 } else {
6749 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6750
6751 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6752 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6753 param_type = ctx->i64;
6754 }
6755
6756 if (param_type != vector_type)
6757 param = LLVMBuildBitCast(builder, param, vector_type, "");
6758
6759 for (unsigned j = 0; j < size; ++j)
6760 out[num_out++] = LLVMBuildExtractElement(
6761 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6762 }
6763
6764 if (i < fninfo.num_sgpr_params)
6765 num_out_sgpr = num_out;
6766 }
6767
6768 memcpy(initial, out, sizeof(out));
6769 initial_num_out = num_out;
6770 initial_num_out_sgpr = num_out_sgpr;
6771
6772 /* Now chain the parts. */
6773 LLVMValueRef ret = NULL;
6774 for (unsigned part = 0; part < num_parts; ++part) {
6775 LLVMValueRef in[48];
6776 LLVMTypeRef ret_type;
6777 unsigned out_idx = 0;
6778 unsigned num_params = LLVMCountParams(parts[part]);
6779
6780 /* Merged shaders are executed conditionally depending
6781 * on the number of enabled threads passed in the input SGPRs. */
6782 if (is_multi_part_shader(ctx) && part == 0) {
6783 LLVMValueRef ena, count = initial[3];
6784
6785 count = LLVMBuildAnd(builder, count,
6786 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6787 ena = LLVMBuildICmp(builder, LLVMIntULT,
6788 ac_get_thread_id(&ctx->ac), count, "");
6789 ac_build_ifcc(&ctx->ac, ena, 6506);
6790 }
6791
6792 /* Derive arguments for the next part from outputs of the
6793 * previous one.
6794 */
6795 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6796 LLVMValueRef param;
6797 LLVMTypeRef param_type;
6798 bool is_sgpr;
6799 unsigned param_size;
6800 LLVMValueRef arg = NULL;
6801
6802 param = LLVMGetParam(parts[part], param_idx);
6803 param_type = LLVMTypeOf(param);
6804 param_size = ac_get_type_size(param_type) / 4;
6805 is_sgpr = ac_is_sgpr_param(param);
6806
6807 if (is_sgpr) {
6808 ac_add_function_attr(ctx->ac.context, parts[part],
6809 param_idx + 1, AC_FUNC_ATTR_INREG);
6810 } else if (out_idx < num_out_sgpr) {
6811 /* Skip returned SGPRs the current part doesn't
6812 * declare on the input. */
6813 out_idx = num_out_sgpr;
6814 }
6815
6816 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6817
6818 if (param_size == 1)
6819 arg = out[out_idx];
6820 else
6821 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6822
6823 if (LLVMTypeOf(arg) != param_type) {
6824 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6825 if (LLVMGetPointerAddressSpace(param_type) ==
6826 AC_ADDR_SPACE_CONST_32BIT) {
6827 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6828 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6829 } else {
6830 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6831 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6832 }
6833 } else {
6834 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6835 }
6836 }
6837
6838 in[param_idx] = arg;
6839 out_idx += param_size;
6840 }
6841
6842 ret = ac_build_call(&ctx->ac, parts[part], in, num_params);
6843
6844 if (is_multi_part_shader(ctx) &&
6845 part + 1 == next_shader_first_part) {
6846 ac_build_endif(&ctx->ac, 6506);
6847
6848 /* The second half of the merged shader should use
6849 * the inputs from the toplevel (wrapper) function,
6850 * not the return value from the last call.
6851 *
6852 * That's because the last call was executed condi-
6853 * tionally, so we can't consume it in the main
6854 * block.
6855 */
6856 memcpy(out, initial, sizeof(initial));
6857 num_out = initial_num_out;
6858 num_out_sgpr = initial_num_out_sgpr;
6859 continue;
6860 }
6861
6862 /* Extract the returned GPRs. */
6863 ret_type = LLVMTypeOf(ret);
6864 num_out = 0;
6865 num_out_sgpr = 0;
6866
6867 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6868 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6869
6870 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6871
6872 for (unsigned i = 0; i < ret_size; ++i) {
6873 LLVMValueRef val =
6874 LLVMBuildExtractValue(builder, ret, i, "");
6875
6876 assert(num_out < ARRAY_SIZE(out));
6877 out[num_out++] = val;
6878
6879 if (LLVMTypeOf(val) == ctx->i32) {
6880 assert(num_out_sgpr + 1 == num_out);
6881 num_out_sgpr = num_out;
6882 }
6883 }
6884 }
6885 }
6886
6887 /* Return the value from the last part. */
6888 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6889 LLVMBuildRetVoid(builder);
6890 else
6891 LLVMBuildRet(builder, ret);
6892 }
6893
6894 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6895 struct si_shader_selector *sel)
6896 {
6897 if (!compiler->low_opt_passes)
6898 return false;
6899
6900 /* Assume a slow CPU. */
6901 assert(!sel->screen->info.has_dedicated_vram &&
6902 sel->screen->info.chip_class <= GFX8);
6903
6904 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6905 * buffer stores. */
6906 return sel->type == PIPE_SHADER_COMPUTE &&
6907 sel->info.num_memory_instructions > 1000;
6908 }
6909
6910 int si_compile_tgsi_shader(struct si_screen *sscreen,
6911 struct ac_llvm_compiler *compiler,
6912 struct si_shader *shader,
6913 struct pipe_debug_callback *debug)
6914 {
6915 struct si_shader_selector *sel = shader->selector;
6916 struct si_shader_context ctx;
6917 int r = -1;
6918
6919 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6920 * conversion fails. */
6921 if (si_can_dump_shader(sscreen, sel->type) &&
6922 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6923 if (sel->tokens)
6924 tgsi_dump(sel->tokens, 0);
6925 else
6926 nir_print_shader(sel->nir, stderr);
6927 si_dump_streamout(&sel->so);
6928 }
6929
6930 si_init_shader_ctx(&ctx, sscreen, compiler, si_get_shader_wave_size(shader));
6931 si_llvm_context_set_tgsi(&ctx, shader);
6932
6933 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6934 sizeof(shader->info.vs_output_param_offset));
6935
6936 shader->info.uses_instanceid = sel->info.uses_instanceid;
6937
6938 if (!si_compile_tgsi_main(&ctx)) {
6939 si_llvm_dispose(&ctx);
6940 return -1;
6941 }
6942
6943 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6944 LLVMValueRef parts[2];
6945 bool need_prolog = sel->vs_needs_prolog;
6946
6947 parts[1] = ctx.main_fn;
6948
6949 if (need_prolog) {
6950 union si_shader_part_key prolog_key;
6951 si_get_vs_prolog_key(&sel->info,
6952 shader->info.num_input_sgprs,
6953 &shader->key.part.vs.prolog,
6954 shader, &prolog_key);
6955 si_build_vs_prolog_function(&ctx, &prolog_key);
6956 parts[0] = ctx.main_fn;
6957 }
6958
6959 si_build_wrapper_function(&ctx, parts + !need_prolog,
6960 1 + need_prolog, need_prolog, 0);
6961
6962 if (ctx.shader->key.opt.vs_as_prim_discard_cs)
6963 si_build_prim_discard_compute_shader(&ctx);
6964 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6965 if (sscreen->info.chip_class >= GFX9) {
6966 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6967 LLVMValueRef parts[4];
6968 bool vs_needs_prolog =
6969 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6970
6971 /* TCS main part */
6972 parts[2] = ctx.main_fn;
6973
6974 /* TCS epilog */
6975 union si_shader_part_key tcs_epilog_key;
6976 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6977 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6978 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6979 parts[3] = ctx.main_fn;
6980
6981 /* VS as LS main part */
6982 struct si_shader shader_ls = {};
6983 shader_ls.selector = ls;
6984 shader_ls.key.as_ls = 1;
6985 shader_ls.key.mono = shader->key.mono;
6986 shader_ls.key.opt = shader->key.opt;
6987 shader_ls.is_monolithic = true;
6988 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6989
6990 if (!si_compile_tgsi_main(&ctx)) {
6991 si_llvm_dispose(&ctx);
6992 return -1;
6993 }
6994 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6995 parts[1] = ctx.main_fn;
6996
6997 /* LS prolog */
6998 if (vs_needs_prolog) {
6999 union si_shader_part_key vs_prolog_key;
7000 si_get_vs_prolog_key(&ls->info,
7001 shader_ls.info.num_input_sgprs,
7002 &shader->key.part.tcs.ls_prolog,
7003 shader, &vs_prolog_key);
7004 vs_prolog_key.vs_prolog.is_monolithic = true;
7005 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
7006 parts[0] = ctx.main_fn;
7007 }
7008
7009 /* Reset the shader context. */
7010 ctx.shader = shader;
7011 ctx.type = PIPE_SHADER_TESS_CTRL;
7012
7013 si_build_wrapper_function(&ctx,
7014 parts + !vs_needs_prolog,
7015 4 - !vs_needs_prolog, vs_needs_prolog,
7016 vs_needs_prolog ? 2 : 1);
7017 } else {
7018 LLVMValueRef parts[2];
7019 union si_shader_part_key epilog_key;
7020
7021 parts[0] = ctx.main_fn;
7022
7023 memset(&epilog_key, 0, sizeof(epilog_key));
7024 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7025 si_build_tcs_epilog_function(&ctx, &epilog_key);
7026 parts[1] = ctx.main_fn;
7027
7028 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
7029 }
7030 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7031 if (ctx.screen->info.chip_class >= GFX9) {
7032 struct si_shader_selector *es = shader->key.part.gs.es;
7033 LLVMValueRef es_prolog = NULL;
7034 LLVMValueRef es_main = NULL;
7035 LLVMValueRef gs_prolog = NULL;
7036 LLVMValueRef gs_main = ctx.main_fn;
7037
7038 /* GS prolog */
7039 union si_shader_part_key gs_prolog_key;
7040 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
7041 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7042 gs_prolog_key.gs_prolog.is_monolithic = true;
7043 gs_prolog_key.gs_prolog.as_ngg = shader->key.as_ngg;
7044 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
7045 gs_prolog = ctx.main_fn;
7046
7047 /* ES main part */
7048 struct si_shader shader_es = {};
7049 shader_es.selector = es;
7050 shader_es.key.as_es = 1;
7051 shader_es.key.as_ngg = shader->key.as_ngg;
7052 shader_es.key.mono = shader->key.mono;
7053 shader_es.key.opt = shader->key.opt;
7054 shader_es.is_monolithic = true;
7055 si_llvm_context_set_tgsi(&ctx, &shader_es);
7056
7057 if (!si_compile_tgsi_main(&ctx)) {
7058 si_llvm_dispose(&ctx);
7059 return -1;
7060 }
7061 shader->info.uses_instanceid |= es->info.uses_instanceid;
7062 es_main = ctx.main_fn;
7063
7064 /* ES prolog */
7065 if (es->vs_needs_prolog) {
7066 union si_shader_part_key vs_prolog_key;
7067 si_get_vs_prolog_key(&es->info,
7068 shader_es.info.num_input_sgprs,
7069 &shader->key.part.gs.vs_prolog,
7070 shader, &vs_prolog_key);
7071 vs_prolog_key.vs_prolog.is_monolithic = true;
7072 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
7073 es_prolog = ctx.main_fn;
7074 }
7075
7076 /* Reset the shader context. */
7077 ctx.shader = shader;
7078 ctx.type = PIPE_SHADER_GEOMETRY;
7079
7080 /* Prepare the array of shader parts. */
7081 LLVMValueRef parts[4];
7082 unsigned num_parts = 0, main_part, next_first_part;
7083
7084 if (es_prolog)
7085 parts[num_parts++] = es_prolog;
7086
7087 parts[main_part = num_parts++] = es_main;
7088 parts[next_first_part = num_parts++] = gs_prolog;
7089 parts[num_parts++] = gs_main;
7090
7091 si_build_wrapper_function(&ctx, parts, num_parts,
7092 main_part, next_first_part);
7093 } else {
7094 LLVMValueRef parts[2];
7095 union si_shader_part_key prolog_key;
7096
7097 parts[1] = ctx.main_fn;
7098
7099 memset(&prolog_key, 0, sizeof(prolog_key));
7100 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7101 si_build_gs_prolog_function(&ctx, &prolog_key);
7102 parts[0] = ctx.main_fn;
7103
7104 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
7105 }
7106 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7107 LLVMValueRef parts[3];
7108 union si_shader_part_key prolog_key;
7109 union si_shader_part_key epilog_key;
7110 bool need_prolog;
7111
7112 si_get_ps_prolog_key(shader, &prolog_key, false);
7113 need_prolog = si_need_ps_prolog(&prolog_key);
7114
7115 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7116
7117 if (need_prolog) {
7118 si_build_ps_prolog_function(&ctx, &prolog_key);
7119 parts[0] = ctx.main_fn;
7120 }
7121
7122 si_get_ps_epilog_key(shader, &epilog_key);
7123 si_build_ps_epilog_function(&ctx, &epilog_key);
7124 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7125
7126 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
7127 need_prolog ? 1 : 0, 0);
7128 }
7129
7130 si_llvm_optimize_module(&ctx);
7131
7132 /* Post-optimization transformations and analysis. */
7133 si_optimize_vs_outputs(&ctx);
7134
7135 if ((debug && debug->debug_message) ||
7136 si_can_dump_shader(sscreen, ctx.type)) {
7137 ctx.shader->info.private_mem_vgprs =
7138 ac_count_scratch_private_memory(ctx.main_fn);
7139 }
7140
7141 /* Make sure the input is a pointer and not integer followed by inttoptr. */
7142 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
7143 LLVMPointerTypeKind);
7144
7145 /* Compile to bytecode. */
7146 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
7147 ctx.ac.module, debug, ctx.type, ctx.ac.wave_size,
7148 si_get_shader_name(shader),
7149 si_should_optimize_less(compiler, shader->selector));
7150 si_llvm_dispose(&ctx);
7151 if (r) {
7152 fprintf(stderr, "LLVM failed to compile shader\n");
7153 return r;
7154 }
7155
7156 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7157 * LLVM 3.9svn has this bug.
7158 */
7159 if (sel->type == PIPE_SHADER_COMPUTE) {
7160 unsigned wave_size = sscreen->compute_wave_size;
7161 unsigned max_vgprs = 256;
7162 unsigned max_sgprs = sscreen->info.chip_class >= GFX8 ? 800 : 512;
7163 unsigned max_sgprs_per_wave = 128;
7164 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7165 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7166 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7167
7168 max_vgprs = max_vgprs / min_waves_per_simd;
7169 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7170
7171 if (shader->config.num_sgprs > max_sgprs ||
7172 shader->config.num_vgprs > max_vgprs) {
7173 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7174 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7175 shader->config.num_sgprs, shader->config.num_vgprs,
7176 max_sgprs, max_vgprs);
7177
7178 /* Just terminate the process, because dependent
7179 * shaders can hang due to bad input data, but use
7180 * the env var to allow shader-db to work.
7181 */
7182 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7183 abort();
7184 }
7185 }
7186
7187 /* Add the scratch offset to input SGPRs. */
7188 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
7189 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7190
7191 /* Calculate the number of fragment input VGPRs. */
7192 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7193 shader->info.num_input_vgprs = 0;
7194 shader->info.face_vgpr_index = -1;
7195 shader->info.ancillary_vgpr_index = -1;
7196
7197 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7198 shader->info.num_input_vgprs += 2;
7199 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7200 shader->info.num_input_vgprs += 2;
7201 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7202 shader->info.num_input_vgprs += 2;
7203 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7204 shader->info.num_input_vgprs += 3;
7205 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7206 shader->info.num_input_vgprs += 2;
7207 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7208 shader->info.num_input_vgprs += 2;
7209 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7210 shader->info.num_input_vgprs += 2;
7211 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7212 shader->info.num_input_vgprs += 1;
7213 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7214 shader->info.num_input_vgprs += 1;
7215 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7216 shader->info.num_input_vgprs += 1;
7217 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7218 shader->info.num_input_vgprs += 1;
7219 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7220 shader->info.num_input_vgprs += 1;
7221 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7222 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7223 shader->info.num_input_vgprs += 1;
7224 }
7225 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7226 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7227 shader->info.num_input_vgprs += 1;
7228 }
7229 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7230 shader->info.num_input_vgprs += 1;
7231 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7232 shader->info.num_input_vgprs += 1;
7233 }
7234
7235 si_calculate_max_simd_waves(shader);
7236 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
7237 return 0;
7238 }
7239
7240 /**
7241 * Create, compile and return a shader part (prolog or epilog).
7242 *
7243 * \param sscreen screen
7244 * \param list list of shader parts of the same category
7245 * \param type shader type
7246 * \param key shader part key
7247 * \param prolog whether the part being requested is a prolog
7248 * \param tm LLVM target machine
7249 * \param debug debug callback
7250 * \param build the callback responsible for building the main function
7251 * \return non-NULL on success
7252 */
7253 static struct si_shader_part *
7254 si_get_shader_part(struct si_screen *sscreen,
7255 struct si_shader_part **list,
7256 enum pipe_shader_type type,
7257 bool prolog,
7258 union si_shader_part_key *key,
7259 struct ac_llvm_compiler *compiler,
7260 struct pipe_debug_callback *debug,
7261 void (*build)(struct si_shader_context *,
7262 union si_shader_part_key *),
7263 const char *name)
7264 {
7265 struct si_shader_part *result;
7266
7267 mtx_lock(&sscreen->shader_parts_mutex);
7268
7269 /* Find existing. */
7270 for (result = *list; result; result = result->next) {
7271 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7272 mtx_unlock(&sscreen->shader_parts_mutex);
7273 return result;
7274 }
7275 }
7276
7277 /* Compile a new one. */
7278 result = CALLOC_STRUCT(si_shader_part);
7279 result->key = *key;
7280
7281 struct si_shader shader = {};
7282
7283 switch (type) {
7284 case PIPE_SHADER_VERTEX:
7285 shader.key.as_ls = key->vs_prolog.as_ls;
7286 shader.key.as_es = key->vs_prolog.as_es;
7287 shader.key.as_ngg = key->vs_prolog.as_ngg;
7288 break;
7289 case PIPE_SHADER_TESS_CTRL:
7290 assert(!prolog);
7291 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7292 break;
7293 case PIPE_SHADER_GEOMETRY:
7294 assert(prolog);
7295 shader.key.as_ngg = key->gs_prolog.as_ngg;
7296 break;
7297 case PIPE_SHADER_FRAGMENT:
7298 if (prolog)
7299 shader.key.part.ps.prolog = key->ps_prolog.states;
7300 else
7301 shader.key.part.ps.epilog = key->ps_epilog.states;
7302 break;
7303 default:
7304 unreachable("bad shader part");
7305 }
7306
7307 struct si_shader_context ctx;
7308 si_init_shader_ctx(&ctx, sscreen, compiler,
7309 si_get_wave_size(sscreen, type, shader.key.as_ngg,
7310 shader.key.as_es));
7311 ctx.shader = &shader;
7312 ctx.type = type;
7313
7314 build(&ctx, key);
7315
7316 /* Compile. */
7317 si_llvm_optimize_module(&ctx);
7318
7319 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7320 ctx.ac.module, debug, ctx.type, ctx.ac.wave_size,
7321 name, false)) {
7322 FREE(result);
7323 result = NULL;
7324 goto out;
7325 }
7326
7327 result->next = *list;
7328 *list = result;
7329
7330 out:
7331 si_llvm_dispose(&ctx);
7332 mtx_unlock(&sscreen->shader_parts_mutex);
7333 return result;
7334 }
7335
7336 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7337 {
7338 LLVMValueRef ptr[2], list;
7339 bool merged_shader = is_merged_shader(ctx);
7340
7341 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7342 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7343 ac_array_in_const32_addr_space(ctx->v4i32), "");
7344 return list;
7345 }
7346
7347 /**
7348 * Build the vertex shader prolog function.
7349 *
7350 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7351 * All inputs are returned unmodified. The vertex load indices are
7352 * stored after them, which will be used by the API VS for fetching inputs.
7353 *
7354 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7355 * input_v0,
7356 * input_v1,
7357 * input_v2,
7358 * input_v3,
7359 * (VertexID + BaseVertex),
7360 * (InstanceID + StartInstance),
7361 * (InstanceID / 2 + StartInstance)
7362 */
7363 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7364 union si_shader_part_key *key)
7365 {
7366 struct si_function_info fninfo;
7367 LLVMTypeRef *returns;
7368 LLVMValueRef ret, func;
7369 int num_returns, i;
7370 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7371 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7372 LLVMValueRef input_vgprs[9];
7373 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7374 num_input_vgprs;
7375 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7376
7377 si_init_function_info(&fninfo);
7378
7379 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7380 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7381 sizeof(LLVMTypeRef));
7382 num_returns = 0;
7383
7384 /* Declare input and output SGPRs. */
7385 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7386 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7387 returns[num_returns++] = ctx->i32;
7388 }
7389
7390 /* Preloaded VGPRs (outputs must be floats) */
7391 for (i = 0; i < num_input_vgprs; i++) {
7392 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7393 returns[num_returns++] = ctx->f32;
7394 }
7395
7396 /* Vertex load indices. */
7397 for (i = 0; i <= key->vs_prolog.last_input; i++)
7398 returns[num_returns++] = ctx->f32;
7399
7400 /* Create the function. */
7401 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7402 func = ctx->main_fn;
7403
7404 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7405 if (!key->vs_prolog.is_monolithic)
7406 si_init_exec_from_input(ctx, 3, 0);
7407
7408 if (key->vs_prolog.as_ls &&
7409 ctx->screen->has_ls_vgpr_init_bug) {
7410 /* If there are no HS threads, SPI loads the LS VGPRs
7411 * starting at VGPR 0. Shift them back to where they
7412 * belong.
7413 */
7414 LLVMValueRef has_hs_threads =
7415 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7416 si_unpack_param(ctx, 3, 8, 8),
7417 ctx->i32_0, "");
7418
7419 for (i = 4; i > 0; --i) {
7420 input_vgprs[i + 1] =
7421 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7422 input_vgprs[i + 1],
7423 input_vgprs[i - 1], "");
7424 }
7425 }
7426 }
7427
7428 unsigned vertex_id_vgpr = first_vs_vgpr;
7429 unsigned instance_id_vgpr =
7430 ctx->screen->info.chip_class >= GFX10 ?
7431 first_vs_vgpr + 3 :
7432 first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1);
7433
7434 ctx->abi.vertex_id = input_vgprs[vertex_id_vgpr];
7435 ctx->abi.instance_id = input_vgprs[instance_id_vgpr];
7436
7437 /* InstanceID = VertexID >> 16;
7438 * VertexID = VertexID & 0xffff;
7439 */
7440 if (key->vs_prolog.states.unpack_instance_id_from_vertex_id) {
7441 ctx->abi.instance_id = LLVMBuildLShr(ctx->ac.builder, ctx->abi.vertex_id,
7442 LLVMConstInt(ctx->i32, 16, 0), "");
7443 ctx->abi.vertex_id = LLVMBuildAnd(ctx->ac.builder, ctx->abi.vertex_id,
7444 LLVMConstInt(ctx->i32, 0xffff, 0), "");
7445 }
7446
7447 /* Copy inputs to outputs. This should be no-op, as the registers match,
7448 * but it will prevent the compiler from overwriting them unintentionally.
7449 */
7450 ret = ctx->return_value;
7451 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7452 LLVMValueRef p = LLVMGetParam(func, i);
7453 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7454 }
7455 for (i = 0; i < num_input_vgprs; i++) {
7456 LLVMValueRef p = input_vgprs[i];
7457
7458 if (i == vertex_id_vgpr)
7459 p = ctx->abi.vertex_id;
7460 else if (i == instance_id_vgpr)
7461 p = ctx->abi.instance_id;
7462
7463 p = ac_to_float(&ctx->ac, p);
7464 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7465 key->vs_prolog.num_input_sgprs + i, "");
7466 }
7467
7468 struct lp_build_if_state wrap_if_state;
7469 LLVMValueRef original_ret = ret;
7470 bool wrapped = false;
7471
7472 if (key->vs_prolog.is_monolithic && key->vs_prolog.as_ngg) {
7473 LLVMValueRef num_threads;
7474 LLVMValueRef ena;
7475
7476 num_threads = si_unpack_param(ctx, 3, 0, 8);
7477 ena = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
7478 ac_get_thread_id(&ctx->ac), num_threads, "");
7479 lp_build_if(&wrap_if_state, &ctx->gallivm, ena);
7480 wrapped = true;
7481 }
7482
7483 /* Compute vertex load indices from instance divisors. */
7484 LLVMValueRef instance_divisor_constbuf = NULL;
7485
7486 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7487 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7488 LLVMValueRef buf_index =
7489 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7490 instance_divisor_constbuf =
7491 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7492 }
7493
7494 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7495 bool divisor_is_one =
7496 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7497 bool divisor_is_fetched =
7498 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7499 LLVMValueRef index = NULL;
7500
7501 if (divisor_is_one) {
7502 index = ctx->abi.instance_id;
7503 } else if (divisor_is_fetched) {
7504 LLVMValueRef udiv_factors[4];
7505
7506 for (unsigned j = 0; j < 4; j++) {
7507 udiv_factors[j] =
7508 buffer_load_const(ctx, instance_divisor_constbuf,
7509 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7510 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7511 }
7512 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7513 * Such InstanceID might not be achievable in a reasonable time though.
7514 */
7515 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7516 udiv_factors[0], udiv_factors[1],
7517 udiv_factors[2], udiv_factors[3]);
7518 }
7519
7520 if (divisor_is_one || divisor_is_fetched) {
7521 /* Add StartInstance. */
7522 index = LLVMBuildAdd(ctx->ac.builder, index,
7523 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7524 SI_SGPR_START_INSTANCE), "");
7525 } else {
7526 /* VertexID + BaseVertex */
7527 index = LLVMBuildAdd(ctx->ac.builder,
7528 ctx->abi.vertex_id,
7529 LLVMGetParam(func, user_sgpr_base +
7530 SI_SGPR_BASE_VERTEX), "");
7531 }
7532
7533 index = ac_to_float(&ctx->ac, index);
7534 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7535 fninfo.num_params + i, "");
7536 }
7537
7538 if (wrapped) {
7539 lp_build_endif(&wrap_if_state);
7540
7541 LLVMValueRef values[2] = {
7542 ret,
7543 original_ret
7544 };
7545 LLVMBasicBlockRef bbs[2] = {
7546 wrap_if_state.true_block,
7547 wrap_if_state.entry_block
7548 };
7549 ret = ac_build_phi(&ctx->ac, LLVMTypeOf(ret), 2, values, bbs);
7550 }
7551
7552 si_llvm_build_ret(ctx, ret);
7553 }
7554
7555 static bool si_get_vs_prolog(struct si_screen *sscreen,
7556 struct ac_llvm_compiler *compiler,
7557 struct si_shader *shader,
7558 struct pipe_debug_callback *debug,
7559 struct si_shader *main_part,
7560 const struct si_vs_prolog_bits *key)
7561 {
7562 struct si_shader_selector *vs = main_part->selector;
7563
7564 if (!si_vs_needs_prolog(vs, key))
7565 return true;
7566
7567 /* Get the prolog. */
7568 union si_shader_part_key prolog_key;
7569 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7570 key, shader, &prolog_key);
7571
7572 shader->prolog =
7573 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7574 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7575 debug, si_build_vs_prolog_function,
7576 "Vertex Shader Prolog");
7577 return shader->prolog != NULL;
7578 }
7579
7580 /**
7581 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7582 */
7583 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7584 struct ac_llvm_compiler *compiler,
7585 struct si_shader *shader,
7586 struct pipe_debug_callback *debug)
7587 {
7588 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7589 &shader->key.part.vs.prolog);
7590 }
7591
7592 /**
7593 * Compile the TCS epilog function. This writes tesselation factors to memory
7594 * based on the output primitive type of the tesselator (determined by TES).
7595 */
7596 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7597 union si_shader_part_key *key)
7598 {
7599 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7600 struct si_function_info fninfo;
7601 LLVMValueRef func;
7602
7603 si_init_function_info(&fninfo);
7604
7605 if (ctx->screen->info.chip_class >= GFX9) {
7606 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7607 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7608 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7609 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7610 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7611 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7612 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7613 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7614 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7615 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7616 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7617 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7618 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7619 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7620 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7621 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7622 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7623 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7624 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7625 } else {
7626 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7627 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7628 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7629 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7630 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7631 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7632 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7633 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7634 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7635 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7636 }
7637
7638 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7639 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7640 unsigned tess_factors_idx =
7641 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7642 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7643 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7644
7645 for (unsigned i = 0; i < 6; i++)
7646 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7647
7648 /* Create the function. */
7649 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7650 ctx->screen->info.chip_class >= GFX7 ? 128 : 0);
7651 ac_declare_lds_as_pointer(&ctx->ac);
7652 func = ctx->main_fn;
7653
7654 LLVMValueRef invoc0_tess_factors[6];
7655 for (unsigned i = 0; i < 6; i++)
7656 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7657
7658 si_write_tess_factors(bld_base,
7659 LLVMGetParam(func, tess_factors_idx),
7660 LLVMGetParam(func, tess_factors_idx + 1),
7661 LLVMGetParam(func, tess_factors_idx + 2),
7662 invoc0_tess_factors, invoc0_tess_factors + 4);
7663
7664 LLVMBuildRetVoid(ctx->ac.builder);
7665 }
7666
7667 /**
7668 * Select and compile (or reuse) TCS parts (epilog).
7669 */
7670 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7671 struct ac_llvm_compiler *compiler,
7672 struct si_shader *shader,
7673 struct pipe_debug_callback *debug)
7674 {
7675 if (sscreen->info.chip_class >= GFX9) {
7676 struct si_shader *ls_main_part =
7677 shader->key.part.tcs.ls->main_shader_part_ls;
7678
7679 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7680 &shader->key.part.tcs.ls_prolog))
7681 return false;
7682
7683 shader->previous_stage = ls_main_part;
7684 }
7685
7686 /* Get the epilog. */
7687 union si_shader_part_key epilog_key;
7688 memset(&epilog_key, 0, sizeof(epilog_key));
7689 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7690
7691 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7692 PIPE_SHADER_TESS_CTRL, false,
7693 &epilog_key, compiler, debug,
7694 si_build_tcs_epilog_function,
7695 "Tessellation Control Shader Epilog");
7696 return shader->epilog != NULL;
7697 }
7698
7699 /**
7700 * Select and compile (or reuse) GS parts (prolog).
7701 */
7702 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7703 struct ac_llvm_compiler *compiler,
7704 struct si_shader *shader,
7705 struct pipe_debug_callback *debug)
7706 {
7707 if (sscreen->info.chip_class >= GFX9) {
7708 struct si_shader *es_main_part;
7709 enum pipe_shader_type es_type = shader->key.part.gs.es->type;
7710
7711 if (es_type == PIPE_SHADER_TESS_EVAL && shader->key.as_ngg)
7712 es_main_part = shader->key.part.gs.es->main_shader_part_ngg_es;
7713 else
7714 es_main_part = shader->key.part.gs.es->main_shader_part_es;
7715
7716 if (es_type == PIPE_SHADER_VERTEX &&
7717 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7718 &shader->key.part.gs.vs_prolog))
7719 return false;
7720
7721 shader->previous_stage = es_main_part;
7722 }
7723
7724 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7725 return true;
7726
7727 union si_shader_part_key prolog_key;
7728 memset(&prolog_key, 0, sizeof(prolog_key));
7729 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7730 prolog_key.gs_prolog.as_ngg = shader->key.as_ngg;
7731
7732 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7733 PIPE_SHADER_GEOMETRY, true,
7734 &prolog_key, compiler, debug,
7735 si_build_gs_prolog_function,
7736 "Geometry Shader Prolog");
7737 return shader->prolog2 != NULL;
7738 }
7739
7740 /**
7741 * Build the pixel shader prolog function. This handles:
7742 * - two-side color selection and interpolation
7743 * - overriding interpolation parameters for the API PS
7744 * - polygon stippling
7745 *
7746 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7747 * overriden by other states. (e.g. per-sample interpolation)
7748 * Interpolated colors are stored after the preloaded VGPRs.
7749 */
7750 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7751 union si_shader_part_key *key)
7752 {
7753 struct si_function_info fninfo;
7754 LLVMValueRef ret, func;
7755 int num_returns, i, num_color_channels;
7756
7757 assert(si_need_ps_prolog(key));
7758
7759 si_init_function_info(&fninfo);
7760
7761 /* Declare inputs. */
7762 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7763 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7764
7765 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7766 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7767
7768 /* Declare outputs (same as inputs + add colors if needed) */
7769 num_returns = fninfo.num_params;
7770 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7771 for (i = 0; i < num_color_channels; i++)
7772 fninfo.types[num_returns++] = ctx->f32;
7773
7774 /* Create the function. */
7775 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7776 &fninfo, 0);
7777 func = ctx->main_fn;
7778
7779 /* Copy inputs to outputs. This should be no-op, as the registers match,
7780 * but it will prevent the compiler from overwriting them unintentionally.
7781 */
7782 ret = ctx->return_value;
7783 for (i = 0; i < fninfo.num_params; i++) {
7784 LLVMValueRef p = LLVMGetParam(func, i);
7785 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7786 }
7787
7788 /* Polygon stippling. */
7789 if (key->ps_prolog.states.poly_stipple) {
7790 /* POS_FIXED_PT is always last. */
7791 unsigned pos = key->ps_prolog.num_input_sgprs +
7792 key->ps_prolog.num_input_vgprs - 1;
7793 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7794
7795 si_llvm_emit_polygon_stipple(ctx, list, pos);
7796 }
7797
7798 if (key->ps_prolog.states.bc_optimize_for_persp ||
7799 key->ps_prolog.states.bc_optimize_for_linear) {
7800 unsigned i, base = key->ps_prolog.num_input_sgprs;
7801 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7802
7803 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7804 * The hw doesn't compute CENTROID if the whole wave only
7805 * contains fully-covered quads.
7806 *
7807 * PRIM_MASK is after user SGPRs.
7808 */
7809 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7810 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7811 LLVMConstInt(ctx->i32, 31, 0), "");
7812 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7813 ctx->i1, "");
7814
7815 if (key->ps_prolog.states.bc_optimize_for_persp) {
7816 /* Read PERSP_CENTER. */
7817 for (i = 0; i < 2; i++)
7818 center[i] = LLVMGetParam(func, base + 2 + i);
7819 /* Read PERSP_CENTROID. */
7820 for (i = 0; i < 2; i++)
7821 centroid[i] = LLVMGetParam(func, base + 4 + i);
7822 /* Select PERSP_CENTROID. */
7823 for (i = 0; i < 2; i++) {
7824 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7825 center[i], centroid[i], "");
7826 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7827 tmp, base + 4 + i, "");
7828 }
7829 }
7830 if (key->ps_prolog.states.bc_optimize_for_linear) {
7831 /* Read LINEAR_CENTER. */
7832 for (i = 0; i < 2; i++)
7833 center[i] = LLVMGetParam(func, base + 8 + i);
7834 /* Read LINEAR_CENTROID. */
7835 for (i = 0; i < 2; i++)
7836 centroid[i] = LLVMGetParam(func, base + 10 + i);
7837 /* Select LINEAR_CENTROID. */
7838 for (i = 0; i < 2; i++) {
7839 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7840 center[i], centroid[i], "");
7841 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7842 tmp, base + 10 + i, "");
7843 }
7844 }
7845 }
7846
7847 /* Force per-sample interpolation. */
7848 if (key->ps_prolog.states.force_persp_sample_interp) {
7849 unsigned i, base = key->ps_prolog.num_input_sgprs;
7850 LLVMValueRef persp_sample[2];
7851
7852 /* Read PERSP_SAMPLE. */
7853 for (i = 0; i < 2; i++)
7854 persp_sample[i] = LLVMGetParam(func, base + i);
7855 /* Overwrite PERSP_CENTER. */
7856 for (i = 0; i < 2; i++)
7857 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7858 persp_sample[i], base + 2 + i, "");
7859 /* Overwrite PERSP_CENTROID. */
7860 for (i = 0; i < 2; i++)
7861 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7862 persp_sample[i], base + 4 + i, "");
7863 }
7864 if (key->ps_prolog.states.force_linear_sample_interp) {
7865 unsigned i, base = key->ps_prolog.num_input_sgprs;
7866 LLVMValueRef linear_sample[2];
7867
7868 /* Read LINEAR_SAMPLE. */
7869 for (i = 0; i < 2; i++)
7870 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7871 /* Overwrite LINEAR_CENTER. */
7872 for (i = 0; i < 2; i++)
7873 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7874 linear_sample[i], base + 8 + i, "");
7875 /* Overwrite LINEAR_CENTROID. */
7876 for (i = 0; i < 2; i++)
7877 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7878 linear_sample[i], base + 10 + i, "");
7879 }
7880
7881 /* Force center interpolation. */
7882 if (key->ps_prolog.states.force_persp_center_interp) {
7883 unsigned i, base = key->ps_prolog.num_input_sgprs;
7884 LLVMValueRef persp_center[2];
7885
7886 /* Read PERSP_CENTER. */
7887 for (i = 0; i < 2; i++)
7888 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7889 /* Overwrite PERSP_SAMPLE. */
7890 for (i = 0; i < 2; i++)
7891 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7892 persp_center[i], base + i, "");
7893 /* Overwrite PERSP_CENTROID. */
7894 for (i = 0; i < 2; i++)
7895 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7896 persp_center[i], base + 4 + i, "");
7897 }
7898 if (key->ps_prolog.states.force_linear_center_interp) {
7899 unsigned i, base = key->ps_prolog.num_input_sgprs;
7900 LLVMValueRef linear_center[2];
7901
7902 /* Read LINEAR_CENTER. */
7903 for (i = 0; i < 2; i++)
7904 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7905 /* Overwrite LINEAR_SAMPLE. */
7906 for (i = 0; i < 2; i++)
7907 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7908 linear_center[i], base + 6 + i, "");
7909 /* Overwrite LINEAR_CENTROID. */
7910 for (i = 0; i < 2; i++)
7911 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7912 linear_center[i], base + 10 + i, "");
7913 }
7914
7915 /* Interpolate colors. */
7916 unsigned color_out_idx = 0;
7917 for (i = 0; i < 2; i++) {
7918 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7919 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7920 key->ps_prolog.face_vgpr_index;
7921 LLVMValueRef interp[2], color[4];
7922 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7923
7924 if (!writemask)
7925 continue;
7926
7927 /* If the interpolation qualifier is not CONSTANT (-1). */
7928 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7929 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7930 key->ps_prolog.color_interp_vgpr_index[i];
7931
7932 /* Get the (i,j) updated by bc_optimize handling. */
7933 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7934 interp_vgpr, "");
7935 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7936 interp_vgpr + 1, "");
7937 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7938 }
7939
7940 /* Use the absolute location of the input. */
7941 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7942
7943 if (key->ps_prolog.states.color_two_side) {
7944 face = LLVMGetParam(func, face_vgpr);
7945 face = ac_to_integer(&ctx->ac, face);
7946 }
7947
7948 interp_fs_input(ctx,
7949 key->ps_prolog.color_attr_index[i],
7950 TGSI_SEMANTIC_COLOR, i,
7951 key->ps_prolog.num_interp_inputs,
7952 key->ps_prolog.colors_read, interp_ij,
7953 prim_mask, face, color);
7954
7955 while (writemask) {
7956 unsigned chan = u_bit_scan(&writemask);
7957 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7958 fninfo.num_params + color_out_idx++, "");
7959 }
7960 }
7961
7962 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7963 * says:
7964 *
7965 * "When per-sample shading is active due to the use of a fragment
7966 * input qualified by sample or due to the use of the gl_SampleID
7967 * or gl_SamplePosition variables, only the bit for the current
7968 * sample is set in gl_SampleMaskIn. When state specifies multiple
7969 * fragment shader invocations for a given fragment, the sample
7970 * mask for any single fragment shader invocation may specify a
7971 * subset of the covered samples for the fragment. In this case,
7972 * the bit corresponding to each covered sample will be set in
7973 * exactly one fragment shader invocation."
7974 *
7975 * The samplemask loaded by hardware is always the coverage of the
7976 * entire pixel/fragment, so mask bits out based on the sample ID.
7977 */
7978 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7979 /* The bit pattern matches that used by fixed function fragment
7980 * processing. */
7981 static const uint16_t ps_iter_masks[] = {
7982 0xffff, /* not used */
7983 0x5555,
7984 0x1111,
7985 0x0101,
7986 0x0001,
7987 };
7988 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7989
7990 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7991 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7992 key->ps_prolog.ancillary_vgpr_index;
7993 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7994 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7995
7996 samplemask = ac_to_integer(&ctx->ac, samplemask);
7997 samplemask = LLVMBuildAnd(
7998 ctx->ac.builder,
7999 samplemask,
8000 LLVMBuildShl(ctx->ac.builder,
8001 LLVMConstInt(ctx->i32, ps_iter_mask, false),
8002 sampleid, ""),
8003 "");
8004 samplemask = ac_to_float(&ctx->ac, samplemask);
8005
8006 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
8007 ancillary_vgpr + 1, "");
8008 }
8009
8010 /* Tell LLVM to insert WQM instruction sequence when needed. */
8011 if (key->ps_prolog.wqm) {
8012 LLVMAddTargetDependentFunctionAttr(func,
8013 "amdgpu-ps-wqm-outputs", "");
8014 }
8015
8016 si_llvm_build_ret(ctx, ret);
8017 }
8018
8019 /**
8020 * Build the pixel shader epilog function. This handles everything that must be
8021 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8022 */
8023 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8024 union si_shader_part_key *key)
8025 {
8026 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8027 struct si_function_info fninfo;
8028 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8029 int i;
8030 struct si_ps_exports exp = {};
8031
8032 si_init_function_info(&fninfo);
8033
8034 /* Declare input SGPRs. */
8035 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8036 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8037 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8038 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8039 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
8040
8041 /* Declare input VGPRs. */
8042 unsigned required_num_params =
8043 fninfo.num_sgpr_params +
8044 util_bitcount(key->ps_epilog.colors_written) * 4 +
8045 key->ps_epilog.writes_z +
8046 key->ps_epilog.writes_stencil +
8047 key->ps_epilog.writes_samplemask;
8048
8049 required_num_params = MAX2(required_num_params,
8050 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8051
8052 while (fninfo.num_params < required_num_params)
8053 add_arg(&fninfo, ARG_VGPR, ctx->f32);
8054
8055 /* Create the function. */
8056 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
8057 /* Disable elimination of unused inputs. */
8058 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
8059 "InitialPSInputAddr", 0xffffff);
8060
8061 /* Process colors. */
8062 unsigned vgpr = fninfo.num_sgpr_params;
8063 unsigned colors_written = key->ps_epilog.colors_written;
8064 int last_color_export = -1;
8065
8066 /* Find the last color export. */
8067 if (!key->ps_epilog.writes_z &&
8068 !key->ps_epilog.writes_stencil &&
8069 !key->ps_epilog.writes_samplemask) {
8070 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8071
8072 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8073 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8074 /* Just set this if any of the colorbuffers are enabled. */
8075 if (spi_format &
8076 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8077 last_color_export = 0;
8078 } else {
8079 for (i = 0; i < 8; i++)
8080 if (colors_written & (1 << i) &&
8081 (spi_format >> (i * 4)) & 0xf)
8082 last_color_export = i;
8083 }
8084 }
8085
8086 while (colors_written) {
8087 LLVMValueRef color[4];
8088 int mrt = u_bit_scan(&colors_written);
8089
8090 for (i = 0; i < 4; i++)
8091 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8092
8093 si_export_mrt_color(bld_base, color, mrt,
8094 fninfo.num_params - 1,
8095 mrt == last_color_export, &exp);
8096 }
8097
8098 /* Process depth, stencil, samplemask. */
8099 if (key->ps_epilog.writes_z)
8100 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8101 if (key->ps_epilog.writes_stencil)
8102 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8103 if (key->ps_epilog.writes_samplemask)
8104 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8105
8106 if (depth || stencil || samplemask)
8107 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8108 else if (last_color_export == -1)
8109 ac_build_export_null(&ctx->ac);
8110
8111 if (exp.num)
8112 si_emit_ps_exports(ctx, &exp);
8113
8114 /* Compile. */
8115 LLVMBuildRetVoid(ctx->ac.builder);
8116 }
8117
8118 /**
8119 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8120 */
8121 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8122 struct ac_llvm_compiler *compiler,
8123 struct si_shader *shader,
8124 struct pipe_debug_callback *debug)
8125 {
8126 union si_shader_part_key prolog_key;
8127 union si_shader_part_key epilog_key;
8128
8129 /* Get the prolog. */
8130 si_get_ps_prolog_key(shader, &prolog_key, true);
8131
8132 /* The prolog is a no-op if these aren't set. */
8133 if (si_need_ps_prolog(&prolog_key)) {
8134 shader->prolog =
8135 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8136 PIPE_SHADER_FRAGMENT, true,
8137 &prolog_key, compiler, debug,
8138 si_build_ps_prolog_function,
8139 "Fragment Shader Prolog");
8140 if (!shader->prolog)
8141 return false;
8142 }
8143
8144 /* Get the epilog. */
8145 si_get_ps_epilog_key(shader, &epilog_key);
8146
8147 shader->epilog =
8148 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8149 PIPE_SHADER_FRAGMENT, false,
8150 &epilog_key, compiler, debug,
8151 si_build_ps_epilog_function,
8152 "Fragment Shader Epilog");
8153 if (!shader->epilog)
8154 return false;
8155
8156 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8157 if (shader->key.part.ps.prolog.poly_stipple) {
8158 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8159 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8160 }
8161
8162 /* Set up the enable bits for per-sample shading if needed. */
8163 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8164 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8165 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8166 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8167 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8168 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8169 }
8170 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8171 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8172 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8173 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8174 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8175 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8176 }
8177 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8178 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8179 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8180 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8181 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8182 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8183 }
8184 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8185 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8186 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8187 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8188 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8189 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8190 }
8191
8192 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8193 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8194 !(shader->config.spi_ps_input_ena & 0xf)) {
8195 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8196 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8197 }
8198
8199 /* At least one pair of interpolation weights must be enabled. */
8200 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8201 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8202 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8203 }
8204
8205 /* Samplemask fixup requires the sample ID. */
8206 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
8207 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
8208 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
8209 }
8210
8211 /* The sample mask input is always enabled, because the API shader always
8212 * passes it through to the epilog. Disable it here if it's unused.
8213 */
8214 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8215 !shader->selector->info.reads_samplemask)
8216 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8217
8218 return true;
8219 }
8220
8221 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8222 unsigned *lds_size)
8223 {
8224 /* If tessellation is all offchip and on-chip GS isn't used, this
8225 * workaround is not needed.
8226 */
8227 return;
8228
8229 /* SPI barrier management bug:
8230 * Make sure we have at least 4k of LDS in use to avoid the bug.
8231 * It applies to workgroup sizes of more than one wavefront.
8232 */
8233 if (sscreen->info.family == CHIP_BONAIRE ||
8234 sscreen->info.family == CHIP_KABINI)
8235 *lds_size = MAX2(*lds_size, 8);
8236 }
8237
8238 static void si_fix_resource_usage(struct si_screen *sscreen,
8239 struct si_shader *shader)
8240 {
8241 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8242
8243 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8244
8245 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8246 si_get_max_workgroup_size(shader) > sscreen->compute_wave_size) {
8247 si_multiwave_lds_size_workaround(sscreen,
8248 &shader->config.lds_size);
8249 }
8250 }
8251
8252 bool si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
8253 struct si_shader *shader,
8254 struct pipe_debug_callback *debug)
8255 {
8256 struct si_shader_selector *sel = shader->selector;
8257 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8258 int r;
8259
8260 /* LS, ES, VS are compiled on demand if the main part hasn't been
8261 * compiled for that stage.
8262 *
8263 * GS are compiled on demand if the main part hasn't been compiled
8264 * for the chosen NGG-ness.
8265 *
8266 * Vertex shaders are compiled on demand when a vertex fetch
8267 * workaround must be applied.
8268 */
8269 if (shader->is_monolithic) {
8270 /* Monolithic shader (compiled as a whole, has many variants,
8271 * may take a long time to compile).
8272 */
8273 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
8274 if (r)
8275 return false;
8276 } else {
8277 /* The shader consists of several parts:
8278 *
8279 * - the middle part is the user shader, it has 1 variant only
8280 * and it was compiled during the creation of the shader
8281 * selector
8282 * - the prolog part is inserted at the beginning
8283 * - the epilog part is inserted at the end
8284 *
8285 * The prolog and epilog have many (but simple) variants.
8286 *
8287 * Starting with gfx9, geometry and tessellation control
8288 * shaders also contain the prolog and user shader parts of
8289 * the previous shader stage.
8290 */
8291
8292 if (!mainp)
8293 return false;
8294
8295 /* Copy the compiled TGSI shader data over. */
8296 shader->is_binary_shared = true;
8297 shader->binary = mainp->binary;
8298 shader->config = mainp->config;
8299 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8300 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8301 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8302 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8303 memcpy(shader->info.vs_output_param_offset,
8304 mainp->info.vs_output_param_offset,
8305 sizeof(mainp->info.vs_output_param_offset));
8306 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8307 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8308 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8309
8310 /* Select prologs and/or epilogs. */
8311 switch (sel->type) {
8312 case PIPE_SHADER_VERTEX:
8313 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8314 return false;
8315 break;
8316 case PIPE_SHADER_TESS_CTRL:
8317 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8318 return false;
8319 break;
8320 case PIPE_SHADER_TESS_EVAL:
8321 break;
8322 case PIPE_SHADER_GEOMETRY:
8323 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8324 return false;
8325 break;
8326 case PIPE_SHADER_FRAGMENT:
8327 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8328 return false;
8329
8330 /* Make sure we have at least as many VGPRs as there
8331 * are allocated inputs.
8332 */
8333 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8334 shader->info.num_input_vgprs);
8335 break;
8336 default:;
8337 }
8338
8339 /* Update SGPR and VGPR counts. */
8340 if (shader->prolog) {
8341 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8342 shader->prolog->config.num_sgprs);
8343 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8344 shader->prolog->config.num_vgprs);
8345 }
8346 if (shader->previous_stage) {
8347 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8348 shader->previous_stage->config.num_sgprs);
8349 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8350 shader->previous_stage->config.num_vgprs);
8351 shader->config.spilled_sgprs =
8352 MAX2(shader->config.spilled_sgprs,
8353 shader->previous_stage->config.spilled_sgprs);
8354 shader->config.spilled_vgprs =
8355 MAX2(shader->config.spilled_vgprs,
8356 shader->previous_stage->config.spilled_vgprs);
8357 shader->info.private_mem_vgprs =
8358 MAX2(shader->info.private_mem_vgprs,
8359 shader->previous_stage->info.private_mem_vgprs);
8360 shader->config.scratch_bytes_per_wave =
8361 MAX2(shader->config.scratch_bytes_per_wave,
8362 shader->previous_stage->config.scratch_bytes_per_wave);
8363 shader->info.uses_instanceid |=
8364 shader->previous_stage->info.uses_instanceid;
8365 }
8366 if (shader->prolog2) {
8367 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8368 shader->prolog2->config.num_sgprs);
8369 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8370 shader->prolog2->config.num_vgprs);
8371 }
8372 if (shader->epilog) {
8373 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8374 shader->epilog->config.num_sgprs);
8375 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8376 shader->epilog->config.num_vgprs);
8377 }
8378 si_calculate_max_simd_waves(shader);
8379 }
8380
8381 if (shader->key.as_ngg) {
8382 assert(!shader->key.as_es && !shader->key.as_ls);
8383 gfx10_ngg_calculate_subgroup_info(shader);
8384 } else if (sscreen->info.chip_class >= GFX9 && sel->type == PIPE_SHADER_GEOMETRY) {
8385 gfx9_get_gs_info(shader->previous_stage_sel, sel, &shader->gs_info);
8386 }
8387
8388 si_fix_resource_usage(sscreen, shader);
8389 si_shader_dump(sscreen, shader, debug, stderr, true);
8390
8391 /* Upload. */
8392 if (!si_shader_binary_upload(sscreen, shader, 0)) {
8393 fprintf(stderr, "LLVM failed to upload shader\n");
8394 return false;
8395 }
8396
8397 return true;
8398 }
8399
8400 void si_shader_destroy(struct si_shader *shader)
8401 {
8402 if (shader->scratch_bo)
8403 si_resource_reference(&shader->scratch_bo, NULL);
8404
8405 si_resource_reference(&shader->bo, NULL);
8406
8407 if (!shader->is_binary_shared)
8408 si_shader_binary_clean(&shader->binary);
8409
8410 free(shader->shader_log);
8411 }