src/gallium/drivers/radeonsi/si_shader_internal.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef SI_SHADER_PRIVATE_H
  25 #define SI_SHADER_PRIVATE_H
  26
  27 #include "si_shader.h"
  28 #include "gallivm/lp_bld_init.h"
  29 #include "gallivm/lp_bld_tgsi.h"
  30 #include "tgsi/tgsi_parse.h"
  31 #include "ac_llvm_util.h"
  32 #include "ac_llvm_build.h"
  33
  34 #include <llvm-c/Core.h>
  35 #include <llvm-c/TargetMachine.h>
  36
  37 struct pipe_debug_callback;
  38 struct ac_shader_binary;
  39
  40 #define RADEON_LLVM_MAX_INPUT_SLOTS 32
  41 #define RADEON_LLVM_MAX_INPUTS 32 * 4
  42 #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
  43
  44 #define RADEON_LLVM_INITIAL_CF_DEPTH 4
  45
  46 #define RADEON_LLVM_MAX_SYSTEM_VALUES 11
  47 #define RADEON_LLVM_MAX_ADDRS 16
  48
  49 struct si_llvm_flow;
  50
  51 struct si_shader_context {
  52         struct lp_build_tgsi_context bld_base;
  53         struct gallivm_state gallivm;
  54         struct ac_llvm_context ac;
  55         struct si_shader *shader;
  56         struct si_screen *screen;
  57
  58         unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
  59
  60         /* Whether the prolog will be compiled separately. */
  61         bool separate_prolog;
  62
  63         /** This function is responsible for initilizing the inputs array and will be
  64           * called once for each input declared in the TGSI shader.
  65           */
  66         void (*load_input)(struct si_shader_context *,
  67                            unsigned input_index,
  68                            const struct tgsi_full_declaration *decl,
  69                            LLVMValueRef out[4]);
  70
  71         void (*load_system_value)(struct si_shader_context *,
  72                                   unsigned index,
  73                                   const struct tgsi_full_declaration *decl);
  74
  75         void (*declare_memory_region)(struct si_shader_context *,
  76                                       const struct tgsi_full_declaration *decl);
  77
  78         /** This array contains the input values for the shader.  Typically these
  79           * values will be in the form of a target intrinsic that will inform the
  80           * backend how to load the actual inputs to the shader.
  81           */
  82         struct tgsi_full_declaration input_decls[RADEON_LLVM_MAX_INPUT_SLOTS];
  83         LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
  84         LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
  85         LLVMValueRef addrs[RADEON_LLVM_MAX_ADDRS][TGSI_NUM_CHANNELS];
  86
  87         /** This pointer is used to contain the temporary values.
  88           * The amount of temporary used in tgsi can't be bound to a max value and
  89           * thus we must allocate this array at runtime.
  90           */
  91         LLVMValueRef *temps;
  92         unsigned temps_count;
  93         LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
  94
  95         LLVMValueRef *imms;
  96         unsigned imms_num;
  97
  98         struct si_llvm_flow *flow;
  99         unsigned flow_depth;
 100         unsigned flow_depth_max;
 101
 102         struct tgsi_array_info *temp_arrays;
 103         LLVMValueRef *temp_array_allocas;
 104
 105         LLVMValueRef undef_alloca;
 106
 107         LLVMValueRef main_fn;
 108         LLVMTypeRef return_type;
 109
 110         /* Parameter indices for LLVMGetParam. */
 111         int param_rw_buffers;
 112         int param_const_buffers;
 113         int param_samplers;
 114         int param_images;
 115         int param_shader_buffers;
 116         /* Common inputs for merged shaders. */
 117         int param_merged_wave_info;
 118         int param_merged_scratch_offset;
 119         /* API VS */
 120         int param_vertex_buffers;
 121         int param_base_vertex;
 122         int param_start_instance;
 123         int param_draw_id;
 124         int param_vertex_id;
 125         int param_rel_auto_id;
 126         int param_vs_prim_id;
 127         int param_instance_id;
 128         int param_vertex_index0;
 129         /* VS states and layout of LS outputs / TCS inputs at the end
 130          *   [0] = clamp vertex color
 131          *   [1] = indexed
 132          *   [8:20] = stride between patches in DW = num_inputs * num_vertices * 4
 133          *            max = 32*32*4 + 32*4
 134          *   [24:31] = stride between vertices in DW = num_inputs * 4
 135          *             max = 32*4
 136          */
 137         int param_vs_state_bits;
 138         /* HW VS */
 139         int param_streamout_config;
 140         int param_streamout_write_index;
 141         int param_streamout_offset[4];
 142
 143         /* API TCS & TES */
 144         /* Layout of TCS outputs in the offchip buffer
 145          * # 6 bits
 146          *   [0:5] = the number of patches per threadgroup, max = NUM_PATCHES (40)
 147          * # 6 bits
 148          *   [6:11] = the number of output vertices per patch, max = 32
 149          * # 20 bits
 150          *   [12:31] = the offset of per patch attributes in the buffer in bytes.
 151          *             max = NUM_PATCHES*32*32*16
 152          */
 153         int param_tcs_offchip_layout;
 154
 155         /* API TCS */
 156         /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 157          *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 158          *   [16:31] = TCS output patch0 offset for per-patch / 16
 159          *             max = (NUM_PATCHES + 1) * 32*32
 160          */
 161         int param_tcs_out_lds_offsets;
 162         /* Layout of TCS outputs / TES inputs:
 163          *   [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
 164          *            max = 32*32*4 + 32*4
 165          *   [13:20] = stride between output vertices in DW = num_inputs * 4
 166          *             max = 32*4
 167          *   [26:31] = gl_PatchVerticesIn, max = 32
 168          */
 169         int param_tcs_out_lds_layout;
 170         int param_tcs_offchip_addr_base64k;
 171         int param_tcs_factor_addr_base64k;
 172         int param_tcs_offchip_offset;
 173         int param_tcs_factor_offset;
 174         int param_tcs_patch_id;
 175         int param_tcs_rel_ids;
 176
 177         /* API TES */
 178         int param_tes_u;
 179         int param_tes_v;
 180         int param_tes_rel_patch_id;
 181         int param_tes_patch_id;
 182         /* HW ES */
 183         int param_es2gs_offset;
 184         /* API GS */
 185         int param_gs2vs_offset;
 186         int param_gs_wave_id; /* GFX6 */
 187         int param_gs_vtx0_offset; /* in dwords (GFX6) */
 188         int param_gs_vtx1_offset; /* in dwords (GFX6) */
 189         int param_gs_prim_id;
 190         int param_gs_vtx2_offset; /* in dwords (GFX6) */
 191         int param_gs_vtx3_offset; /* in dwords (GFX6) */
 192         int param_gs_vtx4_offset; /* in dwords (GFX6) */
 193         int param_gs_vtx5_offset; /* in dwords (GFX6) */
 194         int param_gs_instance_id;
 195         int param_gs_vtx01_offset; /* in dwords (GFX9) */
 196         int param_gs_vtx23_offset; /* in dwords (GFX9) */
 197         int param_gs_vtx45_offset; /* in dwords (GFX9) */
 198
 199         LLVMTargetMachineRef tm;
 200
 201         unsigned range_md_kind;
 202         unsigned fpmath_md_kind;
 203         LLVMValueRef fpmath_md_2p5_ulp;
 204
 205         /* Preloaded descriptors. */
 206         LLVMValueRef esgs_ring;
 207         LLVMValueRef gsvs_ring[4];
 208
 209         LLVMValueRef lds;
 210         LLVMValueRef gs_next_vertex[4];
 211         LLVMValueRef return_value;
 212
 213         LLVMTypeRef voidt;
 214         LLVMTypeRef i1;
 215         LLVMTypeRef i8;
 216         LLVMTypeRef i32;
 217         LLVMTypeRef i64;
 218         LLVMTypeRef i128;
 219         LLVMTypeRef f32;
 220         LLVMTypeRef v16i8;
 221         LLVMTypeRef v2i32;
 222         LLVMTypeRef v4i32;
 223         LLVMTypeRef v4f32;
 224         LLVMTypeRef v8i32;
 225
 226         LLVMValueRef i32_0;
 227         LLVMValueRef i32_1;
 228
 229         LLVMValueRef shared_memory;
 230 };
 231
 232 static inline struct si_shader_context *
 233 si_shader_context(struct lp_build_tgsi_context *bld_base)
 234 {
 235         return (struct si_shader_context*)bld_base;
 236 }
 237
 238 void si_llvm_add_attribute(LLVMValueRef F, const char *name, int value);
 239 void si_llvm_shader_type(LLVMValueRef F, unsigned type);
 240
 241 LLVMTargetRef si_llvm_get_amdgpu_target(const char *triple);
 242
 243 unsigned si_llvm_compile(LLVMModuleRef M, struct ac_shader_binary *binary,
 244                          LLVMTargetMachineRef tm,
 245                          struct pipe_debug_callback *debug);
 246
 247 LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
 248                           enum tgsi_opcode_type type);
 249
 250 LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
 251                      enum tgsi_opcode_type type, LLVMValueRef value);
 252
 253 LLVMValueRef si_llvm_bound_index(struct si_shader_context *ctx,
 254                                  LLVMValueRef index,
 255                                  unsigned num);
 256
 257 void si_llvm_context_init(struct si_shader_context *ctx,
 258                           struct si_screen *sscreen,
 259                           LLVMTargetMachineRef tm);
 260 void si_llvm_context_set_tgsi(struct si_shader_context *ctx,
 261                               struct si_shader *shader);
 262
 263 void si_llvm_create_func(struct si_shader_context *ctx,
 264                          const char *name,
 265                          LLVMTypeRef *return_types, unsigned num_return_elems,
 266                          LLVMTypeRef *ParamTypes, unsigned ParamCount);
 267
 268 void si_llvm_dispose(struct si_shader_context *ctx);
 269
 270 void si_llvm_finalize_module(struct si_shader_context *ctx,
 271                              bool run_verifier);
 272
 273 LLVMValueRef si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
 274                                       enum tgsi_opcode_type type,
 275                                       LLVMValueRef ptr,
 276                                       LLVMValueRef ptr2);
 277
 278 LLVMValueRef si_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
 279                                 const struct tgsi_full_src_register *reg,
 280                                 enum tgsi_opcode_type type,
 281                                 unsigned swizzle);
 282
 283 void si_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
 284                         const struct tgsi_full_instruction *inst,
 285                         const struct tgsi_opcode_info *info,
 286                         LLVMValueRef dst[4]);
 287
 288 void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
 289
 290 #endif