src/gallium/drivers/radeonsi/si_shader_internal.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef SI_SHADER_PRIVATE_H
  25 #define SI_SHADER_PRIVATE_H
  26
  27 #include "si_shader.h"
  28 #include "gallivm/lp_bld_flow.h"
  29 #include "gallivm/lp_bld_init.h"
  30 #include "gallivm/lp_bld_tgsi.h"
  31 #include "tgsi/tgsi_parse.h"
  32 #include "ac_shader_abi.h"
  33 #include "ac_llvm_util.h"
  34 #include "ac_llvm_build.h"
  35
  36 #include <llvm-c/Core.h>
  37 #include <llvm-c/TargetMachine.h>
  38
  39 struct pipe_debug_callback;
  40 struct ac_shader_binary;
  41
  42 #define RADEON_LLVM_MAX_INPUT_SLOTS 32
  43 #define RADEON_LLVM_MAX_INPUTS 32 * 4
  44 #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
  45
  46 #define RADEON_LLVM_INITIAL_CF_DEPTH 4
  47
  48 #define RADEON_LLVM_MAX_SYSTEM_VALUES 11
  49 #define RADEON_LLVM_MAX_ADDRS 16
  50
  51 struct si_llvm_flow;
  52
  53 struct si_shader_context {
  54         struct lp_build_tgsi_context bld_base;
  55         struct gallivm_state gallivm;
  56         struct ac_llvm_context ac;
  57         struct si_shader *shader;
  58         struct si_screen *screen;
  59
  60         unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
  61
  62         /* For clamping the non-constant index in resource indexing: */
  63         unsigned num_const_buffers;
  64         unsigned num_shader_buffers;
  65         unsigned num_images;
  66         unsigned num_samplers;
  67
  68         /* Whether the prolog will be compiled separately. */
  69         bool separate_prolog;
  70
  71         struct ac_shader_abi abi;
  72
  73         /** This function is responsible for initilizing the inputs array and will be
  74           * called once for each input declared in the TGSI shader.
  75           */
  76         void (*load_input)(struct si_shader_context *,
  77                            unsigned input_index,
  78                            const struct tgsi_full_declaration *decl,
  79                            LLVMValueRef out[4]);
  80
  81         void (*load_system_value)(struct si_shader_context *,
  82                                   unsigned index,
  83                                   const struct tgsi_full_declaration *decl);
  84
  85         void (*declare_memory_region)(struct si_shader_context *,
  86                                       const struct tgsi_full_declaration *decl);
  87
  88         /** This array contains the input values for the shader.  Typically these
  89           * values will be in the form of a target intrinsic that will inform the
  90           * backend how to load the actual inputs to the shader.
  91           */
  92         struct tgsi_full_declaration input_decls[RADEON_LLVM_MAX_INPUT_SLOTS];
  93         LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
  94         LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
  95         LLVMValueRef addrs[RADEON_LLVM_MAX_ADDRS][TGSI_NUM_CHANNELS];
  96
  97         /** This pointer is used to contain the temporary values.
  98           * The amount of temporary used in tgsi can't be bound to a max value and
  99           * thus we must allocate this array at runtime.
 100           */
 101         LLVMValueRef *temps;
 102         unsigned temps_count;
 103         LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
 104
 105         LLVMValueRef *imms;
 106         unsigned imms_num;
 107
 108         struct si_llvm_flow *flow;
 109         unsigned flow_depth;
 110         unsigned flow_depth_max;
 111
 112         struct lp_build_if_state merged_wrap_if_state;
 113
 114         struct tgsi_array_info *temp_arrays;
 115         LLVMValueRef *temp_array_allocas;
 116
 117         LLVMValueRef undef_alloca;
 118
 119         LLVMValueRef main_fn;
 120         LLVMTypeRef return_type;
 121
 122         /* Parameter indices for LLVMGetParam. */
 123         int param_rw_buffers;
 124         int param_const_and_shader_buffers;
 125         int param_samplers_and_images;
 126         /* Common inputs for merged shaders. */
 127         int param_merged_wave_info;
 128         int param_merged_scratch_offset;
 129         /* API VS */
 130         int param_vertex_buffers;
 131         int param_rel_auto_id;
 132         int param_vs_prim_id;
 133         int param_vertex_index0;
 134         /* VS states and layout of LS outputs / TCS inputs at the end
 135          *   [0] = clamp vertex color
 136          *   [1] = indexed
 137          *   [8:20] = stride between patches in DW = num_inputs * num_vertices * 4
 138          *            max = 32*32*4 + 32*4
 139          *   [24:31] = stride between vertices in DW = num_inputs * 4
 140          *             max = 32*4
 141          */
 142         int param_vs_state_bits;
 143         /* HW VS */
 144         int param_streamout_config;
 145         int param_streamout_write_index;
 146         int param_streamout_offset[4];
 147
 148         /* API TCS & TES */
 149         /* Layout of TCS outputs in the offchip buffer
 150          * # 6 bits
 151          *   [0:5] = the number of patches per threadgroup, max = NUM_PATCHES (40)
 152          * # 6 bits
 153          *   [6:11] = the number of output vertices per patch, max = 32
 154          * # 20 bits
 155          *   [12:31] = the offset of per patch attributes in the buffer in bytes.
 156          *             max = NUM_PATCHES*32*32*16
 157          */
 158         int param_tcs_offchip_layout;
 159
 160         /* API TCS */
 161         /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 162          *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 163          *   [16:31] = TCS output patch0 offset for per-patch / 16
 164          *             max = (NUM_PATCHES + 1) * 32*32
 165          */
 166         int param_tcs_out_lds_offsets;
 167         /* Layout of TCS outputs / TES inputs:
 168          *   [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
 169          *            max = 32*32*4 + 32*4
 170          *   [13:20] = stride between output vertices in DW = num_inputs * 4
 171          *             max = 32*4
 172          *   [26:31] = gl_PatchVerticesIn, max = 32
 173          */
 174         int param_tcs_out_lds_layout;
 175         int param_tcs_offchip_addr_base64k;
 176         int param_tcs_factor_addr_base64k;
 177         int param_tcs_offchip_offset;
 178         int param_tcs_factor_offset;
 179         int param_tcs_patch_id;
 180         int param_tcs_rel_ids;
 181
 182         /* API TES */
 183         int param_tes_u;
 184         int param_tes_v;
 185         int param_tes_rel_patch_id;
 186         int param_tes_patch_id;
 187         /* HW ES */
 188         int param_es2gs_offset;
 189         /* API GS */
 190         int param_gs2vs_offset;
 191         int param_gs_wave_id; /* GFX6 */
 192         int param_gs_vtx0_offset; /* in dwords (GFX6) */
 193         int param_gs_vtx1_offset; /* in dwords (GFX6) */
 194         int param_gs_prim_id;
 195         int param_gs_vtx2_offset; /* in dwords (GFX6) */
 196         int param_gs_vtx3_offset; /* in dwords (GFX6) */
 197         int param_gs_vtx4_offset; /* in dwords (GFX6) */
 198         int param_gs_vtx5_offset; /* in dwords (GFX6) */
 199         int param_gs_instance_id;
 200         int param_gs_vtx01_offset; /* in dwords (GFX9) */
 201         int param_gs_vtx23_offset; /* in dwords (GFX9) */
 202         int param_gs_vtx45_offset; /* in dwords (GFX9) */
 203         /* CS */
 204         int param_grid_size;
 205         int param_block_size;
 206         int param_block_id[3];
 207         int param_thread_id;
 208
 209         LLVMTargetMachineRef tm;
 210
 211         unsigned range_md_kind;
 212         unsigned fpmath_md_kind;
 213         LLVMValueRef fpmath_md_2p5_ulp;
 214
 215         /* Preloaded descriptors. */
 216         LLVMValueRef esgs_ring;
 217         LLVMValueRef gsvs_ring[4];
 218
 219         LLVMValueRef lds;
 220         LLVMValueRef gs_next_vertex[4];
 221         LLVMValueRef postponed_kill;
 222         LLVMValueRef return_value;
 223
 224         LLVMTypeRef voidt;
 225         LLVMTypeRef i1;
 226         LLVMTypeRef i8;
 227         LLVMTypeRef i32;
 228         LLVMTypeRef i64;
 229         LLVMTypeRef i128;
 230         LLVMTypeRef f32;
 231         LLVMTypeRef v2i32;
 232         LLVMTypeRef v4i32;
 233         LLVMTypeRef v4f32;
 234         LLVMTypeRef v8i32;
 235
 236         LLVMValueRef i32_0;
 237         LLVMValueRef i32_1;
 238
 239         LLVMValueRef shared_memory;
 240 };
 241
 242 static inline struct si_shader_context *
 243 si_shader_context(struct lp_build_tgsi_context *bld_base)
 244 {
 245         return (struct si_shader_context*)bld_base;
 246 }
 247
 248 static inline struct si_shader_context *
 249 si_shader_context_from_abi(struct ac_shader_abi *abi)
 250 {
 251         struct si_shader_context *ctx = NULL;
 252         return container_of(abi, ctx, abi);
 253 }
 254
 255 void si_llvm_add_attribute(LLVMValueRef F, const char *name, int value);
 256
 257 unsigned si_llvm_compile(LLVMModuleRef M, struct ac_shader_binary *binary,
 258                          LLVMTargetMachineRef tm,
 259                          struct pipe_debug_callback *debug);
 260
 261 LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
 262                           enum tgsi_opcode_type type);
 263
 264 LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
 265                      enum tgsi_opcode_type type, LLVMValueRef value);
 266
 267 LLVMValueRef si_llvm_bound_index(struct si_shader_context *ctx,
 268                                  LLVMValueRef index,
 269                                  unsigned num);
 270
 271 void si_llvm_context_init(struct si_shader_context *ctx,
 272                           struct si_screen *sscreen,
 273                           LLVMTargetMachineRef tm);
 274 void si_llvm_context_set_tgsi(struct si_shader_context *ctx,
 275                               struct si_shader *shader);
 276
 277 void si_llvm_create_func(struct si_shader_context *ctx,
 278                          const char *name,
 279                          LLVMTypeRef *return_types, unsigned num_return_elems,
 280                          LLVMTypeRef *ParamTypes, unsigned ParamCount);
 281
 282 void si_llvm_dispose(struct si_shader_context *ctx);
 283
 284 void si_llvm_optimize_module(struct si_shader_context *ctx);
 285
 286 LLVMValueRef si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
 287                                       enum tgsi_opcode_type type,
 288                                       LLVMValueRef ptr,
 289                                       LLVMValueRef ptr2);
 290
 291 LLVMValueRef si_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
 292                                 const struct tgsi_full_src_register *reg,
 293                                 enum tgsi_opcode_type type,
 294                                 unsigned swizzle);
 295
 296 void si_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
 297                         const struct tgsi_full_instruction *inst,
 298                         const struct tgsi_opcode_info *info,
 299                         LLVMValueRef dst[4]);
 300
 301 /* Combine these with & instead of |. */
 302 #define NOOP_WAITCNT 0xf7f
 303 #define LGKM_CNT 0x07f
 304 #define VM_CNT 0xf70
 305
 306 void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16);
 307
 308 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
 309                                            const struct tgsi_ind_register *ind,
 310                                            int rel_index, unsigned num);
 311
 312 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements);
 313
 314 void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
 315 void si_shader_context_init_mem(struct si_shader_context *ctx);
 316
 317 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir);
 318
 319 #endif