radeonsi: put up to 5 VBO descriptors into user SGPRs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_internal.h
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef SI_SHADER_PRIVATE_H
26 #define SI_SHADER_PRIVATE_H
27
28 #include "si_shader.h"
29 #include "ac_shader_abi.h"
30
31 #include <llvm-c/Core.h>
32 #include <llvm-c/TargetMachine.h>
33
34 struct pipe_debug_callback;
35
36 #define RADEON_LLVM_MAX_INPUTS 32 * 4
37
38 struct si_shader_output_values {
39 LLVMValueRef values[4];
40 unsigned semantic_name;
41 unsigned semantic_index;
42 ubyte vertex_stream[4];
43 };
44
45 struct si_shader_context {
46 struct ac_llvm_context ac;
47 struct si_shader *shader;
48 struct si_screen *screen;
49
50 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
51
52 /* For clamping the non-constant index in resource indexing: */
53 unsigned num_const_buffers;
54 unsigned num_shader_buffers;
55 unsigned num_images;
56 unsigned num_samplers;
57
58 struct ac_shader_args args;
59 struct ac_shader_abi abi;
60
61 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
62
63 LLVMBasicBlockRef merged_wrap_if_entry_block;
64 int merged_wrap_if_label;
65
66 LLVMValueRef main_fn;
67 LLVMTypeRef return_type;
68
69 struct ac_arg const_and_shader_buffers;
70 struct ac_arg samplers_and_images;
71
72 /* For merged shaders, the per-stage descriptors for the stage other
73 * than the one we're processing, used to pass them through from the
74 * first stage to the second.
75 */
76 struct ac_arg other_const_and_shader_buffers;
77 struct ac_arg other_samplers_and_images;
78
79 struct ac_arg rw_buffers;
80 struct ac_arg bindless_samplers_and_images;
81 /* Common inputs for merged shaders. */
82 struct ac_arg merged_wave_info;
83 struct ac_arg merged_scratch_offset;
84 /* API VS */
85 struct ac_arg vertex_buffers;
86 struct ac_arg vb_descriptors[5];
87 struct ac_arg rel_auto_id;
88 struct ac_arg vs_prim_id;
89 struct ac_arg vertex_index0;
90 /* VS states and layout of LS outputs / TCS inputs at the end
91 * [0] = clamp vertex color
92 * [1] = indexed
93 * [8:20] = stride between patches in DW = num_inputs * num_vertices * 4
94 * max = 32*32*4 + 32*4
95 * [24:31] = stride between vertices in DW = num_inputs * 4
96 * max = 32*4
97 */
98 struct ac_arg vs_state_bits;
99 struct ac_arg vs_blit_inputs;
100 /* HW VS */
101 struct ac_arg streamout_config;
102 struct ac_arg streamout_write_index;
103 struct ac_arg streamout_offset[4];
104
105 /* API TCS & TES */
106 /* Layout of TCS outputs in the offchip buffer
107 * # 6 bits
108 * [0:5] = the number of patches per threadgroup, max = NUM_PATCHES (40)
109 * # 6 bits
110 * [6:11] = the number of output vertices per patch, max = 32
111 * # 20 bits
112 * [12:31] = the offset of per patch attributes in the buffer in bytes.
113 * max = NUM_PATCHES*32*32*16
114 */
115 struct ac_arg tcs_offchip_layout;
116
117 /* API TCS */
118 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
119 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
120 * [16:31] = TCS output patch0 offset for per-patch / 16
121 * max = (NUM_PATCHES + 1) * 32*32
122 */
123 struct ac_arg tcs_out_lds_offsets;
124 /* Layout of TCS outputs / TES inputs:
125 * [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4
126 * max = 32*32*4 + 32*4
127 * [13:18] = gl_PatchVerticesIn, max = 32
128 * [19:31] = high 13 bits of the 32-bit address of tessellation ring buffers
129 */
130 struct ac_arg tcs_out_lds_layout;
131 struct ac_arg tcs_offchip_offset;
132 struct ac_arg tcs_factor_offset;
133
134 /* API TES */
135 struct ac_arg tes_offchip_addr;
136 struct ac_arg tes_u;
137 struct ac_arg tes_v;
138 struct ac_arg tes_rel_patch_id;
139 /* HW ES */
140 struct ac_arg es2gs_offset;
141 /* HW GS */
142 /* On gfx10:
143 * - bits 0..11: ordered_wave_id
144 * - bits 12..20: number of vertices in group
145 * - bits 22..30: number of primitives in group
146 */
147 struct ac_arg gs_tg_info;
148 /* API GS */
149 struct ac_arg gs2vs_offset;
150 struct ac_arg gs_wave_id; /* GFX6 */
151 struct ac_arg gs_vtx_offset[6]; /* in dwords (GFX6) */
152 struct ac_arg gs_vtx01_offset; /* in dwords (GFX9) */
153 struct ac_arg gs_vtx23_offset; /* in dwords (GFX9) */
154 struct ac_arg gs_vtx45_offset; /* in dwords (GFX9) */
155 /* PS */
156 struct ac_arg pos_fixed_pt;
157 /* CS */
158 struct ac_arg block_size;
159 struct ac_arg cs_user_data;
160
161 struct ac_llvm_compiler *compiler;
162
163 /* Preloaded descriptors. */
164 LLVMValueRef esgs_ring;
165 LLVMValueRef gsvs_ring[4];
166 LLVMValueRef tess_offchip_ring;
167
168 LLVMValueRef invoc0_tess_factors[6]; /* outer[4], inner[2] */
169 LLVMValueRef gs_next_vertex[4];
170 LLVMValueRef gs_curprim_verts[4];
171 LLVMValueRef gs_generated_prims[4];
172 LLVMValueRef gs_ngg_emit;
173 LLVMValueRef gs_ngg_scratch;
174 LLVMValueRef postponed_kill;
175 LLVMValueRef return_value;
176
177 LLVMTypeRef voidt;
178 LLVMTypeRef i1;
179 LLVMTypeRef i8;
180 LLVMTypeRef i32;
181 LLVMTypeRef i64;
182 LLVMTypeRef i128;
183 LLVMTypeRef f32;
184 LLVMTypeRef v2i32;
185 LLVMTypeRef v4i32;
186 LLVMTypeRef v4f32;
187 LLVMTypeRef v8i32;
188
189 LLVMValueRef i32_0;
190 LLVMValueRef i32_1;
191 LLVMValueRef i1false;
192 LLVMValueRef i1true;
193 };
194
195 static inline struct si_shader_context *
196 si_shader_context_from_abi(struct ac_shader_abi *abi)
197 {
198 struct si_shader_context *ctx = NULL;
199 return container_of(abi, ctx, abi);
200 }
201
202 void si_create_function(struct si_shader_context *ctx,
203 const char *name,
204 LLVMTypeRef *returns, unsigned num_returns,
205 unsigned max_workgroup_size);
206 unsigned si_llvm_compile(LLVMModuleRef M, struct si_shader_binary *binary,
207 struct ac_llvm_compiler *compiler,
208 struct pipe_debug_callback *debug,
209 bool less_optimized, unsigned wave_size);
210
211 LLVMValueRef si_llvm_bound_index(struct si_shader_context *ctx,
212 LLVMValueRef index,
213 unsigned num);
214
215 void si_llvm_context_init(struct si_shader_context *ctx,
216 struct si_screen *sscreen,
217 struct ac_llvm_compiler *compiler,
218 unsigned wave_size,
219 unsigned ballot_mask_bits);
220 void si_llvm_context_set_ir(struct si_shader_context *ctx,
221 struct si_shader *shader);
222
223 void si_llvm_create_func(struct si_shader_context *ctx,
224 const char *name,
225 LLVMTypeRef *return_types, unsigned num_return_elems);
226
227 void si_llvm_dispose(struct si_shader_context *ctx);
228
229 void si_llvm_optimize_module(struct si_shader_context *ctx);
230
231 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
232 LLVMTypeRef type,
233 LLVMValueRef vertex_index,
234 LLVMValueRef param_index,
235 unsigned const_index,
236 unsigned location,
237 unsigned driver_location,
238 unsigned component,
239 unsigned num_components,
240 bool is_patch,
241 bool is_compact,
242 bool load_input);
243 LLVMValueRef si_nir_lookup_interp_param(struct ac_shader_abi *abi,
244 enum glsl_interp_mode interp,
245 unsigned location);
246 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx);
247 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
248 LLVMValueRef list, LLVMValueRef index,
249 enum ac_descriptor_type type);
250 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
251 LLVMValueRef list, LLVMValueRef index,
252 enum ac_descriptor_type desc_type,
253 bool uses_store, bool bindless);
254 LLVMValueRef si_nir_emit_fbfetch(struct ac_shader_abi *abi);
255 void si_declare_compute_memory(struct si_shader_context *ctx);
256 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
257 unsigned swizzle);
258 void si_llvm_export_vs(struct si_shader_context *ctx,
259 struct si_shader_output_values *outputs,
260 unsigned noutput);
261 void si_emit_streamout_output(struct si_shader_context *ctx,
262 LLVMValueRef const *so_buffers,
263 LLVMValueRef const *so_write_offsets,
264 struct pipe_stream_output *stream_out,
265 struct si_shader_output_values *shader_out);
266
267 void si_llvm_load_input_vs(
268 struct si_shader_context *ctx,
269 unsigned input_index,
270 LLVMValueRef out[4]);
271
272 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir);
273
274 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
275 struct ac_arg param, unsigned rshift,
276 unsigned bitwidth);
277 LLVMValueRef si_is_es_thread(struct si_shader_context *ctx);
278 LLVMValueRef si_is_gs_thread(struct si_shader_context *ctx);
279
280 void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi,
281 unsigned max_outputs,
282 LLVMValueRef *addrs);
283 void gfx10_ngg_gs_emit_vertex(struct si_shader_context *ctx,
284 unsigned stream,
285 LLVMValueRef *addrs);
286 void gfx10_ngg_gs_emit_prologue(struct si_shader_context *ctx);
287 void gfx10_ngg_gs_emit_epilogue(struct si_shader_context *ctx);
288 void gfx10_ngg_calculate_subgroup_info(struct si_shader *shader);
289
290 #endif