src/gallium/drivers/radeonsi/si_shader_nir.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "ac_nir_to_llvm.h"
  26 #include "compiler/nir/nir.h"
  27 #include "compiler/nir/nir_builder.h"
  28 #include "compiler/nir/nir_deref.h"
  29 #include "compiler/nir_types.h"
  30 #include "si_pipe.h"
  31 #include "si_shader_internal.h"
  32 #include "tgsi/tgsi_from_mesa.h"
  33
  34 static const nir_deref_instr *tex_get_texture_deref(nir_tex_instr *instr)
  35 {
  36    for (unsigned i = 0; i < instr->num_srcs; i++) {
  37       switch (instr->src[i].src_type) {
  38       case nir_tex_src_texture_deref:
  39          return nir_src_as_deref(instr->src[i].src);
  40       default:
  41          break;
  42       }
  43    }
  44
  45    return NULL;
  46 }
  47
  48 static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr,
  49                           bool is_input)
  50 {
  51    unsigned interp = INTERP_MODE_FLAT; /* load_input uses flat shading */
  52
  53    if (intr->intrinsic == nir_intrinsic_load_interpolated_input) {
  54       nir_intrinsic_instr *baryc = nir_instr_as_intrinsic(intr->src[0].ssa->parent_instr);
  55
  56       if (baryc) {
  57          if (nir_intrinsic_infos[baryc->intrinsic].index_map[NIR_INTRINSIC_INTERP_MODE] > 0)
  58             interp = nir_intrinsic_interp_mode(baryc);
  59          else
  60             unreachable("unknown barycentric intrinsic");
  61       } else {
  62          unreachable("unknown barycentric expression");
  63       }
  64    }
  65
  66    unsigned mask, bit_size;
  67    bool dual_slot, is_output_load;
  68
  69    if (nir_intrinsic_infos[intr->intrinsic].index_map[NIR_INTRINSIC_WRMASK] > 0) {
  70       mask = nir_intrinsic_write_mask(intr); /* store */
  71       bit_size = nir_src_bit_size(intr->src[0]);
  72       dual_slot = bit_size == 64 && nir_src_num_components(intr->src[0]) >= 3;
  73       is_output_load = false;
  74    } else {
  75       mask = nir_ssa_def_components_read(&intr->dest.ssa); /* load */
  76       bit_size = intr->dest.ssa.bit_size;
  77       dual_slot = bit_size == 64 && intr->dest.ssa.num_components >= 3;
  78       is_output_load = !is_input;
  79    }
  80
  81    /* Convert the 64-bit component mask to a 32-bit component mask. */
  82    if (bit_size == 64) {
  83       unsigned new_mask = 0;
  84       for (unsigned i = 0; i < 4; i++) {
  85          if (mask & (1 << i))
  86             new_mask |= 0x3 << (2 * i);
  87       }
  88       mask = new_mask;
  89    }
  90
  91    /* Convert the 16-bit component mask to a 32-bit component mask. */
  92    if (bit_size == 16) {
  93       unsigned new_mask = 0;
  94       for (unsigned i = 0; i < 4; i++) {
  95          if (mask & (1 << i))
  96             new_mask |= 0x1 << (i / 2);
  97       }
  98       mask = new_mask;
  99    }
 100
 101    mask <<= nir_intrinsic_component(intr);
 102
 103    nir_src offset = *nir_get_io_offset_src(intr);
 104    bool indirect = !nir_src_is_const(offset);
 105    if (!indirect)
 106       assert(nir_src_as_uint(offset) == 0);
 107
 108    unsigned semantic = 0;
 109    /* VS doesn't have semantics. */
 110    if (info->stage != MESA_SHADER_VERTEX || !is_input)
 111       semantic = nir_intrinsic_io_semantics(intr).location;
 112
 113    if (info->stage == MESA_SHADER_FRAGMENT && !is_input) {
 114       /* Never use FRAG_RESULT_COLOR directly. */
 115       if (semantic == FRAG_RESULT_COLOR) {
 116          semantic = FRAG_RESULT_DATA0;
 117          info->color0_writes_all_cbufs = true;
 118       }
 119       semantic += nir_intrinsic_io_semantics(intr).dual_source_blend_index;
 120    }
 121
 122    unsigned driver_location = nir_intrinsic_base(intr);
 123    unsigned num_slots = indirect ? nir_intrinsic_io_semantics(intr).num_slots : (1 + dual_slot);
 124
 125    if (is_input) {
 126       assert(driver_location + num_slots <= ARRAY_SIZE(info->input_usage_mask));
 127
 128       for (unsigned i = 0; i < num_slots; i++) {
 129          unsigned loc = driver_location + i;
 130          unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
 131
 132          info->input_semantic[loc] = semantic + i;
 133          info->input_interpolate[loc] = interp;
 134
 135          if (slot_mask) {
 136             info->input_usage_mask[loc] |= slot_mask;
 137             info->num_inputs = MAX2(info->num_inputs, loc + 1);
 138
 139             if (semantic == VARYING_SLOT_PRIMITIVE_ID)
 140                info->uses_primid = true;
 141          }
 142       }
 143    } else {
 144       /* Outputs. */
 145       assert(driver_location + num_slots <= ARRAY_SIZE(info->output_usagemask));
 146       assert(semantic + num_slots < ARRAY_SIZE(info->output_semantic_to_slot));
 147
 148       for (unsigned i = 0; i < num_slots; i++) {
 149          unsigned loc = driver_location + i;
 150          unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
 151
 152          info->output_semantic[loc] = semantic + i;
 153          info->output_semantic_to_slot[semantic + i] = loc;
 154
 155          if (is_output_load) {
 156             /* Output loads have only a few things that we need to track. */
 157             info->output_readmask[loc] |= slot_mask;
 158
 159             if (info->stage == MESA_SHADER_FRAGMENT &&
 160                 nir_intrinsic_io_semantics(intr).fb_fetch_output)
 161                info->uses_fbfetch = true;
 162          } else if (slot_mask) {
 163             /* Output stores. */
 164             if (info->stage == MESA_SHADER_GEOMETRY) {
 165                unsigned gs_streams = (uint32_t)nir_intrinsic_io_semantics(intr).gs_streams <<
 166                                      (nir_intrinsic_component(intr) * 2);
 167                unsigned new_mask = slot_mask & ~info->output_usagemask[loc];
 168
 169                for (unsigned i = 0; i < 4; i++) {
 170                   unsigned stream = (gs_streams >> (i * 2)) & 0x3;
 171
 172                   if (new_mask & (1 << i)) {
 173                      info->output_streams[loc] |= stream << (i * 2);
 174                      info->num_stream_output_components[stream]++;
 175                   }
 176                }
 177             }
 178
 179             info->output_usagemask[loc] |= slot_mask;
 180             info->num_outputs = MAX2(info->num_outputs, loc + 1);
 181
 182             if (info->stage == MESA_SHADER_FRAGMENT) {
 183                switch (semantic) {
 184                case FRAG_RESULT_DEPTH:
 185                   info->writes_z = true;
 186                   break;
 187                case FRAG_RESULT_STENCIL:
 188                   info->writes_stencil = true;
 189                   break;
 190                case FRAG_RESULT_SAMPLE_MASK:
 191                   info->writes_samplemask = true;
 192                   break;
 193                default:
 194                   if (semantic >= FRAG_RESULT_DATA0 && semantic <= FRAG_RESULT_DATA7) {
 195                      unsigned index = semantic - FRAG_RESULT_DATA0;
 196                      info->colors_written |= 1 << (index + i);
 197                   }
 198                   break;
 199                }
 200             } else {
 201                switch (semantic) {
 202                case VARYING_SLOT_PRIMITIVE_ID:
 203                   info->writes_primid = true;
 204                   break;
 205                case VARYING_SLOT_VIEWPORT:
 206                   info->writes_viewport_index = true;
 207                   break;
 208                case VARYING_SLOT_LAYER:
 209                   info->writes_layer = true;
 210                   break;
 211                case VARYING_SLOT_PSIZ:
 212                   info->writes_psize = true;
 213                   break;
 214                case VARYING_SLOT_CLIP_VERTEX:
 215                   info->writes_clipvertex = true;
 216                   break;
 217                case VARYING_SLOT_EDGE:
 218                   info->writes_edgeflag = true;
 219                   break;
 220                case VARYING_SLOT_POS:
 221                   info->writes_position = true;
 222                   break;
 223                }
 224             }
 225          }
 226       }
 227    }
 228 }
 229
 230 static void scan_instruction(const struct nir_shader *nir, struct si_shader_info *info,
 231                              nir_instr *instr)
 232 {
 233    if (instr->type == nir_instr_type_alu) {
 234       nir_alu_instr *alu = nir_instr_as_alu(instr);
 235
 236       switch (alu->op) {
 237       case nir_op_fddx:
 238       case nir_op_fddy:
 239       case nir_op_fddx_fine:
 240       case nir_op_fddy_fine:
 241       case nir_op_fddx_coarse:
 242       case nir_op_fddy_coarse:
 243          info->uses_derivatives = true;
 244          break;
 245       default:
 246          break;
 247       }
 248    } else if (instr->type == nir_instr_type_tex) {
 249       nir_tex_instr *tex = nir_instr_as_tex(instr);
 250       const nir_deref_instr *deref = tex_get_texture_deref(tex);
 251       nir_variable *var = deref ? nir_deref_instr_get_variable(deref) : NULL;
 252
 253       if (var) {
 254          if (deref->mode != nir_var_uniform || var->data.bindless)
 255             info->uses_bindless_samplers = true;
 256       }
 257
 258       switch (tex->op) {
 259       case nir_texop_tex:
 260       case nir_texop_txb:
 261       case nir_texop_lod:
 262          info->uses_derivatives = true;
 263          break;
 264       default:
 265          break;
 266       }
 267    } else if (instr->type == nir_instr_type_intrinsic) {
 268       nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 269
 270       switch (intr->intrinsic) {
 271       case nir_intrinsic_load_front_face:
 272          info->uses_frontface = 1;
 273          break;
 274       case nir_intrinsic_load_instance_id:
 275          info->uses_instanceid = 1;
 276          break;
 277       case nir_intrinsic_load_invocation_id:
 278          info->uses_invocationid = true;
 279          break;
 280       case nir_intrinsic_load_num_work_groups:
 281          info->uses_grid_size = true;
 282          break;
 283       case nir_intrinsic_load_local_invocation_index:
 284       case nir_intrinsic_load_subgroup_id:
 285       case nir_intrinsic_load_num_subgroups:
 286          info->uses_subgroup_info = true;
 287          break;
 288       case nir_intrinsic_load_local_group_size:
 289          /* The block size is translated to IMM with a fixed block size. */
 290          if (info->base.cs.local_size[0] == 0)
 291             info->uses_block_size = true;
 292          break;
 293       case nir_intrinsic_load_local_invocation_id:
 294       case nir_intrinsic_load_work_group_id: {
 295          unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
 296          while (mask) {
 297             unsigned i = u_bit_scan(&mask);
 298
 299             if (intr->intrinsic == nir_intrinsic_load_work_group_id)
 300                info->uses_block_id[i] = true;
 301             else
 302                info->uses_thread_id[i] = true;
 303          }
 304          break;
 305       }
 306       case nir_intrinsic_load_draw_id:
 307          info->uses_drawid = 1;
 308          break;
 309       case nir_intrinsic_load_primitive_id:
 310          info->uses_primid = 1;
 311          break;
 312       case nir_intrinsic_load_sample_mask_in:
 313          info->reads_samplemask = true;
 314          break;
 315       case nir_intrinsic_load_tess_level_inner:
 316       case nir_intrinsic_load_tess_level_outer:
 317          info->reads_tess_factors = true;
 318          break;
 319       case nir_intrinsic_bindless_image_load:
 320       case nir_intrinsic_bindless_image_size:
 321       case nir_intrinsic_bindless_image_samples:
 322          info->uses_bindless_images = true;
 323          break;
 324       case nir_intrinsic_bindless_image_store:
 325          info->uses_bindless_images = true;
 326          info->writes_memory = true;
 327          info->num_memory_instructions++; /* we only care about stores */
 328          break;
 329       case nir_intrinsic_image_deref_store:
 330          info->writes_memory = true;
 331          info->num_memory_instructions++; /* we only care about stores */
 332          break;
 333       case nir_intrinsic_bindless_image_atomic_add:
 334       case nir_intrinsic_bindless_image_atomic_imin:
 335       case nir_intrinsic_bindless_image_atomic_umin:
 336       case nir_intrinsic_bindless_image_atomic_imax:
 337       case nir_intrinsic_bindless_image_atomic_umax:
 338       case nir_intrinsic_bindless_image_atomic_and:
 339       case nir_intrinsic_bindless_image_atomic_or:
 340       case nir_intrinsic_bindless_image_atomic_xor:
 341       case nir_intrinsic_bindless_image_atomic_exchange:
 342       case nir_intrinsic_bindless_image_atomic_comp_swap:
 343          info->uses_bindless_images = true;
 344          info->writes_memory = true;
 345          info->num_memory_instructions++; /* we only care about stores */
 346          break;
 347       case nir_intrinsic_image_deref_atomic_add:
 348       case nir_intrinsic_image_deref_atomic_imin:
 349       case nir_intrinsic_image_deref_atomic_umin:
 350       case nir_intrinsic_image_deref_atomic_imax:
 351       case nir_intrinsic_image_deref_atomic_umax:
 352       case nir_intrinsic_image_deref_atomic_and:
 353       case nir_intrinsic_image_deref_atomic_or:
 354       case nir_intrinsic_image_deref_atomic_xor:
 355       case nir_intrinsic_image_deref_atomic_exchange:
 356       case nir_intrinsic_image_deref_atomic_comp_swap:
 357       case nir_intrinsic_image_deref_atomic_inc_wrap:
 358       case nir_intrinsic_image_deref_atomic_dec_wrap:
 359          info->writes_memory = true;
 360          info->num_memory_instructions++; /* we only care about stores */
 361          break;
 362       case nir_intrinsic_store_ssbo:
 363       case nir_intrinsic_ssbo_atomic_add:
 364       case nir_intrinsic_ssbo_atomic_imin:
 365       case nir_intrinsic_ssbo_atomic_umin:
 366       case nir_intrinsic_ssbo_atomic_imax:
 367       case nir_intrinsic_ssbo_atomic_umax:
 368       case nir_intrinsic_ssbo_atomic_and:
 369       case nir_intrinsic_ssbo_atomic_or:
 370       case nir_intrinsic_ssbo_atomic_xor:
 371       case nir_intrinsic_ssbo_atomic_exchange:
 372       case nir_intrinsic_ssbo_atomic_comp_swap:
 373          info->writes_memory = true;
 374          info->num_memory_instructions++; /* we only care about stores */
 375          break;
 376       case nir_intrinsic_load_color0:
 377       case nir_intrinsic_load_color1: {
 378          unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
 379          uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
 380          info->colors_read |= mask << (index * 4);
 381          break;
 382       }
 383       case nir_intrinsic_load_barycentric_pixel:
 384       case nir_intrinsic_load_barycentric_centroid:
 385       case nir_intrinsic_load_barycentric_sample:
 386       case nir_intrinsic_load_barycentric_at_offset:   /* uses center */
 387       case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
 388          unsigned mode = nir_intrinsic_interp_mode(intr);
 389
 390          if (mode == INTERP_MODE_FLAT)
 391             break;
 392
 393          if (mode == INTERP_MODE_NOPERSPECTIVE) {
 394             if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
 395                info->uses_linear_sample = true;
 396             else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
 397                info->uses_linear_centroid = true;
 398             else
 399                info->uses_linear_center = true;
 400          } else {
 401             if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
 402                info->uses_persp_sample = true;
 403             else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
 404                info->uses_persp_centroid = true;
 405             else
 406                info->uses_persp_center = true;
 407          }
 408          if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
 409             info->uses_interp_at_sample = true;
 410          break;
 411       }
 412       case nir_intrinsic_load_input:
 413       case nir_intrinsic_load_per_vertex_input:
 414       case nir_intrinsic_load_input_vertex:
 415       case nir_intrinsic_load_interpolated_input:
 416          scan_io_usage(info, intr, true);
 417          break;
 418       case nir_intrinsic_load_output:
 419       case nir_intrinsic_load_per_vertex_output:
 420       case nir_intrinsic_store_output:
 421       case nir_intrinsic_store_per_vertex_output:
 422          scan_io_usage(info, intr, false);
 423          break;
 424       case nir_intrinsic_load_deref:
 425       case nir_intrinsic_store_deref:
 426       case nir_intrinsic_interp_deref_at_centroid:
 427       case nir_intrinsic_interp_deref_at_sample:
 428       case nir_intrinsic_interp_deref_at_offset:
 429          unreachable("these opcodes should have been lowered");
 430          break;
 431       default:
 432          break;
 433       }
 434    }
 435 }
 436
 437 void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *info)
 438 {
 439    nir_function *func;
 440
 441    info->base = nir->info;
 442    info->stage = nir->info.stage;
 443
 444    if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 445       if (info->base.tess.primitive_mode == GL_ISOLINES)
 446          info->base.tess.primitive_mode = GL_LINES;
 447    }
 448
 449    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 450       /* post_depth_coverage implies early_fragment_tests */
 451       info->base.fs.early_fragment_tests |= info->base.fs.post_depth_coverage;
 452
 453       info->color_interpolate[0] = nir->info.fs.color0_interp;
 454       info->color_interpolate[1] = nir->info.fs.color1_interp;
 455       for (unsigned i = 0; i < 2; i++) {
 456          if (info->color_interpolate[i] == INTERP_MODE_NONE)
 457             info->color_interpolate[i] = INTERP_MODE_COLOR;
 458       }
 459
 460       info->color_interpolate_loc[0] = nir->info.fs.color0_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
 461                                        nir->info.fs.color0_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
 462                                                                       TGSI_INTERPOLATE_LOC_CENTER;
 463       info->color_interpolate_loc[1] = nir->info.fs.color1_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
 464                                        nir->info.fs.color1_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
 465                                                                       TGSI_INTERPOLATE_LOC_CENTER;
 466    }
 467
 468    info->constbuf0_num_slots = nir->num_uniforms;
 469
 470    if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 471       info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir);
 472    }
 473
 474    memset(info->output_semantic_to_slot, -1, sizeof(info->output_semantic_to_slot));
 475
 476    func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
 477    nir_foreach_block (block, func->impl) {
 478       nir_foreach_instr (instr, block)
 479          scan_instruction(nir, info, instr);
 480    }
 481
 482    /* Add color inputs to the list of inputs. */
 483    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 484       for (unsigned i = 0; i < 2; i++) {
 485          if ((info->colors_read >> (i * 4)) & 0xf) {
 486             info->input_semantic[info->num_inputs] = VARYING_SLOT_COL0 + i;
 487             info->input_interpolate[info->num_inputs] = info->color_interpolate[i];
 488             info->input_usage_mask[info->num_inputs] = info->colors_read >> (i * 4);
 489             info->num_inputs++;
 490          }
 491       }
 492    }
 493
 494    /* Trim output read masks based on write masks. */
 495    for (unsigned i = 0; i < info->num_outputs; i++)
 496       info->output_readmask[i] &= info->output_usagemask[i];
 497 }
 498
 499 static void si_nir_opts(struct nir_shader *nir, bool first)
 500 {
 501    bool progress;
 502
 503    NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 504    NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
 505    NIR_PASS_V(nir, nir_lower_phis_to_scalar);
 506
 507    do {
 508       progress = false;
 509       bool lower_alu_to_scalar = false;
 510       bool lower_phis_to_scalar = false;
 511
 512       if (first) {
 513          bool opt_find_array_copies = false;
 514
 515          NIR_PASS(progress, nir, nir_split_array_vars, nir_var_function_temp);
 516          NIR_PASS(lower_alu_to_scalar, nir, nir_shrink_vec_array_vars, nir_var_function_temp);
 517          NIR_PASS(opt_find_array_copies, nir, nir_opt_find_array_copies);
 518          NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
 519
 520          /* Call nir_lower_var_copies() to remove any copies introduced
 521           * by nir_opt_find_array_copies().
 522           */
 523          if (opt_find_array_copies)
 524             NIR_PASS(progress, nir, nir_lower_var_copies);
 525          progress |= opt_find_array_copies;
 526       } else {
 527          NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
 528       }
 529
 530       NIR_PASS(progress, nir, nir_opt_dead_write_vars);
 531
 532       NIR_PASS(lower_alu_to_scalar, nir, nir_opt_trivial_continues);
 533       /* (Constant) copy propagation is needed for txf with offsets. */
 534       NIR_PASS(progress, nir, nir_copy_prop);
 535       NIR_PASS(progress, nir, nir_opt_remove_phis);
 536       NIR_PASS(progress, nir, nir_opt_dce);
 537       NIR_PASS(lower_phis_to_scalar, nir, nir_opt_if, true);
 538       NIR_PASS(progress, nir, nir_opt_dead_cf);
 539
 540       if (lower_alu_to_scalar)
 541          NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
 542       if (lower_phis_to_scalar)
 543          NIR_PASS_V(nir, nir_lower_phis_to_scalar);
 544       progress |= lower_alu_to_scalar | lower_phis_to_scalar;
 545
 546       NIR_PASS(progress, nir, nir_opt_cse);
 547       NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
 548
 549       /* Needed for algebraic lowering */
 550       NIR_PASS(progress, nir, nir_opt_algebraic);
 551       NIR_PASS(progress, nir, nir_opt_constant_folding);
 552
 553       if (!nir->info.flrp_lowered) {
 554          unsigned lower_flrp = (nir->options->lower_flrp16 ? 16 : 0) |
 555                                (nir->options->lower_flrp32 ? 32 : 0) |
 556                                (nir->options->lower_flrp64 ? 64 : 0);
 557          assert(lower_flrp);
 558          bool lower_flrp_progress = false;
 559
 560          NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp, lower_flrp, false /* always_precise */);
 561          if (lower_flrp_progress) {
 562             NIR_PASS(progress, nir, nir_opt_constant_folding);
 563             progress = true;
 564          }
 565
 566          /* Nothing should rematerialize any flrps, so we only
 567           * need to do this lowering once.
 568           */
 569          nir->info.flrp_lowered = true;
 570       }
 571
 572       NIR_PASS(progress, nir, nir_opt_undef);
 573       NIR_PASS(progress, nir, nir_opt_conditional_discard);
 574       if (nir->options->max_unroll_iterations) {
 575          NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
 576       }
 577    } while (progress);
 578 }
 579
 580 static int type_size_vec4(const struct glsl_type *type, bool bindless)
 581 {
 582    return glsl_count_attribute_slots(type, false);
 583 }
 584
 585 static void si_nir_lower_color(nir_shader *nir)
 586 {
 587    nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
 588
 589    nir_builder b;
 590    nir_builder_init(&b, entrypoint);
 591
 592    nir_foreach_block (block, entrypoint) {
 593       nir_foreach_instr_safe (instr, block) {
 594          if (instr->type != nir_instr_type_intrinsic)
 595             continue;
 596
 597          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 598
 599          if (intrin->intrinsic != nir_intrinsic_load_deref)
 600             continue;
 601
 602          nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
 603          if (deref->mode != nir_var_shader_in)
 604             continue;
 605
 606          b.cursor = nir_before_instr(instr);
 607          nir_variable *var = nir_deref_instr_get_variable(deref);
 608          nir_ssa_def *def;
 609
 610          if (var->data.location == VARYING_SLOT_COL0) {
 611             def = nir_load_color0(&b);
 612             nir->info.fs.color0_interp = var->data.interpolation;
 613             nir->info.fs.color0_sample = var->data.sample;
 614             nir->info.fs.color0_centroid = var->data.centroid;
 615          } else if (var->data.location == VARYING_SLOT_COL1) {
 616             def = nir_load_color1(&b);
 617             nir->info.fs.color1_interp = var->data.interpolation;
 618             nir->info.fs.color1_sample = var->data.sample;
 619             nir->info.fs.color1_centroid = var->data.centroid;
 620          } else {
 621             continue;
 622          }
 623
 624          nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
 625          nir_instr_remove(instr);
 626       }
 627    }
 628 }
 629
 630 static void si_lower_io(struct nir_shader *nir)
 631 {
 632    /* HW supports indirect indexing for: | Enabled in driver
 633     * -------------------------------------------------------
 634     * VS inputs                          | No
 635     * TCS inputs                         | Yes
 636     * TES inputs                         | Yes
 637     * GS inputs                          | No
 638     * -------------------------------------------------------
 639     * VS outputs before TCS              | No
 640     * VS outputs before GS               | No
 641     * TCS outputs                        | Yes
 642     * TES outputs before GS              | No
 643     */
 644    bool has_indirect_inputs = nir->info.stage == MESA_SHADER_TESS_CTRL ||
 645                               nir->info.stage == MESA_SHADER_TESS_EVAL;
 646    bool has_indirect_outputs = nir->info.stage == MESA_SHADER_TESS_CTRL;
 647
 648    if (!has_indirect_inputs || !has_indirect_outputs) {
 649       NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir),
 650                  !has_indirect_outputs, !has_indirect_inputs);
 651
 652       /* Since we're doing nir_lower_io_to_temporaries late, we need
 653        * to lower all the copy_deref's introduced by
 654        * lower_io_to_temporaries before calling nir_lower_io.
 655        */
 656       NIR_PASS_V(nir, nir_split_var_copies);
 657       NIR_PASS_V(nir, nir_lower_var_copies);
 658       NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 659    }
 660
 661    if (nir->info.stage == MESA_SHADER_FRAGMENT)
 662       si_nir_lower_color(nir);
 663
 664    NIR_PASS_V(nir, nir_lower_io, nir_var_shader_out | nir_var_shader_in,
 665               type_size_vec4, 0);
 666    nir->info.io_lowered = true;
 667
 668    /* This pass needs actual constants */
 669    NIR_PASS_V(nir, nir_opt_constant_folding);
 670    NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
 671    NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_out);
 672
 673    /* Remove dead derefs, so that nir_validate doesn't fail. */
 674    NIR_PASS_V(nir, nir_opt_dce);
 675
 676    /* Remove input and output nir_variables, because we don't need them
 677     * anymore. Also remove uniforms, because those should have been lowered
 678     * to UBOs already.
 679     */
 680    unsigned modes = nir_var_shader_in | nir_var_shader_out | nir_var_uniform;
 681    nir_foreach_variable_with_modes_safe(var, nir, modes) {
 682       if (var->data.mode == nir_var_uniform &&
 683           (glsl_type_get_image_count(var->type) ||
 684            glsl_type_get_sampler_count(var->type)))
 685          continue;
 686
 687       exec_node_remove(&var->node);
 688    }
 689 }
 690
 691 /**
 692  * Perform "lowering" operations on the NIR that are run once when the shader
 693  * selector is created.
 694  */
 695 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
 696 {
 697    /* Perform lowerings (and optimizations) of code.
 698     *
 699     * Performance considerations aside, we must:
 700     * - lower certain ALU operations
 701     * - ensure constant offsets for texture instructions are folded
 702     *   and copy-propagated
 703     */
 704
 705    static const struct nir_lower_tex_options lower_tex_options = {
 706       .lower_txp = ~0u,
 707    };
 708    NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
 709
 710    const nir_lower_subgroups_options subgroups_options = {
 711       .subgroup_size = 64,
 712       .ballot_bit_size = 64,
 713       .lower_to_scalar = true,
 714       .lower_subgroup_masks = true,
 715       .lower_vote_trivial = false,
 716       .lower_vote_eq_to_ballot = true,
 717    };
 718    NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
 719
 720    /* Lower load constants to scalar and then clean up the mess */
 721    NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
 722    NIR_PASS_V(nir, nir_lower_var_copies);
 723    NIR_PASS_V(nir, nir_lower_pack);
 724    NIR_PASS_V(nir, nir_opt_access);
 725    si_nir_opts(nir, true);
 726
 727    /* Lower large variables that are always constant with load_constant
 728     * intrinsics, which get turned into PC-relative loads from a data
 729     * section next to the shader.
 730     *
 731     * st/mesa calls finalize_nir twice, but we can't call this pass twice.
 732     */
 733    bool changed = false;
 734    if (!nir->constant_data) {
 735       /* The pass crashes if there are dead temps of lowered IO interface types. */
 736       NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
 737       NIR_PASS(changed, nir, nir_opt_large_constants, glsl_get_natural_size_align_bytes, 16);
 738    }
 739
 740    changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
 741    if (changed)
 742       si_nir_opts(nir, false);
 743
 744    NIR_PASS_V(nir, nir_lower_bool_to_int32);
 745    NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
 746
 747    if (sscreen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
 748       NIR_PASS_V(nir, nir_lower_discard_to_demote);
 749 }
 750
 751 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
 752 {
 753    struct si_screen *sscreen = (struct si_screen *)screen;
 754    struct nir_shader *nir = (struct nir_shader *)nirptr;
 755
 756    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 757    si_lower_io(nir);
 758    si_lower_nir(sscreen, nir);
 759 }