46dd6e973fb2ac0b83935ff1124642b36d18b4d0
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_nir_to_llvm.h"
26 #include "compiler/nir/nir.h"
27 #include "compiler/nir/nir_builder.h"
28 #include "compiler/nir/nir_deref.h"
29 #include "compiler/nir_types.h"
30 #include "si_pipe.h"
31 #include "si_shader_internal.h"
32 #include "tgsi/tgsi_from_mesa.h"
33
34 static const nir_deref_instr *tex_get_texture_deref(nir_tex_instr *instr)
35 {
36 for (unsigned i = 0; i < instr->num_srcs; i++) {
37 switch (instr->src[i].src_type) {
38 case nir_tex_src_texture_deref:
39 return nir_src_as_deref(instr->src[i].src);
40 default:
41 break;
42 }
43 }
44
45 return NULL;
46 }
47
48 static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr,
49 bool is_input)
50 {
51 unsigned interp = INTERP_MODE_FLAT; /* load_input uses flat shading */
52
53 if (intr->intrinsic == nir_intrinsic_load_interpolated_input) {
54 nir_intrinsic_instr *baryc = nir_instr_as_intrinsic(intr->src[0].ssa->parent_instr);
55
56 if (baryc) {
57 if (nir_intrinsic_infos[baryc->intrinsic].index_map[NIR_INTRINSIC_INTERP_MODE] > 0)
58 interp = nir_intrinsic_interp_mode(baryc);
59 else
60 unreachable("unknown barycentric intrinsic");
61 } else {
62 unreachable("unknown barycentric expression");
63 }
64 }
65
66 unsigned mask, bit_size;
67 bool dual_slot, is_output_load;
68
69 if (nir_intrinsic_infos[intr->intrinsic].index_map[NIR_INTRINSIC_WRMASK] > 0) {
70 mask = nir_intrinsic_write_mask(intr); /* store */
71 bit_size = nir_src_bit_size(intr->src[0]);
72 dual_slot = bit_size == 64 && nir_src_num_components(intr->src[0]) >= 3;
73 is_output_load = false;
74 } else {
75 mask = nir_ssa_def_components_read(&intr->dest.ssa); /* load */
76 bit_size = intr->dest.ssa.bit_size;
77 dual_slot = bit_size == 64 && intr->dest.ssa.num_components >= 3;
78 is_output_load = !is_input;
79 }
80
81 /* Convert the 64-bit component mask to a 32-bit component mask. */
82 if (bit_size == 64) {
83 unsigned new_mask = 0;
84 for (unsigned i = 0; i < 4; i++) {
85 if (mask & (1 << i))
86 new_mask |= 0x3 << (2 * i);
87 }
88 mask = new_mask;
89 }
90
91 /* Convert the 16-bit component mask to a 32-bit component mask. */
92 if (bit_size == 16) {
93 unsigned new_mask = 0;
94 for (unsigned i = 0; i < 4; i++) {
95 if (mask & (1 << i))
96 new_mask |= 0x1 << (i / 2);
97 }
98 mask = new_mask;
99 }
100
101 mask <<= nir_intrinsic_component(intr);
102
103 nir_src offset = *nir_get_io_offset_src(intr);
104 bool indirect = !nir_src_is_const(offset);
105 if (!indirect)
106 assert(nir_src_as_uint(offset) == 0);
107
108 unsigned semantic = 0;
109 /* VS doesn't have semantics. */
110 if (info->stage != MESA_SHADER_VERTEX || !is_input)
111 semantic = nir_intrinsic_io_semantics(intr).location;
112
113 if (info->stage == MESA_SHADER_FRAGMENT && !is_input) {
114 /* Never use FRAG_RESULT_COLOR directly. */
115 if (semantic == FRAG_RESULT_COLOR) {
116 semantic = FRAG_RESULT_DATA0;
117 info->color0_writes_all_cbufs = true;
118 }
119 semantic += nir_intrinsic_io_semantics(intr).dual_source_blend_index;
120 }
121
122 unsigned driver_location = nir_intrinsic_base(intr);
123 unsigned num_slots = indirect ? nir_intrinsic_io_semantics(intr).num_slots : (1 + dual_slot);
124
125 if (is_input) {
126 assert(driver_location + num_slots <= ARRAY_SIZE(info->input_usage_mask));
127
128 for (unsigned i = 0; i < num_slots; i++) {
129 unsigned loc = driver_location + i;
130 unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
131
132 info->input_semantic[loc] = semantic + i;
133 info->input_interpolate[loc] = interp;
134
135 if (slot_mask) {
136 info->input_usage_mask[loc] |= slot_mask;
137 info->num_inputs = MAX2(info->num_inputs, loc + 1);
138
139 if (semantic == VARYING_SLOT_PRIMITIVE_ID)
140 info->uses_primid = true;
141 }
142 }
143 } else {
144 /* Outputs. */
145 assert(driver_location + num_slots <= ARRAY_SIZE(info->output_usagemask));
146 assert(semantic + num_slots < ARRAY_SIZE(info->output_semantic_to_slot));
147
148 for (unsigned i = 0; i < num_slots; i++) {
149 unsigned loc = driver_location + i;
150 unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
151
152 info->output_semantic[loc] = semantic + i;
153 info->output_semantic_to_slot[semantic + i] = loc;
154
155 if (is_output_load) {
156 /* Output loads have only a few things that we need to track. */
157 info->output_readmask[loc] |= slot_mask;
158
159 if (info->stage == MESA_SHADER_FRAGMENT &&
160 nir_intrinsic_io_semantics(intr).fb_fetch_output)
161 info->uses_fbfetch = true;
162 } else if (slot_mask) {
163 /* Output stores. */
164 if (info->stage == MESA_SHADER_GEOMETRY) {
165 unsigned gs_streams = (uint32_t)nir_intrinsic_io_semantics(intr).gs_streams <<
166 (nir_intrinsic_component(intr) * 2);
167 unsigned new_mask = slot_mask & ~info->output_usagemask[loc];
168
169 for (unsigned i = 0; i < 4; i++) {
170 unsigned stream = (gs_streams >> (i * 2)) & 0x3;
171
172 if (new_mask & (1 << i)) {
173 info->output_streams[loc] |= stream << (i * 2);
174 info->num_stream_output_components[stream]++;
175 }
176 }
177 }
178
179 info->output_usagemask[loc] |= slot_mask;
180 info->num_outputs = MAX2(info->num_outputs, loc + 1);
181
182 if (info->stage == MESA_SHADER_FRAGMENT) {
183 switch (semantic) {
184 case FRAG_RESULT_DEPTH:
185 info->writes_z = true;
186 break;
187 case FRAG_RESULT_STENCIL:
188 info->writes_stencil = true;
189 break;
190 case FRAG_RESULT_SAMPLE_MASK:
191 info->writes_samplemask = true;
192 break;
193 default:
194 if (semantic >= FRAG_RESULT_DATA0 && semantic <= FRAG_RESULT_DATA7) {
195 unsigned index = semantic - FRAG_RESULT_DATA0;
196 info->colors_written |= 1 << (index + i);
197 }
198 break;
199 }
200 } else {
201 switch (semantic) {
202 case VARYING_SLOT_PRIMITIVE_ID:
203 info->writes_primid = true;
204 break;
205 case VARYING_SLOT_VIEWPORT:
206 info->writes_viewport_index = true;
207 break;
208 case VARYING_SLOT_LAYER:
209 info->writes_layer = true;
210 break;
211 case VARYING_SLOT_PSIZ:
212 info->writes_psize = true;
213 break;
214 case VARYING_SLOT_CLIP_VERTEX:
215 info->writes_clipvertex = true;
216 break;
217 case VARYING_SLOT_EDGE:
218 info->writes_edgeflag = true;
219 break;
220 case VARYING_SLOT_POS:
221 info->writes_position = true;
222 break;
223 }
224 }
225 }
226 }
227 }
228 }
229
230 static void scan_instruction(const struct nir_shader *nir, struct si_shader_info *info,
231 nir_instr *instr)
232 {
233 if (instr->type == nir_instr_type_tex) {
234 nir_tex_instr *tex = nir_instr_as_tex(instr);
235 const nir_deref_instr *deref = tex_get_texture_deref(tex);
236 nir_variable *var = deref ? nir_deref_instr_get_variable(deref) : NULL;
237
238 if (var) {
239 if (deref->mode != nir_var_uniform || var->data.bindless)
240 info->uses_bindless_samplers = true;
241 }
242 } else if (instr->type == nir_instr_type_intrinsic) {
243 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
244
245 switch (intr->intrinsic) {
246 case nir_intrinsic_load_front_face:
247 info->uses_frontface = 1;
248 break;
249 case nir_intrinsic_load_instance_id:
250 info->uses_instanceid = 1;
251 break;
252 case nir_intrinsic_load_invocation_id:
253 info->uses_invocationid = true;
254 break;
255 case nir_intrinsic_load_num_work_groups:
256 info->uses_grid_size = true;
257 break;
258 case nir_intrinsic_load_local_invocation_index:
259 case nir_intrinsic_load_subgroup_id:
260 case nir_intrinsic_load_num_subgroups:
261 info->uses_subgroup_info = true;
262 break;
263 case nir_intrinsic_load_local_group_size:
264 /* The block size is translated to IMM with a fixed block size. */
265 if (info->base.cs.local_size[0] == 0)
266 info->uses_block_size = true;
267 break;
268 case nir_intrinsic_load_local_invocation_id:
269 case nir_intrinsic_load_work_group_id: {
270 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
271 while (mask) {
272 unsigned i = u_bit_scan(&mask);
273
274 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
275 info->uses_block_id[i] = true;
276 else
277 info->uses_thread_id[i] = true;
278 }
279 break;
280 }
281 case nir_intrinsic_load_draw_id:
282 info->uses_drawid = 1;
283 break;
284 case nir_intrinsic_load_primitive_id:
285 info->uses_primid = 1;
286 break;
287 case nir_intrinsic_load_sample_mask_in:
288 info->reads_samplemask = true;
289 break;
290 case nir_intrinsic_load_tess_level_inner:
291 case nir_intrinsic_load_tess_level_outer:
292 info->reads_tess_factors = true;
293 break;
294 case nir_intrinsic_bindless_image_load:
295 case nir_intrinsic_bindless_image_size:
296 case nir_intrinsic_bindless_image_samples:
297 info->uses_bindless_images = true;
298 break;
299 case nir_intrinsic_bindless_image_store:
300 info->uses_bindless_images = true;
301 info->num_memory_stores++;
302 break;
303 case nir_intrinsic_image_deref_store:
304 info->num_memory_stores++;
305 break;
306 case nir_intrinsic_bindless_image_atomic_add:
307 case nir_intrinsic_bindless_image_atomic_imin:
308 case nir_intrinsic_bindless_image_atomic_umin:
309 case nir_intrinsic_bindless_image_atomic_imax:
310 case nir_intrinsic_bindless_image_atomic_umax:
311 case nir_intrinsic_bindless_image_atomic_and:
312 case nir_intrinsic_bindless_image_atomic_or:
313 case nir_intrinsic_bindless_image_atomic_xor:
314 case nir_intrinsic_bindless_image_atomic_exchange:
315 case nir_intrinsic_bindless_image_atomic_comp_swap:
316 info->uses_bindless_images = true;
317 info->num_memory_stores++;
318 break;
319 case nir_intrinsic_image_deref_atomic_add:
320 case nir_intrinsic_image_deref_atomic_imin:
321 case nir_intrinsic_image_deref_atomic_umin:
322 case nir_intrinsic_image_deref_atomic_imax:
323 case nir_intrinsic_image_deref_atomic_umax:
324 case nir_intrinsic_image_deref_atomic_and:
325 case nir_intrinsic_image_deref_atomic_or:
326 case nir_intrinsic_image_deref_atomic_xor:
327 case nir_intrinsic_image_deref_atomic_exchange:
328 case nir_intrinsic_image_deref_atomic_comp_swap:
329 case nir_intrinsic_image_deref_atomic_inc_wrap:
330 case nir_intrinsic_image_deref_atomic_dec_wrap:
331 info->num_memory_stores++;
332 break;
333 case nir_intrinsic_store_ssbo:
334 case nir_intrinsic_ssbo_atomic_add:
335 case nir_intrinsic_ssbo_atomic_imin:
336 case nir_intrinsic_ssbo_atomic_umin:
337 case nir_intrinsic_ssbo_atomic_imax:
338 case nir_intrinsic_ssbo_atomic_umax:
339 case nir_intrinsic_ssbo_atomic_and:
340 case nir_intrinsic_ssbo_atomic_or:
341 case nir_intrinsic_ssbo_atomic_xor:
342 case nir_intrinsic_ssbo_atomic_exchange:
343 case nir_intrinsic_ssbo_atomic_comp_swap:
344 info->num_memory_stores++;
345 break;
346 case nir_intrinsic_load_color0:
347 case nir_intrinsic_load_color1: {
348 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
349 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
350 info->colors_read |= mask << (index * 4);
351 break;
352 }
353 case nir_intrinsic_load_barycentric_pixel:
354 case nir_intrinsic_load_barycentric_centroid:
355 case nir_intrinsic_load_barycentric_sample:
356 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
357 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
358 unsigned mode = nir_intrinsic_interp_mode(intr);
359
360 if (mode == INTERP_MODE_FLAT)
361 break;
362
363 if (mode == INTERP_MODE_NOPERSPECTIVE) {
364 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
365 info->uses_linear_sample = true;
366 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
367 info->uses_linear_centroid = true;
368 else
369 info->uses_linear_center = true;
370 } else {
371 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
372 info->uses_persp_sample = true;
373 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
374 info->uses_persp_centroid = true;
375 else
376 info->uses_persp_center = true;
377 }
378 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
379 info->uses_interp_at_sample = true;
380 break;
381 }
382 case nir_intrinsic_load_input:
383 case nir_intrinsic_load_per_vertex_input:
384 case nir_intrinsic_load_input_vertex:
385 case nir_intrinsic_load_interpolated_input:
386 scan_io_usage(info, intr, true);
387 break;
388 case nir_intrinsic_load_output:
389 case nir_intrinsic_load_per_vertex_output:
390 case nir_intrinsic_store_output:
391 case nir_intrinsic_store_per_vertex_output:
392 scan_io_usage(info, intr, false);
393 break;
394 case nir_intrinsic_load_deref:
395 case nir_intrinsic_store_deref:
396 case nir_intrinsic_interp_deref_at_centroid:
397 case nir_intrinsic_interp_deref_at_sample:
398 case nir_intrinsic_interp_deref_at_offset:
399 unreachable("these opcodes should have been lowered");
400 break;
401 default:
402 break;
403 }
404 }
405 }
406
407 void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *info)
408 {
409 nir_function *func;
410
411 info->base = nir->info;
412 info->stage = nir->info.stage;
413
414 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
415 if (info->base.tess.primitive_mode == GL_ISOLINES)
416 info->base.tess.primitive_mode = GL_LINES;
417 }
418
419 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
420 /* post_depth_coverage implies early_fragment_tests */
421 info->base.fs.early_fragment_tests |= info->base.fs.post_depth_coverage;
422
423 info->color_interpolate[0] = nir->info.fs.color0_interp;
424 info->color_interpolate[1] = nir->info.fs.color1_interp;
425 for (unsigned i = 0; i < 2; i++) {
426 if (info->color_interpolate[i] == INTERP_MODE_NONE)
427 info->color_interpolate[i] = INTERP_MODE_COLOR;
428 }
429
430 info->color_interpolate_loc[0] = nir->info.fs.color0_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
431 nir->info.fs.color0_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
432 TGSI_INTERPOLATE_LOC_CENTER;
433 info->color_interpolate_loc[1] = nir->info.fs.color1_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
434 nir->info.fs.color1_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
435 TGSI_INTERPOLATE_LOC_CENTER;
436 }
437
438 info->constbuf0_num_slots = nir->num_uniforms;
439
440 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
441 info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir);
442 }
443
444 memset(info->output_semantic_to_slot, -1, sizeof(info->output_semantic_to_slot));
445
446 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
447 nir_foreach_block (block, func->impl) {
448 nir_foreach_instr (instr, block)
449 scan_instruction(nir, info, instr);
450 }
451
452 /* Add color inputs to the list of inputs. */
453 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
454 for (unsigned i = 0; i < 2; i++) {
455 if ((info->colors_read >> (i * 4)) & 0xf) {
456 info->input_semantic[info->num_inputs] = VARYING_SLOT_COL0 + i;
457 info->input_interpolate[info->num_inputs] = info->color_interpolate[i];
458 info->input_usage_mask[info->num_inputs] = info->colors_read >> (i * 4);
459 info->num_inputs++;
460 }
461 }
462 }
463
464 /* Trim output read masks based on write masks. */
465 for (unsigned i = 0; i < info->num_outputs; i++)
466 info->output_readmask[i] &= info->output_usagemask[i];
467 }
468
469 static void si_nir_opts(struct nir_shader *nir, bool first)
470 {
471 bool progress;
472
473 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
474 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
475 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
476
477 do {
478 progress = false;
479 bool lower_alu_to_scalar = false;
480 bool lower_phis_to_scalar = false;
481
482 if (first) {
483 bool opt_find_array_copies = false;
484
485 NIR_PASS(progress, nir, nir_split_array_vars, nir_var_function_temp);
486 NIR_PASS(lower_alu_to_scalar, nir, nir_shrink_vec_array_vars, nir_var_function_temp);
487 NIR_PASS(opt_find_array_copies, nir, nir_opt_find_array_copies);
488 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
489
490 /* Call nir_lower_var_copies() to remove any copies introduced
491 * by nir_opt_find_array_copies().
492 */
493 if (opt_find_array_copies)
494 NIR_PASS(progress, nir, nir_lower_var_copies);
495 progress |= opt_find_array_copies;
496 } else {
497 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
498 }
499
500 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
501
502 NIR_PASS(lower_alu_to_scalar, nir, nir_opt_trivial_continues);
503 /* (Constant) copy propagation is needed for txf with offsets. */
504 NIR_PASS(progress, nir, nir_copy_prop);
505 NIR_PASS(progress, nir, nir_opt_remove_phis);
506 NIR_PASS(progress, nir, nir_opt_dce);
507 NIR_PASS(lower_phis_to_scalar, nir, nir_opt_if, true);
508 NIR_PASS(progress, nir, nir_opt_dead_cf);
509
510 if (lower_alu_to_scalar)
511 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
512 if (lower_phis_to_scalar)
513 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
514 progress |= lower_alu_to_scalar | lower_phis_to_scalar;
515
516 NIR_PASS(progress, nir, nir_opt_cse);
517 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
518
519 /* Needed for algebraic lowering */
520 NIR_PASS(progress, nir, nir_opt_algebraic);
521 NIR_PASS(progress, nir, nir_opt_constant_folding);
522
523 if (!nir->info.flrp_lowered) {
524 unsigned lower_flrp = (nir->options->lower_flrp16 ? 16 : 0) |
525 (nir->options->lower_flrp32 ? 32 : 0) |
526 (nir->options->lower_flrp64 ? 64 : 0);
527 assert(lower_flrp);
528 bool lower_flrp_progress = false;
529
530 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp, lower_flrp, false /* always_precise */);
531 if (lower_flrp_progress) {
532 NIR_PASS(progress, nir, nir_opt_constant_folding);
533 progress = true;
534 }
535
536 /* Nothing should rematerialize any flrps, so we only
537 * need to do this lowering once.
538 */
539 nir->info.flrp_lowered = true;
540 }
541
542 NIR_PASS(progress, nir, nir_opt_undef);
543 NIR_PASS(progress, nir, nir_opt_conditional_discard);
544 if (nir->options->max_unroll_iterations) {
545 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
546 }
547 } while (progress);
548 }
549
550 static int type_size_vec4(const struct glsl_type *type, bool bindless)
551 {
552 return glsl_count_attribute_slots(type, false);
553 }
554
555 static void si_nir_lower_color(nir_shader *nir)
556 {
557 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
558
559 nir_builder b;
560 nir_builder_init(&b, entrypoint);
561
562 nir_foreach_block (block, entrypoint) {
563 nir_foreach_instr_safe (instr, block) {
564 if (instr->type != nir_instr_type_intrinsic)
565 continue;
566
567 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
568
569 if (intrin->intrinsic != nir_intrinsic_load_deref)
570 continue;
571
572 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
573 if (deref->mode != nir_var_shader_in)
574 continue;
575
576 b.cursor = nir_before_instr(instr);
577 nir_variable *var = nir_deref_instr_get_variable(deref);
578 nir_ssa_def *def;
579
580 if (var->data.location == VARYING_SLOT_COL0) {
581 def = nir_load_color0(&b);
582 nir->info.fs.color0_interp = var->data.interpolation;
583 nir->info.fs.color0_sample = var->data.sample;
584 nir->info.fs.color0_centroid = var->data.centroid;
585 } else if (var->data.location == VARYING_SLOT_COL1) {
586 def = nir_load_color1(&b);
587 nir->info.fs.color1_interp = var->data.interpolation;
588 nir->info.fs.color1_sample = var->data.sample;
589 nir->info.fs.color1_centroid = var->data.centroid;
590 } else {
591 continue;
592 }
593
594 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
595 nir_instr_remove(instr);
596 }
597 }
598 }
599
600 static void si_lower_io(struct nir_shader *nir)
601 {
602 /* HW supports indirect indexing for: | Enabled in driver
603 * -------------------------------------------------------
604 * VS inputs | No
605 * TCS inputs | Yes
606 * TES inputs | Yes
607 * GS inputs | No
608 * -------------------------------------------------------
609 * VS outputs before TCS | No
610 * VS outputs before GS | No
611 * TCS outputs | Yes
612 * TES outputs before GS | No
613 */
614 bool has_indirect_inputs = nir->info.stage == MESA_SHADER_TESS_CTRL ||
615 nir->info.stage == MESA_SHADER_TESS_EVAL;
616 bool has_indirect_outputs = nir->info.stage == MESA_SHADER_TESS_CTRL;
617
618 if (!has_indirect_inputs || !has_indirect_outputs) {
619 NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir),
620 !has_indirect_outputs, !has_indirect_inputs);
621
622 /* Since we're doing nir_lower_io_to_temporaries late, we need
623 * to lower all the copy_deref's introduced by
624 * lower_io_to_temporaries before calling nir_lower_io.
625 */
626 NIR_PASS_V(nir, nir_split_var_copies);
627 NIR_PASS_V(nir, nir_lower_var_copies);
628 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
629 }
630
631 if (nir->info.stage == MESA_SHADER_FRAGMENT)
632 si_nir_lower_color(nir);
633
634 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_out | nir_var_shader_in,
635 type_size_vec4, 0);
636 nir->info.io_lowered = true;
637
638 /* This pass needs actual constants */
639 NIR_PASS_V(nir, nir_opt_constant_folding);
640 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
641 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_out);
642
643 /* Remove dead derefs, so that nir_validate doesn't fail. */
644 NIR_PASS_V(nir, nir_opt_dce);
645
646 /* Remove input and output nir_variables, because we don't need them
647 * anymore. Also remove uniforms, because those should have been lowered
648 * to UBOs already.
649 */
650 unsigned modes = nir_var_shader_in | nir_var_shader_out | nir_var_uniform;
651 nir_foreach_variable_with_modes_safe(var, nir, modes) {
652 if (var->data.mode == nir_var_uniform &&
653 (glsl_type_get_image_count(var->type) ||
654 glsl_type_get_sampler_count(var->type)))
655 continue;
656
657 exec_node_remove(&var->node);
658 }
659 }
660
661 /**
662 * Perform "lowering" operations on the NIR that are run once when the shader
663 * selector is created.
664 */
665 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
666 {
667 /* Perform lowerings (and optimizations) of code.
668 *
669 * Performance considerations aside, we must:
670 * - lower certain ALU operations
671 * - ensure constant offsets for texture instructions are folded
672 * and copy-propagated
673 */
674
675 static const struct nir_lower_tex_options lower_tex_options = {
676 .lower_txp = ~0u,
677 };
678 NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
679
680 const nir_lower_subgroups_options subgroups_options = {
681 .subgroup_size = 64,
682 .ballot_bit_size = 64,
683 .lower_to_scalar = true,
684 .lower_subgroup_masks = true,
685 .lower_vote_trivial = false,
686 .lower_vote_eq_to_ballot = true,
687 };
688 NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
689
690 /* Lower load constants to scalar and then clean up the mess */
691 NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
692 NIR_PASS_V(nir, nir_lower_var_copies);
693 NIR_PASS_V(nir, nir_lower_pack);
694 NIR_PASS_V(nir, nir_opt_access);
695 si_nir_opts(nir, true);
696
697 /* Lower large variables that are always constant with load_constant
698 * intrinsics, which get turned into PC-relative loads from a data
699 * section next to the shader.
700 *
701 * st/mesa calls finalize_nir twice, but we can't call this pass twice.
702 */
703 bool changed = false;
704 if (!nir->constant_data) {
705 /* The pass crashes if there are dead temps of lowered IO interface types. */
706 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
707 NIR_PASS(changed, nir, nir_opt_large_constants, glsl_get_natural_size_align_bytes, 16);
708 }
709
710 changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
711 if (changed)
712 si_nir_opts(nir, false);
713
714 NIR_PASS_V(nir, nir_lower_bool_to_int32);
715 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
716
717 if (sscreen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
718 NIR_PASS_V(nir, nir_lower_discard_to_demote);
719 }
720
721 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
722 {
723 struct si_screen *sscreen = (struct si_screen *)screen;
724 struct nir_shader *nir = (struct nir_shader *)nirptr;
725
726 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
727 si_lower_io(nir);
728 si_lower_nir(sscreen, nir);
729 }