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radeonsi: merge si_tessctrl_info into si_shader_info
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35 #include "compiler/nir/nir_deref.h"
36
37 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
38 {
39 for (unsigned i = 0; i < instr->num_srcs; i++) {
40 switch (instr->src[i].src_type) {
41 case nir_tex_src_texture_deref:
42 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
43 default:
44 break;
45 }
46 }
47
48 return NULL;
49 }
50
51 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
52 {
53 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
54 }
55
56 static void gather_usage_helper(const nir_deref_instr **deref_ptr,
57 unsigned location,
58 uint8_t mask,
59 uint8_t *usage_mask)
60 {
61 for (; *deref_ptr; deref_ptr++) {
62 const nir_deref_instr *deref = *deref_ptr;
63 switch (deref->deref_type) {
64 case nir_deref_type_array: {
65 unsigned elem_size =
66 glsl_count_attribute_slots(deref->type, false);
67 if (nir_src_is_const(deref->arr.index)) {
68 location += elem_size * nir_src_as_uint(deref->arr.index);
69 } else {
70 unsigned array_elems =
71 glsl_get_length(deref_ptr[-1]->type);
72 for (unsigned i = 0; i < array_elems; i++) {
73 gather_usage_helper(deref_ptr + 1,
74 location + elem_size * i,
75 mask, usage_mask);
76 }
77 return;
78 }
79 break;
80 }
81 case nir_deref_type_struct: {
82 const struct glsl_type *parent_type =
83 deref_ptr[-1]->type;
84 unsigned index = deref->strct.index;
85 for (unsigned i = 0; i < index; i++) {
86 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
87 location += glsl_count_attribute_slots(ft, false);
88 }
89 break;
90 }
91 default:
92 unreachable("Unhandled deref type in gather_components_used_helper");
93 }
94 }
95
96 usage_mask[location] |= mask & 0xf;
97 if (mask & 0xf0)
98 usage_mask[location + 1] |= (mask >> 4) & 0xf;
99 }
100
101 static void gather_usage(const nir_deref_instr *deref,
102 uint8_t mask,
103 uint8_t *usage_mask)
104 {
105 nir_deref_path path;
106 nir_deref_path_init(&path, (nir_deref_instr *)deref, NULL);
107
108 unsigned location_frac = path.path[0]->var->data.location_frac;
109 if (glsl_type_is_64bit(deref->type)) {
110 uint8_t new_mask = 0;
111 for (unsigned i = 0; i < 4; i++) {
112 if (mask & (1 << i))
113 new_mask |= 0x3 << (2 * i);
114 }
115 mask = new_mask << location_frac;
116 } else {
117 mask <<= location_frac;
118 mask &= 0xf;
119 }
120
121 gather_usage_helper((const nir_deref_instr **)&path.path[1],
122 path.path[0]->var->data.driver_location,
123 mask, usage_mask);
124
125 nir_deref_path_finish(&path);
126 }
127
128 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
129 const nir_intrinsic_instr *instr,
130 const nir_deref_instr *deref,
131 struct si_shader_info *info)
132 {
133 switch (nir->info.stage) {
134 case MESA_SHADER_VERTEX:
135 gather_usage(deref, nir_ssa_def_components_read(&instr->dest.ssa),
136 info->input_usage_mask);
137 default:;
138 }
139 }
140
141 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
142 const nir_intrinsic_instr *instr,
143 nir_variable *var,
144 struct si_shader_info *info)
145 {
146 assert(var && var->data.mode == nir_var_shader_out);
147
148 switch (nir->info.stage) {
149 case MESA_SHADER_TESS_CTRL:
150 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
151 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
152 info->reads_tessfactor_outputs = true;
153 else if (var->data.patch)
154 info->reads_perpatch_outputs = true;
155 else
156 info->reads_pervertex_outputs = true;
157 break;
158
159 case MESA_SHADER_FRAGMENT:
160 if (var->data.fb_fetch_output)
161 info->uses_fbfetch = true;
162 break;
163 default:;
164 }
165 }
166
167 static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
168 const nir_intrinsic_instr *instr,
169 const nir_deref_instr *deref,
170 struct si_shader_info *info)
171 {
172 switch (nir->info.stage) {
173 case MESA_SHADER_VERTEX: /* needed by LS, ES */
174 case MESA_SHADER_TESS_EVAL: /* needed by ES */
175 case MESA_SHADER_GEOMETRY:
176 gather_usage(deref, nir_intrinsic_write_mask(instr),
177 info->output_usagemask);
178 break;
179 default:;
180 }
181 }
182
183 static void scan_instruction(const struct nir_shader *nir,
184 struct si_shader_info *info,
185 nir_instr *instr)
186 {
187 if (instr->type == nir_instr_type_alu) {
188 nir_alu_instr *alu = nir_instr_as_alu(instr);
189
190 switch (alu->op) {
191 case nir_op_fddx:
192 case nir_op_fddy:
193 case nir_op_fddx_fine:
194 case nir_op_fddy_fine:
195 case nir_op_fddx_coarse:
196 case nir_op_fddy_coarse:
197 info->uses_derivatives = true;
198 break;
199 default:
200 break;
201 }
202 } else if (instr->type == nir_instr_type_tex) {
203 nir_tex_instr *tex = nir_instr_as_tex(instr);
204 nir_variable *texture = tex_get_texture_var(tex);
205
206 if (!texture) {
207 info->samplers_declared |=
208 u_bit_consecutive(tex->sampler_index, 1);
209 } else {
210 if (texture->data.bindless)
211 info->uses_bindless_samplers = true;
212 }
213
214 switch (tex->op) {
215 case nir_texop_tex:
216 case nir_texop_txb:
217 case nir_texop_lod:
218 info->uses_derivatives = true;
219 break;
220 default:
221 break;
222 }
223 } else if (instr->type == nir_instr_type_intrinsic) {
224 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
225
226 switch (intr->intrinsic) {
227 case nir_intrinsic_load_front_face:
228 info->uses_frontface = 1;
229 break;
230 case nir_intrinsic_load_instance_id:
231 info->uses_instanceid = 1;
232 break;
233 case nir_intrinsic_load_invocation_id:
234 info->uses_invocationid = true;
235 break;
236 case nir_intrinsic_load_num_work_groups:
237 info->uses_grid_size = true;
238 break;
239 case nir_intrinsic_load_local_invocation_index:
240 case nir_intrinsic_load_subgroup_id:
241 case nir_intrinsic_load_num_subgroups:
242 info->uses_subgroup_info = true;
243 break;
244 case nir_intrinsic_load_local_group_size:
245 /* The block size is translated to IMM with a fixed block size. */
246 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
247 info->uses_block_size = true;
248 break;
249 case nir_intrinsic_load_local_invocation_id:
250 case nir_intrinsic_load_work_group_id: {
251 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
252 while (mask) {
253 unsigned i = u_bit_scan(&mask);
254
255 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
256 info->uses_block_id[i] = true;
257 else
258 info->uses_thread_id[i] = true;
259 }
260 break;
261 }
262 case nir_intrinsic_load_vertex_id:
263 info->uses_vertexid = 1;
264 break;
265 case nir_intrinsic_load_vertex_id_zero_base:
266 info->uses_vertexid_nobase = 1;
267 break;
268 case nir_intrinsic_load_base_vertex:
269 info->uses_basevertex = 1;
270 break;
271 case nir_intrinsic_load_draw_id:
272 info->uses_drawid = 1;
273 break;
274 case nir_intrinsic_load_primitive_id:
275 info->uses_primid = 1;
276 break;
277 case nir_intrinsic_load_sample_mask_in:
278 info->reads_samplemask = true;
279 break;
280 case nir_intrinsic_load_tess_level_inner:
281 case nir_intrinsic_load_tess_level_outer:
282 info->reads_tess_factors = true;
283 break;
284 case nir_intrinsic_bindless_image_load:
285 info->uses_bindless_images = true;
286
287 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
288 info->uses_bindless_buffer_load = true;
289 else
290 info->uses_bindless_image_load = true;
291 break;
292 case nir_intrinsic_bindless_image_size:
293 case nir_intrinsic_bindless_image_samples:
294 info->uses_bindless_images = true;
295 break;
296 case nir_intrinsic_bindless_image_store:
297 info->uses_bindless_images = true;
298
299 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
300 info->uses_bindless_buffer_store = true;
301 else
302 info->uses_bindless_image_store = true;
303
304 info->writes_memory = true;
305 info->num_memory_instructions++; /* we only care about stores */
306 break;
307 case nir_intrinsic_image_deref_store:
308 info->writes_memory = true;
309 info->num_memory_instructions++; /* we only care about stores */
310 break;
311 case nir_intrinsic_bindless_image_atomic_add:
312 case nir_intrinsic_bindless_image_atomic_imin:
313 case nir_intrinsic_bindless_image_atomic_umin:
314 case nir_intrinsic_bindless_image_atomic_imax:
315 case nir_intrinsic_bindless_image_atomic_umax:
316 case nir_intrinsic_bindless_image_atomic_and:
317 case nir_intrinsic_bindless_image_atomic_or:
318 case nir_intrinsic_bindless_image_atomic_xor:
319 case nir_intrinsic_bindless_image_atomic_exchange:
320 case nir_intrinsic_bindless_image_atomic_comp_swap:
321 info->uses_bindless_images = true;
322
323 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
324 info->uses_bindless_buffer_atomic = true;
325 else
326 info->uses_bindless_image_atomic = true;
327
328 info->writes_memory = true;
329 info->num_memory_instructions++; /* we only care about stores */
330 break;
331 case nir_intrinsic_image_deref_atomic_add:
332 case nir_intrinsic_image_deref_atomic_imin:
333 case nir_intrinsic_image_deref_atomic_umin:
334 case nir_intrinsic_image_deref_atomic_imax:
335 case nir_intrinsic_image_deref_atomic_umax:
336 case nir_intrinsic_image_deref_atomic_and:
337 case nir_intrinsic_image_deref_atomic_or:
338 case nir_intrinsic_image_deref_atomic_xor:
339 case nir_intrinsic_image_deref_atomic_exchange:
340 case nir_intrinsic_image_deref_atomic_comp_swap:
341 case nir_intrinsic_image_deref_atomic_inc_wrap:
342 case nir_intrinsic_image_deref_atomic_dec_wrap:
343 info->writes_memory = true;
344 info->num_memory_instructions++; /* we only care about stores */
345 break;
346 case nir_intrinsic_store_ssbo:
347 case nir_intrinsic_ssbo_atomic_add:
348 case nir_intrinsic_ssbo_atomic_imin:
349 case nir_intrinsic_ssbo_atomic_umin:
350 case nir_intrinsic_ssbo_atomic_imax:
351 case nir_intrinsic_ssbo_atomic_umax:
352 case nir_intrinsic_ssbo_atomic_and:
353 case nir_intrinsic_ssbo_atomic_or:
354 case nir_intrinsic_ssbo_atomic_xor:
355 case nir_intrinsic_ssbo_atomic_exchange:
356 case nir_intrinsic_ssbo_atomic_comp_swap:
357 info->writes_memory = true;
358 info->num_memory_instructions++; /* we only care about stores */
359 break;
360 case nir_intrinsic_load_color0:
361 case nir_intrinsic_load_color1: {
362 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
363 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
364 info->colors_read |= mask << (index * 4);
365 break;
366 }
367 case nir_intrinsic_load_barycentric_pixel:
368 case nir_intrinsic_load_barycentric_centroid:
369 case nir_intrinsic_load_barycentric_sample:
370 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
371 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
372 unsigned mode = nir_intrinsic_interp_mode(intr);
373
374 if (mode == INTERP_MODE_FLAT)
375 break;
376
377 if (mode == INTERP_MODE_NOPERSPECTIVE) {
378 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
379 info->uses_linear_sample = true;
380 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
381 info->uses_linear_centroid = true;
382 else
383 info->uses_linear_center = true;
384
385 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
386 info->uses_linear_opcode_interp_sample = true;
387 } else {
388 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
389 info->uses_persp_sample = true;
390 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
391 info->uses_persp_centroid = true;
392 else
393 info->uses_persp_center = true;
394
395 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
396 info->uses_persp_opcode_interp_sample = true;
397 }
398 break;
399 }
400 case nir_intrinsic_load_deref: {
401 nir_variable *var = intrinsic_get_var(intr);
402 nir_variable_mode mode = var->data.mode;
403
404 if (mode == nir_var_shader_in) {
405 /* PS inputs use the interpolated load intrinsics. */
406 assert(nir->info.stage != MESA_SHADER_FRAGMENT);
407 gather_intrinsic_load_deref_input_info(nir, intr,
408 nir_src_as_deref(intr->src[0]), info);
409 } else if (mode == nir_var_shader_out) {
410 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
411 }
412 break;
413 }
414 case nir_intrinsic_store_deref: {
415 nir_variable *var = intrinsic_get_var(intr);
416
417 if (var->data.mode == nir_var_shader_out)
418 gather_intrinsic_store_deref_output_info(nir, intr,
419 nir_src_as_deref(intr->src[0]), info);
420 break;
421 }
422 case nir_intrinsic_interp_deref_at_centroid:
423 case nir_intrinsic_interp_deref_at_sample:
424 case nir_intrinsic_interp_deref_at_offset:
425 unreachable("interp opcodes should have been lowered");
426 break;
427 default:
428 break;
429 }
430 }
431 }
432
433 static void scan_output_slot(const nir_variable *var,
434 unsigned var_idx,
435 unsigned component, unsigned num_components,
436 struct si_shader_info *info)
437 {
438 assert(component + num_components <= 4);
439 assert(component < 4);
440
441 unsigned semantic_name, semantic_index;
442
443 unsigned location = var->data.location + var_idx;
444 unsigned drv_location = var->data.driver_location + var_idx;
445
446 if (info->processor == PIPE_SHADER_FRAGMENT) {
447 tgsi_get_gl_frag_result_semantic(location,
448 &semantic_name, &semantic_index);
449
450 /* Adjust for dual source blending */
451 if (var->data.index > 0) {
452 semantic_index++;
453 }
454 } else {
455 tgsi_get_gl_varying_semantic(location, true,
456 &semantic_name, &semantic_index);
457 }
458
459 ubyte usagemask = ((1 << num_components) - 1) << component;
460
461 unsigned gs_out_streams;
462 if (var->data.stream & NIR_STREAM_PACKED) {
463 gs_out_streams = var->data.stream & ~NIR_STREAM_PACKED;
464 } else {
465 assert(var->data.stream < 4);
466 gs_out_streams = 0;
467 for (unsigned j = 0; j < num_components; ++j)
468 gs_out_streams |= var->data.stream << (2 * (component + j));
469 }
470
471 unsigned streamx = gs_out_streams & 3;
472 unsigned streamy = (gs_out_streams >> 2) & 3;
473 unsigned streamz = (gs_out_streams >> 4) & 3;
474 unsigned streamw = (gs_out_streams >> 6) & 3;
475
476 if (usagemask & TGSI_WRITEMASK_X) {
477 info->output_streams[drv_location] |= streamx;
478 info->num_stream_output_components[streamx]++;
479 }
480 if (usagemask & TGSI_WRITEMASK_Y) {
481 info->output_streams[drv_location] |= streamy << 2;
482 info->num_stream_output_components[streamy]++;
483 }
484 if (usagemask & TGSI_WRITEMASK_Z) {
485 info->output_streams[drv_location] |= streamz << 4;
486 info->num_stream_output_components[streamz]++;
487 }
488 if (usagemask & TGSI_WRITEMASK_W) {
489 info->output_streams[drv_location] |= streamw << 6;
490 info->num_stream_output_components[streamw]++;
491 }
492
493 info->output_semantic_name[drv_location] = semantic_name;
494 info->output_semantic_index[drv_location] = semantic_index;
495
496 switch (semantic_name) {
497 case TGSI_SEMANTIC_PRIMID:
498 info->writes_primid = true;
499 break;
500 case TGSI_SEMANTIC_VIEWPORT_INDEX:
501 info->writes_viewport_index = true;
502 break;
503 case TGSI_SEMANTIC_LAYER:
504 info->writes_layer = true;
505 break;
506 case TGSI_SEMANTIC_PSIZE:
507 info->writes_psize = true;
508 break;
509 case TGSI_SEMANTIC_CLIPVERTEX:
510 info->writes_clipvertex = true;
511 break;
512 case TGSI_SEMANTIC_COLOR:
513 info->colors_written |= 1 << semantic_index;
514 break;
515 case TGSI_SEMANTIC_STENCIL:
516 info->writes_stencil = true;
517 break;
518 case TGSI_SEMANTIC_SAMPLEMASK:
519 info->writes_samplemask = true;
520 break;
521 case TGSI_SEMANTIC_EDGEFLAG:
522 info->writes_edgeflag = true;
523 break;
524 case TGSI_SEMANTIC_POSITION:
525 if (info->processor == PIPE_SHADER_FRAGMENT)
526 info->writes_z = true;
527 else
528 info->writes_position = true;
529 break;
530 }
531 }
532
533 static void scan_output_helper(const nir_variable *var,
534 unsigned location,
535 const struct glsl_type *type,
536 struct si_shader_info *info)
537 {
538 if (glsl_type_is_struct(type) || glsl_type_is_interface(type)) {
539 for (unsigned i = 0; i < glsl_get_length(type); i++) {
540 const struct glsl_type *ft = glsl_get_struct_field(type, i);
541 scan_output_helper(var, location, ft, info);
542 location += glsl_count_attribute_slots(ft, false);
543 }
544 } else if (glsl_type_is_array_or_matrix(type)) {
545 const struct glsl_type *elem_type =
546 glsl_get_array_element(type);
547 unsigned num_elems = glsl_get_length(type);
548 if (var->data.compact) {
549 assert(glsl_type_is_scalar(elem_type));
550 assert(glsl_get_bit_size(elem_type) == 32);
551 unsigned component = var->data.location_frac;
552 scan_output_slot(var, location, component,
553 MIN2(num_elems, 4 - component), info);
554 if (component + num_elems > 4) {
555 scan_output_slot(var, location + 1, 0,
556 component + num_elems - 4, info);
557 }
558
559 } else {
560 unsigned elem_count = glsl_count_attribute_slots(elem_type, false);
561 for (unsigned i = 0; i < num_elems; i++) {
562 scan_output_helper(var, location, elem_type, info);
563 location += elem_count;
564 }
565 }
566 } else if (glsl_type_is_dual_slot(type)) {
567 unsigned component = var->data.location_frac;
568 scan_output_slot(var, location, component, 4 - component, info);
569 scan_output_slot(var, location + 1, 0, component + 2 * glsl_get_components(type) - 4,
570 info);
571 } else {
572 unsigned component = var->data.location_frac;
573 assert(glsl_type_is_vector_or_scalar(type));
574 unsigned num_components = glsl_get_components(type);
575 if (glsl_type_is_64bit(type))
576 num_components *= 2;
577 scan_output_slot(var, location, component, num_components, info);
578 }
579 }
580
581 void si_nir_scan_shader(const struct nir_shader *nir,
582 struct si_shader_info *info)
583 {
584 nir_function *func;
585 unsigned i;
586
587 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
588 info->num_tokens = 2; /* indicate that the shader is non-empty */
589 info->num_instructions = 2;
590
591 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
592 pipe_shader_type_from_mesa(nir->info.next_stage);
593
594 if (nir->info.stage == MESA_SHADER_VERTEX) {
595 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
596 nir->info.vs.window_space_position;
597 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
598 nir->info.vs.blit_sgprs_amd;
599 }
600
601 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
602 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
603 nir->info.tess.tcs_vertices_out;
604 }
605
606 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
607 if (nir->info.tess.primitive_mode == GL_ISOLINES)
608 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
609 else
610 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
611
612 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
613 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
614 PIPE_TESS_SPACING_FRACTIONAL_ODD);
615 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
616 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
617
618 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
619 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
620 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
621 }
622
623 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
624 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
625 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
626 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
627 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
628 }
629
630 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
631 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
632 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
633 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
634
635 if (nir->info.fs.pixel_center_integer) {
636 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
637 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
638 }
639
640 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
641 switch (nir->info.fs.depth_layout) {
642 case FRAG_DEPTH_LAYOUT_ANY:
643 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
644 break;
645 case FRAG_DEPTH_LAYOUT_GREATER:
646 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
647 break;
648 case FRAG_DEPTH_LAYOUT_LESS:
649 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
650 break;
651 case FRAG_DEPTH_LAYOUT_UNCHANGED:
652 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
653 break;
654 default:
655 unreachable("Unknow depth layout");
656 }
657 }
658 }
659
660 if (gl_shader_stage_is_compute(nir->info.stage)) {
661 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
662 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
663 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
664 info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] = nir->info.cs.user_data_components_amd;
665 }
666
667 i = 0;
668 uint64_t processed_inputs = 0;
669 nir_foreach_variable(variable, &nir->inputs) {
670 unsigned semantic_name, semantic_index;
671
672 const struct glsl_type *type = variable->type;
673 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
674 assert(glsl_type_is_array(type));
675 type = glsl_get_array_element(type);
676 }
677
678 unsigned attrib_count = glsl_count_attribute_slots(type,
679 nir->info.stage == MESA_SHADER_VERTEX);
680
681 i = variable->data.driver_location;
682
683 /* Vertex shader inputs don't have semantics. The state
684 * tracker has already mapped them to attributes via
685 * variable->data.driver_location.
686 */
687 if (nir->info.stage == MESA_SHADER_VERTEX)
688 continue;
689
690 for (unsigned j = 0; j < attrib_count; j++, i++) {
691
692 if (processed_inputs & ((uint64_t)1 << i))
693 continue;
694
695 processed_inputs |= ((uint64_t)1 << i);
696
697 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
698 &semantic_name, &semantic_index);
699
700 info->input_semantic_name[i] = semantic_name;
701 info->input_semantic_index[i] = semantic_index;
702
703 if (semantic_name == TGSI_SEMANTIC_PRIMID)
704 info->uses_primid = true;
705
706 if (semantic_name == TGSI_SEMANTIC_COLOR) {
707 /* We only need this for color inputs. */
708 if (variable->data.sample)
709 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
710 else if (variable->data.centroid)
711 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
712 else
713 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
714 }
715
716 enum glsl_base_type base_type =
717 glsl_get_base_type(glsl_without_array(variable->type));
718
719 switch (variable->data.interpolation) {
720 case INTERP_MODE_NONE:
721 if (glsl_base_type_is_integer(base_type)) {
722 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
723 break;
724 }
725
726 if (semantic_name == TGSI_SEMANTIC_COLOR) {
727 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
728 break;
729 }
730 /* fall-through */
731
732 case INTERP_MODE_SMOOTH:
733 assert(!glsl_base_type_is_integer(base_type));
734
735 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
736 break;
737
738 case INTERP_MODE_NOPERSPECTIVE:
739 assert(!glsl_base_type_is_integer(base_type));
740
741 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
742 break;
743
744 case INTERP_MODE_FLAT:
745 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
746 break;
747 }
748 }
749 }
750
751 nir_foreach_variable(variable, &nir->outputs) {
752 const struct glsl_type *type = variable->type;
753 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
754 assert(glsl_type_is_array(type));
755 type = glsl_get_array_element(type);
756 }
757
758 ASSERTED unsigned attrib_count = glsl_count_attribute_slots(type, false);
759 scan_output_helper(variable, 0, type, info);
760
761 unsigned loc = variable->data.location;
762 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
763 loc == FRAG_RESULT_COLOR &&
764 nir->info.outputs_written & (1ull << loc)) {
765 assert(attrib_count == 1);
766 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
767 }
768 }
769
770 info->num_inputs = nir->num_inputs;
771 info->num_outputs = nir->num_outputs;
772
773 info->const_file_max[0] = nir->num_uniforms - 1;
774 info->shader_buffers_declared = u_bit_consecutive(0, nir->info.num_ssbos);
775 info->const_buffers_declared = u_bit_consecutive(1, nir->info.num_ubos);
776 if (nir->num_uniforms > 0)
777 info->const_buffers_declared |= 1;
778 info->images_declared = u_bit_consecutive(0, nir->info.num_images);
779 info->msaa_images_declared = u_bit_consecutive(0, nir->info.last_msaa_image + 1);
780 info->samplers_declared = nir->info.textures_used;
781
782 info->num_written_clipdistance = nir->info.clip_distance_array_size;
783 info->num_written_culldistance = nir->info.cull_distance_array_size;
784 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
785 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
786
787 if (info->processor == PIPE_SHADER_FRAGMENT)
788 info->uses_kill = nir->info.fs.uses_discard;
789
790 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
791 info->tessfactors_are_def_in_all_invocs =
792 ac_are_tessfactors_def_in_all_invocs(nir);
793 }
794
795 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
796 nir_foreach_block(block, func->impl) {
797 nir_foreach_instr(instr, block)
798 scan_instruction(nir, info, instr);
799 }
800 }
801
802 static void
803 si_nir_opts(struct nir_shader *nir)
804 {
805 bool progress;
806
807 do {
808 progress = false;
809
810 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
811
812 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
813 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
814
815 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
816 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
817
818 /* (Constant) copy propagation is needed for txf with offsets. */
819 NIR_PASS(progress, nir, nir_copy_prop);
820 NIR_PASS(progress, nir, nir_opt_remove_phis);
821 NIR_PASS(progress, nir, nir_opt_dce);
822 if (nir_opt_trivial_continues(nir)) {
823 progress = true;
824 NIR_PASS(progress, nir, nir_copy_prop);
825 NIR_PASS(progress, nir, nir_opt_dce);
826 }
827 NIR_PASS(progress, nir, nir_opt_if, true);
828 NIR_PASS(progress, nir, nir_opt_dead_cf);
829 NIR_PASS(progress, nir, nir_opt_cse);
830 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
831
832 /* Needed for algebraic lowering */
833 NIR_PASS(progress, nir, nir_opt_algebraic);
834 NIR_PASS(progress, nir, nir_opt_constant_folding);
835
836 if (!nir->info.flrp_lowered) {
837 unsigned lower_flrp =
838 (nir->options->lower_flrp16 ? 16 : 0) |
839 (nir->options->lower_flrp32 ? 32 : 0) |
840 (nir->options->lower_flrp64 ? 64 : 0);
841 assert(lower_flrp);
842 bool lower_flrp_progress = false;
843
844 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
845 lower_flrp,
846 false /* always_precise */,
847 nir->options->lower_ffma);
848 if (lower_flrp_progress) {
849 NIR_PASS(progress, nir,
850 nir_opt_constant_folding);
851 progress = true;
852 }
853
854 /* Nothing should rematerialize any flrps, so we only
855 * need to do this lowering once.
856 */
857 nir->info.flrp_lowered = true;
858 }
859
860 NIR_PASS(progress, nir, nir_opt_undef);
861 NIR_PASS(progress, nir, nir_opt_conditional_discard);
862 if (nir->options->max_unroll_iterations) {
863 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
864 }
865 } while (progress);
866 }
867
868 static int
869 type_size_vec4(const struct glsl_type *type, bool bindless)
870 {
871 return glsl_count_attribute_slots(type, false);
872 }
873
874 static void
875 si_nir_lower_color(nir_shader *nir)
876 {
877 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
878
879 nir_builder b;
880 nir_builder_init(&b, entrypoint);
881
882 nir_foreach_block(block, entrypoint) {
883 nir_foreach_instr_safe(instr, block) {
884 if (instr->type != nir_instr_type_intrinsic)
885 continue;
886
887 nir_intrinsic_instr *intrin =
888 nir_instr_as_intrinsic(instr);
889
890 if (intrin->intrinsic != nir_intrinsic_load_deref)
891 continue;
892
893 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
894 if (deref->mode != nir_var_shader_in)
895 continue;
896
897 b.cursor = nir_before_instr(instr);
898 nir_variable *var = nir_deref_instr_get_variable(deref);
899 nir_ssa_def *def;
900
901 if (var->data.location == VARYING_SLOT_COL0) {
902 def = nir_load_color0(&b);
903 } else if (var->data.location == VARYING_SLOT_COL1) {
904 def = nir_load_color1(&b);
905 } else {
906 continue;
907 }
908
909 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
910 nir_instr_remove(instr);
911 }
912 }
913 }
914
915 static void si_nir_lower_ps_inputs(struct nir_shader *nir)
916 {
917 if (nir->info.stage != MESA_SHADER_FRAGMENT)
918 return;
919
920 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
921 nir_shader_get_entrypoint(nir), false, true);
922
923 /* Since we're doing nir_lower_io_to_temporaries late, we need
924 * to lower all the copy_deref's introduced by
925 * lower_io_to_temporaries before calling nir_lower_io.
926 */
927 NIR_PASS_V(nir, nir_split_var_copies);
928 NIR_PASS_V(nir, nir_lower_var_copies);
929 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
930
931 si_nir_lower_color(nir);
932 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
933
934 /* This pass needs actual constants */
935 NIR_PASS_V(nir, nir_opt_constant_folding);
936 NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
937 nir_var_shader_in);
938 }
939
940 void si_nir_adjust_driver_locations(struct nir_shader *nir)
941 {
942 /* Adjust the driver location of inputs and outputs. The state tracker
943 * interprets them as slots, while the ac/nir backend interprets them
944 * as individual components.
945 */
946 if (nir->info.stage != MESA_SHADER_FRAGMENT) {
947 nir_foreach_variable(variable, &nir->inputs)
948 variable->data.driver_location *= 4;
949 }
950
951 nir_foreach_variable(variable, &nir->outputs)
952 variable->data.driver_location *= 4;
953 }
954
955 /**
956 * Perform "lowering" operations on the NIR that are run once when the shader
957 * selector is created.
958 */
959 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
960 {
961 /* Perform lowerings (and optimizations) of code.
962 *
963 * Performance considerations aside, we must:
964 * - lower certain ALU operations
965 * - ensure constant offsets for texture instructions are folded
966 * and copy-propagated
967 */
968
969 static const struct nir_lower_tex_options lower_tex_options = {
970 .lower_txp = ~0u,
971 };
972 NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
973
974 const nir_lower_subgroups_options subgroups_options = {
975 .subgroup_size = 64,
976 .ballot_bit_size = 64,
977 .lower_to_scalar = true,
978 .lower_subgroup_masks = true,
979 .lower_vote_trivial = false,
980 .lower_vote_eq_to_ballot = true,
981 };
982 NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
983
984 /* Lower load constants to scalar and then clean up the mess */
985 NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
986 NIR_PASS_V(nir, nir_lower_var_copies);
987 NIR_PASS_V(nir, nir_lower_pack);
988 NIR_PASS_V(nir, nir_opt_access);
989 si_nir_opts(nir);
990
991 /* Lower large variables that are always constant with load_constant
992 * intrinsics, which get turned into PC-relative loads from a data
993 * section next to the shader.
994 *
995 * st/mesa calls finalize_nir twice, but we can't call this pass twice.
996 */
997 bool changed = false;
998 if (!nir->constant_data) {
999 NIR_PASS(changed, nir, nir_opt_large_constants,
1000 glsl_get_natural_size_align_bytes, 16);
1001 }
1002
1003 changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
1004 if (changed)
1005 si_nir_opts(nir);
1006
1007 NIR_PASS_V(nir, nir_lower_bool_to_int32);
1008 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp);
1009 }
1010
1011 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
1012 {
1013 struct si_screen *sscreen = (struct si_screen *)screen;
1014 struct nir_shader *nir = (struct nir_shader *)nirptr;
1015
1016 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
1017 si_nir_lower_ps_inputs(nir);
1018 si_lower_nir(sscreen, nir);
1019 }
1020
1021 static void declare_nir_input_vs(struct si_shader_context *ctx,
1022 struct nir_variable *variable,
1023 unsigned input_index,
1024 LLVMValueRef out[4])
1025 {
1026 si_llvm_load_input_vs(ctx, input_index, out);
1027 }
1028
1029 LLVMValueRef
1030 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
1031 enum glsl_interp_mode interp, unsigned location)
1032 {
1033 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1034
1035 switch (interp) {
1036 case INTERP_MODE_FLAT:
1037 return NULL;
1038 case INTERP_MODE_SMOOTH:
1039 case INTERP_MODE_NONE:
1040 if (location == INTERP_CENTER)
1041 return ac_get_arg(&ctx->ac, ctx->args.persp_center);
1042 else if (location == INTERP_CENTROID)
1043 return ctx->abi.persp_centroid;
1044 else if (location == INTERP_SAMPLE)
1045 return ac_get_arg(&ctx->ac, ctx->args.persp_sample);
1046 break;
1047 case INTERP_MODE_NOPERSPECTIVE:
1048 if (location == INTERP_CENTER)
1049 return ac_get_arg(&ctx->ac, ctx->args.linear_center);
1050 else if (location == INTERP_CENTROID)
1051 return ac_get_arg(&ctx->ac, ctx->args.linear_centroid);
1052 else if (location == INTERP_SAMPLE)
1053 return ac_get_arg(&ctx->ac, ctx->args.linear_sample);
1054 break;
1055 default:
1056 assert(!"Unhandled interpolation mode.");
1057 }
1058 return NULL;
1059 }
1060
1061 static LLVMValueRef
1062 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1063 unsigned descriptor_set, unsigned base_index,
1064 unsigned constant_index, LLVMValueRef dynamic_index,
1065 enum ac_descriptor_type desc_type, bool image,
1066 bool write, bool bindless)
1067 {
1068 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1069 LLVMBuilderRef builder = ctx->ac.builder;
1070 unsigned const_index = base_index + constant_index;
1071
1072 assert(!descriptor_set);
1073 assert(desc_type <= AC_DESC_BUFFER);
1074
1075 if (bindless) {
1076 LLVMValueRef list = ac_get_arg(&ctx->ac, ctx->bindless_samplers_and_images);
1077
1078 /* dynamic_index is the bindless handle */
1079 if (image) {
1080 /* Bindless image descriptors use 16-dword slots. */
1081 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1082 LLVMConstInt(ctx->i64, 2, 0), "");
1083 /* FMASK is right after the image. */
1084 if (desc_type == AC_DESC_FMASK) {
1085 dynamic_index = LLVMBuildAdd(ctx->ac.builder, dynamic_index,
1086 ctx->i32_1, "");
1087 }
1088
1089 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1090 write, true);
1091 }
1092
1093 /* Since bindless handle arithmetic can contain an unsigned integer
1094 * wraparound and si_load_sampler_desc assumes there isn't any,
1095 * use GEP without "inbounds" (inside ac_build_pointer_add)
1096 * to prevent incorrect code generation and hangs.
1097 */
1098 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1099 LLVMConstInt(ctx->i64, 2, 0), "");
1100 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1101 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1102 }
1103
1104 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1105 assert(const_index < num_slots || dynamic_index);
1106
1107 LLVMValueRef list = ac_get_arg(&ctx->ac, ctx->samplers_and_images);
1108 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1109
1110 if (dynamic_index) {
1111 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1112
1113 /* From the GL_ARB_shader_image_load_store extension spec:
1114 *
1115 * If a shader performs an image load, store, or atomic
1116 * operation using an image variable declared as an array,
1117 * and if the index used to select an individual element is
1118 * negative or greater than or equal to the size of the
1119 * array, the results of the operation are undefined but may
1120 * not lead to termination.
1121 */
1122 index = si_llvm_bound_index(ctx, index, num_slots);
1123 }
1124
1125 if (image) {
1126 /* FMASKs are separate from images. */
1127 if (desc_type == AC_DESC_FMASK) {
1128 index = LLVMBuildAdd(ctx->ac.builder, index,
1129 LLVMConstInt(ctx->i32, SI_NUM_IMAGES, 0), "");
1130 }
1131 index = LLVMBuildSub(ctx->ac.builder,
1132 LLVMConstInt(ctx->i32, SI_NUM_IMAGE_SLOTS - 1, 0),
1133 index, "");
1134 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1135 }
1136
1137 index = LLVMBuildAdd(ctx->ac.builder, index,
1138 LLVMConstInt(ctx->i32, SI_NUM_IMAGE_SLOTS / 2, 0), "");
1139 return si_load_sampler_desc(ctx, list, index, desc_type);
1140 }
1141
1142 static void bitcast_inputs(struct si_shader_context *ctx,
1143 LLVMValueRef data[4],
1144 unsigned input_idx)
1145 {
1146 for (unsigned chan = 0; chan < 4; chan++) {
1147 ctx->inputs[input_idx + chan] =
1148 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1149 }
1150 }
1151
1152 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1153 {
1154 struct si_shader_info *info = &ctx->shader->selector->info;
1155
1156 if (nir->info.stage == MESA_SHADER_VERTEX) {
1157 uint64_t processed_inputs = 0;
1158 nir_foreach_variable(variable, &nir->inputs) {
1159 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1160 true);
1161 unsigned input_idx = variable->data.driver_location;
1162
1163 LLVMValueRef data[4];
1164 unsigned loc = variable->data.location;
1165
1166 for (unsigned i = 0; i < attrib_count; i++) {
1167 /* Packed components share the same location so skip
1168 * them if we have already processed the location.
1169 */
1170 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1171 input_idx += 4;
1172 continue;
1173 }
1174
1175 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1176 bitcast_inputs(ctx, data, input_idx);
1177 if (glsl_type_is_dual_slot(variable->type)) {
1178 input_idx += 4;
1179 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1180 bitcast_inputs(ctx, data, input_idx);
1181 }
1182
1183 processed_inputs |= ((uint64_t)1 << (loc + i));
1184 input_idx += 4;
1185 }
1186 }
1187 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1188 unsigned colors_read =
1189 ctx->shader->selector->info.colors_read;
1190 LLVMValueRef main_fn = ctx->main_fn;
1191
1192 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1193
1194 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1195
1196 if (colors_read & 0x0f) {
1197 unsigned mask = colors_read & 0x0f;
1198 LLVMValueRef values[4];
1199 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1200 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1201 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1202 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1203 ctx->abi.color0 =
1204 ac_to_integer(&ctx->ac,
1205 ac_build_gather_values(&ctx->ac, values, 4));
1206 }
1207 if (colors_read & 0xf0) {
1208 unsigned mask = (colors_read & 0xf0) >> 4;
1209 LLVMValueRef values[4];
1210 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1211 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1212 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1213 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1214 ctx->abi.color1 =
1215 ac_to_integer(&ctx->ac,
1216 ac_build_gather_values(&ctx->ac, values, 4));
1217 }
1218
1219 ctx->abi.interp_at_sample_force_center =
1220 ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
1221 } else if (nir->info.stage == MESA_SHADER_COMPUTE) {
1222 if (nir->info.cs.user_data_components_amd) {
1223 ctx->abi.user_data = ac_get_arg(&ctx->ac, ctx->cs_user_data);
1224 ctx->abi.user_data = ac_build_expand_to_vec4(&ctx->ac, ctx->abi.user_data,
1225 nir->info.cs.user_data_components_amd);
1226 }
1227 }
1228
1229 ctx->abi.inputs = &ctx->inputs[0];
1230 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1231 ctx->abi.clamp_shadow_reference = true;
1232 ctx->abi.robust_buffer_access = true;
1233
1234 ctx->num_samplers = util_last_bit(info->samplers_declared);
1235 ctx->num_images = util_last_bit(info->images_declared);
1236
1237 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1238 assert(gl_shader_stage_is_compute(nir->info.stage));
1239 si_declare_compute_memory(ctx);
1240 }
1241 ac_nir_translate(&ctx->ac, &ctx->abi, &ctx->args, nir);
1242
1243 return true;
1244 }