src/gallium/drivers/radeonsi/si_shader_nir.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_shader_internal.h"
  26 #include "si_pipe.h"
  27
  28 #include "ac_nir_to_llvm.h"
  29
  30 #include "tgsi/tgsi_from_mesa.h"
  31
  32 #include "compiler/nir/nir.h"
  33 #include "compiler/nir_types.h"
  34 #include "compiler/nir/nir_builder.h"
  35 #include "compiler/nir/nir_deref.h"
  36
  37 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
  38 {
  39         for (unsigned i = 0; i < instr->num_srcs; i++) {
  40                 switch (instr->src[i].src_type) {
  41                 case nir_tex_src_texture_deref:
  42                         return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
  43                 default:
  44                         break;
  45                 }
  46         }
  47
  48         return NULL;
  49 }
  50
  51 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
  52 {
  53         return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
  54 }
  55
  56 static void gather_usage_helper(const nir_deref_instr **deref_ptr,
  57                                 unsigned location,
  58                                 uint8_t mask,
  59                                 uint8_t *usage_mask)
  60 {
  61         for (; *deref_ptr; deref_ptr++) {
  62                 const nir_deref_instr *deref = *deref_ptr;
  63                 switch (deref->deref_type) {
  64                 case nir_deref_type_array: {
  65                         unsigned elem_size =
  66                                 glsl_count_attribute_slots(deref->type, false);
  67                         if (nir_src_is_const(deref->arr.index)) {
  68                                 location += elem_size * nir_src_as_uint(deref->arr.index);
  69                         } else {
  70                                 unsigned array_elems =
  71                                         glsl_get_length(deref_ptr[-1]->type);
  72                                 for (unsigned i = 0; i < array_elems; i++) {
  73                                         gather_usage_helper(deref_ptr + 1,
  74                                                             location + elem_size * i,
  75                                                             mask, usage_mask);
  76                                 }
  77                                 return;
  78                         }
  79                         break;
  80                 }
  81                 case nir_deref_type_struct: {
  82                         const struct glsl_type *parent_type =
  83                                 deref_ptr[-1]->type;
  84                         unsigned index = deref->strct.index;
  85                         for (unsigned i = 0; i < index; i++) {
  86                                 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
  87                                 location += glsl_count_attribute_slots(ft, false);
  88                         }
  89                         break;
  90                 }
  91                 default:
  92                         unreachable("Unhandled deref type in gather_components_used_helper");
  93                 }
  94         }
  95
  96         usage_mask[location] |= mask & 0xf;
  97         if (mask & 0xf0)
  98                 usage_mask[location + 1] |= (mask >> 4) & 0xf;
  99 }
 100
 101 static void gather_usage(const nir_deref_instr *deref,
 102                          uint8_t mask,
 103                          uint8_t *usage_mask)
 104 {
 105         nir_deref_path path;
 106         nir_deref_path_init(&path, (nir_deref_instr *)deref, NULL);
 107
 108         unsigned location_frac = path.path[0]->var->data.location_frac;
 109         if (glsl_type_is_64bit(deref->type)) {
 110                 uint8_t new_mask = 0;
 111                 for (unsigned i = 0; i < 4; i++) {
 112                         if (mask & (1 << i))
 113                                 new_mask |= 0x3 << (2 * i);
 114                 }
 115                 mask = new_mask << location_frac;
 116         } else {
 117                 mask <<= location_frac;
 118                 mask &= 0xf;
 119         }
 120
 121         gather_usage_helper((const nir_deref_instr **)&path.path[1],
 122                             path.path[0]->var->data.driver_location,
 123                             mask, usage_mask);
 124
 125         nir_deref_path_finish(&path);
 126 }
 127
 128 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
 129                                                    const nir_intrinsic_instr *instr,
 130                                                    const nir_deref_instr *deref,
 131                                                    struct si_shader_info *info)
 132 {
 133         switch (nir->info.stage) {
 134         case MESA_SHADER_VERTEX:
 135                 gather_usage(deref, nir_ssa_def_components_read(&instr->dest.ssa),
 136                              info->input_usage_mask);
 137         default:;
 138         }
 139 }
 140
 141 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
 142                                                     const nir_intrinsic_instr *instr,
 143                                                     nir_variable *var,
 144                                                     struct si_shader_info *info)
 145 {
 146         assert(var && var->data.mode == nir_var_shader_out);
 147
 148         switch (nir->info.stage) {
 149         case MESA_SHADER_TESS_CTRL:
 150                 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
 151                     var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
 152                         info->reads_tessfactor_outputs = true;
 153                 else if (var->data.patch)
 154                         info->reads_perpatch_outputs = true;
 155                 else
 156                         info->reads_pervertex_outputs = true;
 157                 break;
 158
 159         case MESA_SHADER_FRAGMENT:
 160                 if (var->data.fb_fetch_output)
 161                         info->uses_fbfetch = true;
 162                 break;
 163         default:;
 164         }
 165 }
 166
 167 static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
 168                                                      const nir_intrinsic_instr *instr,
 169                                                      const nir_deref_instr *deref,
 170                                                      struct si_shader_info *info)
 171 {
 172         switch (nir->info.stage) {
 173         case MESA_SHADER_VERTEX: /* needed by LS, ES */
 174         case MESA_SHADER_TESS_EVAL: /* needed by ES */
 175         case MESA_SHADER_GEOMETRY:
 176                 gather_usage(deref, nir_intrinsic_write_mask(instr),
 177                              info->output_usagemask);
 178                 break;
 179         default:;
 180         }
 181 }
 182
 183 static void scan_instruction(const struct nir_shader *nir,
 184                              struct si_shader_info *info,
 185                              nir_instr *instr)
 186 {
 187         if (instr->type == nir_instr_type_alu) {
 188                 nir_alu_instr *alu = nir_instr_as_alu(instr);
 189
 190                 switch (alu->op) {
 191                 case nir_op_fddx:
 192                 case nir_op_fddy:
 193                 case nir_op_fddx_fine:
 194                 case nir_op_fddy_fine:
 195                 case nir_op_fddx_coarse:
 196                 case nir_op_fddy_coarse:
 197                         info->uses_derivatives = true;
 198                         break;
 199                 default:
 200                         break;
 201                 }
 202         } else if (instr->type == nir_instr_type_tex) {
 203                 nir_tex_instr *tex = nir_instr_as_tex(instr);
 204                 nir_variable *texture = tex_get_texture_var(tex);
 205
 206                 if (!texture) {
 207                         info->samplers_declared |=
 208                                 u_bit_consecutive(tex->sampler_index, 1);
 209                 } else {
 210                         if (texture->data.bindless)
 211                                 info->uses_bindless_samplers = true;
 212                 }
 213
 214                 switch (tex->op) {
 215                 case nir_texop_tex:
 216                 case nir_texop_txb:
 217                 case nir_texop_lod:
 218                         info->uses_derivatives = true;
 219                         break;
 220                 default:
 221                         break;
 222                 }
 223         } else if (instr->type == nir_instr_type_intrinsic) {
 224                 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 225
 226                 switch (intr->intrinsic) {
 227                 case nir_intrinsic_load_front_face:
 228                         info->uses_frontface = 1;
 229                         break;
 230                 case nir_intrinsic_load_instance_id:
 231                         info->uses_instanceid = 1;
 232                         break;
 233                 case nir_intrinsic_load_invocation_id:
 234                         info->uses_invocationid = true;
 235                         break;
 236                 case nir_intrinsic_load_num_work_groups:
 237                         info->uses_grid_size = true;
 238                         break;
 239                 case nir_intrinsic_load_local_invocation_index:
 240                 case nir_intrinsic_load_subgroup_id:
 241                 case nir_intrinsic_load_num_subgroups:
 242                         info->uses_subgroup_info = true;
 243                         break;
 244                 case nir_intrinsic_load_local_group_size:
 245                         /* The block size is translated to IMM with a fixed block size. */
 246                         if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
 247                                 info->uses_block_size = true;
 248                         break;
 249                 case nir_intrinsic_load_local_invocation_id:
 250                 case nir_intrinsic_load_work_group_id: {
 251                         unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
 252                         while (mask) {
 253                                 unsigned i = u_bit_scan(&mask);
 254
 255                                 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
 256                                         info->uses_block_id[i] = true;
 257                                 else
 258                                         info->uses_thread_id[i] = true;
 259                         }
 260                         break;
 261                 }
 262                 case nir_intrinsic_load_vertex_id:
 263                         info->uses_vertexid = 1;
 264                         break;
 265                 case nir_intrinsic_load_vertex_id_zero_base:
 266                         info->uses_vertexid_nobase = 1;
 267                         break;
 268                 case nir_intrinsic_load_base_vertex:
 269                         info->uses_basevertex = 1;
 270                         break;
 271                 case nir_intrinsic_load_draw_id:
 272                         info->uses_drawid = 1;
 273                         break;
 274                 case nir_intrinsic_load_primitive_id:
 275                         info->uses_primid = 1;
 276                         break;
 277                 case nir_intrinsic_load_sample_mask_in:
 278                         info->reads_samplemask = true;
 279                         break;
 280                 case nir_intrinsic_load_tess_level_inner:
 281                 case nir_intrinsic_load_tess_level_outer:
 282                         info->reads_tess_factors = true;
 283                         break;
 284                 case nir_intrinsic_bindless_image_load:
 285                 case nir_intrinsic_bindless_image_size:
 286                 case nir_intrinsic_bindless_image_samples:
 287                         info->uses_bindless_images = true;
 288                         break;
 289                 case nir_intrinsic_bindless_image_store:
 290                         info->uses_bindless_images = true;
 291                         info->writes_memory = true;
 292                         info->num_memory_instructions++; /* we only care about stores */
 293                         break;
 294                 case nir_intrinsic_image_deref_store:
 295                         info->writes_memory = true;
 296                         info->num_memory_instructions++; /* we only care about stores */
 297                         break;
 298                 case nir_intrinsic_bindless_image_atomic_add:
 299                 case nir_intrinsic_bindless_image_atomic_imin:
 300                 case nir_intrinsic_bindless_image_atomic_umin:
 301                 case nir_intrinsic_bindless_image_atomic_imax:
 302                 case nir_intrinsic_bindless_image_atomic_umax:
 303                 case nir_intrinsic_bindless_image_atomic_and:
 304                 case nir_intrinsic_bindless_image_atomic_or:
 305                 case nir_intrinsic_bindless_image_atomic_xor:
 306                 case nir_intrinsic_bindless_image_atomic_exchange:
 307                 case nir_intrinsic_bindless_image_atomic_comp_swap:
 308                         info->uses_bindless_images = true;
 309                         info->writes_memory = true;
 310                         info->num_memory_instructions++; /* we only care about stores */
 311                         break;
 312                 case nir_intrinsic_image_deref_atomic_add:
 313                 case nir_intrinsic_image_deref_atomic_imin:
 314                 case nir_intrinsic_image_deref_atomic_umin:
 315                 case nir_intrinsic_image_deref_atomic_imax:
 316                 case nir_intrinsic_image_deref_atomic_umax:
 317                 case nir_intrinsic_image_deref_atomic_and:
 318                 case nir_intrinsic_image_deref_atomic_or:
 319                 case nir_intrinsic_image_deref_atomic_xor:
 320                 case nir_intrinsic_image_deref_atomic_exchange:
 321                 case nir_intrinsic_image_deref_atomic_comp_swap:
 322                 case nir_intrinsic_image_deref_atomic_inc_wrap:
 323                 case nir_intrinsic_image_deref_atomic_dec_wrap:
 324                         info->writes_memory = true;
 325                         info->num_memory_instructions++; /* we only care about stores */
 326                         break;
 327                 case nir_intrinsic_store_ssbo:
 328                 case nir_intrinsic_ssbo_atomic_add:
 329                 case nir_intrinsic_ssbo_atomic_imin:
 330                 case nir_intrinsic_ssbo_atomic_umin:
 331                 case nir_intrinsic_ssbo_atomic_imax:
 332                 case nir_intrinsic_ssbo_atomic_umax:
 333                 case nir_intrinsic_ssbo_atomic_and:
 334                 case nir_intrinsic_ssbo_atomic_or:
 335                 case nir_intrinsic_ssbo_atomic_xor:
 336                 case nir_intrinsic_ssbo_atomic_exchange:
 337                 case nir_intrinsic_ssbo_atomic_comp_swap:
 338                         info->writes_memory = true;
 339                         info->num_memory_instructions++; /* we only care about stores */
 340                         break;
 341                 case nir_intrinsic_load_color0:
 342                 case nir_intrinsic_load_color1: {
 343                         unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
 344                         uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
 345                         info->colors_read |= mask << (index * 4);
 346                         break;
 347                 }
 348                 case nir_intrinsic_load_barycentric_pixel:
 349                 case nir_intrinsic_load_barycentric_centroid:
 350                 case nir_intrinsic_load_barycentric_sample:
 351                 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
 352                 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
 353                         unsigned mode = nir_intrinsic_interp_mode(intr);
 354
 355                         if (mode == INTERP_MODE_FLAT)
 356                                 break;
 357
 358                         if (mode == INTERP_MODE_NOPERSPECTIVE) {
 359                                 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
 360                                         info->uses_linear_sample = true;
 361                                 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
 362                                         info->uses_linear_centroid = true;
 363                                 else
 364                                         info->uses_linear_center = true;
 365
 366                                 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
 367                                         info->uses_linear_opcode_interp_sample = true;
 368                         } else {
 369                                 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
 370                                         info->uses_persp_sample = true;
 371                                 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
 372                                         info->uses_persp_centroid = true;
 373                                 else
 374                                         info->uses_persp_center = true;
 375
 376                                 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
 377                                         info->uses_persp_opcode_interp_sample = true;
 378                         }
 379                         break;
 380                 }
 381                 case nir_intrinsic_load_deref: {
 382                         nir_variable *var = intrinsic_get_var(intr);
 383                         nir_variable_mode mode = var->data.mode;
 384
 385                         if (mode == nir_var_shader_in) {
 386                                 /* PS inputs use the interpolated load intrinsics. */
 387                                 assert(nir->info.stage != MESA_SHADER_FRAGMENT);
 388                                 gather_intrinsic_load_deref_input_info(nir, intr,
 389                                                                        nir_src_as_deref(intr->src[0]), info);
 390                         } else if (mode == nir_var_shader_out) {
 391                                 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
 392                         }
 393                         break;
 394                 }
 395                 case nir_intrinsic_store_deref: {
 396                         nir_variable *var = intrinsic_get_var(intr);
 397
 398                         if (var->data.mode == nir_var_shader_out)
 399                                 gather_intrinsic_store_deref_output_info(nir, intr,
 400                                                                          nir_src_as_deref(intr->src[0]), info);
 401                         break;
 402                 }
 403                 case nir_intrinsic_interp_deref_at_centroid:
 404                 case nir_intrinsic_interp_deref_at_sample:
 405                 case nir_intrinsic_interp_deref_at_offset:
 406                         unreachable("interp opcodes should have been lowered");
 407                         break;
 408                 default:
 409                         break;
 410                 }
 411         }
 412 }
 413
 414 static void scan_output_slot(const nir_variable *var,
 415                              unsigned var_idx,
 416                              unsigned component, unsigned num_components,
 417                              struct si_shader_info *info)
 418 {
 419         assert(component + num_components <= 4);
 420         assert(component < 4);
 421
 422         unsigned semantic_name, semantic_index;
 423
 424         unsigned location = var->data.location + var_idx;
 425         unsigned drv_location = var->data.driver_location + var_idx;
 426
 427         if (info->processor == PIPE_SHADER_FRAGMENT) {
 428                 tgsi_get_gl_frag_result_semantic(location,
 429                         &semantic_name, &semantic_index);
 430
 431                 /* Adjust for dual source blending */
 432                 if (var->data.index > 0) {
 433                         semantic_index++;
 434                 }
 435         } else {
 436                 tgsi_get_gl_varying_semantic(location, true,
 437                                              &semantic_name, &semantic_index);
 438         }
 439
 440         ubyte usagemask = ((1 << num_components) - 1) << component;
 441
 442         unsigned gs_out_streams;
 443         if (var->data.stream & NIR_STREAM_PACKED) {
 444                 gs_out_streams = var->data.stream & ~NIR_STREAM_PACKED;
 445         } else {
 446                 assert(var->data.stream < 4);
 447                 gs_out_streams = 0;
 448                 for (unsigned j = 0; j < num_components; ++j)
 449                         gs_out_streams |= var->data.stream << (2 * (component + j));
 450         }
 451
 452         unsigned streamx = gs_out_streams & 3;
 453         unsigned streamy = (gs_out_streams >> 2) & 3;
 454         unsigned streamz = (gs_out_streams >> 4) & 3;
 455         unsigned streamw = (gs_out_streams >> 6) & 3;
 456
 457         if (usagemask & TGSI_WRITEMASK_X) {
 458                 info->output_streams[drv_location] |= streamx;
 459                 info->num_stream_output_components[streamx]++;
 460         }
 461         if (usagemask & TGSI_WRITEMASK_Y) {
 462                 info->output_streams[drv_location] |= streamy << 2;
 463                 info->num_stream_output_components[streamy]++;
 464         }
 465         if (usagemask & TGSI_WRITEMASK_Z) {
 466                 info->output_streams[drv_location] |= streamz << 4;
 467                 info->num_stream_output_components[streamz]++;
 468         }
 469         if (usagemask & TGSI_WRITEMASK_W) {
 470                 info->output_streams[drv_location] |= streamw << 6;
 471                 info->num_stream_output_components[streamw]++;
 472         }
 473
 474         info->output_semantic_name[drv_location] = semantic_name;
 475         info->output_semantic_index[drv_location] = semantic_index;
 476
 477         switch (semantic_name) {
 478         case TGSI_SEMANTIC_PRIMID:
 479                 info->writes_primid = true;
 480                 break;
 481         case TGSI_SEMANTIC_VIEWPORT_INDEX:
 482                 info->writes_viewport_index = true;
 483                 break;
 484         case TGSI_SEMANTIC_LAYER:
 485                 info->writes_layer = true;
 486                 break;
 487         case TGSI_SEMANTIC_PSIZE:
 488                 info->writes_psize = true;
 489                 break;
 490         case TGSI_SEMANTIC_CLIPVERTEX:
 491                 info->writes_clipvertex = true;
 492                 break;
 493         case TGSI_SEMANTIC_COLOR:
 494                 info->colors_written |= 1 << semantic_index;
 495                 break;
 496         case TGSI_SEMANTIC_STENCIL:
 497                 info->writes_stencil = true;
 498                 break;
 499         case TGSI_SEMANTIC_SAMPLEMASK:
 500                 info->writes_samplemask = true;
 501                 break;
 502         case TGSI_SEMANTIC_EDGEFLAG:
 503                 info->writes_edgeflag = true;
 504                 break;
 505         case TGSI_SEMANTIC_POSITION:
 506                 if (info->processor == PIPE_SHADER_FRAGMENT)
 507                         info->writes_z = true;
 508                 else
 509                         info->writes_position = true;
 510                 break;
 511         }
 512 }
 513
 514 static void scan_output_helper(const nir_variable *var,
 515                                unsigned location,
 516                                const struct glsl_type *type,
 517                                struct si_shader_info *info)
 518 {
 519         if (glsl_type_is_struct(type) || glsl_type_is_interface(type)) {
 520                 for (unsigned i = 0; i < glsl_get_length(type); i++) {
 521                         const struct glsl_type *ft = glsl_get_struct_field(type, i);
 522                         scan_output_helper(var, location, ft, info);
 523                         location += glsl_count_attribute_slots(ft, false);
 524                 }
 525         } else if (glsl_type_is_array_or_matrix(type)) {
 526                 const struct glsl_type *elem_type =
 527                         glsl_get_array_element(type);
 528                 unsigned num_elems = glsl_get_length(type);
 529                 if (var->data.compact) {
 530                         assert(glsl_type_is_scalar(elem_type));
 531                         assert(glsl_get_bit_size(elem_type) == 32);
 532                         unsigned component = var->data.location_frac;
 533                         scan_output_slot(var, location, component,
 534                                          MIN2(num_elems, 4 - component), info);
 535                         if (component + num_elems > 4) {
 536                                 scan_output_slot(var, location + 1, 0,
 537                                                  component + num_elems - 4, info);
 538                         }
 539
 540                 } else {
 541                         unsigned elem_count = glsl_count_attribute_slots(elem_type, false);
 542                         for (unsigned i = 0; i < num_elems; i++) {
 543                                 scan_output_helper(var, location, elem_type, info);
 544                                 location += elem_count;
 545                         }
 546                 }
 547         } else if (glsl_type_is_dual_slot(type)) {
 548                 unsigned component = var->data.location_frac;
 549                 scan_output_slot(var, location, component, 4 - component, info);
 550                 scan_output_slot(var, location + 1, 0, component + 2 * glsl_get_components(type) - 4,
 551                                  info);
 552         } else {
 553                 unsigned component = var->data.location_frac;
 554                 assert(glsl_type_is_vector_or_scalar(type));
 555                 unsigned num_components = glsl_get_components(type);
 556                 if (glsl_type_is_64bit(type))
 557                         num_components *= 2;
 558                 scan_output_slot(var, location, component, num_components, info);
 559         }
 560 }
 561
 562 void si_nir_scan_shader(const struct nir_shader *nir,
 563                         struct si_shader_info *info)
 564 {
 565         nir_function *func;
 566         unsigned i;
 567
 568         info->processor = pipe_shader_type_from_mesa(nir->info.stage);
 569
 570         info->properties[TGSI_PROPERTY_NEXT_SHADER] =
 571                 pipe_shader_type_from_mesa(nir->info.next_stage);
 572
 573         if (nir->info.stage == MESA_SHADER_VERTEX) {
 574                 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
 575                         nir->info.vs.window_space_position;
 576                 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
 577                         nir->info.vs.blit_sgprs_amd;
 578         }
 579
 580         if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 581                 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
 582                         nir->info.tess.tcs_vertices_out;
 583         }
 584
 585         if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 586                 if (nir->info.tess.primitive_mode == GL_ISOLINES)
 587                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
 588                 else
 589                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
 590
 591                 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
 592                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
 593                               PIPE_TESS_SPACING_FRACTIONAL_ODD);
 594                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
 595                               PIPE_TESS_SPACING_FRACTIONAL_EVEN);
 596
 597                 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
 598                 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
 599                 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
 600         }
 601
 602         if (nir->info.stage == MESA_SHADER_GEOMETRY) {
 603                 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
 604                 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
 605                 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
 606                 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
 607         }
 608
 609         if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 610                 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
 611                         nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
 612                 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
 613
 614                 if (nir->info.fs.pixel_center_integer) {
 615                         info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
 616                                 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
 617                 }
 618
 619                 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
 620                         switch (nir->info.fs.depth_layout) {
 621                         case FRAG_DEPTH_LAYOUT_ANY:
 622                                 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
 623                                 break;
 624                         case FRAG_DEPTH_LAYOUT_GREATER:
 625                                 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
 626                                 break;
 627                         case FRAG_DEPTH_LAYOUT_LESS:
 628                                 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
 629                                 break;
 630                         case FRAG_DEPTH_LAYOUT_UNCHANGED:
 631                                 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
 632                                 break;
 633                         default:
 634                                 unreachable("Unknow depth layout");
 635                         }
 636                 }
 637         }
 638
 639         if (gl_shader_stage_is_compute(nir->info.stage)) {
 640                 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
 641                 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
 642                 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
 643                 info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] = nir->info.cs.user_data_components_amd;
 644         }
 645
 646         i = 0;
 647         uint64_t processed_inputs = 0;
 648         nir_foreach_variable(variable, &nir->inputs) {
 649                 unsigned semantic_name, semantic_index;
 650
 651                 const struct glsl_type *type = variable->type;
 652                 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
 653                         assert(glsl_type_is_array(type));
 654                         type = glsl_get_array_element(type);
 655                 }
 656
 657                 unsigned attrib_count = glsl_count_attribute_slots(type,
 658                                                                    nir->info.stage == MESA_SHADER_VERTEX);
 659
 660                 i = variable->data.driver_location;
 661
 662                 /* Vertex shader inputs don't have semantics. The state
 663                  * tracker has already mapped them to attributes via
 664                  * variable->data.driver_location.
 665                  */
 666                 if (nir->info.stage == MESA_SHADER_VERTEX)
 667                         continue;
 668
 669                 for (unsigned j = 0; j < attrib_count; j++, i++) {
 670
 671                         if (processed_inputs & ((uint64_t)1 << i))
 672                                 continue;
 673
 674                         processed_inputs |= ((uint64_t)1 << i);
 675
 676                         tgsi_get_gl_varying_semantic(variable->data.location + j, true,
 677                                                      &semantic_name, &semantic_index);
 678
 679                         info->input_semantic_name[i] = semantic_name;
 680                         info->input_semantic_index[i] = semantic_index;
 681
 682                         if (semantic_name == TGSI_SEMANTIC_PRIMID)
 683                                 info->uses_primid = true;
 684
 685                         if (semantic_name == TGSI_SEMANTIC_COLOR) {
 686                                 /* We only need this for color inputs. */
 687                                 if (variable->data.sample)
 688                                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
 689                                 else if (variable->data.centroid)
 690                                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
 691                                 else
 692                                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
 693                         }
 694
 695                         enum glsl_base_type base_type =
 696                                 glsl_get_base_type(glsl_without_array(variable->type));
 697
 698                         switch (variable->data.interpolation) {
 699                         case INTERP_MODE_NONE:
 700                                 if (glsl_base_type_is_integer(base_type)) {
 701                                         info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 702                                         break;
 703                                 }
 704
 705                                 if (semantic_name == TGSI_SEMANTIC_COLOR) {
 706                                         info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
 707                                         break;
 708                                 }
 709                                 /* fall-through */
 710
 711                         case INTERP_MODE_SMOOTH:
 712                                 assert(!glsl_base_type_is_integer(base_type));
 713
 714                                 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
 715                                 break;
 716
 717                         case INTERP_MODE_NOPERSPECTIVE:
 718                                 assert(!glsl_base_type_is_integer(base_type));
 719
 720                                 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
 721                                 break;
 722
 723                         case INTERP_MODE_FLAT:
 724                                 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 725                                 break;
 726                         }
 727                 }
 728         }
 729
 730         nir_foreach_variable(variable, &nir->outputs) {
 731                 const struct glsl_type *type = variable->type;
 732                 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
 733                         assert(glsl_type_is_array(type));
 734                         type = glsl_get_array_element(type);
 735                 }
 736
 737                 ASSERTED unsigned attrib_count = glsl_count_attribute_slots(type, false);
 738                 scan_output_helper(variable, 0, type, info);
 739
 740                 unsigned loc = variable->data.location;
 741                 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
 742                     loc == FRAG_RESULT_COLOR &&
 743                     nir->info.outputs_written & (1ull << loc)) {
 744                         assert(attrib_count == 1);
 745                         info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
 746                 }
 747         }
 748
 749         info->num_inputs = nir->num_inputs;
 750         info->num_outputs = nir->num_outputs;
 751
 752         info->constbuf0_num_slots = nir->num_uniforms;
 753         info->shader_buffers_declared = u_bit_consecutive(0, nir->info.num_ssbos);
 754         info->const_buffers_declared = u_bit_consecutive(1, nir->info.num_ubos);
 755         if (nir->num_uniforms > 0)
 756                 info->const_buffers_declared |= 1;
 757         info->images_declared = u_bit_consecutive(0, nir->info.num_images);
 758         info->msaa_images_declared = u_bit_consecutive(0, nir->info.last_msaa_image + 1);
 759         info->samplers_declared = nir->info.textures_used;
 760
 761         info->num_written_clipdistance = nir->info.clip_distance_array_size;
 762         info->num_written_culldistance = nir->info.cull_distance_array_size;
 763         info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
 764         info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
 765
 766         if (info->processor == PIPE_SHADER_FRAGMENT)
 767                 info->uses_kill = nir->info.fs.uses_discard;
 768
 769         if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 770                 info->tessfactors_are_def_in_all_invocs =
 771                         ac_are_tessfactors_def_in_all_invocs(nir);
 772         }
 773
 774         func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
 775         nir_foreach_block(block, func->impl) {
 776                 nir_foreach_instr(instr, block)
 777                         scan_instruction(nir, info, instr);
 778         }
 779 }
 780
 781 static void
 782 si_nir_opts(struct nir_shader *nir)
 783 {
 784         bool progress;
 785
 786         do {
 787                 progress = false;
 788
 789                 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 790
 791                 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
 792                 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
 793
 794                 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
 795                 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
 796
 797                 /* (Constant) copy propagation is needed for txf with offsets. */
 798                 NIR_PASS(progress, nir, nir_copy_prop);
 799                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 800                 NIR_PASS(progress, nir, nir_opt_dce);
 801                 if (nir_opt_trivial_continues(nir)) {
 802                         progress = true;
 803                         NIR_PASS(progress, nir, nir_copy_prop);
 804                         NIR_PASS(progress, nir, nir_opt_dce);
 805                 }
 806                 NIR_PASS(progress, nir, nir_opt_if, true);
 807                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 808                 NIR_PASS(progress, nir, nir_opt_cse);
 809                 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
 810
 811                 /* Needed for algebraic lowering */
 812                 NIR_PASS(progress, nir, nir_opt_algebraic);
 813                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 814
 815                 if (!nir->info.flrp_lowered) {
 816                         unsigned lower_flrp =
 817                                 (nir->options->lower_flrp16 ? 16 : 0) |
 818                                 (nir->options->lower_flrp32 ? 32 : 0) |
 819                                 (nir->options->lower_flrp64 ? 64 : 0);
 820                         assert(lower_flrp);
 821                         bool lower_flrp_progress = false;
 822
 823                         NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
 824                                  lower_flrp,
 825                                  false /* always_precise */,
 826                                  nir->options->lower_ffma);
 827                         if (lower_flrp_progress) {
 828                                 NIR_PASS(progress, nir,
 829                                          nir_opt_constant_folding);
 830                                 progress = true;
 831                         }
 832
 833                         /* Nothing should rematerialize any flrps, so we only
 834                          * need to do this lowering once.
 835                          */
 836                         nir->info.flrp_lowered = true;
 837                 }
 838
 839                 NIR_PASS(progress, nir, nir_opt_undef);
 840                 NIR_PASS(progress, nir, nir_opt_conditional_discard);
 841                 if (nir->options->max_unroll_iterations) {
 842                         NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
 843                 }
 844         } while (progress);
 845 }
 846
 847 static int
 848 type_size_vec4(const struct glsl_type *type, bool bindless)
 849 {
 850         return glsl_count_attribute_slots(type, false);
 851 }
 852
 853 static void
 854 si_nir_lower_color(nir_shader *nir)
 855 {
 856         nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
 857
 858         nir_builder b;
 859         nir_builder_init(&b, entrypoint);
 860
 861         nir_foreach_block(block, entrypoint) {
 862                 nir_foreach_instr_safe(instr, block) {
 863                         if (instr->type != nir_instr_type_intrinsic)
 864                                 continue;
 865
 866                         nir_intrinsic_instr *intrin =
 867                                 nir_instr_as_intrinsic(instr);
 868
 869                         if (intrin->intrinsic != nir_intrinsic_load_deref)
 870                                 continue;
 871
 872                         nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
 873                         if (deref->mode != nir_var_shader_in)
 874                                 continue;
 875
 876                         b.cursor = nir_before_instr(instr);
 877                         nir_variable *var = nir_deref_instr_get_variable(deref);
 878                         nir_ssa_def *def;
 879
 880                         if (var->data.location == VARYING_SLOT_COL0) {
 881                                 def = nir_load_color0(&b);
 882                         } else if (var->data.location == VARYING_SLOT_COL1) {
 883                                 def = nir_load_color1(&b);
 884                         } else {
 885                                 continue;
 886                         }
 887
 888                         nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
 889                         nir_instr_remove(instr);
 890                 }
 891         }
 892 }
 893
 894 static void si_nir_lower_ps_inputs(struct nir_shader *nir)
 895 {
 896         if (nir->info.stage != MESA_SHADER_FRAGMENT)
 897                 return;
 898
 899         NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 900                    nir_shader_get_entrypoint(nir), false, true);
 901
 902         /* Since we're doing nir_lower_io_to_temporaries late, we need
 903          * to lower all the copy_deref's introduced by
 904          * lower_io_to_temporaries before calling nir_lower_io.
 905          */
 906         NIR_PASS_V(nir, nir_split_var_copies);
 907         NIR_PASS_V(nir, nir_lower_var_copies);
 908         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 909
 910         si_nir_lower_color(nir);
 911         NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
 912
 913         /* This pass needs actual constants */
 914         NIR_PASS_V(nir, nir_opt_constant_folding);
 915         NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
 916                    nir_var_shader_in);
 917 }
 918
 919 void si_nir_adjust_driver_locations(struct nir_shader *nir)
 920 {
 921         /* Adjust the driver location of inputs and outputs. The state tracker
 922          * interprets them as slots, while the ac/nir backend interprets them
 923          * as individual components.
 924          */
 925         if (nir->info.stage != MESA_SHADER_FRAGMENT) {
 926                 nir_foreach_variable(variable, &nir->inputs)
 927                         variable->data.driver_location *= 4;
 928         }
 929
 930         nir_foreach_variable(variable, &nir->outputs)
 931                 variable->data.driver_location *= 4;
 932 }
 933
 934 /**
 935  * Perform "lowering" operations on the NIR that are run once when the shader
 936  * selector is created.
 937  */
 938 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
 939 {
 940         /* Perform lowerings (and optimizations) of code.
 941          *
 942          * Performance considerations aside, we must:
 943          * - lower certain ALU operations
 944          * - ensure constant offsets for texture instructions are folded
 945          *   and copy-propagated
 946          */
 947
 948         static const struct nir_lower_tex_options lower_tex_options = {
 949                 .lower_txp = ~0u,
 950         };
 951         NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
 952
 953         const nir_lower_subgroups_options subgroups_options = {
 954                 .subgroup_size = 64,
 955                 .ballot_bit_size = 64,
 956                 .lower_to_scalar = true,
 957                 .lower_subgroup_masks = true,
 958                 .lower_vote_trivial = false,
 959                 .lower_vote_eq_to_ballot = true,
 960         };
 961         NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
 962
 963         /* Lower load constants to scalar and then clean up the mess */
 964         NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
 965         NIR_PASS_V(nir, nir_lower_var_copies);
 966         NIR_PASS_V(nir, nir_lower_pack);
 967         NIR_PASS_V(nir, nir_opt_access);
 968         si_nir_opts(nir);
 969
 970         /* Lower large variables that are always constant with load_constant
 971          * intrinsics, which get turned into PC-relative loads from a data
 972          * section next to the shader.
 973          *
 974          * st/mesa calls finalize_nir twice, but we can't call this pass twice.
 975          */
 976         bool changed = false;
 977         if (!nir->constant_data) {
 978                 NIR_PASS(changed, nir, nir_opt_large_constants,
 979                          glsl_get_natural_size_align_bytes, 16);
 980         }
 981
 982         changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
 983         if (changed)
 984                 si_nir_opts(nir);
 985
 986         NIR_PASS_V(nir, nir_lower_bool_to_int32);
 987         NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp);
 988 }
 989
 990 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
 991 {
 992         struct si_screen *sscreen = (struct si_screen *)screen;
 993         struct nir_shader *nir = (struct nir_shader *)nirptr;
 994
 995         nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 996         si_nir_lower_ps_inputs(nir);
 997         si_lower_nir(sscreen, nir);
 998 }
 999
1000 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1001 {
1002         if (nir->info.stage == MESA_SHADER_VERTEX) {
1003                 si_llvm_load_vs_inputs(ctx, nir);
1004         } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1005                 unsigned colors_read =
1006                         ctx->shader->selector->info.colors_read;
1007                 LLVMValueRef main_fn = ctx->main_fn;
1008
1009                 LLVMValueRef undef = LLVMGetUndef(ctx->ac.f32);
1010
1011                 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1012
1013                 if (colors_read & 0x0f) {
1014                         unsigned mask = colors_read & 0x0f;
1015                         LLVMValueRef values[4];
1016                         values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1017                         values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1018                         values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1019                         values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1020                         ctx->abi.color0 =
1021                                 ac_to_integer(&ctx->ac,
1022                                               ac_build_gather_values(&ctx->ac, values, 4));
1023                 }
1024                 if (colors_read & 0xf0) {
1025                         unsigned mask = (colors_read & 0xf0) >> 4;
1026                         LLVMValueRef values[4];
1027                         values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1028                         values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1029                         values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1030                         values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1031                         ctx->abi.color1 =
1032                                 ac_to_integer(&ctx->ac,
1033                                               ac_build_gather_values(&ctx->ac, values, 4));
1034                 }
1035
1036                 ctx->abi.interp_at_sample_force_center =
1037                         ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
1038         } else if (nir->info.stage == MESA_SHADER_COMPUTE) {
1039                 if (nir->info.cs.user_data_components_amd) {
1040                         ctx->abi.user_data = ac_get_arg(&ctx->ac, ctx->cs_user_data);
1041                         ctx->abi.user_data = ac_build_expand_to_vec4(&ctx->ac, ctx->abi.user_data,
1042                                                                      nir->info.cs.user_data_components_amd);
1043                 }
1044         }
1045
1046         ctx->abi.inputs = &ctx->inputs[0];
1047         ctx->abi.clamp_shadow_reference = true;
1048         ctx->abi.robust_buffer_access = true;
1049
1050         if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1051                 assert(gl_shader_stage_is_compute(nir->info.stage));
1052                 si_declare_compute_memory(ctx);
1053         }
1054         ac_nir_translate(&ctx->ac, &ctx->abi, &ctx->args, nir);
1055
1056         return true;
1057 }