8341181dec0372baa8acb37354aac388a16107e8
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_nir_to_llvm.h"
26 #include "compiler/nir/nir.h"
27 #include "compiler/nir/nir_builder.h"
28 #include "compiler/nir/nir_deref.h"
29 #include "compiler/nir_types.h"
30 #include "si_pipe.h"
31 #include "si_shader_internal.h"
32 #include "tgsi/tgsi_from_mesa.h"
33
34 static const nir_deref_instr *tex_get_texture_deref(nir_tex_instr *instr)
35 {
36 for (unsigned i = 0; i < instr->num_srcs; i++) {
37 switch (instr->src[i].src_type) {
38 case nir_tex_src_texture_deref:
39 return nir_src_as_deref(instr->src[i].src);
40 default:
41 break;
42 }
43 }
44
45 return NULL;
46 }
47
48 static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr,
49 bool is_input)
50 {
51 unsigned interp = INTERP_MODE_FLAT; /* load_input uses flat shading */
52
53 if (intr->intrinsic == nir_intrinsic_load_interpolated_input) {
54 nir_intrinsic_instr *baryc = nir_instr_as_intrinsic(intr->src[0].ssa->parent_instr);
55
56 if (baryc) {
57 if (nir_intrinsic_infos[baryc->intrinsic].index_map[NIR_INTRINSIC_INTERP_MODE] > 0)
58 interp = nir_intrinsic_interp_mode(baryc);
59 else
60 unreachable("unknown barycentric intrinsic");
61 } else {
62 unreachable("unknown barycentric expression");
63 }
64 }
65
66 unsigned mask, bit_size;
67 bool dual_slot, is_output_load;
68
69 if (nir_intrinsic_infos[intr->intrinsic].index_map[NIR_INTRINSIC_WRMASK] > 0) {
70 mask = nir_intrinsic_write_mask(intr); /* store */
71 bit_size = nir_src_bit_size(intr->src[0]);
72 dual_slot = bit_size == 64 && nir_src_num_components(intr->src[0]) >= 3;
73 is_output_load = false;
74 } else {
75 mask = nir_ssa_def_components_read(&intr->dest.ssa); /* load */
76 bit_size = intr->dest.ssa.bit_size;
77 dual_slot = bit_size == 64 && intr->dest.ssa.num_components >= 3;
78 is_output_load = !is_input;
79 }
80
81 /* Convert the 64-bit component mask to a 32-bit component mask. */
82 if (bit_size == 64) {
83 unsigned new_mask = 0;
84 for (unsigned i = 0; i < 4; i++) {
85 if (mask & (1 << i))
86 new_mask |= 0x3 << (2 * i);
87 }
88 mask = new_mask;
89 }
90
91 /* Convert the 16-bit component mask to a 32-bit component mask. */
92 if (bit_size == 16) {
93 unsigned new_mask = 0;
94 for (unsigned i = 0; i < 4; i++) {
95 if (mask & (1 << i))
96 new_mask |= 0x1 << (i / 2);
97 }
98 mask = new_mask;
99 }
100
101 mask <<= nir_intrinsic_component(intr);
102
103 nir_src offset = *nir_get_io_offset_src(intr);
104 bool indirect = !nir_src_is_const(offset);
105 if (!indirect)
106 assert(nir_src_as_uint(offset) == 0);
107
108 unsigned semantic = 0;
109 /* VS doesn't have semantics. */
110 if (info->stage != MESA_SHADER_VERTEX || !is_input)
111 semantic = nir_intrinsic_io_semantics(intr).location;
112
113 if (info->stage == MESA_SHADER_FRAGMENT && !is_input) {
114 /* Never use FRAG_RESULT_COLOR directly. */
115 if (semantic == FRAG_RESULT_COLOR) {
116 semantic = FRAG_RESULT_DATA0;
117 info->color0_writes_all_cbufs = true;
118 }
119 semantic += nir_intrinsic_io_semantics(intr).dual_source_blend_index;
120 }
121
122 unsigned driver_location = nir_intrinsic_base(intr);
123 unsigned num_slots = indirect ? nir_intrinsic_io_semantics(intr).num_slots : (1 + dual_slot);
124
125 if (is_input) {
126 assert(driver_location + num_slots <= ARRAY_SIZE(info->input_usage_mask));
127
128 for (unsigned i = 0; i < num_slots; i++) {
129 unsigned loc = driver_location + i;
130 unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
131
132 info->input_semantic[loc] = semantic + i;
133 info->input_interpolate[loc] = interp;
134
135 if (slot_mask) {
136 info->input_usage_mask[loc] |= slot_mask;
137 info->num_inputs = MAX2(info->num_inputs, loc + 1);
138
139 if (semantic == VARYING_SLOT_PRIMITIVE_ID)
140 info->uses_primid = true;
141 }
142 }
143 } else {
144 /* Outputs. */
145 assert(driver_location + num_slots <= ARRAY_SIZE(info->output_usagemask));
146 assert(semantic + num_slots < ARRAY_SIZE(info->output_semantic_to_slot));
147
148 for (unsigned i = 0; i < num_slots; i++) {
149 unsigned loc = driver_location + i;
150 unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
151
152 info->output_semantic[loc] = semantic + i;
153 info->output_semantic_to_slot[semantic + i] = loc;
154
155 if (is_output_load) {
156 /* Output loads have only a few things that we need to track. */
157 info->output_readmask[loc] |= slot_mask;
158
159 if (info->stage == MESA_SHADER_FRAGMENT &&
160 nir_intrinsic_io_semantics(intr).fb_fetch_output)
161 info->uses_fbfetch = true;
162 } else if (slot_mask) {
163 /* Output stores. */
164 if (info->stage == MESA_SHADER_GEOMETRY) {
165 unsigned gs_streams = (uint32_t)nir_intrinsic_io_semantics(intr).gs_streams <<
166 (nir_intrinsic_component(intr) * 2);
167 unsigned new_mask = slot_mask & ~info->output_usagemask[loc];
168
169 for (unsigned i = 0; i < 4; i++) {
170 unsigned stream = (gs_streams >> (i * 2)) & 0x3;
171
172 if (new_mask & (1 << i)) {
173 info->output_streams[loc] |= stream << (i * 2);
174 info->num_stream_output_components[stream]++;
175 }
176 }
177 }
178
179 info->output_usagemask[loc] |= slot_mask;
180 info->num_outputs = MAX2(info->num_outputs, loc + 1);
181
182 if (info->stage == MESA_SHADER_FRAGMENT) {
183 switch (semantic) {
184 case FRAG_RESULT_DEPTH:
185 info->writes_z = true;
186 break;
187 case FRAG_RESULT_STENCIL:
188 info->writes_stencil = true;
189 break;
190 case FRAG_RESULT_SAMPLE_MASK:
191 info->writes_samplemask = true;
192 break;
193 default:
194 if (semantic >= FRAG_RESULT_DATA0 && semantic <= FRAG_RESULT_DATA7) {
195 unsigned index = semantic - FRAG_RESULT_DATA0;
196 info->colors_written |= 1 << (index + i);
197 }
198 break;
199 }
200 } else {
201 switch (semantic) {
202 case VARYING_SLOT_PRIMITIVE_ID:
203 info->writes_primid = true;
204 break;
205 case VARYING_SLOT_VIEWPORT:
206 info->writes_viewport_index = true;
207 break;
208 case VARYING_SLOT_LAYER:
209 info->writes_layer = true;
210 break;
211 case VARYING_SLOT_PSIZ:
212 info->writes_psize = true;
213 break;
214 case VARYING_SLOT_CLIP_VERTEX:
215 info->writes_clipvertex = true;
216 break;
217 case VARYING_SLOT_EDGE:
218 info->writes_edgeflag = true;
219 break;
220 case VARYING_SLOT_POS:
221 info->writes_position = true;
222 break;
223 }
224 }
225 }
226 }
227 }
228 }
229
230 static void scan_instruction(const struct nir_shader *nir, struct si_shader_info *info,
231 nir_instr *instr)
232 {
233 if (instr->type == nir_instr_type_alu) {
234 nir_alu_instr *alu = nir_instr_as_alu(instr);
235
236 switch (alu->op) {
237 case nir_op_fddx:
238 case nir_op_fddy:
239 case nir_op_fddx_fine:
240 case nir_op_fddy_fine:
241 case nir_op_fddx_coarse:
242 case nir_op_fddy_coarse:
243 info->uses_derivatives = true;
244 break;
245 default:
246 break;
247 }
248 } else if (instr->type == nir_instr_type_tex) {
249 nir_tex_instr *tex = nir_instr_as_tex(instr);
250 const nir_deref_instr *deref = tex_get_texture_deref(tex);
251 nir_variable *var = deref ? nir_deref_instr_get_variable(deref) : NULL;
252
253 if (var) {
254 if (deref->mode != nir_var_uniform || var->data.bindless)
255 info->uses_bindless_samplers = true;
256 }
257
258 switch (tex->op) {
259 case nir_texop_tex:
260 case nir_texop_txb:
261 case nir_texop_lod:
262 info->uses_derivatives = true;
263 break;
264 default:
265 break;
266 }
267 } else if (instr->type == nir_instr_type_intrinsic) {
268 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
269
270 switch (intr->intrinsic) {
271 case nir_intrinsic_load_front_face:
272 info->uses_frontface = 1;
273 break;
274 case nir_intrinsic_load_instance_id:
275 info->uses_instanceid = 1;
276 break;
277 case nir_intrinsic_load_invocation_id:
278 info->uses_invocationid = true;
279 break;
280 case nir_intrinsic_load_num_work_groups:
281 info->uses_grid_size = true;
282 break;
283 case nir_intrinsic_load_local_invocation_index:
284 case nir_intrinsic_load_subgroup_id:
285 case nir_intrinsic_load_num_subgroups:
286 info->uses_subgroup_info = true;
287 break;
288 case nir_intrinsic_load_local_group_size:
289 /* The block size is translated to IMM with a fixed block size. */
290 if (info->base.cs.local_size[0] == 0)
291 info->uses_block_size = true;
292 break;
293 case nir_intrinsic_load_local_invocation_id:
294 case nir_intrinsic_load_work_group_id: {
295 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
296 while (mask) {
297 unsigned i = u_bit_scan(&mask);
298
299 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
300 info->uses_block_id[i] = true;
301 else
302 info->uses_thread_id[i] = true;
303 }
304 break;
305 }
306 case nir_intrinsic_load_vertex_id:
307 info->uses_vertexid = 1;
308 break;
309 case nir_intrinsic_load_vertex_id_zero_base:
310 info->uses_vertexid_nobase = 1;
311 break;
312 case nir_intrinsic_load_base_vertex:
313 info->uses_basevertex = 1;
314 break;
315 case nir_intrinsic_load_draw_id:
316 info->uses_drawid = 1;
317 break;
318 case nir_intrinsic_load_primitive_id:
319 info->uses_primid = 1;
320 break;
321 case nir_intrinsic_load_sample_mask_in:
322 info->reads_samplemask = true;
323 break;
324 case nir_intrinsic_load_tess_level_inner:
325 case nir_intrinsic_load_tess_level_outer:
326 info->reads_tess_factors = true;
327 break;
328 case nir_intrinsic_bindless_image_load:
329 case nir_intrinsic_bindless_image_size:
330 case nir_intrinsic_bindless_image_samples:
331 info->uses_bindless_images = true;
332 break;
333 case nir_intrinsic_bindless_image_store:
334 info->uses_bindless_images = true;
335 info->writes_memory = true;
336 info->num_memory_instructions++; /* we only care about stores */
337 break;
338 case nir_intrinsic_image_deref_store:
339 info->writes_memory = true;
340 info->num_memory_instructions++; /* we only care about stores */
341 break;
342 case nir_intrinsic_bindless_image_atomic_add:
343 case nir_intrinsic_bindless_image_atomic_imin:
344 case nir_intrinsic_bindless_image_atomic_umin:
345 case nir_intrinsic_bindless_image_atomic_imax:
346 case nir_intrinsic_bindless_image_atomic_umax:
347 case nir_intrinsic_bindless_image_atomic_and:
348 case nir_intrinsic_bindless_image_atomic_or:
349 case nir_intrinsic_bindless_image_atomic_xor:
350 case nir_intrinsic_bindless_image_atomic_exchange:
351 case nir_intrinsic_bindless_image_atomic_comp_swap:
352 info->uses_bindless_images = true;
353 info->writes_memory = true;
354 info->num_memory_instructions++; /* we only care about stores */
355 break;
356 case nir_intrinsic_image_deref_atomic_add:
357 case nir_intrinsic_image_deref_atomic_imin:
358 case nir_intrinsic_image_deref_atomic_umin:
359 case nir_intrinsic_image_deref_atomic_imax:
360 case nir_intrinsic_image_deref_atomic_umax:
361 case nir_intrinsic_image_deref_atomic_and:
362 case nir_intrinsic_image_deref_atomic_or:
363 case nir_intrinsic_image_deref_atomic_xor:
364 case nir_intrinsic_image_deref_atomic_exchange:
365 case nir_intrinsic_image_deref_atomic_comp_swap:
366 case nir_intrinsic_image_deref_atomic_inc_wrap:
367 case nir_intrinsic_image_deref_atomic_dec_wrap:
368 info->writes_memory = true;
369 info->num_memory_instructions++; /* we only care about stores */
370 break;
371 case nir_intrinsic_store_ssbo:
372 case nir_intrinsic_ssbo_atomic_add:
373 case nir_intrinsic_ssbo_atomic_imin:
374 case nir_intrinsic_ssbo_atomic_umin:
375 case nir_intrinsic_ssbo_atomic_imax:
376 case nir_intrinsic_ssbo_atomic_umax:
377 case nir_intrinsic_ssbo_atomic_and:
378 case nir_intrinsic_ssbo_atomic_or:
379 case nir_intrinsic_ssbo_atomic_xor:
380 case nir_intrinsic_ssbo_atomic_exchange:
381 case nir_intrinsic_ssbo_atomic_comp_swap:
382 info->writes_memory = true;
383 info->num_memory_instructions++; /* we only care about stores */
384 break;
385 case nir_intrinsic_load_color0:
386 case nir_intrinsic_load_color1: {
387 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
388 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
389 info->colors_read |= mask << (index * 4);
390 break;
391 }
392 case nir_intrinsic_load_barycentric_pixel:
393 case nir_intrinsic_load_barycentric_centroid:
394 case nir_intrinsic_load_barycentric_sample:
395 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
396 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
397 unsigned mode = nir_intrinsic_interp_mode(intr);
398
399 if (mode == INTERP_MODE_FLAT)
400 break;
401
402 if (mode == INTERP_MODE_NOPERSPECTIVE) {
403 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
404 info->uses_linear_sample = true;
405 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
406 info->uses_linear_centroid = true;
407 else
408 info->uses_linear_center = true;
409
410 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
411 info->uses_linear_opcode_interp_sample = true;
412 } else {
413 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
414 info->uses_persp_sample = true;
415 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
416 info->uses_persp_centroid = true;
417 else
418 info->uses_persp_center = true;
419
420 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
421 info->uses_persp_opcode_interp_sample = true;
422 }
423 break;
424 }
425 case nir_intrinsic_load_input:
426 case nir_intrinsic_load_per_vertex_input:
427 case nir_intrinsic_load_input_vertex:
428 case nir_intrinsic_load_interpolated_input:
429 scan_io_usage(info, intr, true);
430 break;
431 case nir_intrinsic_load_output:
432 case nir_intrinsic_load_per_vertex_output:
433 case nir_intrinsic_store_output:
434 case nir_intrinsic_store_per_vertex_output:
435 scan_io_usage(info, intr, false);
436 break;
437 case nir_intrinsic_load_deref:
438 case nir_intrinsic_store_deref:
439 case nir_intrinsic_interp_deref_at_centroid:
440 case nir_intrinsic_interp_deref_at_sample:
441 case nir_intrinsic_interp_deref_at_offset:
442 unreachable("these opcodes should have been lowered");
443 break;
444 default:
445 break;
446 }
447 }
448 }
449
450 void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *info)
451 {
452 nir_function *func;
453
454 info->base = nir->info;
455 info->stage = nir->info.stage;
456
457 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
458 if (info->base.tess.primitive_mode == GL_ISOLINES)
459 info->base.tess.primitive_mode = GL_LINES;
460 }
461
462 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
463 /* post_depth_coverage implies early_fragment_tests */
464 info->base.fs.early_fragment_tests |= info->base.fs.post_depth_coverage;
465
466 info->color_interpolate[0] = nir->info.fs.color0_interp;
467 info->color_interpolate[1] = nir->info.fs.color1_interp;
468 for (unsigned i = 0; i < 2; i++) {
469 if (info->color_interpolate[i] == INTERP_MODE_NONE)
470 info->color_interpolate[i] = INTERP_MODE_COLOR;
471 }
472
473 info->color_interpolate_loc[0] = nir->info.fs.color0_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
474 nir->info.fs.color0_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
475 TGSI_INTERPOLATE_LOC_CENTER;
476 info->color_interpolate_loc[1] = nir->info.fs.color1_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
477 nir->info.fs.color1_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
478 TGSI_INTERPOLATE_LOC_CENTER;
479 }
480
481 info->constbuf0_num_slots = nir->num_uniforms;
482
483 if (info->stage == MESA_SHADER_FRAGMENT)
484 info->uses_kill = nir->info.fs.uses_discard;
485
486 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
487 info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir);
488 }
489
490 memset(info->output_semantic_to_slot, -1, sizeof(info->output_semantic_to_slot));
491
492 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
493 nir_foreach_block (block, func->impl) {
494 nir_foreach_instr (instr, block)
495 scan_instruction(nir, info, instr);
496 }
497
498 /* Add color inputs to the list of inputs. */
499 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
500 for (unsigned i = 0; i < 2; i++) {
501 if ((info->colors_read >> (i * 4)) & 0xf) {
502 info->input_semantic[info->num_inputs] = VARYING_SLOT_COL0 + i;
503 info->input_interpolate[info->num_inputs] = info->color_interpolate[i];
504 info->input_usage_mask[info->num_inputs] = info->colors_read >> (i * 4);
505 info->num_inputs++;
506 }
507 }
508 }
509
510 /* Trim output read masks based on write masks. */
511 for (unsigned i = 0; i < info->num_outputs; i++)
512 info->output_readmask[i] &= info->output_usagemask[i];
513 }
514
515 static void si_nir_opts(struct nir_shader *nir, bool first)
516 {
517 bool progress;
518
519 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
520 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
521 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
522
523 do {
524 progress = false;
525 bool lower_alu_to_scalar = false;
526 bool lower_phis_to_scalar = false;
527
528 if (first) {
529 bool opt_find_array_copies = false;
530
531 NIR_PASS(progress, nir, nir_split_array_vars, nir_var_function_temp);
532 NIR_PASS(lower_alu_to_scalar, nir, nir_shrink_vec_array_vars, nir_var_function_temp);
533 NIR_PASS(opt_find_array_copies, nir, nir_opt_find_array_copies);
534 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
535
536 /* Call nir_lower_var_copies() to remove any copies introduced
537 * by nir_opt_find_array_copies().
538 */
539 if (opt_find_array_copies)
540 NIR_PASS(progress, nir, nir_lower_var_copies);
541 progress |= opt_find_array_copies;
542 } else {
543 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
544 }
545
546 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
547
548 NIR_PASS(lower_alu_to_scalar, nir, nir_opt_trivial_continues);
549 /* (Constant) copy propagation is needed for txf with offsets. */
550 NIR_PASS(progress, nir, nir_copy_prop);
551 NIR_PASS(progress, nir, nir_opt_remove_phis);
552 NIR_PASS(progress, nir, nir_opt_dce);
553 NIR_PASS(lower_phis_to_scalar, nir, nir_opt_if, true);
554 NIR_PASS(progress, nir, nir_opt_dead_cf);
555
556 if (lower_alu_to_scalar)
557 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
558 if (lower_phis_to_scalar)
559 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
560 progress |= lower_alu_to_scalar | lower_phis_to_scalar;
561
562 NIR_PASS(progress, nir, nir_opt_cse);
563 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
564
565 /* Needed for algebraic lowering */
566 NIR_PASS(progress, nir, nir_opt_algebraic);
567 NIR_PASS(progress, nir, nir_opt_constant_folding);
568
569 if (!nir->info.flrp_lowered) {
570 unsigned lower_flrp = (nir->options->lower_flrp16 ? 16 : 0) |
571 (nir->options->lower_flrp32 ? 32 : 0) |
572 (nir->options->lower_flrp64 ? 64 : 0);
573 assert(lower_flrp);
574 bool lower_flrp_progress = false;
575
576 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp, lower_flrp, false /* always_precise */);
577 if (lower_flrp_progress) {
578 NIR_PASS(progress, nir, nir_opt_constant_folding);
579 progress = true;
580 }
581
582 /* Nothing should rematerialize any flrps, so we only
583 * need to do this lowering once.
584 */
585 nir->info.flrp_lowered = true;
586 }
587
588 NIR_PASS(progress, nir, nir_opt_undef);
589 NIR_PASS(progress, nir, nir_opt_conditional_discard);
590 if (nir->options->max_unroll_iterations) {
591 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
592 }
593 } while (progress);
594 }
595
596 static int type_size_vec4(const struct glsl_type *type, bool bindless)
597 {
598 return glsl_count_attribute_slots(type, false);
599 }
600
601 static void si_nir_lower_color(nir_shader *nir)
602 {
603 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
604
605 nir_builder b;
606 nir_builder_init(&b, entrypoint);
607
608 nir_foreach_block (block, entrypoint) {
609 nir_foreach_instr_safe (instr, block) {
610 if (instr->type != nir_instr_type_intrinsic)
611 continue;
612
613 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
614
615 if (intrin->intrinsic != nir_intrinsic_load_deref)
616 continue;
617
618 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
619 if (deref->mode != nir_var_shader_in)
620 continue;
621
622 b.cursor = nir_before_instr(instr);
623 nir_variable *var = nir_deref_instr_get_variable(deref);
624 nir_ssa_def *def;
625
626 if (var->data.location == VARYING_SLOT_COL0) {
627 def = nir_load_color0(&b);
628 nir->info.fs.color0_interp = var->data.interpolation;
629 nir->info.fs.color0_sample = var->data.sample;
630 nir->info.fs.color0_centroid = var->data.centroid;
631 } else if (var->data.location == VARYING_SLOT_COL1) {
632 def = nir_load_color1(&b);
633 nir->info.fs.color1_interp = var->data.interpolation;
634 nir->info.fs.color1_sample = var->data.sample;
635 nir->info.fs.color1_centroid = var->data.centroid;
636 } else {
637 continue;
638 }
639
640 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
641 nir_instr_remove(instr);
642 }
643 }
644 }
645
646 static void si_lower_io(struct nir_shader *nir)
647 {
648 /* HW supports indirect indexing for: | Enabled in driver
649 * -------------------------------------------------------
650 * VS inputs | No
651 * TCS inputs | Yes
652 * TES inputs | Yes
653 * GS inputs | No
654 * -------------------------------------------------------
655 * VS outputs before TCS | No
656 * VS outputs before GS | No
657 * TCS outputs | Yes
658 * TES outputs before GS | No
659 */
660 bool has_indirect_inputs = nir->info.stage == MESA_SHADER_TESS_CTRL ||
661 nir->info.stage == MESA_SHADER_TESS_EVAL;
662 bool has_indirect_outputs = nir->info.stage == MESA_SHADER_TESS_CTRL;
663
664 if (!has_indirect_inputs || !has_indirect_outputs) {
665 NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir),
666 !has_indirect_outputs, !has_indirect_inputs);
667
668 /* Since we're doing nir_lower_io_to_temporaries late, we need
669 * to lower all the copy_deref's introduced by
670 * lower_io_to_temporaries before calling nir_lower_io.
671 */
672 NIR_PASS_V(nir, nir_split_var_copies);
673 NIR_PASS_V(nir, nir_lower_var_copies);
674 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
675 }
676
677 if (nir->info.stage == MESA_SHADER_FRAGMENT)
678 si_nir_lower_color(nir);
679
680 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_out | nir_var_shader_in,
681 type_size_vec4, 0);
682 nir->info.io_lowered = true;
683
684 /* This pass needs actual constants */
685 NIR_PASS_V(nir, nir_opt_constant_folding);
686 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
687 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_out);
688
689 /* Remove dead derefs, so that nir_validate doesn't fail. */
690 NIR_PASS_V(nir, nir_opt_dce);
691
692 /* Remove input and output nir_variables, because we don't need them
693 * anymore. Also remove uniforms, because those should have been lowered
694 * to UBOs already.
695 */
696 unsigned modes = nir_var_shader_in | nir_var_shader_out | nir_var_uniform;
697 nir_foreach_variable_with_modes_safe(var, nir, modes) {
698 if (var->data.mode == nir_var_uniform &&
699 (glsl_type_get_image_count(var->type) ||
700 glsl_type_get_sampler_count(var->type)))
701 continue;
702
703 exec_node_remove(&var->node);
704 }
705 }
706
707 /**
708 * Perform "lowering" operations on the NIR that are run once when the shader
709 * selector is created.
710 */
711 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
712 {
713 /* Perform lowerings (and optimizations) of code.
714 *
715 * Performance considerations aside, we must:
716 * - lower certain ALU operations
717 * - ensure constant offsets for texture instructions are folded
718 * and copy-propagated
719 */
720
721 static const struct nir_lower_tex_options lower_tex_options = {
722 .lower_txp = ~0u,
723 };
724 NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
725
726 const nir_lower_subgroups_options subgroups_options = {
727 .subgroup_size = 64,
728 .ballot_bit_size = 64,
729 .lower_to_scalar = true,
730 .lower_subgroup_masks = true,
731 .lower_vote_trivial = false,
732 .lower_vote_eq_to_ballot = true,
733 };
734 NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
735
736 /* Lower load constants to scalar and then clean up the mess */
737 NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
738 NIR_PASS_V(nir, nir_lower_var_copies);
739 NIR_PASS_V(nir, nir_lower_pack);
740 NIR_PASS_V(nir, nir_opt_access);
741 si_nir_opts(nir, true);
742
743 /* Lower large variables that are always constant with load_constant
744 * intrinsics, which get turned into PC-relative loads from a data
745 * section next to the shader.
746 *
747 * st/mesa calls finalize_nir twice, but we can't call this pass twice.
748 */
749 bool changed = false;
750 if (!nir->constant_data) {
751 /* The pass crashes if there are dead temps of lowered IO interface types. */
752 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
753 NIR_PASS(changed, nir, nir_opt_large_constants, glsl_get_natural_size_align_bytes, 16);
754 }
755
756 changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
757 if (changed)
758 si_nir_opts(nir, false);
759
760 NIR_PASS_V(nir, nir_lower_bool_to_int32);
761 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
762
763 if (sscreen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
764 NIR_PASS_V(nir, nir_lower_discard_to_demote);
765 }
766
767 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
768 {
769 struct si_screen *sscreen = (struct si_screen *)screen;
770 struct nir_shader *nir = (struct nir_shader *)nirptr;
771
772 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
773 si_lower_io(nir);
774 si_lower_nir(sscreen, nir);
775 }