2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "ac_nir_to_llvm.h"
26 #include "compiler/nir/nir.h"
27 #include "compiler/nir/nir_builder.h"
28 #include "compiler/nir/nir_deref.h"
29 #include "compiler/nir_types.h"
31 #include "si_shader_internal.h"
32 #include "tgsi/tgsi_from_mesa.h"
34 static const nir_deref_instr
*tex_get_texture_deref(nir_tex_instr
*instr
)
36 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
37 switch (instr
->src
[i
].src_type
) {
38 case nir_tex_src_texture_deref
:
39 return nir_src_as_deref(instr
->src
[i
].src
);
48 static void scan_io_usage(struct si_shader_info
*info
, nir_intrinsic_instr
*intr
,
51 unsigned interp
= TGSI_INTERPOLATE_CONSTANT
; /* load_input uses flat shading */
53 if (intr
->intrinsic
== nir_intrinsic_load_interpolated_input
) {
54 nir_intrinsic_instr
*baryc
= nir_instr_as_intrinsic(intr
->src
[0].ssa
->parent_instr
);
57 if (nir_intrinsic_infos
[baryc
->intrinsic
].index_map
[NIR_INTRINSIC_INTERP_MODE
] > 0)
58 interp
= tgsi_get_interp_mode(nir_intrinsic_interp_mode(baryc
), false);
60 unreachable("unknown barycentric intrinsic");
62 unreachable("unknown barycentric expression");
66 unsigned mask
, bit_size
;
67 bool dual_slot
, is_output_load
;
69 if (nir_intrinsic_infos
[intr
->intrinsic
].index_map
[NIR_INTRINSIC_WRMASK
] > 0) {
70 mask
= nir_intrinsic_write_mask(intr
); /* store */
71 bit_size
= nir_src_bit_size(intr
->src
[0]);
72 dual_slot
= bit_size
== 64 && nir_src_num_components(intr
->src
[0]) >= 3;
73 is_output_load
= false;
75 mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
); /* load */
76 bit_size
= intr
->dest
.ssa
.bit_size
;
77 dual_slot
= bit_size
== 64 && intr
->dest
.ssa
.num_components
>= 3;
78 is_output_load
= !is_input
;
81 /* Convert the 64-bit component mask to a 32-bit component mask. */
83 unsigned new_mask
= 0;
84 for (unsigned i
= 0; i
< 4; i
++) {
86 new_mask
|= 0x3 << (2 * i
);
91 /* Convert the 16-bit component mask to a 32-bit component mask. */
93 unsigned new_mask
= 0;
94 for (unsigned i
= 0; i
< 4; i
++) {
96 new_mask
|= 0x1 << (i
/ 2);
101 mask
<<= nir_intrinsic_component(intr
);
103 unsigned name
, index
;
104 if (info
->stage
== MESA_SHADER_VERTEX
&& is_input
) {
105 /* VS doesn't have semantics. */
108 } else if (info
->stage
== MESA_SHADER_FRAGMENT
&& !is_input
) {
109 tgsi_get_gl_frag_result_semantic(nir_intrinsic_io_semantics(intr
).location
,
111 /* Adjust for dual source blending. */
112 if (nir_intrinsic_io_semantics(intr
).dual_source_blend_index
)
115 tgsi_get_gl_varying_semantic(nir_intrinsic_io_semantics(intr
).location
,
116 true, &name
, &index
);
119 nir_src offset
= *nir_get_io_offset_src(intr
);
120 bool indirect
= !nir_src_is_const(offset
);
122 assert(nir_src_as_uint(offset
) == 0);
124 unsigned driver_location
= nir_intrinsic_base(intr
);
125 unsigned num_slots
= indirect
? nir_intrinsic_io_semantics(intr
).num_slots
: (1 + dual_slot
);
128 assert(driver_location
+ num_slots
<= ARRAY_SIZE(info
->input_usage_mask
));
130 for (unsigned i
= 0; i
< num_slots
; i
++) {
131 unsigned loc
= driver_location
+ i
;
132 unsigned slot_mask
= (dual_slot
&& i
% 2 ? mask
>> 4 : mask
) & 0xf;
134 info
->input_semantic_name
[loc
] = name
;
135 info
->input_semantic_index
[loc
] = index
+ i
;
136 info
->input_interpolate
[loc
] = interp
;
139 info
->input_usage_mask
[loc
] |= slot_mask
;
140 info
->num_inputs
= MAX2(info
->num_inputs
, loc
+ 1);
142 if (name
== TGSI_SEMANTIC_PRIMID
)
143 info
->uses_primid
= true;
148 assert(driver_location
+ num_slots
<= ARRAY_SIZE(info
->output_usagemask
));
150 for (unsigned i
= 0; i
< num_slots
; i
++) {
151 unsigned loc
= driver_location
+ i
;
152 unsigned slot_mask
= (dual_slot
&& i
% 2 ? mask
>> 4 : mask
) & 0xf;
154 info
->output_semantic_name
[loc
] = name
;
155 info
->output_semantic_index
[loc
] = index
+ i
;
157 if (is_output_load
) {
158 /* Output loads have only a few things that we need to track. */
159 info
->output_readmask
[loc
] |= slot_mask
;
161 if (info
->stage
== MESA_SHADER_FRAGMENT
&&
162 nir_intrinsic_io_semantics(intr
).fb_fetch_output
)
163 info
->uses_fbfetch
= true;
164 } else if (slot_mask
) {
166 if (info
->stage
== MESA_SHADER_GEOMETRY
) {
167 unsigned gs_streams
= (uint32_t)nir_intrinsic_io_semantics(intr
).gs_streams
<<
168 (nir_intrinsic_component(intr
) * 2);
169 unsigned new_mask
= slot_mask
& ~info
->output_usagemask
[loc
];
171 for (unsigned i
= 0; i
< 4; i
++) {
172 unsigned stream
= (gs_streams
>> (i
* 2)) & 0x3;
174 if (new_mask
& (1 << i
)) {
175 info
->output_streams
[loc
] |= stream
<< (i
* 2);
176 info
->num_stream_output_components
[stream
]++;
181 info
->output_usagemask
[loc
] |= slot_mask
;
182 info
->num_outputs
= MAX2(info
->num_outputs
, loc
+ 1);
185 case TGSI_SEMANTIC_PRIMID
:
186 info
->writes_primid
= true;
188 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
189 info
->writes_viewport_index
= true;
191 case TGSI_SEMANTIC_LAYER
:
192 info
->writes_layer
= true;
194 case TGSI_SEMANTIC_PSIZE
:
195 info
->writes_psize
= true;
197 case TGSI_SEMANTIC_CLIPVERTEX
:
198 info
->writes_clipvertex
= true;
200 case TGSI_SEMANTIC_COLOR
:
201 info
->colors_written
|= 1 << (index
+ i
);
203 if (info
->stage
== MESA_SHADER_FRAGMENT
&&
204 nir_intrinsic_io_semantics(intr
).location
== FRAG_RESULT_COLOR
)
205 info
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] = true;
207 case TGSI_SEMANTIC_STENCIL
:
208 info
->writes_stencil
= true;
210 case TGSI_SEMANTIC_SAMPLEMASK
:
211 info
->writes_samplemask
= true;
213 case TGSI_SEMANTIC_EDGEFLAG
:
214 info
->writes_edgeflag
= true;
216 case TGSI_SEMANTIC_POSITION
:
217 if (info
->stage
== MESA_SHADER_FRAGMENT
)
218 info
->writes_z
= true;
220 info
->writes_position
= true;
228 static void scan_instruction(const struct nir_shader
*nir
, struct si_shader_info
*info
,
231 if (instr
->type
== nir_instr_type_alu
) {
232 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
237 case nir_op_fddx_fine
:
238 case nir_op_fddy_fine
:
239 case nir_op_fddx_coarse
:
240 case nir_op_fddy_coarse
:
241 info
->uses_derivatives
= true;
246 } else if (instr
->type
== nir_instr_type_tex
) {
247 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
248 const nir_deref_instr
*deref
= tex_get_texture_deref(tex
);
249 nir_variable
*var
= deref
? nir_deref_instr_get_variable(deref
) : NULL
;
252 info
->samplers_declared
|= u_bit_consecutive(tex
->sampler_index
, 1);
254 if (deref
->mode
!= nir_var_uniform
|| var
->data
.bindless
)
255 info
->uses_bindless_samplers
= true;
262 info
->uses_derivatives
= true;
267 } else if (instr
->type
== nir_instr_type_intrinsic
) {
268 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
270 switch (intr
->intrinsic
) {
271 case nir_intrinsic_load_front_face
:
272 info
->uses_frontface
= 1;
274 case nir_intrinsic_load_instance_id
:
275 info
->uses_instanceid
= 1;
277 case nir_intrinsic_load_invocation_id
:
278 info
->uses_invocationid
= true;
280 case nir_intrinsic_load_num_work_groups
:
281 info
->uses_grid_size
= true;
283 case nir_intrinsic_load_local_invocation_index
:
284 case nir_intrinsic_load_subgroup_id
:
285 case nir_intrinsic_load_num_subgroups
:
286 info
->uses_subgroup_info
= true;
288 case nir_intrinsic_load_local_group_size
:
289 /* The block size is translated to IMM with a fixed block size. */
290 if (info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
291 info
->uses_block_size
= true;
293 case nir_intrinsic_load_local_invocation_id
:
294 case nir_intrinsic_load_work_group_id
: {
295 unsigned mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
297 unsigned i
= u_bit_scan(&mask
);
299 if (intr
->intrinsic
== nir_intrinsic_load_work_group_id
)
300 info
->uses_block_id
[i
] = true;
302 info
->uses_thread_id
[i
] = true;
306 case nir_intrinsic_load_vertex_id
:
307 info
->uses_vertexid
= 1;
309 case nir_intrinsic_load_vertex_id_zero_base
:
310 info
->uses_vertexid_nobase
= 1;
312 case nir_intrinsic_load_base_vertex
:
313 info
->uses_basevertex
= 1;
315 case nir_intrinsic_load_draw_id
:
316 info
->uses_drawid
= 1;
318 case nir_intrinsic_load_primitive_id
:
319 info
->uses_primid
= 1;
321 case nir_intrinsic_load_sample_mask_in
:
322 info
->reads_samplemask
= true;
324 case nir_intrinsic_load_tess_level_inner
:
325 case nir_intrinsic_load_tess_level_outer
:
326 info
->reads_tess_factors
= true;
328 case nir_intrinsic_bindless_image_load
:
329 case nir_intrinsic_bindless_image_size
:
330 case nir_intrinsic_bindless_image_samples
:
331 info
->uses_bindless_images
= true;
333 case nir_intrinsic_bindless_image_store
:
334 info
->uses_bindless_images
= true;
335 info
->writes_memory
= true;
336 info
->num_memory_instructions
++; /* we only care about stores */
338 case nir_intrinsic_image_deref_store
:
339 info
->writes_memory
= true;
340 info
->num_memory_instructions
++; /* we only care about stores */
342 case nir_intrinsic_bindless_image_atomic_add
:
343 case nir_intrinsic_bindless_image_atomic_imin
:
344 case nir_intrinsic_bindless_image_atomic_umin
:
345 case nir_intrinsic_bindless_image_atomic_imax
:
346 case nir_intrinsic_bindless_image_atomic_umax
:
347 case nir_intrinsic_bindless_image_atomic_and
:
348 case nir_intrinsic_bindless_image_atomic_or
:
349 case nir_intrinsic_bindless_image_atomic_xor
:
350 case nir_intrinsic_bindless_image_atomic_exchange
:
351 case nir_intrinsic_bindless_image_atomic_comp_swap
:
352 info
->uses_bindless_images
= true;
353 info
->writes_memory
= true;
354 info
->num_memory_instructions
++; /* we only care about stores */
356 case nir_intrinsic_image_deref_atomic_add
:
357 case nir_intrinsic_image_deref_atomic_imin
:
358 case nir_intrinsic_image_deref_atomic_umin
:
359 case nir_intrinsic_image_deref_atomic_imax
:
360 case nir_intrinsic_image_deref_atomic_umax
:
361 case nir_intrinsic_image_deref_atomic_and
:
362 case nir_intrinsic_image_deref_atomic_or
:
363 case nir_intrinsic_image_deref_atomic_xor
:
364 case nir_intrinsic_image_deref_atomic_exchange
:
365 case nir_intrinsic_image_deref_atomic_comp_swap
:
366 case nir_intrinsic_image_deref_atomic_inc_wrap
:
367 case nir_intrinsic_image_deref_atomic_dec_wrap
:
368 info
->writes_memory
= true;
369 info
->num_memory_instructions
++; /* we only care about stores */
371 case nir_intrinsic_store_ssbo
:
372 case nir_intrinsic_ssbo_atomic_add
:
373 case nir_intrinsic_ssbo_atomic_imin
:
374 case nir_intrinsic_ssbo_atomic_umin
:
375 case nir_intrinsic_ssbo_atomic_imax
:
376 case nir_intrinsic_ssbo_atomic_umax
:
377 case nir_intrinsic_ssbo_atomic_and
:
378 case nir_intrinsic_ssbo_atomic_or
:
379 case nir_intrinsic_ssbo_atomic_xor
:
380 case nir_intrinsic_ssbo_atomic_exchange
:
381 case nir_intrinsic_ssbo_atomic_comp_swap
:
382 info
->writes_memory
= true;
383 info
->num_memory_instructions
++; /* we only care about stores */
385 case nir_intrinsic_load_color0
:
386 case nir_intrinsic_load_color1
: {
387 unsigned index
= intr
->intrinsic
== nir_intrinsic_load_color1
;
388 uint8_t mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
389 info
->colors_read
|= mask
<< (index
* 4);
392 case nir_intrinsic_load_barycentric_pixel
:
393 case nir_intrinsic_load_barycentric_centroid
:
394 case nir_intrinsic_load_barycentric_sample
:
395 case nir_intrinsic_load_barycentric_at_offset
: /* uses center */
396 case nir_intrinsic_load_barycentric_at_sample
: { /* uses center */
397 unsigned mode
= nir_intrinsic_interp_mode(intr
);
399 if (mode
== INTERP_MODE_FLAT
)
402 if (mode
== INTERP_MODE_NOPERSPECTIVE
) {
403 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
404 info
->uses_linear_sample
= true;
405 else if (intr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
406 info
->uses_linear_centroid
= true;
408 info
->uses_linear_center
= true;
410 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_at_sample
)
411 info
->uses_linear_opcode_interp_sample
= true;
413 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
414 info
->uses_persp_sample
= true;
415 else if (intr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
416 info
->uses_persp_centroid
= true;
418 info
->uses_persp_center
= true;
420 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_at_sample
)
421 info
->uses_persp_opcode_interp_sample
= true;
425 case nir_intrinsic_load_input
:
426 case nir_intrinsic_load_per_vertex_input
:
427 case nir_intrinsic_load_input_vertex
:
428 case nir_intrinsic_load_interpolated_input
:
429 scan_io_usage(info
, intr
, true);
431 case nir_intrinsic_load_output
:
432 case nir_intrinsic_load_per_vertex_output
:
433 case nir_intrinsic_store_output
:
434 case nir_intrinsic_store_per_vertex_output
:
435 scan_io_usage(info
, intr
, false);
437 case nir_intrinsic_load_deref
:
438 case nir_intrinsic_store_deref
:
439 case nir_intrinsic_interp_deref_at_centroid
:
440 case nir_intrinsic_interp_deref_at_sample
:
441 case nir_intrinsic_interp_deref_at_offset
:
442 unreachable("these opcodes should have been lowered");
450 void si_nir_scan_shader(const struct nir_shader
*nir
, struct si_shader_info
*info
)
454 info
->stage
= nir
->info
.stage
;
455 info
->properties
[TGSI_PROPERTY_NEXT_SHADER
] = pipe_shader_type_from_mesa(nir
->info
.next_stage
);
457 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
458 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] = nir
->info
.vs
.window_space_position
;
459 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] = nir
->info
.vs
.blit_sgprs_amd
;
462 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
463 info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] = nir
->info
.tess
.tcs_vertices_out
;
466 if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
467 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
468 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = PIPE_PRIM_LINES
;
470 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = nir
->info
.tess
.primitive_mode
;
472 STATIC_ASSERT((TESS_SPACING_EQUAL
+ 1) % 3 == PIPE_TESS_SPACING_EQUAL
);
473 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD
+ 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_ODD
);
474 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN
+ 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_EVEN
);
476 info
->properties
[TGSI_PROPERTY_TES_SPACING
] = (nir
->info
.tess
.spacing
+ 1) % 3;
477 info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
] = !nir
->info
.tess
.ccw
;
478 info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
] = nir
->info
.tess
.point_mode
;
481 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
482 info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] = nir
->info
.gs
.input_primitive
;
483 info
->properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
] = nir
->info
.gs
.output_primitive
;
484 info
->properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
] = nir
->info
.gs
.vertices_out
;
485 info
->properties
[TGSI_PROPERTY_GS_INVOCATIONS
] = nir
->info
.gs
.invocations
;
488 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
489 info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] =
490 nir
->info
.fs
.early_fragment_tests
| nir
->info
.fs
.post_depth_coverage
;
491 info
->properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
] = nir
->info
.fs
.post_depth_coverage
;
493 if (nir
->info
.fs
.pixel_center_integer
) {
494 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] = TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
497 if (nir
->info
.fs
.depth_layout
!= FRAG_DEPTH_LAYOUT_NONE
) {
498 switch (nir
->info
.fs
.depth_layout
) {
499 case FRAG_DEPTH_LAYOUT_ANY
:
500 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_ANY
;
502 case FRAG_DEPTH_LAYOUT_GREATER
:
503 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_GREATER
;
505 case FRAG_DEPTH_LAYOUT_LESS
:
506 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_LESS
;
508 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
509 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED
;
512 unreachable("Unknow depth layout");
516 info
->color_interpolate
[0] = tgsi_get_interp_mode(nir
->info
.fs
.color0_interp
, true);
517 info
->color_interpolate
[1] = tgsi_get_interp_mode(nir
->info
.fs
.color1_interp
, true);
518 info
->color_interpolate_loc
[0] = nir
->info
.fs
.color0_sample
? TGSI_INTERPOLATE_LOC_SAMPLE
:
519 nir
->info
.fs
.color0_centroid
? TGSI_INTERPOLATE_LOC_CENTROID
:
520 TGSI_INTERPOLATE_LOC_CENTER
;
521 info
->color_interpolate_loc
[1] = nir
->info
.fs
.color1_sample
? TGSI_INTERPOLATE_LOC_SAMPLE
:
522 nir
->info
.fs
.color1_centroid
? TGSI_INTERPOLATE_LOC_CENTROID
:
523 TGSI_INTERPOLATE_LOC_CENTER
;
526 if (gl_shader_stage_is_compute(nir
->info
.stage
)) {
527 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] = nir
->info
.cs
.local_size
[0];
528 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] = nir
->info
.cs
.local_size
[1];
529 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
] = nir
->info
.cs
.local_size
[2];
530 info
->properties
[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD
] =
531 nir
->info
.cs
.user_data_components_amd
;
534 info
->constbuf0_num_slots
= nir
->num_uniforms
;
535 info
->shader_buffers_declared
= u_bit_consecutive(0, nir
->info
.num_ssbos
);
536 info
->const_buffers_declared
= u_bit_consecutive(0, nir
->info
.num_ubos
);
537 info
->images_declared
= u_bit_consecutive(0, nir
->info
.num_images
);
538 info
->msaa_images_declared
= nir
->info
.msaa_images
;
539 info
->image_buffers
= nir
->info
.image_buffers
;
540 info
->samplers_declared
= nir
->info
.textures_used
;
542 info
->num_written_clipdistance
= nir
->info
.clip_distance_array_size
;
543 info
->num_written_culldistance
= nir
->info
.cull_distance_array_size
;
544 info
->clipdist_writemask
= u_bit_consecutive(0, info
->num_written_clipdistance
);
545 info
->culldist_writemask
= u_bit_consecutive(0, info
->num_written_culldistance
);
547 if (info
->stage
== MESA_SHADER_FRAGMENT
)
548 info
->uses_kill
= nir
->info
.fs
.uses_discard
;
550 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
551 info
->tessfactors_are_def_in_all_invocs
= ac_are_tessfactors_def_in_all_invocs(nir
);
554 func
= (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
555 nir_foreach_block (block
, func
->impl
) {
556 nir_foreach_instr (instr
, block
)
557 scan_instruction(nir
, info
, instr
);
560 /* Add color inputs to the list of inputs. */
561 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
562 for (unsigned i
= 0; i
< 2; i
++) {
563 if ((info
->colors_read
>> (i
* 4)) & 0xf) {
564 info
->input_semantic_name
[info
->num_inputs
] = TGSI_SEMANTIC_COLOR
;
565 info
->input_semantic_index
[info
->num_inputs
] = i
;
566 info
->input_interpolate
[info
->num_inputs
] = info
->color_interpolate
[i
];
567 info
->input_usage_mask
[info
->num_inputs
] = info
->colors_read
>> (i
* 4);
573 /* Trim output read masks based on write masks. */
574 for (unsigned i
= 0; i
< info
->num_outputs
; i
++)
575 info
->output_readmask
[i
] &= info
->output_usagemask
[i
];
578 static void si_nir_opts(struct nir_shader
*nir
, bool first
)
582 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
583 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
584 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
588 bool lower_alu_to_scalar
= false;
589 bool lower_phis_to_scalar
= false;
592 bool opt_find_array_copies
= false;
594 NIR_PASS(progress
, nir
, nir_split_array_vars
, nir_var_function_temp
);
595 NIR_PASS(lower_alu_to_scalar
, nir
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
596 NIR_PASS(opt_find_array_copies
, nir
, nir_opt_find_array_copies
);
597 NIR_PASS(progress
, nir
, nir_opt_copy_prop_vars
);
599 /* Call nir_lower_var_copies() to remove any copies introduced
600 * by nir_opt_find_array_copies().
602 if (opt_find_array_copies
)
603 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
604 progress
|= opt_find_array_copies
;
606 NIR_PASS(progress
, nir
, nir_opt_copy_prop_vars
);
609 NIR_PASS(progress
, nir
, nir_opt_dead_write_vars
);
611 NIR_PASS(lower_alu_to_scalar
, nir
, nir_opt_trivial_continues
);
612 /* (Constant) copy propagation is needed for txf with offsets. */
613 NIR_PASS(progress
, nir
, nir_copy_prop
);
614 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
615 NIR_PASS(progress
, nir
, nir_opt_dce
);
616 NIR_PASS(lower_phis_to_scalar
, nir
, nir_opt_if
, true);
617 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
619 if (lower_alu_to_scalar
)
620 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
621 if (lower_phis_to_scalar
)
622 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
623 progress
|= lower_alu_to_scalar
| lower_phis_to_scalar
;
625 NIR_PASS(progress
, nir
, nir_opt_cse
);
626 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 8, true, true);
628 /* Needed for algebraic lowering */
629 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
630 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
632 if (!nir
->info
.flrp_lowered
) {
633 unsigned lower_flrp
= (nir
->options
->lower_flrp16
? 16 : 0) |
634 (nir
->options
->lower_flrp32
? 32 : 0) |
635 (nir
->options
->lower_flrp64
? 64 : 0);
637 bool lower_flrp_progress
= false;
639 NIR_PASS(lower_flrp_progress
, nir
, nir_lower_flrp
, lower_flrp
, false /* always_precise */,
640 nir
->options
->lower_ffma
);
641 if (lower_flrp_progress
) {
642 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
646 /* Nothing should rematerialize any flrps, so we only
647 * need to do this lowering once.
649 nir
->info
.flrp_lowered
= true;
652 NIR_PASS(progress
, nir
, nir_opt_undef
);
653 NIR_PASS(progress
, nir
, nir_opt_conditional_discard
);
654 if (nir
->options
->max_unroll_iterations
) {
655 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
, 0);
660 static int type_size_vec4(const struct glsl_type
*type
, bool bindless
)
662 return glsl_count_attribute_slots(type
, false);
665 static void si_nir_lower_color(nir_shader
*nir
)
667 nir_function_impl
*entrypoint
= nir_shader_get_entrypoint(nir
);
670 nir_builder_init(&b
, entrypoint
);
672 nir_foreach_block (block
, entrypoint
) {
673 nir_foreach_instr_safe (instr
, block
) {
674 if (instr
->type
!= nir_instr_type_intrinsic
)
677 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
679 if (intrin
->intrinsic
!= nir_intrinsic_load_deref
)
682 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
683 if (deref
->mode
!= nir_var_shader_in
)
686 b
.cursor
= nir_before_instr(instr
);
687 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
690 if (var
->data
.location
== VARYING_SLOT_COL0
) {
691 def
= nir_load_color0(&b
);
692 nir
->info
.fs
.color0_interp
= var
->data
.interpolation
;
693 nir
->info
.fs
.color0_sample
= var
->data
.sample
;
694 nir
->info
.fs
.color0_centroid
= var
->data
.centroid
;
695 } else if (var
->data
.location
== VARYING_SLOT_COL1
) {
696 def
= nir_load_color1(&b
);
697 nir
->info
.fs
.color1_interp
= var
->data
.interpolation
;
698 nir
->info
.fs
.color1_sample
= var
->data
.sample
;
699 nir
->info
.fs
.color1_centroid
= var
->data
.centroid
;
704 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(def
));
705 nir_instr_remove(instr
);
710 static void si_lower_io(struct nir_shader
*nir
)
712 /* HW supports indirect indexing for: | Enabled in driver
713 * -------------------------------------------------------
718 * -------------------------------------------------------
719 * VS outputs before TCS | No
720 * VS outputs before GS | No
722 * TES outputs before GS | No
724 bool has_indirect_inputs
= nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
725 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
;
726 bool has_indirect_outputs
= nir
->info
.stage
== MESA_SHADER_TESS_CTRL
;
728 if (!has_indirect_inputs
|| !has_indirect_outputs
) {
729 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
, nir_shader_get_entrypoint(nir
),
730 !has_indirect_outputs
, !has_indirect_inputs
);
732 /* Since we're doing nir_lower_io_to_temporaries late, we need
733 * to lower all the copy_deref's introduced by
734 * lower_io_to_temporaries before calling nir_lower_io.
736 NIR_PASS_V(nir
, nir_split_var_copies
);
737 NIR_PASS_V(nir
, nir_lower_var_copies
);
738 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
741 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
742 si_nir_lower_color(nir
);
744 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_out
| nir_var_shader_in
,
746 nir
->info
.io_lowered
= true;
748 /* This pass needs actual constants */
749 NIR_PASS_V(nir
, nir_opt_constant_folding
);
750 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
, nir_var_shader_in
);
751 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
, nir_var_shader_out
);
753 /* Remove dead derefs, so that nir_validate doesn't fail. */
754 NIR_PASS_V(nir
, nir_opt_dce
);
756 /* Remove input and output nir_variables, because we don't need them
757 * anymore. Also remove uniforms, because those should have been lowered
760 unsigned modes
= nir_var_shader_in
| nir_var_shader_out
| nir_var_uniform
;
761 nir_foreach_variable_with_modes_safe(var
, nir
, modes
) {
762 if (var
->data
.mode
== nir_var_uniform
&&
763 (glsl_type_get_image_count(var
->type
) ||
764 glsl_type_get_sampler_count(var
->type
)))
767 exec_node_remove(&var
->node
);
772 * Perform "lowering" operations on the NIR that are run once when the shader
773 * selector is created.
775 static void si_lower_nir(struct si_screen
*sscreen
, struct nir_shader
*nir
)
777 /* Perform lowerings (and optimizations) of code.
779 * Performance considerations aside, we must:
780 * - lower certain ALU operations
781 * - ensure constant offsets for texture instructions are folded
782 * and copy-propagated
785 static const struct nir_lower_tex_options lower_tex_options
= {
788 NIR_PASS_V(nir
, nir_lower_tex
, &lower_tex_options
);
790 const nir_lower_subgroups_options subgroups_options
= {
792 .ballot_bit_size
= 64,
793 .lower_to_scalar
= true,
794 .lower_subgroup_masks
= true,
795 .lower_vote_trivial
= false,
796 .lower_vote_eq_to_ballot
= true,
798 NIR_PASS_V(nir
, nir_lower_subgroups
, &subgroups_options
);
800 /* Lower load constants to scalar and then clean up the mess */
801 NIR_PASS_V(nir
, nir_lower_load_const_to_scalar
);
802 NIR_PASS_V(nir
, nir_lower_var_copies
);
803 NIR_PASS_V(nir
, nir_lower_pack
);
804 NIR_PASS_V(nir
, nir_opt_access
);
805 si_nir_opts(nir
, true);
807 /* Lower large variables that are always constant with load_constant
808 * intrinsics, which get turned into PC-relative loads from a data
809 * section next to the shader.
811 * st/mesa calls finalize_nir twice, but we can't call this pass twice.
813 bool changed
= false;
814 if (!nir
->constant_data
) {
815 /* The pass crashes if there are dead temps of lowered IO interface types. */
816 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
, NULL
);
817 NIR_PASS(changed
, nir
, nir_opt_large_constants
, glsl_get_natural_size_align_bytes
, 16);
820 changed
|= ac_lower_indirect_derefs(nir
, sscreen
->info
.chip_class
);
822 si_nir_opts(nir
, false);
824 NIR_PASS_V(nir
, nir_lower_bool_to_int32
);
825 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
, NULL
);
827 if (sscreen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
))
828 NIR_PASS_V(nir
, nir_lower_discard_to_demote
);
831 void si_finalize_nir(struct pipe_screen
*screen
, void *nirptr
, bool optimize
)
833 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
834 struct nir_shader
*nir
= (struct nir_shader
*)nirptr
;
836 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
838 si_lower_nir(sscreen
, nir
);