src/gallium/drivers/radeonsi/si_shader_nir.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "ac_nir_to_llvm.h"
  26 #include "compiler/nir/nir.h"
  27 #include "compiler/nir/nir_builder.h"
  28 #include "compiler/nir/nir_deref.h"
  29 #include "compiler/nir_types.h"
  30 #include "si_pipe.h"
  31 #include "si_shader_internal.h"
  32 #include "tgsi/tgsi_from_mesa.h"
  33
  34 static const nir_deref_instr *tex_get_texture_deref(nir_tex_instr *instr)
  35 {
  36    for (unsigned i = 0; i < instr->num_srcs; i++) {
  37       switch (instr->src[i].src_type) {
  38       case nir_tex_src_texture_deref:
  39          return nir_src_as_deref(instr->src[i].src);
  40       default:
  41          break;
  42       }
  43    }
  44
  45    return NULL;
  46 }
  47
  48 static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr,
  49                           bool is_input)
  50 {
  51    unsigned interp = INTERP_MODE_FLAT; /* load_input uses flat shading */
  52
  53    if (intr->intrinsic == nir_intrinsic_load_interpolated_input) {
  54       nir_intrinsic_instr *baryc = nir_instr_as_intrinsic(intr->src[0].ssa->parent_instr);
  55
  56       if (baryc) {
  57          if (nir_intrinsic_infos[baryc->intrinsic].index_map[NIR_INTRINSIC_INTERP_MODE] > 0)
  58             interp = nir_intrinsic_interp_mode(baryc);
  59          else
  60             unreachable("unknown barycentric intrinsic");
  61       } else {
  62          unreachable("unknown barycentric expression");
  63       }
  64    }
  65
  66    unsigned mask, bit_size;
  67    bool dual_slot, is_output_load;
  68
  69    if (nir_intrinsic_infos[intr->intrinsic].index_map[NIR_INTRINSIC_WRMASK] > 0) {
  70       mask = nir_intrinsic_write_mask(intr); /* store */
  71       bit_size = nir_src_bit_size(intr->src[0]);
  72       dual_slot = bit_size == 64 && nir_src_num_components(intr->src[0]) >= 3;
  73       is_output_load = false;
  74    } else {
  75       mask = nir_ssa_def_components_read(&intr->dest.ssa); /* load */
  76       bit_size = intr->dest.ssa.bit_size;
  77       dual_slot = bit_size == 64 && intr->dest.ssa.num_components >= 3;
  78       is_output_load = !is_input;
  79    }
  80
  81    /* Convert the 64-bit component mask to a 32-bit component mask. */
  82    if (bit_size == 64) {
  83       unsigned new_mask = 0;
  84       for (unsigned i = 0; i < 4; i++) {
  85          if (mask & (1 << i))
  86             new_mask |= 0x3 << (2 * i);
  87       }
  88       mask = new_mask;
  89    }
  90
  91    /* Convert the 16-bit component mask to a 32-bit component mask. */
  92    if (bit_size == 16) {
  93       unsigned new_mask = 0;
  94       for (unsigned i = 0; i < 4; i++) {
  95          if (mask & (1 << i))
  96             new_mask |= 0x1 << (i / 2);
  97       }
  98       mask = new_mask;
  99    }
 100
 101    mask <<= nir_intrinsic_component(intr);
 102
 103    nir_src offset = *nir_get_io_offset_src(intr);
 104    bool indirect = !nir_src_is_const(offset);
 105    if (!indirect)
 106       assert(nir_src_as_uint(offset) == 0);
 107
 108    unsigned semantic = 0;
 109    /* VS doesn't have semantics. */
 110    if (info->stage != MESA_SHADER_VERTEX || !is_input)
 111       semantic = nir_intrinsic_io_semantics(intr).location;
 112
 113    if (info->stage == MESA_SHADER_FRAGMENT && !is_input) {
 114       /* Never use FRAG_RESULT_COLOR directly. */
 115       if (semantic == FRAG_RESULT_COLOR) {
 116          semantic = FRAG_RESULT_DATA0;
 117          info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
 118       }
 119       semantic += nir_intrinsic_io_semantics(intr).dual_source_blend_index;
 120    }
 121
 122    unsigned driver_location = nir_intrinsic_base(intr);
 123    unsigned num_slots = indirect ? nir_intrinsic_io_semantics(intr).num_slots : (1 + dual_slot);
 124
 125    if (is_input) {
 126       assert(driver_location + num_slots <= ARRAY_SIZE(info->input_usage_mask));
 127
 128       for (unsigned i = 0; i < num_slots; i++) {
 129          unsigned loc = driver_location + i;
 130          unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
 131
 132          info->input_semantic[loc] = semantic + i;
 133          info->input_interpolate[loc] = interp;
 134
 135          if (slot_mask) {
 136             info->input_usage_mask[loc] |= slot_mask;
 137             info->num_inputs = MAX2(info->num_inputs, loc + 1);
 138
 139             if (semantic == VARYING_SLOT_PRIMITIVE_ID)
 140                info->uses_primid = true;
 141          }
 142       }
 143    } else {
 144       /* Outputs. */
 145       assert(driver_location + num_slots <= ARRAY_SIZE(info->output_usagemask));
 146       assert(semantic + num_slots < ARRAY_SIZE(info->output_semantic_to_slot));
 147
 148       for (unsigned i = 0; i < num_slots; i++) {
 149          unsigned loc = driver_location + i;
 150          unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
 151
 152          info->output_semantic[loc] = semantic + i;
 153          info->output_semantic_to_slot[semantic + i] = loc;
 154
 155          if (is_output_load) {
 156             /* Output loads have only a few things that we need to track. */
 157             info->output_readmask[loc] |= slot_mask;
 158
 159             if (info->stage == MESA_SHADER_FRAGMENT &&
 160                 nir_intrinsic_io_semantics(intr).fb_fetch_output)
 161                info->uses_fbfetch = true;
 162          } else if (slot_mask) {
 163             /* Output stores. */
 164             if (info->stage == MESA_SHADER_GEOMETRY) {
 165                unsigned gs_streams = (uint32_t)nir_intrinsic_io_semantics(intr).gs_streams <<
 166                                      (nir_intrinsic_component(intr) * 2);
 167                unsigned new_mask = slot_mask & ~info->output_usagemask[loc];
 168
 169                for (unsigned i = 0; i < 4; i++) {
 170                   unsigned stream = (gs_streams >> (i * 2)) & 0x3;
 171
 172                   if (new_mask & (1 << i)) {
 173                      info->output_streams[loc] |= stream << (i * 2);
 174                      info->num_stream_output_components[stream]++;
 175                   }
 176                }
 177             }
 178
 179             info->output_usagemask[loc] |= slot_mask;
 180             info->num_outputs = MAX2(info->num_outputs, loc + 1);
 181
 182             if (info->stage == MESA_SHADER_FRAGMENT) {
 183                switch (semantic) {
 184                case FRAG_RESULT_DEPTH:
 185                   info->writes_z = true;
 186                   break;
 187                case FRAG_RESULT_STENCIL:
 188                   info->writes_stencil = true;
 189                   break;
 190                case FRAG_RESULT_SAMPLE_MASK:
 191                   info->writes_samplemask = true;
 192                   break;
 193                default:
 194                   if (semantic >= FRAG_RESULT_DATA0 && semantic <= FRAG_RESULT_DATA7) {
 195                      unsigned index = semantic - FRAG_RESULT_DATA0;
 196                      info->colors_written |= 1 << (index + i);
 197                   }
 198                   break;
 199                }
 200             } else {
 201                switch (semantic) {
 202                case VARYING_SLOT_PRIMITIVE_ID:
 203                   info->writes_primid = true;
 204                   break;
 205                case VARYING_SLOT_VIEWPORT:
 206                   info->writes_viewport_index = true;
 207                   break;
 208                case VARYING_SLOT_LAYER:
 209                   info->writes_layer = true;
 210                   break;
 211                case VARYING_SLOT_PSIZ:
 212                   info->writes_psize = true;
 213                   break;
 214                case VARYING_SLOT_CLIP_VERTEX:
 215                   info->writes_clipvertex = true;
 216                   break;
 217                case VARYING_SLOT_EDGE:
 218                   info->writes_edgeflag = true;
 219                   break;
 220                case VARYING_SLOT_POS:
 221                   info->writes_position = true;
 222                   break;
 223                }
 224             }
 225          }
 226       }
 227    }
 228 }
 229
 230 static void scan_instruction(const struct nir_shader *nir, struct si_shader_info *info,
 231                              nir_instr *instr)
 232 {
 233    if (instr->type == nir_instr_type_alu) {
 234       nir_alu_instr *alu = nir_instr_as_alu(instr);
 235
 236       switch (alu->op) {
 237       case nir_op_fddx:
 238       case nir_op_fddy:
 239       case nir_op_fddx_fine:
 240       case nir_op_fddy_fine:
 241       case nir_op_fddx_coarse:
 242       case nir_op_fddy_coarse:
 243          info->uses_derivatives = true;
 244          break;
 245       default:
 246          break;
 247       }
 248    } else if (instr->type == nir_instr_type_tex) {
 249       nir_tex_instr *tex = nir_instr_as_tex(instr);
 250       const nir_deref_instr *deref = tex_get_texture_deref(tex);
 251       nir_variable *var = deref ? nir_deref_instr_get_variable(deref) : NULL;
 252
 253       if (!var) {
 254          info->samplers_declared |= u_bit_consecutive(tex->sampler_index, 1);
 255       } else {
 256          if (deref->mode != nir_var_uniform || var->data.bindless)
 257             info->uses_bindless_samplers = true;
 258       }
 259
 260       switch (tex->op) {
 261       case nir_texop_tex:
 262       case nir_texop_txb:
 263       case nir_texop_lod:
 264          info->uses_derivatives = true;
 265          break;
 266       default:
 267          break;
 268       }
 269    } else if (instr->type == nir_instr_type_intrinsic) {
 270       nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 271
 272       switch (intr->intrinsic) {
 273       case nir_intrinsic_load_front_face:
 274          info->uses_frontface = 1;
 275          break;
 276       case nir_intrinsic_load_instance_id:
 277          info->uses_instanceid = 1;
 278          break;
 279       case nir_intrinsic_load_invocation_id:
 280          info->uses_invocationid = true;
 281          break;
 282       case nir_intrinsic_load_num_work_groups:
 283          info->uses_grid_size = true;
 284          break;
 285       case nir_intrinsic_load_local_invocation_index:
 286       case nir_intrinsic_load_subgroup_id:
 287       case nir_intrinsic_load_num_subgroups:
 288          info->uses_subgroup_info = true;
 289          break;
 290       case nir_intrinsic_load_local_group_size:
 291          /* The block size is translated to IMM with a fixed block size. */
 292          if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
 293             info->uses_block_size = true;
 294          break;
 295       case nir_intrinsic_load_local_invocation_id:
 296       case nir_intrinsic_load_work_group_id: {
 297          unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
 298          while (mask) {
 299             unsigned i = u_bit_scan(&mask);
 300
 301             if (intr->intrinsic == nir_intrinsic_load_work_group_id)
 302                info->uses_block_id[i] = true;
 303             else
 304                info->uses_thread_id[i] = true;
 305          }
 306          break;
 307       }
 308       case nir_intrinsic_load_vertex_id:
 309          info->uses_vertexid = 1;
 310          break;
 311       case nir_intrinsic_load_vertex_id_zero_base:
 312          info->uses_vertexid_nobase = 1;
 313          break;
 314       case nir_intrinsic_load_base_vertex:
 315          info->uses_basevertex = 1;
 316          break;
 317       case nir_intrinsic_load_draw_id:
 318          info->uses_drawid = 1;
 319          break;
 320       case nir_intrinsic_load_primitive_id:
 321          info->uses_primid = 1;
 322          break;
 323       case nir_intrinsic_load_sample_mask_in:
 324          info->reads_samplemask = true;
 325          break;
 326       case nir_intrinsic_load_tess_level_inner:
 327       case nir_intrinsic_load_tess_level_outer:
 328          info->reads_tess_factors = true;
 329          break;
 330       case nir_intrinsic_bindless_image_load:
 331       case nir_intrinsic_bindless_image_size:
 332       case nir_intrinsic_bindless_image_samples:
 333          info->uses_bindless_images = true;
 334          break;
 335       case nir_intrinsic_bindless_image_store:
 336          info->uses_bindless_images = true;
 337          info->writes_memory = true;
 338          info->num_memory_instructions++; /* we only care about stores */
 339          break;
 340       case nir_intrinsic_image_deref_store:
 341          info->writes_memory = true;
 342          info->num_memory_instructions++; /* we only care about stores */
 343          break;
 344       case nir_intrinsic_bindless_image_atomic_add:
 345       case nir_intrinsic_bindless_image_atomic_imin:
 346       case nir_intrinsic_bindless_image_atomic_umin:
 347       case nir_intrinsic_bindless_image_atomic_imax:
 348       case nir_intrinsic_bindless_image_atomic_umax:
 349       case nir_intrinsic_bindless_image_atomic_and:
 350       case nir_intrinsic_bindless_image_atomic_or:
 351       case nir_intrinsic_bindless_image_atomic_xor:
 352       case nir_intrinsic_bindless_image_atomic_exchange:
 353       case nir_intrinsic_bindless_image_atomic_comp_swap:
 354          info->uses_bindless_images = true;
 355          info->writes_memory = true;
 356          info->num_memory_instructions++; /* we only care about stores */
 357          break;
 358       case nir_intrinsic_image_deref_atomic_add:
 359       case nir_intrinsic_image_deref_atomic_imin:
 360       case nir_intrinsic_image_deref_atomic_umin:
 361       case nir_intrinsic_image_deref_atomic_imax:
 362       case nir_intrinsic_image_deref_atomic_umax:
 363       case nir_intrinsic_image_deref_atomic_and:
 364       case nir_intrinsic_image_deref_atomic_or:
 365       case nir_intrinsic_image_deref_atomic_xor:
 366       case nir_intrinsic_image_deref_atomic_exchange:
 367       case nir_intrinsic_image_deref_atomic_comp_swap:
 368       case nir_intrinsic_image_deref_atomic_inc_wrap:
 369       case nir_intrinsic_image_deref_atomic_dec_wrap:
 370          info->writes_memory = true;
 371          info->num_memory_instructions++; /* we only care about stores */
 372          break;
 373       case nir_intrinsic_store_ssbo:
 374       case nir_intrinsic_ssbo_atomic_add:
 375       case nir_intrinsic_ssbo_atomic_imin:
 376       case nir_intrinsic_ssbo_atomic_umin:
 377       case nir_intrinsic_ssbo_atomic_imax:
 378       case nir_intrinsic_ssbo_atomic_umax:
 379       case nir_intrinsic_ssbo_atomic_and:
 380       case nir_intrinsic_ssbo_atomic_or:
 381       case nir_intrinsic_ssbo_atomic_xor:
 382       case nir_intrinsic_ssbo_atomic_exchange:
 383       case nir_intrinsic_ssbo_atomic_comp_swap:
 384          info->writes_memory = true;
 385          info->num_memory_instructions++; /* we only care about stores */
 386          break;
 387       case nir_intrinsic_load_color0:
 388       case nir_intrinsic_load_color1: {
 389          unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
 390          uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
 391          info->colors_read |= mask << (index * 4);
 392          break;
 393       }
 394       case nir_intrinsic_load_barycentric_pixel:
 395       case nir_intrinsic_load_barycentric_centroid:
 396       case nir_intrinsic_load_barycentric_sample:
 397       case nir_intrinsic_load_barycentric_at_offset:   /* uses center */
 398       case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
 399          unsigned mode = nir_intrinsic_interp_mode(intr);
 400
 401          if (mode == INTERP_MODE_FLAT)
 402             break;
 403
 404          if (mode == INTERP_MODE_NOPERSPECTIVE) {
 405             if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
 406                info->uses_linear_sample = true;
 407             else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
 408                info->uses_linear_centroid = true;
 409             else
 410                info->uses_linear_center = true;
 411
 412             if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
 413                info->uses_linear_opcode_interp_sample = true;
 414          } else {
 415             if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
 416                info->uses_persp_sample = true;
 417             else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
 418                info->uses_persp_centroid = true;
 419             else
 420                info->uses_persp_center = true;
 421
 422             if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
 423                info->uses_persp_opcode_interp_sample = true;
 424          }
 425          break;
 426       }
 427       case nir_intrinsic_load_input:
 428       case nir_intrinsic_load_per_vertex_input:
 429       case nir_intrinsic_load_input_vertex:
 430       case nir_intrinsic_load_interpolated_input:
 431          scan_io_usage(info, intr, true);
 432          break;
 433       case nir_intrinsic_load_output:
 434       case nir_intrinsic_load_per_vertex_output:
 435       case nir_intrinsic_store_output:
 436       case nir_intrinsic_store_per_vertex_output:
 437          scan_io_usage(info, intr, false);
 438          break;
 439       case nir_intrinsic_load_deref:
 440       case nir_intrinsic_store_deref:
 441       case nir_intrinsic_interp_deref_at_centroid:
 442       case nir_intrinsic_interp_deref_at_sample:
 443       case nir_intrinsic_interp_deref_at_offset:
 444          unreachable("these opcodes should have been lowered");
 445          break;
 446       default:
 447          break;
 448       }
 449    }
 450 }
 451
 452 void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *info)
 453 {
 454    nir_function *func;
 455
 456    info->base = nir->info;
 457    info->stage = nir->info.stage;
 458
 459    if (nir->info.stage == MESA_SHADER_VERTEX) {
 460       info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] = nir->info.vs.window_space_position;
 461       info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] = nir->info.vs.blit_sgprs_amd;
 462    }
 463
 464    if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 465       info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] = nir->info.tess.tcs_vertices_out;
 466    }
 467
 468    if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 469       if (nir->info.tess.primitive_mode == GL_ISOLINES)
 470          info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
 471       else
 472          info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
 473
 474       STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
 475       STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_ODD);
 476       STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_EVEN);
 477
 478       info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
 479       info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
 480       info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
 481    }
 482
 483    if (nir->info.stage == MESA_SHADER_GEOMETRY) {
 484       info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
 485       info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
 486       info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
 487       info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
 488    }
 489
 490    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 491       info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
 492          nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
 493       info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
 494
 495       if (nir->info.fs.pixel_center_integer) {
 496          info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] = TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
 497       }
 498
 499       if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
 500          switch (nir->info.fs.depth_layout) {
 501          case FRAG_DEPTH_LAYOUT_ANY:
 502             info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
 503             break;
 504          case FRAG_DEPTH_LAYOUT_GREATER:
 505             info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
 506             break;
 507          case FRAG_DEPTH_LAYOUT_LESS:
 508             info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
 509             break;
 510          case FRAG_DEPTH_LAYOUT_UNCHANGED:
 511             info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
 512             break;
 513          default:
 514             unreachable("Unknow depth layout");
 515          }
 516       }
 517
 518       info->color_interpolate[0] = nir->info.fs.color0_interp;
 519       info->color_interpolate[1] = nir->info.fs.color1_interp;
 520       for (unsigned i = 0; i < 2; i++) {
 521          if (info->color_interpolate[i] == INTERP_MODE_NONE)
 522             info->color_interpolate[i] = INTERP_MODE_COLOR;
 523       }
 524
 525       info->color_interpolate_loc[0] = nir->info.fs.color0_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
 526                                        nir->info.fs.color0_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
 527                                                                       TGSI_INTERPOLATE_LOC_CENTER;
 528       info->color_interpolate_loc[1] = nir->info.fs.color1_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
 529                                        nir->info.fs.color1_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
 530                                                                       TGSI_INTERPOLATE_LOC_CENTER;
 531    }
 532
 533    if (gl_shader_stage_is_compute(nir->info.stage)) {
 534       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
 535       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
 536       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
 537       info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] =
 538          nir->info.cs.user_data_components_amd;
 539    }
 540
 541    info->constbuf0_num_slots = nir->num_uniforms;
 542    info->shader_buffers_declared = u_bit_consecutive(0, nir->info.num_ssbos);
 543    info->const_buffers_declared = u_bit_consecutive(0, nir->info.num_ubos);
 544    info->images_declared = u_bit_consecutive(0, nir->info.num_images);
 545    info->msaa_images_declared = nir->info.msaa_images;
 546    info->image_buffers = nir->info.image_buffers;
 547    info->samplers_declared = nir->info.textures_used;
 548
 549    info->num_written_clipdistance = nir->info.clip_distance_array_size;
 550    info->num_written_culldistance = nir->info.cull_distance_array_size;
 551    info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
 552    info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
 553
 554    if (info->stage == MESA_SHADER_FRAGMENT)
 555       info->uses_kill = nir->info.fs.uses_discard;
 556
 557    if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 558       info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir);
 559    }
 560
 561    memset(info->output_semantic_to_slot, -1, sizeof(info->output_semantic_to_slot));
 562
 563    func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
 564    nir_foreach_block (block, func->impl) {
 565       nir_foreach_instr (instr, block)
 566          scan_instruction(nir, info, instr);
 567    }
 568
 569    /* Add color inputs to the list of inputs. */
 570    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 571       for (unsigned i = 0; i < 2; i++) {
 572          if ((info->colors_read >> (i * 4)) & 0xf) {
 573             info->input_semantic[info->num_inputs] = VARYING_SLOT_COL0 + i;
 574             info->input_interpolate[info->num_inputs] = info->color_interpolate[i];
 575             info->input_usage_mask[info->num_inputs] = info->colors_read >> (i * 4);
 576             info->num_inputs++;
 577          }
 578       }
 579    }
 580
 581    /* Trim output read masks based on write masks. */
 582    for (unsigned i = 0; i < info->num_outputs; i++)
 583       info->output_readmask[i] &= info->output_usagemask[i];
 584 }
 585
 586 static void si_nir_opts(struct nir_shader *nir, bool first)
 587 {
 588    bool progress;
 589
 590    NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 591    NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
 592    NIR_PASS_V(nir, nir_lower_phis_to_scalar);
 593
 594    do {
 595       progress = false;
 596       bool lower_alu_to_scalar = false;
 597       bool lower_phis_to_scalar = false;
 598
 599       if (first) {
 600          bool opt_find_array_copies = false;
 601
 602          NIR_PASS(progress, nir, nir_split_array_vars, nir_var_function_temp);
 603          NIR_PASS(lower_alu_to_scalar, nir, nir_shrink_vec_array_vars, nir_var_function_temp);
 604          NIR_PASS(opt_find_array_copies, nir, nir_opt_find_array_copies);
 605          NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
 606
 607          /* Call nir_lower_var_copies() to remove any copies introduced
 608           * by nir_opt_find_array_copies().
 609           */
 610          if (opt_find_array_copies)
 611             NIR_PASS(progress, nir, nir_lower_var_copies);
 612          progress |= opt_find_array_copies;
 613       } else {
 614          NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
 615       }
 616
 617       NIR_PASS(progress, nir, nir_opt_dead_write_vars);
 618
 619       NIR_PASS(lower_alu_to_scalar, nir, nir_opt_trivial_continues);
 620       /* (Constant) copy propagation is needed for txf with offsets. */
 621       NIR_PASS(progress, nir, nir_copy_prop);
 622       NIR_PASS(progress, nir, nir_opt_remove_phis);
 623       NIR_PASS(progress, nir, nir_opt_dce);
 624       NIR_PASS(lower_phis_to_scalar, nir, nir_opt_if, true);
 625       NIR_PASS(progress, nir, nir_opt_dead_cf);
 626
 627       if (lower_alu_to_scalar)
 628          NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
 629       if (lower_phis_to_scalar)
 630          NIR_PASS_V(nir, nir_lower_phis_to_scalar);
 631       progress |= lower_alu_to_scalar | lower_phis_to_scalar;
 632
 633       NIR_PASS(progress, nir, nir_opt_cse);
 634       NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
 635
 636       /* Needed for algebraic lowering */
 637       NIR_PASS(progress, nir, nir_opt_algebraic);
 638       NIR_PASS(progress, nir, nir_opt_constant_folding);
 639
 640       if (!nir->info.flrp_lowered) {
 641          unsigned lower_flrp = (nir->options->lower_flrp16 ? 16 : 0) |
 642                                (nir->options->lower_flrp32 ? 32 : 0) |
 643                                (nir->options->lower_flrp64 ? 64 : 0);
 644          assert(lower_flrp);
 645          bool lower_flrp_progress = false;
 646
 647          NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp, lower_flrp, false /* always_precise */);
 648          if (lower_flrp_progress) {
 649             NIR_PASS(progress, nir, nir_opt_constant_folding);
 650             progress = true;
 651          }
 652
 653          /* Nothing should rematerialize any flrps, so we only
 654           * need to do this lowering once.
 655           */
 656          nir->info.flrp_lowered = true;
 657       }
 658
 659       NIR_PASS(progress, nir, nir_opt_undef);
 660       NIR_PASS(progress, nir, nir_opt_conditional_discard);
 661       if (nir->options->max_unroll_iterations) {
 662          NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
 663       }
 664    } while (progress);
 665 }
 666
 667 static int type_size_vec4(const struct glsl_type *type, bool bindless)
 668 {
 669    return glsl_count_attribute_slots(type, false);
 670 }
 671
 672 static void si_nir_lower_color(nir_shader *nir)
 673 {
 674    nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
 675
 676    nir_builder b;
 677    nir_builder_init(&b, entrypoint);
 678
 679    nir_foreach_block (block, entrypoint) {
 680       nir_foreach_instr_safe (instr, block) {
 681          if (instr->type != nir_instr_type_intrinsic)
 682             continue;
 683
 684          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 685
 686          if (intrin->intrinsic != nir_intrinsic_load_deref)
 687             continue;
 688
 689          nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
 690          if (deref->mode != nir_var_shader_in)
 691             continue;
 692
 693          b.cursor = nir_before_instr(instr);
 694          nir_variable *var = nir_deref_instr_get_variable(deref);
 695          nir_ssa_def *def;
 696
 697          if (var->data.location == VARYING_SLOT_COL0) {
 698             def = nir_load_color0(&b);
 699             nir->info.fs.color0_interp = var->data.interpolation;
 700             nir->info.fs.color0_sample = var->data.sample;
 701             nir->info.fs.color0_centroid = var->data.centroid;
 702          } else if (var->data.location == VARYING_SLOT_COL1) {
 703             def = nir_load_color1(&b);
 704             nir->info.fs.color1_interp = var->data.interpolation;
 705             nir->info.fs.color1_sample = var->data.sample;
 706             nir->info.fs.color1_centroid = var->data.centroid;
 707          } else {
 708             continue;
 709          }
 710
 711          nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
 712          nir_instr_remove(instr);
 713       }
 714    }
 715 }
 716
 717 static void si_lower_io(struct nir_shader *nir)
 718 {
 719    /* HW supports indirect indexing for: | Enabled in driver
 720     * -------------------------------------------------------
 721     * VS inputs                          | No
 722     * TCS inputs                         | Yes
 723     * TES inputs                         | Yes
 724     * GS inputs                          | No
 725     * -------------------------------------------------------
 726     * VS outputs before TCS              | No
 727     * VS outputs before GS               | No
 728     * TCS outputs                        | Yes
 729     * TES outputs before GS              | No
 730     */
 731    bool has_indirect_inputs = nir->info.stage == MESA_SHADER_TESS_CTRL ||
 732                               nir->info.stage == MESA_SHADER_TESS_EVAL;
 733    bool has_indirect_outputs = nir->info.stage == MESA_SHADER_TESS_CTRL;
 734
 735    if (!has_indirect_inputs || !has_indirect_outputs) {
 736       NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir),
 737                  !has_indirect_outputs, !has_indirect_inputs);
 738
 739       /* Since we're doing nir_lower_io_to_temporaries late, we need
 740        * to lower all the copy_deref's introduced by
 741        * lower_io_to_temporaries before calling nir_lower_io.
 742        */
 743       NIR_PASS_V(nir, nir_split_var_copies);
 744       NIR_PASS_V(nir, nir_lower_var_copies);
 745       NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 746    }
 747
 748    if (nir->info.stage == MESA_SHADER_FRAGMENT)
 749       si_nir_lower_color(nir);
 750
 751    NIR_PASS_V(nir, nir_lower_io, nir_var_shader_out | nir_var_shader_in,
 752               type_size_vec4, 0);
 753    nir->info.io_lowered = true;
 754
 755    /* This pass needs actual constants */
 756    NIR_PASS_V(nir, nir_opt_constant_folding);
 757    NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
 758    NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_out);
 759
 760    /* Remove dead derefs, so that nir_validate doesn't fail. */
 761    NIR_PASS_V(nir, nir_opt_dce);
 762
 763    /* Remove input and output nir_variables, because we don't need them
 764     * anymore. Also remove uniforms, because those should have been lowered
 765     * to UBOs already.
 766     */
 767    unsigned modes = nir_var_shader_in | nir_var_shader_out | nir_var_uniform;
 768    nir_foreach_variable_with_modes_safe(var, nir, modes) {
 769       if (var->data.mode == nir_var_uniform &&
 770           (glsl_type_get_image_count(var->type) ||
 771            glsl_type_get_sampler_count(var->type)))
 772          continue;
 773
 774       exec_node_remove(&var->node);
 775    }
 776 }
 777
 778 /**
 779  * Perform "lowering" operations on the NIR that are run once when the shader
 780  * selector is created.
 781  */
 782 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
 783 {
 784    /* Perform lowerings (and optimizations) of code.
 785     *
 786     * Performance considerations aside, we must:
 787     * - lower certain ALU operations
 788     * - ensure constant offsets for texture instructions are folded
 789     *   and copy-propagated
 790     */
 791
 792    static const struct nir_lower_tex_options lower_tex_options = {
 793       .lower_txp = ~0u,
 794    };
 795    NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
 796
 797    const nir_lower_subgroups_options subgroups_options = {
 798       .subgroup_size = 64,
 799       .ballot_bit_size = 64,
 800       .lower_to_scalar = true,
 801       .lower_subgroup_masks = true,
 802       .lower_vote_trivial = false,
 803       .lower_vote_eq_to_ballot = true,
 804    };
 805    NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
 806
 807    /* Lower load constants to scalar and then clean up the mess */
 808    NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
 809    NIR_PASS_V(nir, nir_lower_var_copies);
 810    NIR_PASS_V(nir, nir_lower_pack);
 811    NIR_PASS_V(nir, nir_opt_access);
 812    si_nir_opts(nir, true);
 813
 814    /* Lower large variables that are always constant with load_constant
 815     * intrinsics, which get turned into PC-relative loads from a data
 816     * section next to the shader.
 817     *
 818     * st/mesa calls finalize_nir twice, but we can't call this pass twice.
 819     */
 820    bool changed = false;
 821    if (!nir->constant_data) {
 822       /* The pass crashes if there are dead temps of lowered IO interface types. */
 823       NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
 824       NIR_PASS(changed, nir, nir_opt_large_constants, glsl_get_natural_size_align_bytes, 16);
 825    }
 826
 827    changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
 828    if (changed)
 829       si_nir_opts(nir, false);
 830
 831    NIR_PASS_V(nir, nir_lower_bool_to_int32);
 832    NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
 833
 834    if (sscreen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
 835       NIR_PASS_V(nir, nir_lower_discard_to_demote);
 836 }
 837
 838 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
 839 {
 840    struct si_screen *sscreen = (struct si_screen *)screen;
 841    struct nir_shader *nir = (struct nir_shader *)nirptr;
 842
 843    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 844    si_lower_io(nir);
 845    si_lower_nir(sscreen, nir);
 846 }