2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "ac_nir_to_llvm.h"
30 #include "tgsi/tgsi_from_mesa.h"
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35 #include "compiler/nir/nir_deref.h"
37 static nir_variable
* tex_get_texture_var(nir_tex_instr
*instr
)
39 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
40 switch (instr
->src
[i
].src_type
) {
41 case nir_tex_src_texture_deref
:
42 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
));
51 static nir_variable
* intrinsic_get_var(nir_intrinsic_instr
*instr
)
53 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[0]));
56 static void gather_usage_helper(const nir_deref_instr
**deref_ptr
,
61 for (; *deref_ptr
; deref_ptr
++) {
62 const nir_deref_instr
*deref
= *deref_ptr
;
63 switch (deref
->deref_type
) {
64 case nir_deref_type_array
: {
66 glsl_count_attribute_slots(deref
->type
, false);
67 if (nir_src_is_const(deref
->arr
.index
)) {
68 location
+= elem_size
* nir_src_as_uint(deref
->arr
.index
);
70 unsigned array_elems
=
71 glsl_get_length(deref_ptr
[-1]->type
);
72 for (unsigned i
= 0; i
< array_elems
; i
++) {
73 gather_usage_helper(deref_ptr
+ 1,
74 location
+ elem_size
* i
,
81 case nir_deref_type_struct
: {
82 const struct glsl_type
*parent_type
=
84 unsigned index
= deref
->strct
.index
;
85 for (unsigned i
= 0; i
< index
; i
++) {
86 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
87 location
+= glsl_count_attribute_slots(ft
, false);
92 unreachable("Unhandled deref type in gather_components_used_helper");
96 usage_mask
[location
] |= mask
& 0xf;
98 usage_mask
[location
+ 1] |= (mask
>> 4) & 0xf;
101 static void gather_usage(const nir_deref_instr
*deref
,
106 nir_deref_path_init(&path
, (nir_deref_instr
*)deref
, NULL
);
108 unsigned location_frac
= path
.path
[0]->var
->data
.location_frac
;
109 if (glsl_type_is_64bit(deref
->type
)) {
110 uint8_t new_mask
= 0;
111 for (unsigned i
= 0; i
< 4; i
++) {
113 new_mask
|= 0x3 << (2 * i
);
115 mask
= new_mask
<< location_frac
;
117 mask
<<= location_frac
;
121 gather_usage_helper((const nir_deref_instr
**)&path
.path
[1],
122 path
.path
[0]->var
->data
.driver_location
,
125 nir_deref_path_finish(&path
);
128 static void gather_intrinsic_load_deref_input_info(const nir_shader
*nir
,
129 const nir_intrinsic_instr
*instr
,
130 const nir_deref_instr
*deref
,
131 struct tgsi_shader_info
*info
)
133 switch (nir
->info
.stage
) {
134 case MESA_SHADER_VERTEX
:
135 gather_usage(deref
, nir_ssa_def_components_read(&instr
->dest
.ssa
),
136 info
->input_usage_mask
);
141 static void gather_intrinsic_load_deref_output_info(const nir_shader
*nir
,
142 const nir_intrinsic_instr
*instr
,
144 struct tgsi_shader_info
*info
)
146 assert(var
&& var
->data
.mode
== nir_var_shader_out
);
148 switch (nir
->info
.stage
) {
149 case MESA_SHADER_TESS_CTRL
:
150 if (var
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
||
151 var
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
152 info
->reads_tessfactor_outputs
= true;
153 else if (var
->data
.patch
)
154 info
->reads_perpatch_outputs
= true;
156 info
->reads_pervertex_outputs
= true;
159 case MESA_SHADER_FRAGMENT
:
160 if (var
->data
.fb_fetch_output
)
161 info
->uses_fbfetch
= true;
167 static void gather_intrinsic_store_deref_output_info(const nir_shader
*nir
,
168 const nir_intrinsic_instr
*instr
,
169 const nir_deref_instr
*deref
,
170 struct tgsi_shader_info
*info
)
172 switch (nir
->info
.stage
) {
173 case MESA_SHADER_VERTEX
: /* needed by LS, ES */
174 case MESA_SHADER_TESS_EVAL
: /* needed by ES */
175 case MESA_SHADER_GEOMETRY
:
176 gather_usage(deref
, nir_intrinsic_write_mask(instr
),
177 info
->output_usagemask
);
183 static void scan_instruction(const struct nir_shader
*nir
,
184 struct tgsi_shader_info
*info
,
187 if (instr
->type
== nir_instr_type_alu
) {
188 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
193 case nir_op_fddx_fine
:
194 case nir_op_fddy_fine
:
195 case nir_op_fddx_coarse
:
196 case nir_op_fddy_coarse
:
197 info
->uses_derivatives
= true;
202 } else if (instr
->type
== nir_instr_type_tex
) {
203 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
204 nir_variable
*texture
= tex_get_texture_var(tex
);
207 info
->samplers_declared
|=
208 u_bit_consecutive(tex
->sampler_index
, 1);
210 if (texture
->data
.bindless
)
211 info
->uses_bindless_samplers
= true;
218 info
->uses_derivatives
= true;
223 } else if (instr
->type
== nir_instr_type_intrinsic
) {
224 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
226 switch (intr
->intrinsic
) {
227 case nir_intrinsic_load_front_face
:
228 info
->uses_frontface
= 1;
230 case nir_intrinsic_load_instance_id
:
231 info
->uses_instanceid
= 1;
233 case nir_intrinsic_load_invocation_id
:
234 info
->uses_invocationid
= true;
236 case nir_intrinsic_load_num_work_groups
:
237 info
->uses_grid_size
= true;
239 case nir_intrinsic_load_local_group_size
:
240 /* The block size is translated to IMM with a fixed block size. */
241 if (info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
242 info
->uses_block_size
= true;
244 case nir_intrinsic_load_local_invocation_id
:
245 case nir_intrinsic_load_work_group_id
: {
246 unsigned mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
248 unsigned i
= u_bit_scan(&mask
);
250 if (intr
->intrinsic
== nir_intrinsic_load_work_group_id
)
251 info
->uses_block_id
[i
] = true;
253 info
->uses_thread_id
[i
] = true;
257 case nir_intrinsic_load_vertex_id
:
258 info
->uses_vertexid
= 1;
260 case nir_intrinsic_load_vertex_id_zero_base
:
261 info
->uses_vertexid_nobase
= 1;
263 case nir_intrinsic_load_base_vertex
:
264 info
->uses_basevertex
= 1;
266 case nir_intrinsic_load_draw_id
:
267 info
->uses_drawid
= 1;
269 case nir_intrinsic_load_primitive_id
:
270 info
->uses_primid
= 1;
272 case nir_intrinsic_load_sample_mask_in
:
273 info
->reads_samplemask
= true;
275 case nir_intrinsic_load_tess_level_inner
:
276 case nir_intrinsic_load_tess_level_outer
:
277 info
->reads_tess_factors
= true;
279 case nir_intrinsic_bindless_image_load
:
280 info
->uses_bindless_images
= true;
282 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
283 info
->uses_bindless_buffer_load
= true;
285 info
->uses_bindless_image_load
= true;
287 case nir_intrinsic_bindless_image_size
:
288 case nir_intrinsic_bindless_image_samples
:
289 info
->uses_bindless_images
= true;
291 case nir_intrinsic_bindless_image_store
:
292 info
->uses_bindless_images
= true;
294 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
295 info
->uses_bindless_buffer_store
= true;
297 info
->uses_bindless_image_store
= true;
299 info
->writes_memory
= true;
300 info
->num_memory_instructions
++; /* we only care about stores */
302 case nir_intrinsic_image_deref_store
:
303 info
->writes_memory
= true;
304 info
->num_memory_instructions
++; /* we only care about stores */
306 case nir_intrinsic_bindless_image_atomic_add
:
307 case nir_intrinsic_bindless_image_atomic_imin
:
308 case nir_intrinsic_bindless_image_atomic_umin
:
309 case nir_intrinsic_bindless_image_atomic_imax
:
310 case nir_intrinsic_bindless_image_atomic_umax
:
311 case nir_intrinsic_bindless_image_atomic_and
:
312 case nir_intrinsic_bindless_image_atomic_or
:
313 case nir_intrinsic_bindless_image_atomic_xor
:
314 case nir_intrinsic_bindless_image_atomic_exchange
:
315 case nir_intrinsic_bindless_image_atomic_comp_swap
:
316 info
->uses_bindless_images
= true;
318 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
319 info
->uses_bindless_buffer_atomic
= true;
321 info
->uses_bindless_image_atomic
= true;
323 info
->writes_memory
= true;
324 info
->num_memory_instructions
++; /* we only care about stores */
326 case nir_intrinsic_image_deref_atomic_add
:
327 case nir_intrinsic_image_deref_atomic_imin
:
328 case nir_intrinsic_image_deref_atomic_umin
:
329 case nir_intrinsic_image_deref_atomic_imax
:
330 case nir_intrinsic_image_deref_atomic_umax
:
331 case nir_intrinsic_image_deref_atomic_and
:
332 case nir_intrinsic_image_deref_atomic_or
:
333 case nir_intrinsic_image_deref_atomic_xor
:
334 case nir_intrinsic_image_deref_atomic_exchange
:
335 case nir_intrinsic_image_deref_atomic_comp_swap
:
336 case nir_intrinsic_image_deref_atomic_inc_wrap
:
337 case nir_intrinsic_image_deref_atomic_dec_wrap
:
338 info
->writes_memory
= true;
339 info
->num_memory_instructions
++; /* we only care about stores */
341 case nir_intrinsic_store_ssbo
:
342 case nir_intrinsic_ssbo_atomic_add
:
343 case nir_intrinsic_ssbo_atomic_imin
:
344 case nir_intrinsic_ssbo_atomic_umin
:
345 case nir_intrinsic_ssbo_atomic_imax
:
346 case nir_intrinsic_ssbo_atomic_umax
:
347 case nir_intrinsic_ssbo_atomic_and
:
348 case nir_intrinsic_ssbo_atomic_or
:
349 case nir_intrinsic_ssbo_atomic_xor
:
350 case nir_intrinsic_ssbo_atomic_exchange
:
351 case nir_intrinsic_ssbo_atomic_comp_swap
:
352 info
->writes_memory
= true;
353 info
->num_memory_instructions
++; /* we only care about stores */
355 case nir_intrinsic_load_color0
:
356 case nir_intrinsic_load_color1
: {
357 unsigned index
= intr
->intrinsic
== nir_intrinsic_load_color1
;
358 uint8_t mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
359 info
->colors_read
|= mask
<< (index
* 4);
362 case nir_intrinsic_load_barycentric_pixel
:
363 case nir_intrinsic_load_barycentric_centroid
:
364 case nir_intrinsic_load_barycentric_sample
:
365 case nir_intrinsic_load_barycentric_at_offset
: /* uses center */
366 case nir_intrinsic_load_barycentric_at_sample
: { /* uses center */
367 unsigned mode
= nir_intrinsic_interp_mode(intr
);
369 if (mode
== INTERP_MODE_FLAT
)
372 if (mode
== INTERP_MODE_NOPERSPECTIVE
) {
373 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
374 info
->uses_linear_sample
= true;
375 else if (intr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
376 info
->uses_linear_centroid
= true;
378 info
->uses_linear_center
= true;
380 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_at_sample
)
381 info
->uses_linear_opcode_interp_sample
= true;
383 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
384 info
->uses_persp_sample
= true;
385 else if (intr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
386 info
->uses_persp_centroid
= true;
388 info
->uses_persp_center
= true;
390 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_at_sample
)
391 info
->uses_persp_opcode_interp_sample
= true;
395 case nir_intrinsic_load_deref
: {
396 nir_variable
*var
= intrinsic_get_var(intr
);
397 nir_variable_mode mode
= var
->data
.mode
;
399 if (mode
== nir_var_shader_in
) {
400 /* PS inputs use the interpolated load intrinsics. */
401 assert(nir
->info
.stage
!= MESA_SHADER_FRAGMENT
);
402 gather_intrinsic_load_deref_input_info(nir
, intr
,
403 nir_src_as_deref(intr
->src
[0]), info
);
404 } else if (mode
== nir_var_shader_out
) {
405 gather_intrinsic_load_deref_output_info(nir
, intr
, var
, info
);
409 case nir_intrinsic_store_deref
: {
410 nir_variable
*var
= intrinsic_get_var(intr
);
412 if (var
->data
.mode
== nir_var_shader_out
)
413 gather_intrinsic_store_deref_output_info(nir
, intr
,
414 nir_src_as_deref(intr
->src
[0]), info
);
417 case nir_intrinsic_interp_deref_at_centroid
:
418 case nir_intrinsic_interp_deref_at_sample
:
419 case nir_intrinsic_interp_deref_at_offset
:
420 unreachable("interp opcodes should have been lowered");
428 void si_nir_scan_tess_ctrl(const struct nir_shader
*nir
,
429 struct tgsi_tessctrl_info
*out
)
431 memset(out
, 0, sizeof(*out
));
433 if (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
436 out
->tessfactors_are_def_in_all_invocs
=
437 ac_are_tessfactors_def_in_all_invocs(nir
);
440 static void scan_output_slot(const nir_variable
*var
,
442 unsigned component
, unsigned num_components
,
443 struct tgsi_shader_info
*info
)
445 assert(component
+ num_components
<= 4);
446 assert(component
< 4);
448 unsigned semantic_name
, semantic_index
;
450 unsigned location
= var
->data
.location
+ var_idx
;
451 unsigned drv_location
= var
->data
.driver_location
+ var_idx
;
453 if (info
->processor
== PIPE_SHADER_FRAGMENT
) {
454 tgsi_get_gl_frag_result_semantic(location
,
455 &semantic_name
, &semantic_index
);
457 /* Adjust for dual source blending */
458 if (var
->data
.index
> 0) {
462 tgsi_get_gl_varying_semantic(location
, true,
463 &semantic_name
, &semantic_index
);
466 ubyte usagemask
= ((1 << num_components
) - 1) << component
;
468 unsigned gs_out_streams
;
469 if (var
->data
.stream
& (1u << 31)) {
470 gs_out_streams
= var
->data
.stream
& ~(1u << 31);
472 assert(var
->data
.stream
< 4);
474 for (unsigned j
= 0; j
< num_components
; ++j
)
475 gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ j
));
478 unsigned streamx
= gs_out_streams
& 3;
479 unsigned streamy
= (gs_out_streams
>> 2) & 3;
480 unsigned streamz
= (gs_out_streams
>> 4) & 3;
481 unsigned streamw
= (gs_out_streams
>> 6) & 3;
483 if (usagemask
& TGSI_WRITEMASK_X
) {
484 info
->output_streams
[drv_location
] |= streamx
;
485 info
->num_stream_output_components
[streamx
]++;
487 if (usagemask
& TGSI_WRITEMASK_Y
) {
488 info
->output_streams
[drv_location
] |= streamy
<< 2;
489 info
->num_stream_output_components
[streamy
]++;
491 if (usagemask
& TGSI_WRITEMASK_Z
) {
492 info
->output_streams
[drv_location
] |= streamz
<< 4;
493 info
->num_stream_output_components
[streamz
]++;
495 if (usagemask
& TGSI_WRITEMASK_W
) {
496 info
->output_streams
[drv_location
] |= streamw
<< 6;
497 info
->num_stream_output_components
[streamw
]++;
500 info
->output_semantic_name
[drv_location
] = semantic_name
;
501 info
->output_semantic_index
[drv_location
] = semantic_index
;
503 switch (semantic_name
) {
504 case TGSI_SEMANTIC_PRIMID
:
505 info
->writes_primid
= true;
507 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
508 info
->writes_viewport_index
= true;
510 case TGSI_SEMANTIC_LAYER
:
511 info
->writes_layer
= true;
513 case TGSI_SEMANTIC_PSIZE
:
514 info
->writes_psize
= true;
516 case TGSI_SEMANTIC_CLIPVERTEX
:
517 info
->writes_clipvertex
= true;
519 case TGSI_SEMANTIC_COLOR
:
520 info
->colors_written
|= 1 << semantic_index
;
522 case TGSI_SEMANTIC_STENCIL
:
523 info
->writes_stencil
= true;
525 case TGSI_SEMANTIC_SAMPLEMASK
:
526 info
->writes_samplemask
= true;
528 case TGSI_SEMANTIC_EDGEFLAG
:
529 info
->writes_edgeflag
= true;
531 case TGSI_SEMANTIC_POSITION
:
532 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
533 info
->writes_z
= true;
535 info
->writes_position
= true;
540 static void scan_output_helper(const nir_variable
*var
,
542 const struct glsl_type
*type
,
543 struct tgsi_shader_info
*info
)
545 if (glsl_type_is_struct(type
)) {
546 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
547 const struct glsl_type
*ft
= glsl_get_struct_field(type
, i
);
548 scan_output_helper(var
, location
, ft
, info
);
549 location
+= glsl_count_attribute_slots(ft
, false);
551 } else if (glsl_type_is_array_or_matrix(type
)) {
552 const struct glsl_type
*elem_type
=
553 glsl_get_array_element(type
);
554 unsigned num_elems
= glsl_get_length(type
);
555 if (var
->data
.compact
) {
556 assert(glsl_type_is_scalar(elem_type
));
557 assert(glsl_get_bit_size(elem_type
) == 32);
558 unsigned component
= var
->data
.location_frac
;
559 scan_output_slot(var
, location
, component
,
560 MIN2(num_elems
, 4 - component
), info
);
561 if (component
+ num_elems
> 4) {
562 scan_output_slot(var
, location
+ 1, 0,
563 component
+ num_elems
- 4, info
);
567 unsigned elem_count
= glsl_count_attribute_slots(elem_type
, false);
568 for (unsigned i
= 0; i
< num_elems
; i
++) {
569 scan_output_helper(var
, location
, elem_type
, info
);
570 location
+= elem_count
;
573 } else if (glsl_type_is_dual_slot(type
)) {
574 unsigned component
= var
->data
.location_frac
;
575 scan_output_slot(var
, location
, component
, 4 - component
, info
);
576 scan_output_slot(var
, location
+ 1, 0, component
+ 2 * glsl_get_components(type
) - 4,
579 unsigned component
= var
->data
.location_frac
;
580 assert(glsl_type_is_vector_or_scalar(type
));
581 unsigned num_components
= glsl_get_components(type
);
582 if (glsl_type_is_64bit(type
))
584 scan_output_slot(var
, location
, component
, num_components
, info
);
588 void si_nir_scan_shader(const struct nir_shader
*nir
,
589 struct tgsi_shader_info
*info
)
594 info
->processor
= pipe_shader_type_from_mesa(nir
->info
.stage
);
595 info
->num_tokens
= 2; /* indicate that the shader is non-empty */
596 info
->num_instructions
= 2;
598 info
->properties
[TGSI_PROPERTY_NEXT_SHADER
] =
599 pipe_shader_type_from_mesa(nir
->info
.next_stage
);
601 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
602 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] =
603 nir
->info
.vs
.window_space_position
;
604 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] =
605 nir
->info
.vs
.blit_sgprs_amd
;
608 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
609 info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] =
610 nir
->info
.tess
.tcs_vertices_out
;
613 if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
614 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
615 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = PIPE_PRIM_LINES
;
617 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = nir
->info
.tess
.primitive_mode
;
619 STATIC_ASSERT((TESS_SPACING_EQUAL
+ 1) % 3 == PIPE_TESS_SPACING_EQUAL
);
620 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD
+ 1) % 3 ==
621 PIPE_TESS_SPACING_FRACTIONAL_ODD
);
622 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN
+ 1) % 3 ==
623 PIPE_TESS_SPACING_FRACTIONAL_EVEN
);
625 info
->properties
[TGSI_PROPERTY_TES_SPACING
] = (nir
->info
.tess
.spacing
+ 1) % 3;
626 info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
] = !nir
->info
.tess
.ccw
;
627 info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
] = nir
->info
.tess
.point_mode
;
630 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
631 info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] = nir
->info
.gs
.input_primitive
;
632 info
->properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
] = nir
->info
.gs
.output_primitive
;
633 info
->properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
] = nir
->info
.gs
.vertices_out
;
634 info
->properties
[TGSI_PROPERTY_GS_INVOCATIONS
] = nir
->info
.gs
.invocations
;
637 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
638 info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] =
639 nir
->info
.fs
.early_fragment_tests
| nir
->info
.fs
.post_depth_coverage
;
640 info
->properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
] = nir
->info
.fs
.post_depth_coverage
;
642 if (nir
->info
.fs
.pixel_center_integer
) {
643 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] =
644 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
647 if (nir
->info
.fs
.depth_layout
!= FRAG_DEPTH_LAYOUT_NONE
) {
648 switch (nir
->info
.fs
.depth_layout
) {
649 case FRAG_DEPTH_LAYOUT_ANY
:
650 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_ANY
;
652 case FRAG_DEPTH_LAYOUT_GREATER
:
653 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_GREATER
;
655 case FRAG_DEPTH_LAYOUT_LESS
:
656 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_LESS
;
658 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
659 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED
;
662 unreachable("Unknow depth layout");
667 if (gl_shader_stage_is_compute(nir
->info
.stage
)) {
668 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] = nir
->info
.cs
.local_size
[0];
669 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] = nir
->info
.cs
.local_size
[1];
670 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
] = nir
->info
.cs
.local_size
[2];
671 info
->properties
[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD
] = nir
->info
.cs
.user_data_components_amd
;
675 uint64_t processed_inputs
= 0;
676 nir_foreach_variable(variable
, &nir
->inputs
) {
677 unsigned semantic_name
, semantic_index
;
679 const struct glsl_type
*type
= variable
->type
;
680 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
681 assert(glsl_type_is_array(type
));
682 type
= glsl_get_array_element(type
);
685 unsigned attrib_count
= glsl_count_attribute_slots(type
,
686 nir
->info
.stage
== MESA_SHADER_VERTEX
);
688 i
= variable
->data
.driver_location
;
690 /* Vertex shader inputs don't have semantics. The state
691 * tracker has already mapped them to attributes via
692 * variable->data.driver_location.
694 if (nir
->info
.stage
== MESA_SHADER_VERTEX
)
697 for (unsigned j
= 0; j
< attrib_count
; j
++, i
++) {
699 if (processed_inputs
& ((uint64_t)1 << i
))
702 processed_inputs
|= ((uint64_t)1 << i
);
704 tgsi_get_gl_varying_semantic(variable
->data
.location
+ j
, true,
705 &semantic_name
, &semantic_index
);
707 info
->input_semantic_name
[i
] = semantic_name
;
708 info
->input_semantic_index
[i
] = semantic_index
;
710 if (semantic_name
== TGSI_SEMANTIC_PRIMID
)
711 info
->uses_primid
= true;
713 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
714 /* We only need this for color inputs. */
715 if (variable
->data
.sample
)
716 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_SAMPLE
;
717 else if (variable
->data
.centroid
)
718 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTROID
;
720 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTER
;
723 enum glsl_base_type base_type
=
724 glsl_get_base_type(glsl_without_array(variable
->type
));
726 switch (variable
->data
.interpolation
) {
727 case INTERP_MODE_NONE
:
728 if (glsl_base_type_is_integer(base_type
)) {
729 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
733 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
734 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_COLOR
;
739 case INTERP_MODE_SMOOTH
:
740 assert(!glsl_base_type_is_integer(base_type
));
742 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_PERSPECTIVE
;
745 case INTERP_MODE_NOPERSPECTIVE
:
746 assert(!glsl_base_type_is_integer(base_type
));
748 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_LINEAR
;
751 case INTERP_MODE_FLAT
:
752 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
758 nir_foreach_variable(variable
, &nir
->outputs
) {
759 const struct glsl_type
*type
= variable
->type
;
760 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
761 assert(glsl_type_is_array(type
));
762 type
= glsl_get_array_element(type
);
765 ASSERTED
unsigned attrib_count
= glsl_count_attribute_slots(type
, false);
766 scan_output_helper(variable
, 0, type
, info
);
768 unsigned loc
= variable
->data
.location
;
769 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
770 loc
== FRAG_RESULT_COLOR
&&
771 nir
->info
.outputs_written
& (1ull << loc
)) {
772 assert(attrib_count
== 1);
773 info
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] = true;
777 info
->num_inputs
= nir
->num_inputs
;
778 info
->num_outputs
= nir
->num_outputs
;
780 info
->const_file_max
[0] = nir
->num_uniforms
- 1;
781 info
->shader_buffers_declared
= u_bit_consecutive(0, nir
->info
.num_ssbos
);
782 info
->const_buffers_declared
= u_bit_consecutive(1, nir
->info
.num_ubos
);
783 if (nir
->num_uniforms
> 0)
784 info
->const_buffers_declared
|= 1;
785 info
->images_declared
= u_bit_consecutive(0, nir
->info
.num_images
);
786 info
->samplers_declared
= u_bit_consecutive(0, nir
->info
.num_textures
);
788 info
->num_written_clipdistance
= nir
->info
.clip_distance_array_size
;
789 info
->num_written_culldistance
= nir
->info
.cull_distance_array_size
;
790 info
->clipdist_writemask
= u_bit_consecutive(0, info
->num_written_clipdistance
);
791 info
->culldist_writemask
= u_bit_consecutive(0, info
->num_written_culldistance
);
793 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
794 info
->uses_kill
= nir
->info
.fs
.uses_discard
;
796 func
= (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
797 nir_foreach_block(block
, func
->impl
) {
798 nir_foreach_instr(instr
, block
)
799 scan_instruction(nir
, info
, instr
);
804 si_nir_opts(struct nir_shader
*nir
)
807 unsigned lower_flrp
=
808 (nir
->options
->lower_flrp16
? 16 : 0) |
809 (nir
->options
->lower_flrp32
? 32 : 0) |
810 (nir
->options
->lower_flrp64
? 64 : 0);
815 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
817 NIR_PASS(progress
, nir
, nir_opt_copy_prop_vars
);
818 NIR_PASS(progress
, nir
, nir_opt_dead_write_vars
);
820 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, NULL
);
821 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
823 /* (Constant) copy propagation is needed for txf with offsets. */
824 NIR_PASS(progress
, nir
, nir_copy_prop
);
825 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
826 NIR_PASS(progress
, nir
, nir_opt_dce
);
827 if (nir_opt_trivial_continues(nir
)) {
829 NIR_PASS(progress
, nir
, nir_copy_prop
);
830 NIR_PASS(progress
, nir
, nir_opt_dce
);
832 NIR_PASS(progress
, nir
, nir_opt_if
, true);
833 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
834 NIR_PASS(progress
, nir
, nir_opt_cse
);
835 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 8, true, true);
837 /* Needed for algebraic lowering */
838 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
839 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
841 if (lower_flrp
!= 0) {
842 bool lower_flrp_progress
= false;
844 NIR_PASS(lower_flrp_progress
, nir
, nir_lower_flrp
,
846 false /* always_precise */,
847 nir
->options
->lower_ffma
);
848 if (lower_flrp_progress
) {
849 NIR_PASS(progress
, nir
,
850 nir_opt_constant_folding
);
854 /* Nothing should rematerialize any flrps, so we only
855 * need to do this lowering once.
860 NIR_PASS(progress
, nir
, nir_opt_undef
);
861 NIR_PASS(progress
, nir
, nir_opt_conditional_discard
);
862 if (nir
->options
->max_unroll_iterations
) {
863 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
, 0);
869 type_size_vec4(const struct glsl_type
*type
, bool bindless
)
871 return glsl_count_attribute_slots(type
, false);
875 si_nir_lower_color(nir_shader
*nir
)
877 nir_function_impl
*entrypoint
= nir_shader_get_entrypoint(nir
);
880 nir_builder_init(&b
, entrypoint
);
882 nir_foreach_block(block
, entrypoint
) {
883 nir_foreach_instr_safe(instr
, block
) {
884 if (instr
->type
!= nir_instr_type_intrinsic
)
887 nir_intrinsic_instr
*intrin
=
888 nir_instr_as_intrinsic(instr
);
890 if (intrin
->intrinsic
!= nir_intrinsic_load_deref
)
893 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
894 if (deref
->mode
!= nir_var_shader_in
)
897 b
.cursor
= nir_before_instr(instr
);
898 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
901 if (var
->data
.location
== VARYING_SLOT_COL0
) {
902 def
= nir_load_color0(&b
);
903 } else if (var
->data
.location
== VARYING_SLOT_COL1
) {
904 def
= nir_load_color1(&b
);
909 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(def
));
910 nir_instr_remove(instr
);
915 void si_nir_lower_ps_inputs(struct nir_shader
*nir
)
917 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
920 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
921 nir_shader_get_entrypoint(nir
), false, true);
923 /* Since we're doing nir_lower_io_to_temporaries late, we need
924 * to lower all the copy_deref's introduced by
925 * lower_io_to_temporaries before calling nir_lower_io.
927 NIR_PASS_V(nir
, nir_split_var_copies
);
928 NIR_PASS_V(nir
, nir_lower_var_copies
);
929 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
931 si_nir_lower_color(nir
);
932 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
, type_size_vec4
, 0);
934 /* This pass needs actual constants */
935 NIR_PASS_V(nir
, nir_opt_constant_folding
);
936 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
,
941 * Perform "lowering" operations on the NIR that are run once when the shader
942 * selector is created.
944 void si_lower_nir(struct si_shader_selector
*sel
)
946 /* Adjust the driver location of inputs and outputs. The state tracker
947 * interprets them as slots, while the ac/nir backend interprets them
948 * as individual components.
950 if (sel
->nir
->info
.stage
!= MESA_SHADER_FRAGMENT
) {
951 nir_foreach_variable(variable
, &sel
->nir
->inputs
)
952 variable
->data
.driver_location
*= 4;
955 nir_foreach_variable(variable
, &sel
->nir
->outputs
) {
956 variable
->data
.driver_location
*= 4;
958 if (sel
->nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
959 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
960 variable
->data
.driver_location
+= 2;
961 else if (variable
->data
.location
== FRAG_RESULT_STENCIL
)
962 variable
->data
.driver_location
+= 1;
966 /* Perform lowerings (and optimizations) of code.
968 * Performance considerations aside, we must:
969 * - lower certain ALU operations
970 * - ensure constant offsets for texture instructions are folded
971 * and copy-propagated
974 static const struct nir_lower_tex_options lower_tex_options
= {
977 NIR_PASS_V(sel
->nir
, nir_lower_tex
, &lower_tex_options
);
979 const nir_lower_subgroups_options subgroups_options
= {
981 .ballot_bit_size
= 64,
982 .lower_to_scalar
= true,
983 .lower_subgroup_masks
= true,
984 .lower_vote_trivial
= false,
985 .lower_vote_eq_to_ballot
= true,
987 NIR_PASS_V(sel
->nir
, nir_lower_subgroups
, &subgroups_options
);
989 /* Lower large variables that are always constant with load_constant
990 * intrinsics, which get turned into PC-relative loads from a data
991 * section next to the shader.
993 NIR_PASS_V(sel
->nir
, nir_opt_large_constants
,
994 glsl_get_natural_size_align_bytes
, 16);
996 ac_lower_indirect_derefs(sel
->nir
, sel
->screen
->info
.chip_class
);
998 si_nir_opts(sel
->nir
);
1000 NIR_PASS_V(sel
->nir
, nir_lower_bool_to_int32
);
1002 /* Strip the resulting shader so that the shader cache is more likely
1003 * to hit from other similar shaders.
1005 nir_strip(sel
->nir
);
1008 static void declare_nir_input_vs(struct si_shader_context
*ctx
,
1009 struct nir_variable
*variable
,
1010 unsigned input_index
,
1011 LLVMValueRef out
[4])
1013 si_llvm_load_input_vs(ctx
, input_index
, out
);
1017 si_nir_lookup_interp_param(struct ac_shader_abi
*abi
,
1018 enum glsl_interp_mode interp
, unsigned location
)
1020 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1023 case INTERP_MODE_FLAT
:
1025 case INTERP_MODE_SMOOTH
:
1026 case INTERP_MODE_NONE
:
1027 if (location
== INTERP_CENTER
)
1028 return ctx
->abi
.persp_center
;
1029 else if (location
== INTERP_CENTROID
)
1030 return ctx
->abi
.persp_centroid
;
1031 else if (location
== INTERP_SAMPLE
)
1032 return ctx
->abi
.persp_sample
;
1034 case INTERP_MODE_NOPERSPECTIVE
:
1035 if (location
== INTERP_CENTER
)
1036 return ctx
->abi
.linear_center
;
1037 else if (location
== INTERP_CENTROID
)
1038 return ctx
->abi
.linear_centroid
;
1039 else if (location
== INTERP_SAMPLE
)
1040 return ctx
->abi
.linear_sample
;
1043 assert(!"Unhandled interpolation mode.");
1049 si_nir_load_sampler_desc(struct ac_shader_abi
*abi
,
1050 unsigned descriptor_set
, unsigned base_index
,
1051 unsigned constant_index
, LLVMValueRef dynamic_index
,
1052 enum ac_descriptor_type desc_type
, bool image
,
1053 bool write
, bool bindless
)
1055 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1056 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1057 unsigned const_index
= base_index
+ constant_index
;
1059 assert(!descriptor_set
);
1060 assert(!image
|| desc_type
== AC_DESC_IMAGE
|| desc_type
== AC_DESC_BUFFER
);
1064 LLVMGetParam(ctx
->main_fn
, ctx
->param_bindless_samplers_and_images
);
1066 /* dynamic_index is the bindless handle */
1068 /* For simplicity, bindless image descriptors use fixed
1069 * 16-dword slots for now.
1071 dynamic_index
= LLVMBuildMul(ctx
->ac
.builder
, dynamic_index
,
1072 LLVMConstInt(ctx
->i64
, 2, 0), "");
1074 return si_load_image_desc(ctx
, list
, dynamic_index
, desc_type
,
1078 /* Since bindless handle arithmetic can contain an unsigned integer
1079 * wraparound and si_load_sampler_desc assumes there isn't any,
1080 * use GEP without "inbounds" (inside ac_build_pointer_add)
1081 * to prevent incorrect code generation and hangs.
1083 dynamic_index
= LLVMBuildMul(ctx
->ac
.builder
, dynamic_index
,
1084 LLVMConstInt(ctx
->i64
, 2, 0), "");
1085 list
= ac_build_pointer_add(&ctx
->ac
, list
, dynamic_index
);
1086 return si_load_sampler_desc(ctx
, list
, ctx
->i32_0
, desc_type
);
1089 unsigned num_slots
= image
? ctx
->num_images
: ctx
->num_samplers
;
1090 assert(const_index
< num_slots
|| dynamic_index
);
1092 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1093 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, const_index
, false);
1095 if (dynamic_index
) {
1096 index
= LLVMBuildAdd(builder
, index
, dynamic_index
, "");
1098 /* From the GL_ARB_shader_image_load_store extension spec:
1100 * If a shader performs an image load, store, or atomic
1101 * operation using an image variable declared as an array,
1102 * and if the index used to select an individual element is
1103 * negative or greater than or equal to the size of the
1104 * array, the results of the operation are undefined but may
1105 * not lead to termination.
1107 index
= si_llvm_bound_index(ctx
, index
, num_slots
);
1111 index
= LLVMBuildSub(ctx
->ac
.builder
,
1112 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
1114 return si_load_image_desc(ctx
, list
, index
, desc_type
, write
, false);
1117 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1118 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1119 return si_load_sampler_desc(ctx
, list
, index
, desc_type
);
1122 static void bitcast_inputs(struct si_shader_context
*ctx
,
1123 LLVMValueRef data
[4],
1126 for (unsigned chan
= 0; chan
< 4; chan
++) {
1127 ctx
->inputs
[input_idx
+ chan
] =
1128 LLVMBuildBitCast(ctx
->ac
.builder
, data
[chan
], ctx
->ac
.i32
, "");
1132 bool si_nir_build_llvm(struct si_shader_context
*ctx
, struct nir_shader
*nir
)
1134 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1136 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
1137 uint64_t processed_inputs
= 0;
1138 nir_foreach_variable(variable
, &nir
->inputs
) {
1139 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
,
1141 unsigned input_idx
= variable
->data
.driver_location
;
1143 LLVMValueRef data
[4];
1144 unsigned loc
= variable
->data
.location
;
1146 for (unsigned i
= 0; i
< attrib_count
; i
++) {
1147 /* Packed components share the same location so skip
1148 * them if we have already processed the location.
1150 if (processed_inputs
& ((uint64_t)1 << (loc
+ i
))) {
1155 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
1156 bitcast_inputs(ctx
, data
, input_idx
);
1157 if (glsl_type_is_dual_slot(variable
->type
)) {
1159 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
1160 bitcast_inputs(ctx
, data
, input_idx
);
1163 processed_inputs
|= ((uint64_t)1 << (loc
+ i
));
1167 } else if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1168 unsigned colors_read
=
1169 ctx
->shader
->selector
->info
.colors_read
;
1170 LLVMValueRef main_fn
= ctx
->main_fn
;
1172 LLVMValueRef undef
= LLVMGetUndef(ctx
->f32
);
1174 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1;
1176 if (colors_read
& 0x0f) {
1177 unsigned mask
= colors_read
& 0x0f;
1178 LLVMValueRef values
[4];
1179 values
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1180 values
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1181 values
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1182 values
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1184 ac_to_integer(&ctx
->ac
,
1185 ac_build_gather_values(&ctx
->ac
, values
, 4));
1187 if (colors_read
& 0xf0) {
1188 unsigned mask
= (colors_read
& 0xf0) >> 4;
1189 LLVMValueRef values
[4];
1190 values
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1191 values
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1192 values
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1193 values
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1195 ac_to_integer(&ctx
->ac
,
1196 ac_build_gather_values(&ctx
->ac
, values
, 4));
1199 ctx
->abi
.interp_at_sample_force_center
=
1200 ctx
->shader
->key
.mono
.u
.ps
.interpolate_at_sample_force_center
;
1201 } else if (nir
->info
.stage
== MESA_SHADER_COMPUTE
) {
1202 if (nir
->info
.cs
.user_data_components_amd
) {
1203 ctx
->abi
.user_data
= LLVMGetParam(ctx
->main_fn
, ctx
->param_cs_user_data
);
1204 ctx
->abi
.user_data
= ac_build_expand_to_vec4(&ctx
->ac
, ctx
->abi
.user_data
,
1205 nir
->info
.cs
.user_data_components_amd
);
1209 ctx
->abi
.inputs
= &ctx
->inputs
[0];
1210 ctx
->abi
.load_sampler_desc
= si_nir_load_sampler_desc
;
1211 ctx
->abi
.clamp_shadow_reference
= true;
1212 ctx
->abi
.robust_buffer_access
= true;
1214 ctx
->num_samplers
= util_last_bit(info
->samplers_declared
);
1215 ctx
->num_images
= util_last_bit(info
->images_declared
);
1217 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_CS_LOCAL_SIZE
]) {
1218 assert(gl_shader_stage_is_compute(nir
->info
.stage
));
1219 si_declare_compute_memory(ctx
);
1221 ac_nir_translate(&ctx
->ac
, &ctx
->abi
, nir
);