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radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35 #include "compiler/nir/nir_deref.h"
36
37 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
38 {
39 for (unsigned i = 0; i < instr->num_srcs; i++) {
40 switch (instr->src[i].src_type) {
41 case nir_tex_src_texture_deref:
42 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
43 default:
44 break;
45 }
46 }
47
48 return NULL;
49 }
50
51 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
52 {
53 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
54 }
55
56 static void gather_usage_helper(const nir_deref_instr **deref_ptr,
57 unsigned location,
58 uint8_t mask,
59 uint8_t *usage_mask)
60 {
61 for (; *deref_ptr; deref_ptr++) {
62 const nir_deref_instr *deref = *deref_ptr;
63 switch (deref->deref_type) {
64 case nir_deref_type_array: {
65 unsigned elem_size =
66 glsl_count_attribute_slots(deref->type, false);
67 if (nir_src_is_const(deref->arr.index)) {
68 location += elem_size * nir_src_as_uint(deref->arr.index);
69 } else {
70 unsigned array_elems =
71 glsl_get_length(deref_ptr[-1]->type);
72 for (unsigned i = 0; i < array_elems; i++) {
73 gather_usage_helper(deref_ptr + 1,
74 location + elem_size * i,
75 mask, usage_mask);
76 }
77 return;
78 }
79 break;
80 }
81 case nir_deref_type_struct: {
82 const struct glsl_type *parent_type =
83 deref_ptr[-1]->type;
84 unsigned index = deref->strct.index;
85 for (unsigned i = 0; i < index; i++) {
86 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
87 location += glsl_count_attribute_slots(ft, false);
88 }
89 break;
90 }
91 default:
92 unreachable("Unhandled deref type in gather_components_used_helper");
93 }
94 }
95
96 usage_mask[location] |= mask & 0xf;
97 if (mask & 0xf0)
98 usage_mask[location + 1] |= (mask >> 4) & 0xf;
99 }
100
101 static void gather_usage(const nir_deref_instr *deref,
102 uint8_t mask,
103 uint8_t *usage_mask)
104 {
105 nir_deref_path path;
106 nir_deref_path_init(&path, (nir_deref_instr *)deref, NULL);
107
108 unsigned location_frac = path.path[0]->var->data.location_frac;
109 if (glsl_type_is_64bit(deref->type)) {
110 uint8_t new_mask = 0;
111 for (unsigned i = 0; i < 4; i++) {
112 if (mask & (1 << i))
113 new_mask |= 0x3 << (2 * i);
114 }
115 mask = new_mask << location_frac;
116 } else {
117 mask <<= location_frac;
118 mask &= 0xf;
119 }
120
121 gather_usage_helper((const nir_deref_instr **)&path.path[1],
122 path.path[0]->var->data.driver_location,
123 mask, usage_mask);
124
125 nir_deref_path_finish(&path);
126 }
127
128 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
129 const nir_intrinsic_instr *instr,
130 const nir_deref_instr *deref,
131 struct si_shader_info *info)
132 {
133 switch (nir->info.stage) {
134 case MESA_SHADER_VERTEX:
135 gather_usage(deref, nir_ssa_def_components_read(&instr->dest.ssa),
136 info->input_usage_mask);
137 default:;
138 }
139 }
140
141 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
142 const nir_intrinsic_instr *instr,
143 nir_variable *var,
144 struct si_shader_info *info)
145 {
146 assert(var && var->data.mode == nir_var_shader_out);
147
148 switch (nir->info.stage) {
149 case MESA_SHADER_TESS_CTRL:
150 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
151 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
152 info->reads_tessfactor_outputs = true;
153 else if (var->data.patch)
154 info->reads_perpatch_outputs = true;
155 else
156 info->reads_pervertex_outputs = true;
157 break;
158
159 case MESA_SHADER_FRAGMENT:
160 if (var->data.fb_fetch_output)
161 info->uses_fbfetch = true;
162 break;
163 default:;
164 }
165 }
166
167 static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
168 const nir_intrinsic_instr *instr,
169 const nir_deref_instr *deref,
170 struct si_shader_info *info)
171 {
172 switch (nir->info.stage) {
173 case MESA_SHADER_VERTEX: /* needed by LS, ES */
174 case MESA_SHADER_TESS_EVAL: /* needed by ES */
175 case MESA_SHADER_GEOMETRY:
176 gather_usage(deref, nir_intrinsic_write_mask(instr),
177 info->output_usagemask);
178 break;
179 default:;
180 }
181 }
182
183 static void scan_instruction(const struct nir_shader *nir,
184 struct si_shader_info *info,
185 nir_instr *instr)
186 {
187 if (instr->type == nir_instr_type_alu) {
188 nir_alu_instr *alu = nir_instr_as_alu(instr);
189
190 switch (alu->op) {
191 case nir_op_fddx:
192 case nir_op_fddy:
193 case nir_op_fddx_fine:
194 case nir_op_fddy_fine:
195 case nir_op_fddx_coarse:
196 case nir_op_fddy_coarse:
197 info->uses_derivatives = true;
198 break;
199 default:
200 break;
201 }
202 } else if (instr->type == nir_instr_type_tex) {
203 nir_tex_instr *tex = nir_instr_as_tex(instr);
204 nir_variable *texture = tex_get_texture_var(tex);
205
206 if (!texture) {
207 info->samplers_declared |=
208 u_bit_consecutive(tex->sampler_index, 1);
209 } else {
210 if (texture->data.bindless)
211 info->uses_bindless_samplers = true;
212 }
213
214 switch (tex->op) {
215 case nir_texop_tex:
216 case nir_texop_txb:
217 case nir_texop_lod:
218 info->uses_derivatives = true;
219 break;
220 default:
221 break;
222 }
223 } else if (instr->type == nir_instr_type_intrinsic) {
224 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
225
226 switch (intr->intrinsic) {
227 case nir_intrinsic_load_front_face:
228 info->uses_frontface = 1;
229 break;
230 case nir_intrinsic_load_instance_id:
231 info->uses_instanceid = 1;
232 break;
233 case nir_intrinsic_load_invocation_id:
234 info->uses_invocationid = true;
235 break;
236 case nir_intrinsic_load_num_work_groups:
237 info->uses_grid_size = true;
238 break;
239 case nir_intrinsic_load_local_invocation_index:
240 case nir_intrinsic_load_subgroup_id:
241 case nir_intrinsic_load_num_subgroups:
242 info->uses_subgroup_info = true;
243 break;
244 case nir_intrinsic_load_local_group_size:
245 /* The block size is translated to IMM with a fixed block size. */
246 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
247 info->uses_block_size = true;
248 break;
249 case nir_intrinsic_load_local_invocation_id:
250 case nir_intrinsic_load_work_group_id: {
251 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
252 while (mask) {
253 unsigned i = u_bit_scan(&mask);
254
255 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
256 info->uses_block_id[i] = true;
257 else
258 info->uses_thread_id[i] = true;
259 }
260 break;
261 }
262 case nir_intrinsic_load_vertex_id:
263 info->uses_vertexid = 1;
264 break;
265 case nir_intrinsic_load_vertex_id_zero_base:
266 info->uses_vertexid_nobase = 1;
267 break;
268 case nir_intrinsic_load_base_vertex:
269 info->uses_basevertex = 1;
270 break;
271 case nir_intrinsic_load_draw_id:
272 info->uses_drawid = 1;
273 break;
274 case nir_intrinsic_load_primitive_id:
275 info->uses_primid = 1;
276 break;
277 case nir_intrinsic_load_sample_mask_in:
278 info->reads_samplemask = true;
279 break;
280 case nir_intrinsic_load_tess_level_inner:
281 case nir_intrinsic_load_tess_level_outer:
282 info->reads_tess_factors = true;
283 break;
284 case nir_intrinsic_bindless_image_load:
285 info->uses_bindless_images = true;
286
287 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
288 info->uses_bindless_buffer_load = true;
289 else
290 info->uses_bindless_image_load = true;
291 break;
292 case nir_intrinsic_bindless_image_size:
293 case nir_intrinsic_bindless_image_samples:
294 info->uses_bindless_images = true;
295 break;
296 case nir_intrinsic_bindless_image_store:
297 info->uses_bindless_images = true;
298
299 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
300 info->uses_bindless_buffer_store = true;
301 else
302 info->uses_bindless_image_store = true;
303
304 info->writes_memory = true;
305 info->num_memory_instructions++; /* we only care about stores */
306 break;
307 case nir_intrinsic_image_deref_store:
308 info->writes_memory = true;
309 info->num_memory_instructions++; /* we only care about stores */
310 break;
311 case nir_intrinsic_bindless_image_atomic_add:
312 case nir_intrinsic_bindless_image_atomic_imin:
313 case nir_intrinsic_bindless_image_atomic_umin:
314 case nir_intrinsic_bindless_image_atomic_imax:
315 case nir_intrinsic_bindless_image_atomic_umax:
316 case nir_intrinsic_bindless_image_atomic_and:
317 case nir_intrinsic_bindless_image_atomic_or:
318 case nir_intrinsic_bindless_image_atomic_xor:
319 case nir_intrinsic_bindless_image_atomic_exchange:
320 case nir_intrinsic_bindless_image_atomic_comp_swap:
321 info->uses_bindless_images = true;
322
323 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
324 info->uses_bindless_buffer_atomic = true;
325 else
326 info->uses_bindless_image_atomic = true;
327
328 info->writes_memory = true;
329 info->num_memory_instructions++; /* we only care about stores */
330 break;
331 case nir_intrinsic_image_deref_atomic_add:
332 case nir_intrinsic_image_deref_atomic_imin:
333 case nir_intrinsic_image_deref_atomic_umin:
334 case nir_intrinsic_image_deref_atomic_imax:
335 case nir_intrinsic_image_deref_atomic_umax:
336 case nir_intrinsic_image_deref_atomic_and:
337 case nir_intrinsic_image_deref_atomic_or:
338 case nir_intrinsic_image_deref_atomic_xor:
339 case nir_intrinsic_image_deref_atomic_exchange:
340 case nir_intrinsic_image_deref_atomic_comp_swap:
341 case nir_intrinsic_image_deref_atomic_inc_wrap:
342 case nir_intrinsic_image_deref_atomic_dec_wrap:
343 info->writes_memory = true;
344 info->num_memory_instructions++; /* we only care about stores */
345 break;
346 case nir_intrinsic_store_ssbo:
347 case nir_intrinsic_ssbo_atomic_add:
348 case nir_intrinsic_ssbo_atomic_imin:
349 case nir_intrinsic_ssbo_atomic_umin:
350 case nir_intrinsic_ssbo_atomic_imax:
351 case nir_intrinsic_ssbo_atomic_umax:
352 case nir_intrinsic_ssbo_atomic_and:
353 case nir_intrinsic_ssbo_atomic_or:
354 case nir_intrinsic_ssbo_atomic_xor:
355 case nir_intrinsic_ssbo_atomic_exchange:
356 case nir_intrinsic_ssbo_atomic_comp_swap:
357 info->writes_memory = true;
358 info->num_memory_instructions++; /* we only care about stores */
359 break;
360 case nir_intrinsic_load_color0:
361 case nir_intrinsic_load_color1: {
362 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
363 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
364 info->colors_read |= mask << (index * 4);
365 break;
366 }
367 case nir_intrinsic_load_barycentric_pixel:
368 case nir_intrinsic_load_barycentric_centroid:
369 case nir_intrinsic_load_barycentric_sample:
370 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
371 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
372 unsigned mode = nir_intrinsic_interp_mode(intr);
373
374 if (mode == INTERP_MODE_FLAT)
375 break;
376
377 if (mode == INTERP_MODE_NOPERSPECTIVE) {
378 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
379 info->uses_linear_sample = true;
380 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
381 info->uses_linear_centroid = true;
382 else
383 info->uses_linear_center = true;
384
385 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
386 info->uses_linear_opcode_interp_sample = true;
387 } else {
388 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
389 info->uses_persp_sample = true;
390 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
391 info->uses_persp_centroid = true;
392 else
393 info->uses_persp_center = true;
394
395 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
396 info->uses_persp_opcode_interp_sample = true;
397 }
398 break;
399 }
400 case nir_intrinsic_load_deref: {
401 nir_variable *var = intrinsic_get_var(intr);
402 nir_variable_mode mode = var->data.mode;
403
404 if (mode == nir_var_shader_in) {
405 /* PS inputs use the interpolated load intrinsics. */
406 assert(nir->info.stage != MESA_SHADER_FRAGMENT);
407 gather_intrinsic_load_deref_input_info(nir, intr,
408 nir_src_as_deref(intr->src[0]), info);
409 } else if (mode == nir_var_shader_out) {
410 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
411 }
412 break;
413 }
414 case nir_intrinsic_store_deref: {
415 nir_variable *var = intrinsic_get_var(intr);
416
417 if (var->data.mode == nir_var_shader_out)
418 gather_intrinsic_store_deref_output_info(nir, intr,
419 nir_src_as_deref(intr->src[0]), info);
420 break;
421 }
422 case nir_intrinsic_interp_deref_at_centroid:
423 case nir_intrinsic_interp_deref_at_sample:
424 case nir_intrinsic_interp_deref_at_offset:
425 unreachable("interp opcodes should have been lowered");
426 break;
427 default:
428 break;
429 }
430 }
431 }
432
433 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
434 struct si_tessctrl_info *out)
435 {
436 memset(out, 0, sizeof(*out));
437
438 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
439 return;
440
441 out->tessfactors_are_def_in_all_invocs =
442 ac_are_tessfactors_def_in_all_invocs(nir);
443 }
444
445 static void scan_output_slot(const nir_variable *var,
446 unsigned var_idx,
447 unsigned component, unsigned num_components,
448 struct si_shader_info *info)
449 {
450 assert(component + num_components <= 4);
451 assert(component < 4);
452
453 unsigned semantic_name, semantic_index;
454
455 unsigned location = var->data.location + var_idx;
456 unsigned drv_location = var->data.driver_location + var_idx;
457
458 if (info->processor == PIPE_SHADER_FRAGMENT) {
459 tgsi_get_gl_frag_result_semantic(location,
460 &semantic_name, &semantic_index);
461
462 /* Adjust for dual source blending */
463 if (var->data.index > 0) {
464 semantic_index++;
465 }
466 } else {
467 tgsi_get_gl_varying_semantic(location, true,
468 &semantic_name, &semantic_index);
469 }
470
471 ubyte usagemask = ((1 << num_components) - 1) << component;
472
473 unsigned gs_out_streams;
474 if (var->data.stream & NIR_STREAM_PACKED) {
475 gs_out_streams = var->data.stream & ~NIR_STREAM_PACKED;
476 } else {
477 assert(var->data.stream < 4);
478 gs_out_streams = 0;
479 for (unsigned j = 0; j < num_components; ++j)
480 gs_out_streams |= var->data.stream << (2 * (component + j));
481 }
482
483 unsigned streamx = gs_out_streams & 3;
484 unsigned streamy = (gs_out_streams >> 2) & 3;
485 unsigned streamz = (gs_out_streams >> 4) & 3;
486 unsigned streamw = (gs_out_streams >> 6) & 3;
487
488 if (usagemask & TGSI_WRITEMASK_X) {
489 info->output_streams[drv_location] |= streamx;
490 info->num_stream_output_components[streamx]++;
491 }
492 if (usagemask & TGSI_WRITEMASK_Y) {
493 info->output_streams[drv_location] |= streamy << 2;
494 info->num_stream_output_components[streamy]++;
495 }
496 if (usagemask & TGSI_WRITEMASK_Z) {
497 info->output_streams[drv_location] |= streamz << 4;
498 info->num_stream_output_components[streamz]++;
499 }
500 if (usagemask & TGSI_WRITEMASK_W) {
501 info->output_streams[drv_location] |= streamw << 6;
502 info->num_stream_output_components[streamw]++;
503 }
504
505 info->output_semantic_name[drv_location] = semantic_name;
506 info->output_semantic_index[drv_location] = semantic_index;
507
508 switch (semantic_name) {
509 case TGSI_SEMANTIC_PRIMID:
510 info->writes_primid = true;
511 break;
512 case TGSI_SEMANTIC_VIEWPORT_INDEX:
513 info->writes_viewport_index = true;
514 break;
515 case TGSI_SEMANTIC_LAYER:
516 info->writes_layer = true;
517 break;
518 case TGSI_SEMANTIC_PSIZE:
519 info->writes_psize = true;
520 break;
521 case TGSI_SEMANTIC_CLIPVERTEX:
522 info->writes_clipvertex = true;
523 break;
524 case TGSI_SEMANTIC_COLOR:
525 info->colors_written |= 1 << semantic_index;
526 break;
527 case TGSI_SEMANTIC_STENCIL:
528 info->writes_stencil = true;
529 break;
530 case TGSI_SEMANTIC_SAMPLEMASK:
531 info->writes_samplemask = true;
532 break;
533 case TGSI_SEMANTIC_EDGEFLAG:
534 info->writes_edgeflag = true;
535 break;
536 case TGSI_SEMANTIC_POSITION:
537 if (info->processor == PIPE_SHADER_FRAGMENT)
538 info->writes_z = true;
539 else
540 info->writes_position = true;
541 break;
542 }
543 }
544
545 static void scan_output_helper(const nir_variable *var,
546 unsigned location,
547 const struct glsl_type *type,
548 struct si_shader_info *info)
549 {
550 if (glsl_type_is_struct(type) || glsl_type_is_interface(type)) {
551 for (unsigned i = 0; i < glsl_get_length(type); i++) {
552 const struct glsl_type *ft = glsl_get_struct_field(type, i);
553 scan_output_helper(var, location, ft, info);
554 location += glsl_count_attribute_slots(ft, false);
555 }
556 } else if (glsl_type_is_array_or_matrix(type)) {
557 const struct glsl_type *elem_type =
558 glsl_get_array_element(type);
559 unsigned num_elems = glsl_get_length(type);
560 if (var->data.compact) {
561 assert(glsl_type_is_scalar(elem_type));
562 assert(glsl_get_bit_size(elem_type) == 32);
563 unsigned component = var->data.location_frac;
564 scan_output_slot(var, location, component,
565 MIN2(num_elems, 4 - component), info);
566 if (component + num_elems > 4) {
567 scan_output_slot(var, location + 1, 0,
568 component + num_elems - 4, info);
569 }
570
571 } else {
572 unsigned elem_count = glsl_count_attribute_slots(elem_type, false);
573 for (unsigned i = 0; i < num_elems; i++) {
574 scan_output_helper(var, location, elem_type, info);
575 location += elem_count;
576 }
577 }
578 } else if (glsl_type_is_dual_slot(type)) {
579 unsigned component = var->data.location_frac;
580 scan_output_slot(var, location, component, 4 - component, info);
581 scan_output_slot(var, location + 1, 0, component + 2 * glsl_get_components(type) - 4,
582 info);
583 } else {
584 unsigned component = var->data.location_frac;
585 assert(glsl_type_is_vector_or_scalar(type));
586 unsigned num_components = glsl_get_components(type);
587 if (glsl_type_is_64bit(type))
588 num_components *= 2;
589 scan_output_slot(var, location, component, num_components, info);
590 }
591 }
592
593 void si_nir_scan_shader(const struct nir_shader *nir,
594 struct si_shader_info *info)
595 {
596 nir_function *func;
597 unsigned i;
598
599 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
600 info->num_tokens = 2; /* indicate that the shader is non-empty */
601 info->num_instructions = 2;
602
603 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
604 pipe_shader_type_from_mesa(nir->info.next_stage);
605
606 if (nir->info.stage == MESA_SHADER_VERTEX) {
607 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
608 nir->info.vs.window_space_position;
609 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
610 nir->info.vs.blit_sgprs_amd;
611 }
612
613 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
614 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
615 nir->info.tess.tcs_vertices_out;
616 }
617
618 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
619 if (nir->info.tess.primitive_mode == GL_ISOLINES)
620 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
621 else
622 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
623
624 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
625 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
626 PIPE_TESS_SPACING_FRACTIONAL_ODD);
627 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
628 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
629
630 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
631 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
632 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
633 }
634
635 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
636 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
637 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
638 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
639 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
640 }
641
642 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
643 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
644 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
645 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
646
647 if (nir->info.fs.pixel_center_integer) {
648 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
649 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
650 }
651
652 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
653 switch (nir->info.fs.depth_layout) {
654 case FRAG_DEPTH_LAYOUT_ANY:
655 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
656 break;
657 case FRAG_DEPTH_LAYOUT_GREATER:
658 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
659 break;
660 case FRAG_DEPTH_LAYOUT_LESS:
661 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
662 break;
663 case FRAG_DEPTH_LAYOUT_UNCHANGED:
664 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
665 break;
666 default:
667 unreachable("Unknow depth layout");
668 }
669 }
670 }
671
672 if (gl_shader_stage_is_compute(nir->info.stage)) {
673 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
674 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
675 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
676 info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] = nir->info.cs.user_data_components_amd;
677 }
678
679 i = 0;
680 uint64_t processed_inputs = 0;
681 nir_foreach_variable(variable, &nir->inputs) {
682 unsigned semantic_name, semantic_index;
683
684 const struct glsl_type *type = variable->type;
685 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
686 assert(glsl_type_is_array(type));
687 type = glsl_get_array_element(type);
688 }
689
690 unsigned attrib_count = glsl_count_attribute_slots(type,
691 nir->info.stage == MESA_SHADER_VERTEX);
692
693 i = variable->data.driver_location;
694
695 /* Vertex shader inputs don't have semantics. The state
696 * tracker has already mapped them to attributes via
697 * variable->data.driver_location.
698 */
699 if (nir->info.stage == MESA_SHADER_VERTEX)
700 continue;
701
702 for (unsigned j = 0; j < attrib_count; j++, i++) {
703
704 if (processed_inputs & ((uint64_t)1 << i))
705 continue;
706
707 processed_inputs |= ((uint64_t)1 << i);
708
709 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
710 &semantic_name, &semantic_index);
711
712 info->input_semantic_name[i] = semantic_name;
713 info->input_semantic_index[i] = semantic_index;
714
715 if (semantic_name == TGSI_SEMANTIC_PRIMID)
716 info->uses_primid = true;
717
718 if (semantic_name == TGSI_SEMANTIC_COLOR) {
719 /* We only need this for color inputs. */
720 if (variable->data.sample)
721 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
722 else if (variable->data.centroid)
723 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
724 else
725 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
726 }
727
728 enum glsl_base_type base_type =
729 glsl_get_base_type(glsl_without_array(variable->type));
730
731 switch (variable->data.interpolation) {
732 case INTERP_MODE_NONE:
733 if (glsl_base_type_is_integer(base_type)) {
734 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
735 break;
736 }
737
738 if (semantic_name == TGSI_SEMANTIC_COLOR) {
739 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
740 break;
741 }
742 /* fall-through */
743
744 case INTERP_MODE_SMOOTH:
745 assert(!glsl_base_type_is_integer(base_type));
746
747 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
748 break;
749
750 case INTERP_MODE_NOPERSPECTIVE:
751 assert(!glsl_base_type_is_integer(base_type));
752
753 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
754 break;
755
756 case INTERP_MODE_FLAT:
757 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
758 break;
759 }
760 }
761 }
762
763 nir_foreach_variable(variable, &nir->outputs) {
764 const struct glsl_type *type = variable->type;
765 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
766 assert(glsl_type_is_array(type));
767 type = glsl_get_array_element(type);
768 }
769
770 ASSERTED unsigned attrib_count = glsl_count_attribute_slots(type, false);
771 scan_output_helper(variable, 0, type, info);
772
773 unsigned loc = variable->data.location;
774 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
775 loc == FRAG_RESULT_COLOR &&
776 nir->info.outputs_written & (1ull << loc)) {
777 assert(attrib_count == 1);
778 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
779 }
780 }
781
782 info->num_inputs = nir->num_inputs;
783 info->num_outputs = nir->num_outputs;
784
785 info->const_file_max[0] = nir->num_uniforms - 1;
786 info->shader_buffers_declared = u_bit_consecutive(0, nir->info.num_ssbos);
787 info->const_buffers_declared = u_bit_consecutive(1, nir->info.num_ubos);
788 if (nir->num_uniforms > 0)
789 info->const_buffers_declared |= 1;
790 info->images_declared = u_bit_consecutive(0, nir->info.num_images);
791 info->msaa_images_declared = u_bit_consecutive(0, nir->info.last_msaa_image + 1);
792 info->samplers_declared = nir->info.textures_used;
793
794 info->num_written_clipdistance = nir->info.clip_distance_array_size;
795 info->num_written_culldistance = nir->info.cull_distance_array_size;
796 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
797 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
798
799 if (info->processor == PIPE_SHADER_FRAGMENT)
800 info->uses_kill = nir->info.fs.uses_discard;
801
802 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
803 nir_foreach_block(block, func->impl) {
804 nir_foreach_instr(instr, block)
805 scan_instruction(nir, info, instr);
806 }
807 }
808
809 static void
810 si_nir_opts(struct nir_shader *nir)
811 {
812 bool progress;
813
814 do {
815 progress = false;
816
817 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
818
819 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
820 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
821
822 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
823 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
824
825 /* (Constant) copy propagation is needed for txf with offsets. */
826 NIR_PASS(progress, nir, nir_copy_prop);
827 NIR_PASS(progress, nir, nir_opt_remove_phis);
828 NIR_PASS(progress, nir, nir_opt_dce);
829 if (nir_opt_trivial_continues(nir)) {
830 progress = true;
831 NIR_PASS(progress, nir, nir_copy_prop);
832 NIR_PASS(progress, nir, nir_opt_dce);
833 }
834 NIR_PASS(progress, nir, nir_opt_if, true);
835 NIR_PASS(progress, nir, nir_opt_dead_cf);
836 NIR_PASS(progress, nir, nir_opt_cse);
837 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
838
839 /* Needed for algebraic lowering */
840 NIR_PASS(progress, nir, nir_opt_algebraic);
841 NIR_PASS(progress, nir, nir_opt_constant_folding);
842
843 if (!nir->info.flrp_lowered) {
844 unsigned lower_flrp =
845 (nir->options->lower_flrp16 ? 16 : 0) |
846 (nir->options->lower_flrp32 ? 32 : 0) |
847 (nir->options->lower_flrp64 ? 64 : 0);
848 assert(lower_flrp);
849 bool lower_flrp_progress = false;
850
851 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
852 lower_flrp,
853 false /* always_precise */,
854 nir->options->lower_ffma);
855 if (lower_flrp_progress) {
856 NIR_PASS(progress, nir,
857 nir_opt_constant_folding);
858 progress = true;
859 }
860
861 /* Nothing should rematerialize any flrps, so we only
862 * need to do this lowering once.
863 */
864 nir->info.flrp_lowered = true;
865 }
866
867 NIR_PASS(progress, nir, nir_opt_undef);
868 NIR_PASS(progress, nir, nir_opt_conditional_discard);
869 if (nir->options->max_unroll_iterations) {
870 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
871 }
872 } while (progress);
873 }
874
875 static int
876 type_size_vec4(const struct glsl_type *type, bool bindless)
877 {
878 return glsl_count_attribute_slots(type, false);
879 }
880
881 static void
882 si_nir_lower_color(nir_shader *nir)
883 {
884 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
885
886 nir_builder b;
887 nir_builder_init(&b, entrypoint);
888
889 nir_foreach_block(block, entrypoint) {
890 nir_foreach_instr_safe(instr, block) {
891 if (instr->type != nir_instr_type_intrinsic)
892 continue;
893
894 nir_intrinsic_instr *intrin =
895 nir_instr_as_intrinsic(instr);
896
897 if (intrin->intrinsic != nir_intrinsic_load_deref)
898 continue;
899
900 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
901 if (deref->mode != nir_var_shader_in)
902 continue;
903
904 b.cursor = nir_before_instr(instr);
905 nir_variable *var = nir_deref_instr_get_variable(deref);
906 nir_ssa_def *def;
907
908 if (var->data.location == VARYING_SLOT_COL0) {
909 def = nir_load_color0(&b);
910 } else if (var->data.location == VARYING_SLOT_COL1) {
911 def = nir_load_color1(&b);
912 } else {
913 continue;
914 }
915
916 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
917 nir_instr_remove(instr);
918 }
919 }
920 }
921
922 static void si_nir_lower_ps_inputs(struct nir_shader *nir)
923 {
924 if (nir->info.stage != MESA_SHADER_FRAGMENT)
925 return;
926
927 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
928 nir_shader_get_entrypoint(nir), false, true);
929
930 /* Since we're doing nir_lower_io_to_temporaries late, we need
931 * to lower all the copy_deref's introduced by
932 * lower_io_to_temporaries before calling nir_lower_io.
933 */
934 NIR_PASS_V(nir, nir_split_var_copies);
935 NIR_PASS_V(nir, nir_lower_var_copies);
936 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
937
938 si_nir_lower_color(nir);
939 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
940
941 /* This pass needs actual constants */
942 NIR_PASS_V(nir, nir_opt_constant_folding);
943 NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
944 nir_var_shader_in);
945 }
946
947 void si_nir_adjust_driver_locations(struct nir_shader *nir)
948 {
949 /* Adjust the driver location of inputs and outputs. The state tracker
950 * interprets them as slots, while the ac/nir backend interprets them
951 * as individual components.
952 */
953 if (nir->info.stage != MESA_SHADER_FRAGMENT) {
954 nir_foreach_variable(variable, &nir->inputs)
955 variable->data.driver_location *= 4;
956 }
957
958 nir_foreach_variable(variable, &nir->outputs)
959 variable->data.driver_location *= 4;
960 }
961
962 /**
963 * Perform "lowering" operations on the NIR that are run once when the shader
964 * selector is created.
965 */
966 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
967 {
968 /* Perform lowerings (and optimizations) of code.
969 *
970 * Performance considerations aside, we must:
971 * - lower certain ALU operations
972 * - ensure constant offsets for texture instructions are folded
973 * and copy-propagated
974 */
975
976 static const struct nir_lower_tex_options lower_tex_options = {
977 .lower_txp = ~0u,
978 };
979 NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
980
981 const nir_lower_subgroups_options subgroups_options = {
982 .subgroup_size = 64,
983 .ballot_bit_size = 64,
984 .lower_to_scalar = true,
985 .lower_subgroup_masks = true,
986 .lower_vote_trivial = false,
987 .lower_vote_eq_to_ballot = true,
988 };
989 NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
990
991 /* Lower load constants to scalar and then clean up the mess */
992 NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
993 NIR_PASS_V(nir, nir_lower_var_copies);
994 NIR_PASS_V(nir, nir_lower_pack);
995 NIR_PASS_V(nir, nir_opt_access);
996 si_nir_opts(nir);
997
998 /* Lower large variables that are always constant with load_constant
999 * intrinsics, which get turned into PC-relative loads from a data
1000 * section next to the shader.
1001 *
1002 * st/mesa calls finalize_nir twice, but we can't call this pass twice.
1003 */
1004 bool changed = false;
1005 if (!nir->constant_data) {
1006 NIR_PASS(changed, nir, nir_opt_large_constants,
1007 glsl_get_natural_size_align_bytes, 16);
1008 }
1009
1010 changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
1011 if (changed)
1012 si_nir_opts(nir);
1013
1014 NIR_PASS_V(nir, nir_lower_bool_to_int32);
1015 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp);
1016 }
1017
1018 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
1019 {
1020 struct si_screen *sscreen = (struct si_screen *)screen;
1021 struct nir_shader *nir = (struct nir_shader *)nirptr;
1022
1023 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
1024 si_nir_lower_ps_inputs(nir);
1025 si_lower_nir(sscreen, nir);
1026 }
1027
1028 static void declare_nir_input_vs(struct si_shader_context *ctx,
1029 struct nir_variable *variable,
1030 unsigned input_index,
1031 LLVMValueRef out[4])
1032 {
1033 si_llvm_load_input_vs(ctx, input_index, out);
1034 }
1035
1036 LLVMValueRef
1037 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
1038 enum glsl_interp_mode interp, unsigned location)
1039 {
1040 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1041
1042 switch (interp) {
1043 case INTERP_MODE_FLAT:
1044 return NULL;
1045 case INTERP_MODE_SMOOTH:
1046 case INTERP_MODE_NONE:
1047 if (location == INTERP_CENTER)
1048 return ac_get_arg(&ctx->ac, ctx->args.persp_center);
1049 else if (location == INTERP_CENTROID)
1050 return ctx->abi.persp_centroid;
1051 else if (location == INTERP_SAMPLE)
1052 return ac_get_arg(&ctx->ac, ctx->args.persp_sample);
1053 break;
1054 case INTERP_MODE_NOPERSPECTIVE:
1055 if (location == INTERP_CENTER)
1056 return ac_get_arg(&ctx->ac, ctx->args.linear_center);
1057 else if (location == INTERP_CENTROID)
1058 return ac_get_arg(&ctx->ac, ctx->args.linear_centroid);
1059 else if (location == INTERP_SAMPLE)
1060 return ac_get_arg(&ctx->ac, ctx->args.linear_sample);
1061 break;
1062 default:
1063 assert(!"Unhandled interpolation mode.");
1064 }
1065 return NULL;
1066 }
1067
1068 static LLVMValueRef
1069 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1070 unsigned descriptor_set, unsigned base_index,
1071 unsigned constant_index, LLVMValueRef dynamic_index,
1072 enum ac_descriptor_type desc_type, bool image,
1073 bool write, bool bindless)
1074 {
1075 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1076 LLVMBuilderRef builder = ctx->ac.builder;
1077 unsigned const_index = base_index + constant_index;
1078
1079 assert(!descriptor_set);
1080 assert(desc_type <= AC_DESC_BUFFER);
1081
1082 if (bindless) {
1083 LLVMValueRef list = ac_get_arg(&ctx->ac, ctx->bindless_samplers_and_images);
1084
1085 /* dynamic_index is the bindless handle */
1086 if (image) {
1087 /* Bindless image descriptors use 16-dword slots. */
1088 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1089 LLVMConstInt(ctx->i64, 2, 0), "");
1090 /* FMASK is right after the image. */
1091 if (desc_type == AC_DESC_FMASK) {
1092 dynamic_index = LLVMBuildAdd(ctx->ac.builder, dynamic_index,
1093 ctx->i32_1, "");
1094 }
1095
1096 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1097 write, true);
1098 }
1099
1100 /* Since bindless handle arithmetic can contain an unsigned integer
1101 * wraparound and si_load_sampler_desc assumes there isn't any,
1102 * use GEP without "inbounds" (inside ac_build_pointer_add)
1103 * to prevent incorrect code generation and hangs.
1104 */
1105 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1106 LLVMConstInt(ctx->i64, 2, 0), "");
1107 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1108 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1109 }
1110
1111 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1112 assert(const_index < num_slots || dynamic_index);
1113
1114 LLVMValueRef list = ac_get_arg(&ctx->ac, ctx->samplers_and_images);
1115 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1116
1117 if (dynamic_index) {
1118 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1119
1120 /* From the GL_ARB_shader_image_load_store extension spec:
1121 *
1122 * If a shader performs an image load, store, or atomic
1123 * operation using an image variable declared as an array,
1124 * and if the index used to select an individual element is
1125 * negative or greater than or equal to the size of the
1126 * array, the results of the operation are undefined but may
1127 * not lead to termination.
1128 */
1129 index = si_llvm_bound_index(ctx, index, num_slots);
1130 }
1131
1132 if (image) {
1133 /* FMASKs are separate from images. */
1134 if (desc_type == AC_DESC_FMASK) {
1135 index = LLVMBuildAdd(ctx->ac.builder, index,
1136 LLVMConstInt(ctx->i32, SI_NUM_IMAGES, 0), "");
1137 }
1138 index = LLVMBuildSub(ctx->ac.builder,
1139 LLVMConstInt(ctx->i32, SI_NUM_IMAGE_SLOTS - 1, 0),
1140 index, "");
1141 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1142 }
1143
1144 index = LLVMBuildAdd(ctx->ac.builder, index,
1145 LLVMConstInt(ctx->i32, SI_NUM_IMAGE_SLOTS / 2, 0), "");
1146 return si_load_sampler_desc(ctx, list, index, desc_type);
1147 }
1148
1149 static void bitcast_inputs(struct si_shader_context *ctx,
1150 LLVMValueRef data[4],
1151 unsigned input_idx)
1152 {
1153 for (unsigned chan = 0; chan < 4; chan++) {
1154 ctx->inputs[input_idx + chan] =
1155 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1156 }
1157 }
1158
1159 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1160 {
1161 struct si_shader_info *info = &ctx->shader->selector->info;
1162
1163 if (nir->info.stage == MESA_SHADER_VERTEX) {
1164 uint64_t processed_inputs = 0;
1165 nir_foreach_variable(variable, &nir->inputs) {
1166 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1167 true);
1168 unsigned input_idx = variable->data.driver_location;
1169
1170 LLVMValueRef data[4];
1171 unsigned loc = variable->data.location;
1172
1173 for (unsigned i = 0; i < attrib_count; i++) {
1174 /* Packed components share the same location so skip
1175 * them if we have already processed the location.
1176 */
1177 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1178 input_idx += 4;
1179 continue;
1180 }
1181
1182 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1183 bitcast_inputs(ctx, data, input_idx);
1184 if (glsl_type_is_dual_slot(variable->type)) {
1185 input_idx += 4;
1186 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1187 bitcast_inputs(ctx, data, input_idx);
1188 }
1189
1190 processed_inputs |= ((uint64_t)1 << (loc + i));
1191 input_idx += 4;
1192 }
1193 }
1194 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1195 unsigned colors_read =
1196 ctx->shader->selector->info.colors_read;
1197 LLVMValueRef main_fn = ctx->main_fn;
1198
1199 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1200
1201 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1202
1203 if (colors_read & 0x0f) {
1204 unsigned mask = colors_read & 0x0f;
1205 LLVMValueRef values[4];
1206 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1207 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1208 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1209 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1210 ctx->abi.color0 =
1211 ac_to_integer(&ctx->ac,
1212 ac_build_gather_values(&ctx->ac, values, 4));
1213 }
1214 if (colors_read & 0xf0) {
1215 unsigned mask = (colors_read & 0xf0) >> 4;
1216 LLVMValueRef values[4];
1217 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1218 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1219 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1220 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1221 ctx->abi.color1 =
1222 ac_to_integer(&ctx->ac,
1223 ac_build_gather_values(&ctx->ac, values, 4));
1224 }
1225
1226 ctx->abi.interp_at_sample_force_center =
1227 ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
1228 } else if (nir->info.stage == MESA_SHADER_COMPUTE) {
1229 if (nir->info.cs.user_data_components_amd) {
1230 ctx->abi.user_data = ac_get_arg(&ctx->ac, ctx->cs_user_data);
1231 ctx->abi.user_data = ac_build_expand_to_vec4(&ctx->ac, ctx->abi.user_data,
1232 nir->info.cs.user_data_components_amd);
1233 }
1234 }
1235
1236 ctx->abi.inputs = &ctx->inputs[0];
1237 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1238 ctx->abi.clamp_shadow_reference = true;
1239 ctx->abi.robust_buffer_access = true;
1240
1241 ctx->num_samplers = util_last_bit(info->samplers_declared);
1242 ctx->num_images = util_last_bit(info->images_declared);
1243
1244 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1245 assert(gl_shader_stage_is_compute(nir->info.stage));
1246 si_declare_compute_memory(ctx);
1247 }
1248 ac_nir_translate(&ctx->ac, &ctx->abi, &ctx->args, nir);
1249
1250 return true;
1251 }