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radeonsi/nir: Delete unreachable code
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34
35 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
36 {
37 for (unsigned i = 0; i < instr->num_srcs; i++) {
38 switch (instr->src[i].src_type) {
39 case nir_tex_src_texture_deref:
40 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
41 default:
42 break;
43 }
44 }
45
46 return NULL;
47 }
48
49 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
50 {
51 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
52 }
53
54 static void gather_intrinsic_load_deref_info(const nir_shader *nir,
55 const nir_intrinsic_instr *instr,
56 nir_variable *var,
57 struct tgsi_shader_info *info)
58 {
59 assert(var && var->data.mode == nir_var_shader_in);
60
61 switch (nir->info.stage) {
62 case MESA_SHADER_VERTEX: {
63 unsigned i = var->data.driver_location;
64 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
65
66 for (unsigned j = 0; j < attrib_count; j++, i++) {
67 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
68 /* TODO: set usage mask more accurately for doubles */
69 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
70 } else {
71 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
72 info->input_usage_mask[i] |= mask << var->data.location_frac;
73 }
74 }
75 break;
76 }
77 default: {
78 unsigned semantic_name, semantic_index;
79 tgsi_get_gl_varying_semantic(var->data.location, true,
80 &semantic_name, &semantic_index);
81
82 if (semantic_name == TGSI_SEMANTIC_COLOR) {
83 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
84 info->colors_read |= mask << (semantic_index * 4);
85 }
86 break;
87 }
88 }
89 }
90
91 static void scan_instruction(const struct nir_shader *nir,
92 struct tgsi_shader_info *info,
93 nir_instr *instr)
94 {
95 if (instr->type == nir_instr_type_alu) {
96 nir_alu_instr *alu = nir_instr_as_alu(instr);
97
98 switch (alu->op) {
99 case nir_op_fddx:
100 case nir_op_fddy:
101 case nir_op_fddx_fine:
102 case nir_op_fddy_fine:
103 case nir_op_fddx_coarse:
104 case nir_op_fddy_coarse:
105 info->uses_derivatives = true;
106 break;
107 default:
108 break;
109 }
110 } else if (instr->type == nir_instr_type_tex) {
111 nir_tex_instr *tex = nir_instr_as_tex(instr);
112 nir_variable *texture = tex_get_texture_var(tex);
113
114 if (!texture) {
115 info->samplers_declared |=
116 u_bit_consecutive(tex->sampler_index, 1);
117 } else {
118 if (texture->data.bindless)
119 info->uses_bindless_samplers = true;
120 }
121
122 switch (tex->op) {
123 case nir_texop_tex:
124 case nir_texop_txb:
125 case nir_texop_lod:
126 info->uses_derivatives = true;
127 break;
128 default:
129 break;
130 }
131 } else if (instr->type == nir_instr_type_intrinsic) {
132 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
133
134 switch (intr->intrinsic) {
135 case nir_intrinsic_load_front_face:
136 info->uses_frontface = 1;
137 break;
138 case nir_intrinsic_load_instance_id:
139 info->uses_instanceid = 1;
140 break;
141 case nir_intrinsic_load_invocation_id:
142 info->uses_invocationid = true;
143 break;
144 case nir_intrinsic_load_num_work_groups:
145 info->uses_grid_size = true;
146 break;
147 case nir_intrinsic_load_local_group_size:
148 /* The block size is translated to IMM with a fixed block size. */
149 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
150 info->uses_block_size = true;
151 break;
152 case nir_intrinsic_load_local_invocation_id:
153 case nir_intrinsic_load_work_group_id: {
154 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
155 while (mask) {
156 unsigned i = u_bit_scan(&mask);
157
158 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
159 info->uses_block_id[i] = true;
160 else
161 info->uses_thread_id[i] = true;
162 }
163 break;
164 }
165 case nir_intrinsic_load_vertex_id:
166 info->uses_vertexid = 1;
167 break;
168 case nir_intrinsic_load_vertex_id_zero_base:
169 info->uses_vertexid_nobase = 1;
170 break;
171 case nir_intrinsic_load_base_vertex:
172 info->uses_basevertex = 1;
173 break;
174 case nir_intrinsic_load_draw_id:
175 info->uses_drawid = 1;
176 break;
177 case nir_intrinsic_load_primitive_id:
178 info->uses_primid = 1;
179 break;
180 case nir_intrinsic_load_sample_mask_in:
181 info->reads_samplemask = true;
182 break;
183 case nir_intrinsic_load_tess_level_inner:
184 case nir_intrinsic_load_tess_level_outer:
185 info->reads_tess_factors = true;
186 break;
187 case nir_intrinsic_bindless_image_load:
188 info->uses_bindless_images = true;
189
190 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
191 info->uses_bindless_buffer_load = true;
192 else
193 info->uses_bindless_image_load = true;
194 break;
195 case nir_intrinsic_bindless_image_size:
196 case nir_intrinsic_bindless_image_samples:
197 info->uses_bindless_images = true;
198 break;
199 case nir_intrinsic_bindless_image_store:
200 info->uses_bindless_images = true;
201
202 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
203 info->uses_bindless_buffer_store = true;
204 else
205 info->uses_bindless_image_store = true;
206
207 info->writes_memory = true;
208 break;
209 case nir_intrinsic_image_deref_store:
210 info->writes_memory = true;
211 break;
212 case nir_intrinsic_bindless_image_atomic_add:
213 case nir_intrinsic_bindless_image_atomic_min:
214 case nir_intrinsic_bindless_image_atomic_max:
215 case nir_intrinsic_bindless_image_atomic_and:
216 case nir_intrinsic_bindless_image_atomic_or:
217 case nir_intrinsic_bindless_image_atomic_xor:
218 case nir_intrinsic_bindless_image_atomic_exchange:
219 case nir_intrinsic_bindless_image_atomic_comp_swap:
220 info->uses_bindless_images = true;
221
222 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
223 info->uses_bindless_buffer_atomic = true;
224 else
225 info->uses_bindless_image_atomic = true;
226
227 info->writes_memory = true;
228 break;
229 case nir_intrinsic_image_deref_atomic_add:
230 case nir_intrinsic_image_deref_atomic_min:
231 case nir_intrinsic_image_deref_atomic_max:
232 case nir_intrinsic_image_deref_atomic_and:
233 case nir_intrinsic_image_deref_atomic_or:
234 case nir_intrinsic_image_deref_atomic_xor:
235 case nir_intrinsic_image_deref_atomic_exchange:
236 case nir_intrinsic_image_deref_atomic_comp_swap:
237 info->writes_memory = true;
238 break;
239 case nir_intrinsic_store_ssbo:
240 case nir_intrinsic_ssbo_atomic_add:
241 case nir_intrinsic_ssbo_atomic_imin:
242 case nir_intrinsic_ssbo_atomic_umin:
243 case nir_intrinsic_ssbo_atomic_imax:
244 case nir_intrinsic_ssbo_atomic_umax:
245 case nir_intrinsic_ssbo_atomic_and:
246 case nir_intrinsic_ssbo_atomic_or:
247 case nir_intrinsic_ssbo_atomic_xor:
248 case nir_intrinsic_ssbo_atomic_exchange:
249 case nir_intrinsic_ssbo_atomic_comp_swap:
250 info->writes_memory = true;
251 break;
252 case nir_intrinsic_load_deref: {
253 nir_variable *var = intrinsic_get_var(intr);
254 nir_variable_mode mode = var->data.mode;
255 enum glsl_base_type base_type =
256 glsl_get_base_type(glsl_without_array(var->type));
257
258 if (mode == nir_var_shader_in) {
259 gather_intrinsic_load_deref_info(nir, intr, var, info);
260
261 switch (var->data.interpolation) {
262 case INTERP_MODE_NONE:
263 if (glsl_base_type_is_integer(base_type))
264 break;
265
266 /* fall-through */
267 case INTERP_MODE_SMOOTH:
268 if (var->data.sample)
269 info->uses_persp_sample = true;
270 else if (var->data.centroid)
271 info->uses_persp_centroid = true;
272 else
273 info->uses_persp_center = true;
274 break;
275
276 case INTERP_MODE_NOPERSPECTIVE:
277 if (var->data.sample)
278 info->uses_linear_sample = true;
279 else if (var->data.centroid)
280 info->uses_linear_centroid = true;
281 else
282 info->uses_linear_center = true;
283 break;
284 }
285 }
286 break;
287 }
288 case nir_intrinsic_interp_deref_at_centroid:
289 case nir_intrinsic_interp_deref_at_sample:
290 case nir_intrinsic_interp_deref_at_offset: {
291 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
292 switch (interp) {
293 case INTERP_MODE_SMOOTH:
294 case INTERP_MODE_NONE:
295 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
296 info->uses_persp_opcode_interp_centroid = true;
297 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
298 info->uses_persp_opcode_interp_sample = true;
299 else
300 info->uses_persp_opcode_interp_offset = true;
301 break;
302 case INTERP_MODE_NOPERSPECTIVE:
303 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
304 info->uses_linear_opcode_interp_centroid = true;
305 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
306 info->uses_linear_opcode_interp_sample = true;
307 else
308 info->uses_linear_opcode_interp_offset = true;
309 break;
310 case INTERP_MODE_FLAT:
311 break;
312 default:
313 unreachable("Unsupported interpoation type");
314 }
315 break;
316 }
317 default:
318 break;
319 }
320 }
321 }
322
323 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
324 struct tgsi_tessctrl_info *out)
325 {
326 memset(out, 0, sizeof(*out));
327
328 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
329 return;
330
331 out->tessfactors_are_def_in_all_invocs =
332 ac_are_tessfactors_def_in_all_invocs(nir);
333 }
334
335 void si_nir_scan_shader(const struct nir_shader *nir,
336 struct tgsi_shader_info *info)
337 {
338 nir_function *func;
339 unsigned i;
340
341 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
342 info->num_tokens = 2; /* indicate that the shader is non-empty */
343 info->num_instructions = 2;
344
345 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
346 pipe_shader_type_from_mesa(nir->info.next_stage);
347
348 if (nir->info.stage == MESA_SHADER_VERTEX) {
349 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
350 nir->info.vs.window_space_position;
351 }
352
353 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
354 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
355 nir->info.tess.tcs_vertices_out;
356 }
357
358 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
359 if (nir->info.tess.primitive_mode == GL_ISOLINES)
360 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
361 else
362 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
363
364 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
365 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
366 PIPE_TESS_SPACING_FRACTIONAL_ODD);
367 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
368 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
369
370 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
371 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
372 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
373 }
374
375 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
376 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
377 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
378 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
379 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
380 }
381
382 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
383 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
384 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
385 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
386
387 if (nir->info.fs.pixel_center_integer) {
388 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
389 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
390 }
391
392 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
393 switch (nir->info.fs.depth_layout) {
394 case FRAG_DEPTH_LAYOUT_ANY:
395 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
396 break;
397 case FRAG_DEPTH_LAYOUT_GREATER:
398 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
399 break;
400 case FRAG_DEPTH_LAYOUT_LESS:
401 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
402 break;
403 case FRAG_DEPTH_LAYOUT_UNCHANGED:
404 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
405 break;
406 default:
407 unreachable("Unknow depth layout");
408 }
409 }
410 }
411
412 if (gl_shader_stage_is_compute(nir->info.stage)) {
413 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
414 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
415 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
416 }
417
418 i = 0;
419 uint64_t processed_inputs = 0;
420 unsigned num_inputs = 0;
421 nir_foreach_variable(variable, &nir->inputs) {
422 unsigned semantic_name, semantic_index;
423
424 const struct glsl_type *type = variable->type;
425 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
426 assert(glsl_type_is_array(type));
427 type = glsl_get_array_element(type);
428 }
429
430 unsigned attrib_count = glsl_count_attribute_slots(type,
431 nir->info.stage == MESA_SHADER_VERTEX);
432
433 i = variable->data.driver_location;
434
435 /* Vertex shader inputs don't have semantics. The state
436 * tracker has already mapped them to attributes via
437 * variable->data.driver_location.
438 */
439 if (nir->info.stage == MESA_SHADER_VERTEX) {
440 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
441 num_inputs++;
442
443 num_inputs++;
444 continue;
445 }
446
447 for (unsigned j = 0; j < attrib_count; j++, i++) {
448
449 if (processed_inputs & ((uint64_t)1 << i))
450 continue;
451
452 processed_inputs |= ((uint64_t)1 << i);
453 num_inputs++;
454
455 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
456 &semantic_name, &semantic_index);
457
458 info->input_semantic_name[i] = semantic_name;
459 info->input_semantic_index[i] = semantic_index;
460
461 if (semantic_name == TGSI_SEMANTIC_PRIMID)
462 info->uses_primid = true;
463
464 if (variable->data.sample)
465 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
466 else if (variable->data.centroid)
467 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
468 else
469 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
470
471 enum glsl_base_type base_type =
472 glsl_get_base_type(glsl_without_array(variable->type));
473
474 switch (variable->data.interpolation) {
475 case INTERP_MODE_NONE:
476 if (glsl_base_type_is_integer(base_type)) {
477 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
478 break;
479 }
480
481 if (semantic_name == TGSI_SEMANTIC_COLOR) {
482 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
483 break;
484 }
485 /* fall-through */
486
487 case INTERP_MODE_SMOOTH:
488 assert(!glsl_base_type_is_integer(base_type));
489
490 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
491 break;
492
493 case INTERP_MODE_NOPERSPECTIVE:
494 assert(!glsl_base_type_is_integer(base_type));
495
496 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
497 break;
498
499 case INTERP_MODE_FLAT:
500 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
501 break;
502 }
503 }
504 }
505
506 info->num_inputs = num_inputs;
507
508
509 i = 0;
510 uint64_t processed_outputs = 0;
511 unsigned num_outputs = 0;
512 nir_foreach_variable(variable, &nir->outputs) {
513 unsigned semantic_name, semantic_index;
514
515 i = variable->data.driver_location;
516
517 const struct glsl_type *type = variable->type;
518 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
519 assert(glsl_type_is_array(type));
520 type = glsl_get_array_element(type);
521 }
522
523 unsigned attrib_count = glsl_count_attribute_slots(type, false);
524 for (unsigned k = 0; k < attrib_count; k++, i++) {
525
526 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
527 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
528 &semantic_name, &semantic_index);
529
530 /* Adjust for dual source blending */
531 if (variable->data.index > 0) {
532 semantic_index++;
533 }
534 } else {
535 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
536 &semantic_name, &semantic_index);
537 }
538
539 unsigned num_components = 4;
540 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
541 if (vector_elements)
542 num_components = vector_elements;
543
544 unsigned component = variable->data.location_frac;
545 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
546 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
547 num_components = (num_components * 2) - 4;
548 component = 0;
549 } else {
550 num_components = MIN2(num_components * 2, 4);
551 }
552 }
553
554 ubyte usagemask = 0;
555 for (unsigned j = component; j < num_components + component; j++) {
556 switch (j) {
557 case 0:
558 usagemask |= TGSI_WRITEMASK_X;
559 break;
560 case 1:
561 usagemask |= TGSI_WRITEMASK_Y;
562 break;
563 case 2:
564 usagemask |= TGSI_WRITEMASK_Z;
565 break;
566 case 3:
567 usagemask |= TGSI_WRITEMASK_W;
568 break;
569 default:
570 unreachable("error calculating component index");
571 }
572 }
573
574 unsigned gs_out_streams;
575 if (variable->data.stream & (1u << 31)) {
576 gs_out_streams = variable->data.stream & ~(1u << 31);
577 } else {
578 assert(variable->data.stream < 4);
579 gs_out_streams = 0;
580 for (unsigned j = 0; j < num_components; ++j)
581 gs_out_streams |= variable->data.stream << (2 * (component + j));
582 }
583
584 unsigned streamx = gs_out_streams & 3;
585 unsigned streamy = (gs_out_streams >> 2) & 3;
586 unsigned streamz = (gs_out_streams >> 4) & 3;
587 unsigned streamw = (gs_out_streams >> 6) & 3;
588
589 if (usagemask & TGSI_WRITEMASK_X) {
590 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
591 info->output_streams[i] |= streamx;
592 info->num_stream_output_components[streamx]++;
593 }
594 if (usagemask & TGSI_WRITEMASK_Y) {
595 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
596 info->output_streams[i] |= streamy << 2;
597 info->num_stream_output_components[streamy]++;
598 }
599 if (usagemask & TGSI_WRITEMASK_Z) {
600 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
601 info->output_streams[i] |= streamz << 4;
602 info->num_stream_output_components[streamz]++;
603 }
604 if (usagemask & TGSI_WRITEMASK_W) {
605 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
606 info->output_streams[i] |= streamw << 6;
607 info->num_stream_output_components[streamw]++;
608 }
609
610 /* make sure we only count this location once against
611 * the num_outputs counter.
612 */
613 if (processed_outputs & ((uint64_t)1 << i))
614 continue;
615
616 processed_outputs |= ((uint64_t)1 << i);
617 num_outputs++;
618
619 info->output_semantic_name[i] = semantic_name;
620 info->output_semantic_index[i] = semantic_index;
621
622 switch (semantic_name) {
623 case TGSI_SEMANTIC_PRIMID:
624 info->writes_primid = true;
625 break;
626 case TGSI_SEMANTIC_VIEWPORT_INDEX:
627 info->writes_viewport_index = true;
628 break;
629 case TGSI_SEMANTIC_LAYER:
630 info->writes_layer = true;
631 break;
632 case TGSI_SEMANTIC_PSIZE:
633 info->writes_psize = true;
634 break;
635 case TGSI_SEMANTIC_CLIPVERTEX:
636 info->writes_clipvertex = true;
637 break;
638 case TGSI_SEMANTIC_COLOR:
639 info->colors_written |= 1 << semantic_index;
640 break;
641 case TGSI_SEMANTIC_STENCIL:
642 info->writes_stencil = true;
643 break;
644 case TGSI_SEMANTIC_SAMPLEMASK:
645 info->writes_samplemask = true;
646 break;
647 case TGSI_SEMANTIC_EDGEFLAG:
648 info->writes_edgeflag = true;
649 break;
650 case TGSI_SEMANTIC_POSITION:
651 if (info->processor == PIPE_SHADER_FRAGMENT)
652 info->writes_z = true;
653 else
654 info->writes_position = true;
655 break;
656 }
657
658 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
659 switch (semantic_name) {
660 case TGSI_SEMANTIC_PATCH:
661 info->reads_perpatch_outputs = true;
662 break;
663 case TGSI_SEMANTIC_TESSINNER:
664 case TGSI_SEMANTIC_TESSOUTER:
665 info->reads_tessfactor_outputs = true;
666 break;
667 default:
668 info->reads_pervertex_outputs = true;
669 }
670 }
671 }
672
673 unsigned loc = variable->data.location;
674 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
675 loc == FRAG_RESULT_COLOR &&
676 nir->info.outputs_written & (1ull << loc)) {
677 assert(attrib_count == 1);
678 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
679 }
680 }
681
682 info->num_outputs = num_outputs;
683
684 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
685 _mesa_key_pointer_equal);
686 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
687 _mesa_key_pointer_equal);
688
689 /* Intialise const_file_max[0] */
690 info->const_file_max[0] = -1;
691
692 /* The first 8 are reserved for atomic counters using ssbo */
693 unsigned ssbo_idx = 8;
694
695 unsigned ubo_idx = 1;
696 nir_foreach_variable(variable, &nir->uniforms) {
697 const struct glsl_type *type = variable->type;
698 enum glsl_base_type base_type =
699 glsl_get_base_type(glsl_without_array(type));
700 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
701 unsigned loc = variable->data.driver_location / 4;
702 int slot_count = glsl_count_attribute_slots(type, false);
703 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
704
705 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
706 * really use the mask (other than ubo_idx == 1 for regular
707 * uniforms) its really only used for getting the buffer count
708 * so we don't need to worry about the ordering.
709 */
710 if (variable->interface_type != NULL) {
711 if (variable->data.mode == nir_var_uniform ||
712 variable->data.mode == nir_var_mem_ubo ||
713 variable->data.mode == nir_var_mem_ssbo) {
714
715 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
716 ssbo_set : ubo_set;
717
718 unsigned block_count;
719 if (base_type != GLSL_TYPE_INTERFACE) {
720 struct set_entry *entry =
721 _mesa_set_search(buf_set, variable->interface_type);
722
723 /* Check if we have already processed
724 * a member from this ubo.
725 */
726 if (entry)
727 continue;
728
729 block_count = 1;
730 } else {
731 block_count = aoa_size;
732 }
733
734 if (variable->data.mode == nir_var_uniform ||
735 variable->data.mode == nir_var_mem_ubo) {
736 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
737 ubo_idx += block_count;
738 } else {
739 assert(variable->data.mode == nir_var_mem_ssbo);
740
741 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
742 ssbo_idx += block_count;
743 }
744
745 _mesa_set_add(buf_set, variable->interface_type);
746 }
747
748 continue;
749 }
750
751 /* We rely on the fact that nir_lower_samplers_as_deref has
752 * eliminated struct dereferences.
753 */
754 if (base_type == GLSL_TYPE_SAMPLER) {
755 if (variable->data.bindless) {
756 info->const_buffers_declared |= 1;
757 info->const_file_max[0] = max_slot;
758 } else {
759 info->samplers_declared |=
760 u_bit_consecutive(variable->data.binding, aoa_size);
761 }
762 } else if (base_type == GLSL_TYPE_IMAGE) {
763 if (variable->data.bindless) {
764 info->const_buffers_declared |= 1;
765 info->const_file_max[0] = max_slot;
766 } else {
767 info->images_declared |=
768 u_bit_consecutive(variable->data.binding, aoa_size);
769 }
770 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
771 info->const_buffers_declared |= 1;
772 info->const_file_max[0] = max_slot;
773 }
774 }
775
776 _mesa_set_destroy(ubo_set, NULL);
777 _mesa_set_destroy(ssbo_set, NULL);
778
779 info->num_written_clipdistance = nir->info.clip_distance_array_size;
780 info->num_written_culldistance = nir->info.cull_distance_array_size;
781 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
782 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
783
784 if (info->processor == PIPE_SHADER_FRAGMENT)
785 info->uses_kill = nir->info.fs.uses_discard;
786
787 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
788 nir_foreach_block(block, func->impl) {
789 nir_foreach_instr(instr, block)
790 scan_instruction(nir, info, instr);
791 }
792 }
793
794 void
795 si_nir_opts(struct nir_shader *nir)
796 {
797 bool progress;
798 unsigned lower_flrp =
799 (nir->options->lower_flrp16 ? 16 : 0) |
800 (nir->options->lower_flrp32 ? 32 : 0) |
801 (nir->options->lower_flrp64 ? 64 : 0);
802
803 do {
804 progress = false;
805
806 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
807
808 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
809 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
810
811 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
812 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
813
814 /* (Constant) copy propagation is needed for txf with offsets. */
815 NIR_PASS(progress, nir, nir_copy_prop);
816 NIR_PASS(progress, nir, nir_opt_remove_phis);
817 NIR_PASS(progress, nir, nir_opt_dce);
818 if (nir_opt_trivial_continues(nir)) {
819 progress = true;
820 NIR_PASS(progress, nir, nir_copy_prop);
821 NIR_PASS(progress, nir, nir_opt_dce);
822 }
823 NIR_PASS(progress, nir, nir_opt_if, true);
824 NIR_PASS(progress, nir, nir_opt_dead_cf);
825 NIR_PASS(progress, nir, nir_opt_cse);
826 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
827
828 /* Needed for algebraic lowering */
829 NIR_PASS(progress, nir, nir_opt_algebraic);
830 NIR_PASS(progress, nir, nir_opt_constant_folding);
831
832 if (lower_flrp != 0) {
833 bool lower_flrp_progress = false;
834
835 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
836 lower_flrp,
837 false /* always_precise */,
838 nir->options->lower_ffma);
839 if (lower_flrp_progress) {
840 NIR_PASS(progress, nir,
841 nir_opt_constant_folding);
842 progress = true;
843 }
844
845 /* Nothing should rematerialize any flrps, so we only
846 * need to do this lowering once.
847 */
848 lower_flrp = 0;
849 }
850
851 NIR_PASS(progress, nir, nir_opt_undef);
852 NIR_PASS(progress, nir, nir_opt_conditional_discard);
853 if (nir->options->max_unroll_iterations) {
854 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
855 }
856 } while (progress);
857 }
858
859 /**
860 * Perform "lowering" operations on the NIR that are run once when the shader
861 * selector is created.
862 */
863 void
864 si_lower_nir(struct si_shader_selector* sel)
865 {
866 /* Adjust the driver location of inputs and outputs. The state tracker
867 * interprets them as slots, while the ac/nir backend interprets them
868 * as individual components.
869 */
870 nir_foreach_variable(variable, &sel->nir->inputs)
871 variable->data.driver_location *= 4;
872
873 nir_foreach_variable(variable, &sel->nir->outputs) {
874 variable->data.driver_location *= 4;
875
876 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
877 if (variable->data.location == FRAG_RESULT_DEPTH)
878 variable->data.driver_location += 2;
879 else if (variable->data.location == FRAG_RESULT_STENCIL)
880 variable->data.driver_location += 1;
881 }
882 }
883
884 /* Perform lowerings (and optimizations) of code.
885 *
886 * Performance considerations aside, we must:
887 * - lower certain ALU operations
888 * - ensure constant offsets for texture instructions are folded
889 * and copy-propagated
890 */
891
892 static const struct nir_lower_tex_options lower_tex_options = {
893 .lower_txp = ~0u,
894 };
895 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
896
897 const nir_lower_subgroups_options subgroups_options = {
898 .subgroup_size = 64,
899 .ballot_bit_size = 64,
900 .lower_to_scalar = true,
901 .lower_subgroup_masks = true,
902 .lower_vote_trivial = false,
903 .lower_vote_eq_to_ballot = true,
904 };
905 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
906
907 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
908
909 si_nir_opts(sel->nir);
910
911 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
912
913 /* Strip the resulting shader so that the shader cache is more likely
914 * to hit from other similar shaders.
915 */
916 nir_strip(sel->nir);
917 }
918
919 static void declare_nir_input_vs(struct si_shader_context *ctx,
920 struct nir_variable *variable,
921 unsigned input_index,
922 LLVMValueRef out[4])
923 {
924 si_llvm_load_input_vs(ctx, input_index, out);
925 }
926
927 static void declare_nir_input_fs(struct si_shader_context *ctx,
928 struct nir_variable *variable,
929 unsigned input_index,
930 LLVMValueRef out[4])
931 {
932 unsigned slot = variable->data.location;
933 if (slot == VARYING_SLOT_POS) {
934 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
935 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
936 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
937 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
938 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
939 return;
940 }
941
942 si_llvm_load_input_fs(ctx, input_index, out);
943 }
944
945 LLVMValueRef
946 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
947 enum glsl_interp_mode interp, unsigned location)
948 {
949 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
950 int interp_param_idx = -1;
951
952 switch (interp) {
953 case INTERP_MODE_FLAT:
954 return NULL;
955 case INTERP_MODE_SMOOTH:
956 case INTERP_MODE_NONE:
957 if (location == INTERP_CENTER)
958 interp_param_idx = SI_PARAM_PERSP_CENTER;
959 else if (location == INTERP_CENTROID)
960 interp_param_idx = SI_PARAM_PERSP_CENTROID;
961 else if (location == INTERP_SAMPLE)
962 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
963 break;
964 case INTERP_MODE_NOPERSPECTIVE:
965 if (location == INTERP_CENTER)
966 interp_param_idx = SI_PARAM_LINEAR_CENTER;
967 else if (location == INTERP_CENTROID)
968 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
969 else if (location == INTERP_SAMPLE)
970 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
971 break;
972 default:
973 assert(!"Unhandled interpolation mode.");
974 return NULL;
975 }
976
977 return interp_param_idx != -1 ?
978 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
979 }
980
981 static LLVMValueRef
982 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
983 unsigned descriptor_set, unsigned base_index,
984 unsigned constant_index, LLVMValueRef dynamic_index,
985 enum ac_descriptor_type desc_type, bool image,
986 bool write, bool bindless)
987 {
988 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
989 LLVMBuilderRef builder = ctx->ac.builder;
990 unsigned const_index = base_index + constant_index;
991 bool dcc_off = write;
992
993 assert(!descriptor_set);
994 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
995
996 if (bindless) {
997 LLVMValueRef list =
998 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
999
1000 /* dynamic_index is the bindless handle */
1001 if (image) {
1002 /* For simplicity, bindless image descriptors use fixed
1003 * 16-dword slots for now.
1004 */
1005 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1006 LLVMConstInt(ctx->i64, 2, 0), "");
1007
1008 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1009 dcc_off, true);
1010 }
1011
1012 /* Since bindless handle arithmetic can contain an unsigned integer
1013 * wraparound and si_load_sampler_desc assumes there isn't any,
1014 * use GEP without "inbounds" (inside ac_build_pointer_add)
1015 * to prevent incorrect code generation and hangs.
1016 */
1017 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1018 LLVMConstInt(ctx->i64, 2, 0), "");
1019 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1020 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1021 }
1022
1023 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1024 assert(const_index < num_slots);
1025
1026 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1027 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1028
1029 if (dynamic_index) {
1030 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1031
1032 /* From the GL_ARB_shader_image_load_store extension spec:
1033 *
1034 * If a shader performs an image load, store, or atomic
1035 * operation using an image variable declared as an array,
1036 * and if the index used to select an individual element is
1037 * negative or greater than or equal to the size of the
1038 * array, the results of the operation are undefined but may
1039 * not lead to termination.
1040 */
1041 index = si_llvm_bound_index(ctx, index, num_slots);
1042 }
1043
1044 if (image) {
1045 index = LLVMBuildSub(ctx->ac.builder,
1046 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1047 index, "");
1048 return si_load_image_desc(ctx, list, index, desc_type, dcc_off, false);
1049 }
1050
1051 index = LLVMBuildAdd(ctx->ac.builder, index,
1052 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1053 return si_load_sampler_desc(ctx, list, index, desc_type);
1054 }
1055
1056 static void bitcast_inputs(struct si_shader_context *ctx,
1057 LLVMValueRef data[4],
1058 unsigned input_idx)
1059 {
1060 for (unsigned chan = 0; chan < 4; chan++) {
1061 ctx->inputs[input_idx + chan] =
1062 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1063 }
1064 }
1065
1066 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1067 {
1068 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1069
1070 if (nir->info.stage == MESA_SHADER_VERTEX ||
1071 nir->info.stage == MESA_SHADER_FRAGMENT) {
1072 uint64_t processed_inputs = 0;
1073 nir_foreach_variable(variable, &nir->inputs) {
1074 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1075 nir->info.stage == MESA_SHADER_VERTEX);
1076 unsigned input_idx = variable->data.driver_location;
1077
1078 LLVMValueRef data[4];
1079 unsigned loc = variable->data.location;
1080
1081 if (loc >= VARYING_SLOT_VAR0 && nir->info.stage == MESA_SHADER_FRAGMENT)
1082 ctx->abi.fs_input_attr_indices[loc - VARYING_SLOT_VAR0] = input_idx / 4;
1083
1084 for (unsigned i = 0; i < attrib_count; i++) {
1085 /* Packed components share the same location so skip
1086 * them if we have already processed the location.
1087 */
1088 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1089 input_idx += 4;
1090 continue;
1091 }
1092
1093 if (nir->info.stage == MESA_SHADER_VERTEX) {
1094 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1095 bitcast_inputs(ctx, data, input_idx);
1096 if (glsl_type_is_dual_slot(variable->type)) {
1097 input_idx += 4;
1098 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1099 bitcast_inputs(ctx, data, input_idx);
1100 }
1101 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1102 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
1103 bitcast_inputs(ctx, data, input_idx);
1104 }
1105
1106 processed_inputs |= ((uint64_t)1 << (loc + i));
1107 input_idx += 4;
1108 }
1109 }
1110 }
1111
1112 ctx->abi.inputs = &ctx->inputs[0];
1113 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1114 ctx->abi.clamp_shadow_reference = true;
1115
1116 ctx->num_samplers = util_last_bit(info->samplers_declared);
1117 ctx->num_images = util_last_bit(info->images_declared);
1118
1119 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1120 assert(gl_shader_stage_is_compute(nir->info.stage));
1121 si_declare_compute_memory(ctx);
1122 }
1123 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1124
1125 return true;
1126 }