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radeonsi: add support for Raven2 (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 static unsigned si_map_swizzle(unsigned swizzle)
38 {
39 switch (swizzle) {
40 case PIPE_SWIZZLE_Y:
41 return V_008F0C_SQ_SEL_Y;
42 case PIPE_SWIZZLE_Z:
43 return V_008F0C_SQ_SEL_Z;
44 case PIPE_SWIZZLE_W:
45 return V_008F0C_SQ_SEL_W;
46 case PIPE_SWIZZLE_0:
47 return V_008F0C_SQ_SEL_0;
48 case PIPE_SWIZZLE_1:
49 return V_008F0C_SQ_SEL_1;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X;
52 }
53 }
54
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x)
57 {
58 return x <= 0 ? 0 :
59 x >= 4096 ? 0xffff : x * 16;
60 }
61
62 /*
63 * Inferred framebuffer and blender state.
64 *
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
67 */
68 static void si_emit_cb_render_state(struct si_context *sctx)
69 {
70 struct radeon_cmdbuf *cs = sctx->gfx_cs;
71 struct si_state_blend *blend = sctx->queued.named.blend;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
75 unsigned i;
76
77 if (blend)
78 cb_target_mask &= blend->cb_target_mask;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend && blend->dual_src_blend &&
87 sctx->ps_shader.cso &&
88 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
89 cb_target_mask = 0;
90
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
93 */
94 if (sctx->screen->dfsm_allowed &&
95 sctx->last_cb_target_mask != cb_target_mask) {
96 sctx->last_cb_target_mask = cb_target_mask;
97
98 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
99 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
100 }
101
102 unsigned initial_cdw = cs->current.cdw;
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
104 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
105
106 if (sctx->chip_class >= VI) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
110 */
111 bool oc_disable = (sctx->chip_class == VI ||
112 sctx->chip_class == GFX9) &&
113 blend &&
114 blend->blend_enable_4bit & cb_target_mask &&
115 sctx->framebuffer.nr_samples >= 2;
116 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
117
118 radeon_opt_set_context_reg(
119 sctx, R_028424_CB_DCC_CONTROL,
120 SI_TRACKED_CB_DCC_CONTROL,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->family == CHIP_RAVEN2));
125 }
126
127 /* RB+ register settings. */
128 if (sctx->screen->rbplus_allowed) {
129 unsigned spi_shader_col_format =
130 sctx->ps_shader.cso ?
131 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
132 unsigned sx_ps_downconvert = 0;
133 unsigned sx_blend_opt_epsilon = 0;
134 unsigned sx_blend_opt_control = 0;
135
136 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
137 struct si_surface *surf =
138 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
139 unsigned format, swap, spi_format, colormask;
140 bool has_alpha, has_rgb;
141
142 if (!surf)
143 continue;
144
145 format = G_028C70_FORMAT(surf->cb_color_info);
146 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
147 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
148 colormask = (cb_target_mask >> (i * 4)) & 0xf;
149
150 /* Set if RGB and A are present. */
151 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
152
153 if (format == V_028C70_COLOR_8 ||
154 format == V_028C70_COLOR_16 ||
155 format == V_028C70_COLOR_32)
156 has_rgb = !has_alpha;
157 else
158 has_rgb = true;
159
160 /* Check the colormask and export format. */
161 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
162 has_rgb = false;
163 if (!(colormask & PIPE_MASK_A))
164 has_alpha = false;
165
166 if (spi_format == V_028714_SPI_SHADER_ZERO) {
167 has_rgb = false;
168 has_alpha = false;
169 }
170
171 /* Disable value checking for disabled channels. */
172 if (!has_rgb)
173 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
174 if (!has_alpha)
175 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
176
177 /* Enable down-conversion for 32bpp and smaller formats. */
178 switch (format) {
179 case V_028C70_COLOR_8:
180 case V_028C70_COLOR_8_8:
181 case V_028C70_COLOR_8_8_8_8:
182 /* For 1 and 2-channel formats, use the superset thereof. */
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
185 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_5_6_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_1_5_5_5:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_4_4_4_4:
206 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
208 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
209 }
210 break;
211
212 case V_028C70_COLOR_32:
213 if (swap == V_028C70_SWAP_STD &&
214 spi_format == V_028714_SPI_SHADER_32_R)
215 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
216 else if (swap == V_028C70_SWAP_ALT_REV &&
217 spi_format == V_028714_SPI_SHADER_32_AR)
218 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
219 break;
220
221 case V_028C70_COLOR_16:
222 case V_028C70_COLOR_16_16:
223 /* For 1-channel formats, use the superset thereof. */
224 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
227 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
228 if (swap == V_028C70_SWAP_STD ||
229 swap == V_028C70_SWAP_STD_REV)
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
231 else
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_10_11_11:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
240 }
241 break;
242
243 case V_028C70_COLOR_2_10_10_10:
244 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
246 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
247 }
248 break;
249 }
250 }
251
252 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
253 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
254 SI_TRACKED_SX_PS_DOWNCONVERT,
255 sx_ps_downconvert, sx_blend_opt_epsilon,
256 sx_blend_opt_control);
257 }
258 if (initial_cdw != cs->current.cdw)
259 sctx->context_roll_counter++;
260 }
261
262 /*
263 * Blender functions
264 */
265
266 static uint32_t si_translate_blend_function(int blend_func)
267 {
268 switch (blend_func) {
269 case PIPE_BLEND_ADD:
270 return V_028780_COMB_DST_PLUS_SRC;
271 case PIPE_BLEND_SUBTRACT:
272 return V_028780_COMB_SRC_MINUS_DST;
273 case PIPE_BLEND_REVERSE_SUBTRACT:
274 return V_028780_COMB_DST_MINUS_SRC;
275 case PIPE_BLEND_MIN:
276 return V_028780_COMB_MIN_DST_SRC;
277 case PIPE_BLEND_MAX:
278 return V_028780_COMB_MAX_DST_SRC;
279 default:
280 PRINT_ERR("Unknown blend function %d\n", blend_func);
281 assert(0);
282 break;
283 }
284 return 0;
285 }
286
287 static uint32_t si_translate_blend_factor(int blend_fact)
288 {
289 switch (blend_fact) {
290 case PIPE_BLENDFACTOR_ONE:
291 return V_028780_BLEND_ONE;
292 case PIPE_BLENDFACTOR_SRC_COLOR:
293 return V_028780_BLEND_SRC_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA:
295 return V_028780_BLEND_SRC_ALPHA;
296 case PIPE_BLENDFACTOR_DST_ALPHA:
297 return V_028780_BLEND_DST_ALPHA;
298 case PIPE_BLENDFACTOR_DST_COLOR:
299 return V_028780_BLEND_DST_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
301 return V_028780_BLEND_SRC_ALPHA_SATURATE;
302 case PIPE_BLENDFACTOR_CONST_COLOR:
303 return V_028780_BLEND_CONSTANT_COLOR;
304 case PIPE_BLENDFACTOR_CONST_ALPHA:
305 return V_028780_BLEND_CONSTANT_ALPHA;
306 case PIPE_BLENDFACTOR_ZERO:
307 return V_028780_BLEND_ZERO;
308 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
309 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
310 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
311 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
312 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_COLOR:
315 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
316 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_SRC1_COLOR:
321 return V_028780_BLEND_SRC1_COLOR;
322 case PIPE_BLENDFACTOR_SRC1_ALPHA:
323 return V_028780_BLEND_SRC1_ALPHA;
324 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
325 return V_028780_BLEND_INV_SRC1_COLOR;
326 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
327 return V_028780_BLEND_INV_SRC1_ALPHA;
328 default:
329 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
330 assert(0);
331 break;
332 }
333 return 0;
334 }
335
336 static uint32_t si_translate_blend_opt_function(int blend_func)
337 {
338 switch (blend_func) {
339 case PIPE_BLEND_ADD:
340 return V_028760_OPT_COMB_ADD;
341 case PIPE_BLEND_SUBTRACT:
342 return V_028760_OPT_COMB_SUBTRACT;
343 case PIPE_BLEND_REVERSE_SUBTRACT:
344 return V_028760_OPT_COMB_REVSUBTRACT;
345 case PIPE_BLEND_MIN:
346 return V_028760_OPT_COMB_MIN;
347 case PIPE_BLEND_MAX:
348 return V_028760_OPT_COMB_MAX;
349 default:
350 return V_028760_OPT_COMB_BLEND_DISABLED;
351 }
352 }
353
354 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
355 {
356 switch (blend_fact) {
357 case PIPE_BLENDFACTOR_ZERO:
358 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
359 case PIPE_BLENDFACTOR_ONE:
360 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
361 case PIPE_BLENDFACTOR_SRC_COLOR:
362 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
363 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
364 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
365 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
366 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
367 case PIPE_BLENDFACTOR_SRC_ALPHA:
368 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
369 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
371 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
372 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
373 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
374 default:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
376 }
377 }
378
379 static void si_blend_check_commutativity(struct si_screen *sscreen,
380 struct si_state_blend *blend,
381 enum pipe_blend_func func,
382 enum pipe_blendfactor src,
383 enum pipe_blendfactor dst,
384 unsigned chanmask)
385 {
386 /* Src factor is allowed when it does not depend on Dst */
387 static const uint32_t src_allowed =
388 (1u << PIPE_BLENDFACTOR_ONE) |
389 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
392 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
393 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
394 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
395 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
396 (1u << PIPE_BLENDFACTOR_ZERO) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
399 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
401 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
403
404 if (dst == PIPE_BLENDFACTOR_ONE &&
405 (src_allowed & (1u << src))) {
406 /* Addition is commutative, but floating point addition isn't
407 * associative: subtle changes can be introduced via different
408 * rounding.
409 *
410 * Out-of-order is also non-deterministic, which means that
411 * this breaks OpenGL invariance requirements. So only enable
412 * out-of-order additive blending if explicitly allowed by a
413 * setting.
414 */
415 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
416 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
417 blend->commutative_4bit |= chanmask;
418 }
419 }
420
421 /**
422 * Get rid of DST in the blend factors by commuting the operands:
423 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
424 */
425 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
426 unsigned *dst_factor, unsigned expected_dst,
427 unsigned replacement_src)
428 {
429 if (*src_factor == expected_dst &&
430 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
431 *src_factor = PIPE_BLENDFACTOR_ZERO;
432 *dst_factor = replacement_src;
433
434 /* Commuting the operands requires reversing subtractions. */
435 if (*func == PIPE_BLEND_SUBTRACT)
436 *func = PIPE_BLEND_REVERSE_SUBTRACT;
437 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
438 *func = PIPE_BLEND_SUBTRACT;
439 }
440 }
441
442 static bool si_blend_factor_uses_dst(unsigned factor)
443 {
444 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
445 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
446 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
447 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
448 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
449 }
450
451 static void *si_create_blend_state_mode(struct pipe_context *ctx,
452 const struct pipe_blend_state *state,
453 unsigned mode)
454 {
455 struct si_context *sctx = (struct si_context*)ctx;
456 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
457 struct si_pm4_state *pm4 = &blend->pm4;
458 uint32_t sx_mrt_blend_opt[8] = {0};
459 uint32_t color_control = 0;
460
461 if (!blend)
462 return NULL;
463
464 blend->alpha_to_coverage = state->alpha_to_coverage;
465 blend->alpha_to_one = state->alpha_to_one;
466 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
467 blend->logicop_enable = state->logicop_enable;
468
469 if (state->logicop_enable) {
470 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
471 } else {
472 color_control |= S_028808_ROP3(0xcc);
473 }
474
475 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
476 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
477 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
478 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
479 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
480 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
481
482 if (state->alpha_to_coverage)
483 blend->need_src_alpha_4bit |= 0xf;
484
485 blend->cb_target_mask = 0;
486 blend->cb_target_enabled_4bit = 0;
487
488 for (int i = 0; i < 8; i++) {
489 /* state->rt entries > 0 only written if independent blending */
490 const int j = state->independent_blend_enable ? i : 0;
491
492 unsigned eqRGB = state->rt[j].rgb_func;
493 unsigned srcRGB = state->rt[j].rgb_src_factor;
494 unsigned dstRGB = state->rt[j].rgb_dst_factor;
495 unsigned eqA = state->rt[j].alpha_func;
496 unsigned srcA = state->rt[j].alpha_src_factor;
497 unsigned dstA = state->rt[j].alpha_dst_factor;
498
499 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
500 unsigned blend_cntl = 0;
501
502 sx_mrt_blend_opt[i] =
503 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
504 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
505
506 /* Only set dual source blending for MRT0 to avoid a hang. */
507 if (i >= 1 && blend->dual_src_blend) {
508 /* Vulkan does this for dual source blending. */
509 if (i == 1)
510 blend_cntl |= S_028780_ENABLE(1);
511
512 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
513 continue;
514 }
515
516 /* Only addition and subtraction equations are supported with
517 * dual source blending.
518 */
519 if (blend->dual_src_blend &&
520 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
521 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
522 assert(!"Unsupported equation for dual source blending");
523 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
524 continue;
525 }
526
527 /* cb_render_state will disable unused ones */
528 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
529 if (state->rt[j].colormask)
530 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
531
532 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
533 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
534 continue;
535 }
536
537 si_blend_check_commutativity(sctx->screen, blend,
538 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
539 si_blend_check_commutativity(sctx->screen, blend,
540 eqA, srcA, dstA, 0x8 << (4 * i));
541
542 /* Blending optimizations for RB+.
543 * These transformations don't change the behavior.
544 *
545 * First, get rid of DST in the blend factors:
546 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
547 */
548 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
549 PIPE_BLENDFACTOR_DST_COLOR,
550 PIPE_BLENDFACTOR_SRC_COLOR);
551 si_blend_remove_dst(&eqA, &srcA, &dstA,
552 PIPE_BLENDFACTOR_DST_COLOR,
553 PIPE_BLENDFACTOR_SRC_COLOR);
554 si_blend_remove_dst(&eqA, &srcA, &dstA,
555 PIPE_BLENDFACTOR_DST_ALPHA,
556 PIPE_BLENDFACTOR_SRC_ALPHA);
557
558 /* Look up the ideal settings from tables. */
559 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
560 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
561 srcA_opt = si_translate_blend_opt_factor(srcA, true);
562 dstA_opt = si_translate_blend_opt_factor(dstA, true);
563
564 /* Handle interdependencies. */
565 if (si_blend_factor_uses_dst(srcRGB))
566 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
567 if (si_blend_factor_uses_dst(srcA))
568 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
569
570 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
571 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
572 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
573 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
574 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
575
576 /* Set the final value. */
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
579 S_028760_COLOR_DST_OPT(dstRGB_opt) |
580 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
581 S_028760_ALPHA_SRC_OPT(srcA_opt) |
582 S_028760_ALPHA_DST_OPT(dstA_opt) |
583 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
584
585 /* Set blend state. */
586 blend_cntl |= S_028780_ENABLE(1);
587 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
588 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
589 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
590
591 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
592 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
593 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
594 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
595 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
596 }
597 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
598
599 blend->blend_enable_4bit |= 0xfu << (i * 4);
600
601 /* This is only important for formats without alpha. */
602 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
603 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
604 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
605 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
606 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
607 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
608 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
609 }
610
611 if (blend->cb_target_mask) {
612 color_control |= S_028808_MODE(mode);
613 } else {
614 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
615 }
616
617 if (sctx->screen->rbplus_allowed) {
618 /* Disable RB+ blend optimizations for dual source blending.
619 * Vulkan does this.
620 */
621 if (blend->dual_src_blend) {
622 for (int i = 0; i < 8; i++) {
623 sx_mrt_blend_opt[i] =
624 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
625 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
626 }
627 }
628
629 for (int i = 0; i < 8; i++)
630 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
631 sx_mrt_blend_opt[i]);
632
633 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
634 if (blend->dual_src_blend || state->logicop_enable ||
635 mode == V_028808_CB_RESOLVE)
636 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
637 }
638
639 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
640 return blend;
641 }
642
643 static void *si_create_blend_state(struct pipe_context *ctx,
644 const struct pipe_blend_state *state)
645 {
646 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
647 }
648
649 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
650 {
651 struct si_context *sctx = (struct si_context *)ctx;
652 struct si_state_blend *old_blend = sctx->queued.named.blend;
653 struct si_state_blend *blend = (struct si_state_blend *)state;
654
655 if (!state)
656 return;
657
658 si_pm4_bind_state(sctx, blend, state);
659
660 if (!old_blend ||
661 old_blend->cb_target_mask != blend->cb_target_mask ||
662 old_blend->dual_src_blend != blend->dual_src_blend ||
663 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
664 sctx->framebuffer.nr_samples >= 2 &&
665 sctx->screen->dcc_msaa_allowed))
666 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
667
668 if (!old_blend ||
669 old_blend->cb_target_mask != blend->cb_target_mask ||
670 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
671 old_blend->alpha_to_one != blend->alpha_to_one ||
672 old_blend->dual_src_blend != blend->dual_src_blend ||
673 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
674 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
675 sctx->do_update_shaders = true;
676
677 if (sctx->screen->dpbb_allowed &&
678 (!old_blend ||
679 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
680 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
681 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
682 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
683
684 if (sctx->screen->has_out_of_order_rast &&
685 (!old_blend ||
686 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
687 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
688 old_blend->commutative_4bit != blend->commutative_4bit ||
689 old_blend->logicop_enable != blend->logicop_enable)))
690 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
691 }
692
693 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
694 {
695 struct si_context *sctx = (struct si_context *)ctx;
696 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
697 }
698
699 static void si_set_blend_color(struct pipe_context *ctx,
700 const struct pipe_blend_color *state)
701 {
702 struct si_context *sctx = (struct si_context *)ctx;
703 static const struct pipe_blend_color zeros;
704
705 sctx->blend_color.state = *state;
706 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
707 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
708 }
709
710 static void si_emit_blend_color(struct si_context *sctx)
711 {
712 struct radeon_cmdbuf *cs = sctx->gfx_cs;
713
714 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
715 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
716 }
717
718 /*
719 * Clipping
720 */
721
722 static void si_set_clip_state(struct pipe_context *ctx,
723 const struct pipe_clip_state *state)
724 {
725 struct si_context *sctx = (struct si_context *)ctx;
726 struct pipe_constant_buffer cb;
727 static const struct pipe_clip_state zeros;
728
729 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
730 return;
731
732 sctx->clip_state.state = *state;
733 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
734 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
735
736 cb.buffer = NULL;
737 cb.user_buffer = state->ucp;
738 cb.buffer_offset = 0;
739 cb.buffer_size = 4*4*8;
740 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
741 pipe_resource_reference(&cb.buffer, NULL);
742 }
743
744 static void si_emit_clip_state(struct si_context *sctx)
745 {
746 struct radeon_cmdbuf *cs = sctx->gfx_cs;
747
748 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
749 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
750 }
751
752 static void si_emit_clip_regs(struct si_context *sctx)
753 {
754 struct si_shader *vs = si_get_vs_state(sctx);
755 struct si_shader_selector *vs_sel = vs->selector;
756 struct tgsi_shader_info *info = &vs_sel->info;
757 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
758 unsigned window_space =
759 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
760 unsigned clipdist_mask = vs_sel->clipdist_mask;
761 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
762 unsigned culldist_mask = vs_sel->culldist_mask;
763 unsigned total_mask;
764
765 if (vs->key.opt.clip_disable) {
766 assert(!info->culldist_writemask);
767 clipdist_mask = 0;
768 culldist_mask = 0;
769 }
770 total_mask = clipdist_mask | culldist_mask;
771
772 /* Clip distances on points have no effect, so need to be implemented
773 * as cull distances. This applies for the clipvertex case as well.
774 *
775 * Setting this for primitives other than points should have no adverse
776 * effects.
777 */
778 clipdist_mask &= rs->clip_plane_enable;
779 culldist_mask |= clipdist_mask;
780
781 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
782 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
783 SI_TRACKED_PA_CL_VS_OUT_CNTL,
784 vs_sel->pa_cl_vs_out_cntl |
785 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
786 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
787 clipdist_mask | (culldist_mask << 8));
788 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
789 SI_TRACKED_PA_CL_CLIP_CNTL,
790 rs->pa_cl_clip_cntl |
791 ucp_mask |
792 S_028810_CLIP_DISABLE(window_space));
793
794 if (initial_cdw != sctx->gfx_cs->current.cdw)
795 sctx->context_roll_counter++;
796 }
797
798 /*
799 * inferred state between framebuffer and rasterizer
800 */
801 static void si_update_poly_offset_state(struct si_context *sctx)
802 {
803 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
804
805 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
806 si_pm4_bind_state(sctx, poly_offset, NULL);
807 return;
808 }
809
810 /* Use the user format, not db_render_format, so that the polygon
811 * offset behaves as expected by applications.
812 */
813 switch (sctx->framebuffer.state.zsbuf->texture->format) {
814 case PIPE_FORMAT_Z16_UNORM:
815 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
816 break;
817 default: /* 24-bit */
818 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
819 break;
820 case PIPE_FORMAT_Z32_FLOAT:
821 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
822 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
823 break;
824 }
825 }
826
827 /*
828 * Rasterizer
829 */
830
831 static uint32_t si_translate_fill(uint32_t func)
832 {
833 switch(func) {
834 case PIPE_POLYGON_MODE_FILL:
835 return V_028814_X_DRAW_TRIANGLES;
836 case PIPE_POLYGON_MODE_LINE:
837 return V_028814_X_DRAW_LINES;
838 case PIPE_POLYGON_MODE_POINT:
839 return V_028814_X_DRAW_POINTS;
840 default:
841 assert(0);
842 return V_028814_X_DRAW_POINTS;
843 }
844 }
845
846 static void *si_create_rs_state(struct pipe_context *ctx,
847 const struct pipe_rasterizer_state *state)
848 {
849 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
850 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
851 struct si_pm4_state *pm4 = &rs->pm4;
852 unsigned tmp, i;
853 float psize_min, psize_max;
854
855 if (!rs) {
856 return NULL;
857 }
858
859 rs->scissor_enable = state->scissor;
860 rs->clip_halfz = state->clip_halfz;
861 rs->two_side = state->light_twoside;
862 rs->multisample_enable = state->multisample;
863 rs->force_persample_interp = state->force_persample_interp;
864 rs->clip_plane_enable = state->clip_plane_enable;
865 rs->half_pixel_center = state->half_pixel_center;
866 rs->line_stipple_enable = state->line_stipple_enable;
867 rs->poly_stipple_enable = state->poly_stipple_enable;
868 rs->line_smooth = state->line_smooth;
869 rs->line_width = state->line_width;
870 rs->poly_smooth = state->poly_smooth;
871 rs->uses_poly_offset = state->offset_point || state->offset_line ||
872 state->offset_tri;
873 rs->clamp_fragment_color = state->clamp_fragment_color;
874 rs->clamp_vertex_color = state->clamp_vertex_color;
875 rs->flatshade = state->flatshade;
876 rs->sprite_coord_enable = state->sprite_coord_enable;
877 rs->rasterizer_discard = state->rasterizer_discard;
878 rs->pa_sc_line_stipple = state->line_stipple_enable ?
879 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
880 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
881 rs->pa_cl_clip_cntl =
882 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
883 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
884 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
885 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
886 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
887
888 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
889 S_0286D4_FLAT_SHADE_ENA(1) |
890 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
891 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
892 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
893 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
894 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
895 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
896
897 /* point size 12.4 fixed point */
898 tmp = (unsigned)(state->point_size * 8.0);
899 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
900
901 if (state->point_size_per_vertex) {
902 psize_min = util_get_min_point_size(state);
903 psize_max = SI_MAX_POINT_SIZE;
904 } else {
905 /* Force the point size to be as if the vertex output was disabled. */
906 psize_min = state->point_size;
907 psize_max = state->point_size;
908 }
909 rs->max_point_size = psize_max;
910
911 /* Divide by two, because 0.5 = 1 pixel. */
912 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
913 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
914 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
915
916 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
917 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
918 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
919 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
920 S_028A48_MSAA_ENABLE(state->multisample ||
921 state->poly_smooth ||
922 state->line_smooth) |
923 S_028A48_VPORT_SCISSOR_ENABLE(1) |
924 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
925
926 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
927 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
928 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
929 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
930 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
931 S_028814_FACE(!state->front_ccw) |
932 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
933 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
934 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
935 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
936 state->fill_back != PIPE_POLYGON_MODE_FILL) |
937 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
938 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
939
940 if (!rs->uses_poly_offset)
941 return rs;
942
943 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
944 if (!rs->pm4_poly_offset) {
945 FREE(rs);
946 return NULL;
947 }
948
949 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
950 for (i = 0; i < 3; i++) {
951 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
952 float offset_units = state->offset_units;
953 float offset_scale = state->offset_scale * 16.0f;
954 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
955
956 if (!state->offset_units_unscaled) {
957 switch (i) {
958 case 0: /* 16-bit zbuffer */
959 offset_units *= 4.0f;
960 pa_su_poly_offset_db_fmt_cntl =
961 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
962 break;
963 case 1: /* 24-bit zbuffer */
964 offset_units *= 2.0f;
965 pa_su_poly_offset_db_fmt_cntl =
966 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
967 break;
968 case 2: /* 32-bit zbuffer */
969 offset_units *= 1.0f;
970 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
971 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
972 break;
973 }
974 }
975
976 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
977 fui(offset_scale));
978 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
979 fui(offset_units));
980 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
981 fui(offset_scale));
982 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
983 fui(offset_units));
984 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
985 pa_su_poly_offset_db_fmt_cntl);
986 }
987
988 return rs;
989 }
990
991 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
992 {
993 struct si_context *sctx = (struct si_context *)ctx;
994 struct si_state_rasterizer *old_rs =
995 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
996 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
997
998 if (!state)
999 return;
1000
1001 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1002 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1003
1004 /* Update the small primitive filter workaround if necessary. */
1005 if (sctx->screen->has_msaa_sample_loc_bug &&
1006 sctx->framebuffer.nr_samples > 1)
1007 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1008 }
1009
1010 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1011 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1012
1013 si_pm4_bind_state(sctx, rasterizer, rs);
1014 si_update_poly_offset_state(sctx);
1015
1016 if (!old_rs ||
1017 old_rs->scissor_enable != rs->scissor_enable) {
1018 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1019 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1020 }
1021
1022 if (!old_rs ||
1023 old_rs->line_width != rs->line_width ||
1024 old_rs->max_point_size != rs->max_point_size ||
1025 old_rs->half_pixel_center != rs->half_pixel_center)
1026 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1027
1028 if (!old_rs ||
1029 old_rs->clip_halfz != rs->clip_halfz) {
1030 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1031 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1032 }
1033
1034 if (!old_rs ||
1035 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1036 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1037 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1038
1039 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1040 rs->line_stipple_enable;
1041
1042 if (!old_rs ||
1043 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1044 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1045 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1046 old_rs->flatshade != rs->flatshade ||
1047 old_rs->two_side != rs->two_side ||
1048 old_rs->multisample_enable != rs->multisample_enable ||
1049 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1050 old_rs->poly_smooth != rs->poly_smooth ||
1051 old_rs->line_smooth != rs->line_smooth ||
1052 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1053 old_rs->force_persample_interp != rs->force_persample_interp)
1054 sctx->do_update_shaders = true;
1055 }
1056
1057 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1058 {
1059 struct si_context *sctx = (struct si_context *)ctx;
1060 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1061
1062 if (sctx->queued.named.rasterizer == state)
1063 si_pm4_bind_state(sctx, poly_offset, NULL);
1064
1065 FREE(rs->pm4_poly_offset);
1066 si_pm4_delete_state(sctx, rasterizer, rs);
1067 }
1068
1069 /*
1070 * infeered state between dsa and stencil ref
1071 */
1072 static void si_emit_stencil_ref(struct si_context *sctx)
1073 {
1074 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1075 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1076 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1077
1078 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1079 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1080 S_028430_STENCILMASK(dsa->valuemask[0]) |
1081 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1082 S_028430_STENCILOPVAL(1));
1083 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1084 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1085 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1086 S_028434_STENCILOPVAL_BF(1));
1087 }
1088
1089 static void si_set_stencil_ref(struct pipe_context *ctx,
1090 const struct pipe_stencil_ref *state)
1091 {
1092 struct si_context *sctx = (struct si_context *)ctx;
1093
1094 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1095 return;
1096
1097 sctx->stencil_ref.state = *state;
1098 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1099 }
1100
1101
1102 /*
1103 * DSA
1104 */
1105
1106 static uint32_t si_translate_stencil_op(int s_op)
1107 {
1108 switch (s_op) {
1109 case PIPE_STENCIL_OP_KEEP:
1110 return V_02842C_STENCIL_KEEP;
1111 case PIPE_STENCIL_OP_ZERO:
1112 return V_02842C_STENCIL_ZERO;
1113 case PIPE_STENCIL_OP_REPLACE:
1114 return V_02842C_STENCIL_REPLACE_TEST;
1115 case PIPE_STENCIL_OP_INCR:
1116 return V_02842C_STENCIL_ADD_CLAMP;
1117 case PIPE_STENCIL_OP_DECR:
1118 return V_02842C_STENCIL_SUB_CLAMP;
1119 case PIPE_STENCIL_OP_INCR_WRAP:
1120 return V_02842C_STENCIL_ADD_WRAP;
1121 case PIPE_STENCIL_OP_DECR_WRAP:
1122 return V_02842C_STENCIL_SUB_WRAP;
1123 case PIPE_STENCIL_OP_INVERT:
1124 return V_02842C_STENCIL_INVERT;
1125 default:
1126 PRINT_ERR("Unknown stencil op %d", s_op);
1127 assert(0);
1128 break;
1129 }
1130 return 0;
1131 }
1132
1133 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1134 {
1135 return s->enabled && s->writemask &&
1136 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1137 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1138 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1139 }
1140
1141 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1142 {
1143 /* REPLACE is normally order invariant, except when the stencil
1144 * reference value is written by the fragment shader. Tracking this
1145 * interaction does not seem worth the effort, so be conservative. */
1146 return op != PIPE_STENCIL_OP_INCR &&
1147 op != PIPE_STENCIL_OP_DECR &&
1148 op != PIPE_STENCIL_OP_REPLACE;
1149 }
1150
1151 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1152 * invariant in the sense that the set of passing fragments as well as the
1153 * final stencil buffer result does not depend on the order of fragments. */
1154 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1155 {
1156 return !state->enabled || !state->writemask ||
1157 /* The following assumes that Z writes are disabled. */
1158 (state->func == PIPE_FUNC_ALWAYS &&
1159 si_order_invariant_stencil_op(state->zpass_op) &&
1160 si_order_invariant_stencil_op(state->zfail_op)) ||
1161 (state->func == PIPE_FUNC_NEVER &&
1162 si_order_invariant_stencil_op(state->fail_op));
1163 }
1164
1165 static void *si_create_dsa_state(struct pipe_context *ctx,
1166 const struct pipe_depth_stencil_alpha_state *state)
1167 {
1168 struct si_context *sctx = (struct si_context *)ctx;
1169 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1170 struct si_pm4_state *pm4 = &dsa->pm4;
1171 unsigned db_depth_control;
1172 uint32_t db_stencil_control = 0;
1173
1174 if (!dsa) {
1175 return NULL;
1176 }
1177
1178 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1179 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1180 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1181 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1182
1183 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1184 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1185 S_028800_ZFUNC(state->depth.func) |
1186 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1187
1188 /* stencil */
1189 if (state->stencil[0].enabled) {
1190 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1191 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1192 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1193 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1194 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1195
1196 if (state->stencil[1].enabled) {
1197 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1198 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1199 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1200 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1201 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1202 }
1203 }
1204
1205 /* alpha */
1206 if (state->alpha.enabled) {
1207 dsa->alpha_func = state->alpha.func;
1208
1209 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1210 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1211 } else {
1212 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1213 }
1214
1215 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1216 if (state->stencil[0].enabled)
1217 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1218 if (state->depth.bounds_test) {
1219 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1220 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1221 }
1222
1223 dsa->depth_enabled = state->depth.enabled;
1224 dsa->depth_write_enabled = state->depth.enabled &&
1225 state->depth.writemask;
1226 dsa->stencil_enabled = state->stencil[0].enabled;
1227 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1228 (si_dsa_writes_stencil(&state->stencil[0]) ||
1229 si_dsa_writes_stencil(&state->stencil[1]));
1230 dsa->db_can_write = dsa->depth_write_enabled ||
1231 dsa->stencil_write_enabled;
1232
1233 bool zfunc_is_ordered =
1234 state->depth.func == PIPE_FUNC_NEVER ||
1235 state->depth.func == PIPE_FUNC_LESS ||
1236 state->depth.func == PIPE_FUNC_LEQUAL ||
1237 state->depth.func == PIPE_FUNC_GREATER ||
1238 state->depth.func == PIPE_FUNC_GEQUAL;
1239
1240 bool nozwrite_and_order_invariant_stencil =
1241 !dsa->db_can_write ||
1242 (!dsa->depth_write_enabled &&
1243 si_order_invariant_stencil_state(&state->stencil[0]) &&
1244 si_order_invariant_stencil_state(&state->stencil[1]));
1245
1246 dsa->order_invariance[1].zs =
1247 nozwrite_and_order_invariant_stencil ||
1248 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1249 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1250
1251 dsa->order_invariance[1].pass_set =
1252 nozwrite_and_order_invariant_stencil ||
1253 (!dsa->stencil_write_enabled &&
1254 (state->depth.func == PIPE_FUNC_ALWAYS ||
1255 state->depth.func == PIPE_FUNC_NEVER));
1256 dsa->order_invariance[0].pass_set =
1257 !dsa->depth_write_enabled ||
1258 (state->depth.func == PIPE_FUNC_ALWAYS ||
1259 state->depth.func == PIPE_FUNC_NEVER);
1260
1261 dsa->order_invariance[1].pass_last =
1262 sctx->screen->assume_no_z_fights &&
1263 !dsa->stencil_write_enabled &&
1264 dsa->depth_write_enabled && zfunc_is_ordered;
1265 dsa->order_invariance[0].pass_last =
1266 sctx->screen->assume_no_z_fights &&
1267 dsa->depth_write_enabled && zfunc_is_ordered;
1268
1269 return dsa;
1270 }
1271
1272 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1273 {
1274 struct si_context *sctx = (struct si_context *)ctx;
1275 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1276 struct si_state_dsa *dsa = state;
1277
1278 if (!state)
1279 return;
1280
1281 si_pm4_bind_state(sctx, dsa, dsa);
1282
1283 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1284 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1285 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1286 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1287 }
1288
1289 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1290 sctx->do_update_shaders = true;
1291
1292 if (sctx->screen->dpbb_allowed &&
1293 (!old_dsa ||
1294 (old_dsa->depth_enabled != dsa->depth_enabled ||
1295 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1296 old_dsa->db_can_write != dsa->db_can_write)))
1297 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1298
1299 if (sctx->screen->has_out_of_order_rast &&
1300 (!old_dsa ||
1301 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1302 sizeof(old_dsa->order_invariance))))
1303 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1304 }
1305
1306 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1307 {
1308 struct si_context *sctx = (struct si_context *)ctx;
1309 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1310 }
1311
1312 static void *si_create_db_flush_dsa(struct si_context *sctx)
1313 {
1314 struct pipe_depth_stencil_alpha_state dsa = {};
1315
1316 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1317 }
1318
1319 /* DB RENDER STATE */
1320
1321 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1322 {
1323 struct si_context *sctx = (struct si_context*)ctx;
1324
1325 /* Pipeline stat & streamout queries. */
1326 if (enable) {
1327 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1328 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1329 } else {
1330 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1331 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1332 }
1333
1334 /* Occlusion queries. */
1335 if (sctx->occlusion_queries_disabled != !enable) {
1336 sctx->occlusion_queries_disabled = !enable;
1337 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1338 }
1339 }
1340
1341 void si_set_occlusion_query_state(struct si_context *sctx,
1342 bool old_perfect_enable)
1343 {
1344 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1345
1346 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1347
1348 if (perfect_enable != old_perfect_enable)
1349 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1350 }
1351
1352 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1353 {
1354 st->saved_compute = sctx->cs_shader_state.program;
1355
1356 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1357 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1358 }
1359
1360 static void si_emit_db_render_state(struct si_context *sctx)
1361 {
1362 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1363 unsigned db_shader_control, db_render_control, db_count_control;
1364 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1365
1366 /* DB_RENDER_CONTROL */
1367 if (sctx->dbcb_depth_copy_enabled ||
1368 sctx->dbcb_stencil_copy_enabled) {
1369 db_render_control =
1370 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1371 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1372 S_028000_COPY_CENTROID(1) |
1373 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1374 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1375 db_render_control =
1376 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1377 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1378 } else {
1379 db_render_control =
1380 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1381 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1382 }
1383
1384 /* DB_COUNT_CONTROL (occlusion queries) */
1385 if (sctx->num_occlusion_queries > 0 &&
1386 !sctx->occlusion_queries_disabled) {
1387 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1388
1389 if (sctx->chip_class >= CIK) {
1390 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1391
1392 /* Stoney doesn't increment occlusion query counters
1393 * if the sample rate is 16x. Use 8x sample rate instead.
1394 */
1395 if (sctx->family == CHIP_STONEY)
1396 log_sample_rate = MIN2(log_sample_rate, 3);
1397
1398 db_count_control =
1399 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1400 S_028004_SAMPLE_RATE(log_sample_rate) |
1401 S_028004_ZPASS_ENABLE(1) |
1402 S_028004_SLICE_EVEN_ENABLE(1) |
1403 S_028004_SLICE_ODD_ENABLE(1);
1404 } else {
1405 db_count_control =
1406 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1407 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1408 }
1409 } else {
1410 /* Disable occlusion queries. */
1411 if (sctx->chip_class >= CIK) {
1412 db_count_control = 0;
1413 } else {
1414 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1415 }
1416 }
1417
1418 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1419 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1420 db_count_control);
1421
1422 /* DB_RENDER_OVERRIDE2 */
1423 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1424 SI_TRACKED_DB_RENDER_OVERRIDE2,
1425 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1426 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1427 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1428
1429 db_shader_control = sctx->ps_db_shader_control;
1430
1431 /* Bug workaround for smoothing (overrasterization) on SI. */
1432 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1433 db_shader_control &= C_02880C_Z_ORDER;
1434 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1435 }
1436
1437 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1438 if (!rs->multisample_enable)
1439 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1440
1441 if (sctx->screen->has_rbplus &&
1442 !sctx->screen->rbplus_allowed)
1443 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1444
1445 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1446 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1447
1448 if (initial_cdw != sctx->gfx_cs->current.cdw)
1449 sctx->context_roll_counter++;
1450 }
1451
1452 /*
1453 * format translation
1454 */
1455 static uint32_t si_translate_colorformat(enum pipe_format format)
1456 {
1457 const struct util_format_description *desc = util_format_description(format);
1458 if (!desc)
1459 return V_028C70_COLOR_INVALID;
1460
1461 #define HAS_SIZE(x,y,z,w) \
1462 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1463 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1464
1465 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1466 return V_028C70_COLOR_10_11_11;
1467
1468 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1469 return V_028C70_COLOR_INVALID;
1470
1471 /* hw cannot support mixed formats (except depth/stencil, since
1472 * stencil is not written to). */
1473 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1474 return V_028C70_COLOR_INVALID;
1475
1476 switch (desc->nr_channels) {
1477 case 1:
1478 switch (desc->channel[0].size) {
1479 case 8:
1480 return V_028C70_COLOR_8;
1481 case 16:
1482 return V_028C70_COLOR_16;
1483 case 32:
1484 return V_028C70_COLOR_32;
1485 }
1486 break;
1487 case 2:
1488 if (desc->channel[0].size == desc->channel[1].size) {
1489 switch (desc->channel[0].size) {
1490 case 8:
1491 return V_028C70_COLOR_8_8;
1492 case 16:
1493 return V_028C70_COLOR_16_16;
1494 case 32:
1495 return V_028C70_COLOR_32_32;
1496 }
1497 } else if (HAS_SIZE(8,24,0,0)) {
1498 return V_028C70_COLOR_24_8;
1499 } else if (HAS_SIZE(24,8,0,0)) {
1500 return V_028C70_COLOR_8_24;
1501 }
1502 break;
1503 case 3:
1504 if (HAS_SIZE(5,6,5,0)) {
1505 return V_028C70_COLOR_5_6_5;
1506 } else if (HAS_SIZE(32,8,24,0)) {
1507 return V_028C70_COLOR_X24_8_32_FLOAT;
1508 }
1509 break;
1510 case 4:
1511 if (desc->channel[0].size == desc->channel[1].size &&
1512 desc->channel[0].size == desc->channel[2].size &&
1513 desc->channel[0].size == desc->channel[3].size) {
1514 switch (desc->channel[0].size) {
1515 case 4:
1516 return V_028C70_COLOR_4_4_4_4;
1517 case 8:
1518 return V_028C70_COLOR_8_8_8_8;
1519 case 16:
1520 return V_028C70_COLOR_16_16_16_16;
1521 case 32:
1522 return V_028C70_COLOR_32_32_32_32;
1523 }
1524 } else if (HAS_SIZE(5,5,5,1)) {
1525 return V_028C70_COLOR_1_5_5_5;
1526 } else if (HAS_SIZE(1,5,5,5)) {
1527 return V_028C70_COLOR_5_5_5_1;
1528 } else if (HAS_SIZE(10,10,10,2)) {
1529 return V_028C70_COLOR_2_10_10_10;
1530 }
1531 break;
1532 }
1533 return V_028C70_COLOR_INVALID;
1534 }
1535
1536 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1537 {
1538 if (SI_BIG_ENDIAN) {
1539 switch(colorformat) {
1540 /* 8-bit buffers. */
1541 case V_028C70_COLOR_8:
1542 return V_028C70_ENDIAN_NONE;
1543
1544 /* 16-bit buffers. */
1545 case V_028C70_COLOR_5_6_5:
1546 case V_028C70_COLOR_1_5_5_5:
1547 case V_028C70_COLOR_4_4_4_4:
1548 case V_028C70_COLOR_16:
1549 case V_028C70_COLOR_8_8:
1550 return V_028C70_ENDIAN_8IN16;
1551
1552 /* 32-bit buffers. */
1553 case V_028C70_COLOR_8_8_8_8:
1554 case V_028C70_COLOR_2_10_10_10:
1555 case V_028C70_COLOR_8_24:
1556 case V_028C70_COLOR_24_8:
1557 case V_028C70_COLOR_16_16:
1558 return V_028C70_ENDIAN_8IN32;
1559
1560 /* 64-bit buffers. */
1561 case V_028C70_COLOR_16_16_16_16:
1562 return V_028C70_ENDIAN_8IN16;
1563
1564 case V_028C70_COLOR_32_32:
1565 return V_028C70_ENDIAN_8IN32;
1566
1567 /* 128-bit buffers. */
1568 case V_028C70_COLOR_32_32_32_32:
1569 return V_028C70_ENDIAN_8IN32;
1570 default:
1571 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1572 }
1573 } else {
1574 return V_028C70_ENDIAN_NONE;
1575 }
1576 }
1577
1578 static uint32_t si_translate_dbformat(enum pipe_format format)
1579 {
1580 switch (format) {
1581 case PIPE_FORMAT_Z16_UNORM:
1582 return V_028040_Z_16;
1583 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1584 case PIPE_FORMAT_X8Z24_UNORM:
1585 case PIPE_FORMAT_Z24X8_UNORM:
1586 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1587 return V_028040_Z_24; /* deprecated on SI */
1588 case PIPE_FORMAT_Z32_FLOAT:
1589 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1590 return V_028040_Z_32_FLOAT;
1591 default:
1592 return V_028040_Z_INVALID;
1593 }
1594 }
1595
1596 /*
1597 * Texture translation
1598 */
1599
1600 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1601 enum pipe_format format,
1602 const struct util_format_description *desc,
1603 int first_non_void)
1604 {
1605 struct si_screen *sscreen = (struct si_screen*)screen;
1606 bool uniform = true;
1607 int i;
1608
1609 /* Colorspace (return non-RGB formats directly). */
1610 switch (desc->colorspace) {
1611 /* Depth stencil formats */
1612 case UTIL_FORMAT_COLORSPACE_ZS:
1613 switch (format) {
1614 case PIPE_FORMAT_Z16_UNORM:
1615 return V_008F14_IMG_DATA_FORMAT_16;
1616 case PIPE_FORMAT_X24S8_UINT:
1617 case PIPE_FORMAT_S8X24_UINT:
1618 /*
1619 * Implemented as an 8_8_8_8 data format to fix texture
1620 * gathers in stencil sampling. This affects at least
1621 * GL45-CTS.texture_cube_map_array.sampling on VI.
1622 */
1623 if (sscreen->info.chip_class <= VI)
1624 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1625
1626 if (format == PIPE_FORMAT_X24S8_UINT)
1627 return V_008F14_IMG_DATA_FORMAT_8_24;
1628 else
1629 return V_008F14_IMG_DATA_FORMAT_24_8;
1630 case PIPE_FORMAT_Z24X8_UNORM:
1631 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1632 return V_008F14_IMG_DATA_FORMAT_8_24;
1633 case PIPE_FORMAT_X8Z24_UNORM:
1634 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1635 return V_008F14_IMG_DATA_FORMAT_24_8;
1636 case PIPE_FORMAT_S8_UINT:
1637 return V_008F14_IMG_DATA_FORMAT_8;
1638 case PIPE_FORMAT_Z32_FLOAT:
1639 return V_008F14_IMG_DATA_FORMAT_32;
1640 case PIPE_FORMAT_X32_S8X24_UINT:
1641 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1642 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1643 default:
1644 goto out_unknown;
1645 }
1646
1647 case UTIL_FORMAT_COLORSPACE_YUV:
1648 goto out_unknown; /* TODO */
1649
1650 case UTIL_FORMAT_COLORSPACE_SRGB:
1651 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1652 goto out_unknown;
1653 break;
1654
1655 default:
1656 break;
1657 }
1658
1659 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1660 if (!sscreen->info.has_format_bc1_through_bc7)
1661 goto out_unknown;
1662
1663 switch (format) {
1664 case PIPE_FORMAT_RGTC1_SNORM:
1665 case PIPE_FORMAT_LATC1_SNORM:
1666 case PIPE_FORMAT_RGTC1_UNORM:
1667 case PIPE_FORMAT_LATC1_UNORM:
1668 return V_008F14_IMG_DATA_FORMAT_BC4;
1669 case PIPE_FORMAT_RGTC2_SNORM:
1670 case PIPE_FORMAT_LATC2_SNORM:
1671 case PIPE_FORMAT_RGTC2_UNORM:
1672 case PIPE_FORMAT_LATC2_UNORM:
1673 return V_008F14_IMG_DATA_FORMAT_BC5;
1674 default:
1675 goto out_unknown;
1676 }
1677 }
1678
1679 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1680 (sscreen->info.family == CHIP_STONEY ||
1681 sscreen->info.family == CHIP_VEGA10 ||
1682 sscreen->info.family == CHIP_RAVEN)) {
1683 switch (format) {
1684 case PIPE_FORMAT_ETC1_RGB8:
1685 case PIPE_FORMAT_ETC2_RGB8:
1686 case PIPE_FORMAT_ETC2_SRGB8:
1687 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1688 case PIPE_FORMAT_ETC2_RGB8A1:
1689 case PIPE_FORMAT_ETC2_SRGB8A1:
1690 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1691 case PIPE_FORMAT_ETC2_RGBA8:
1692 case PIPE_FORMAT_ETC2_SRGBA8:
1693 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1694 case PIPE_FORMAT_ETC2_R11_UNORM:
1695 case PIPE_FORMAT_ETC2_R11_SNORM:
1696 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1697 case PIPE_FORMAT_ETC2_RG11_UNORM:
1698 case PIPE_FORMAT_ETC2_RG11_SNORM:
1699 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1700 default:
1701 goto out_unknown;
1702 }
1703 }
1704
1705 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1706 if (!sscreen->info.has_format_bc1_through_bc7)
1707 goto out_unknown;
1708
1709 switch (format) {
1710 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1711 case PIPE_FORMAT_BPTC_SRGBA:
1712 return V_008F14_IMG_DATA_FORMAT_BC7;
1713 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1714 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1715 return V_008F14_IMG_DATA_FORMAT_BC6;
1716 default:
1717 goto out_unknown;
1718 }
1719 }
1720
1721 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1722 switch (format) {
1723 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1724 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1725 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1726 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1727 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1728 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1729 default:
1730 goto out_unknown;
1731 }
1732 }
1733
1734 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1735 if (!sscreen->info.has_format_bc1_through_bc7)
1736 goto out_unknown;
1737
1738 switch (format) {
1739 case PIPE_FORMAT_DXT1_RGB:
1740 case PIPE_FORMAT_DXT1_RGBA:
1741 case PIPE_FORMAT_DXT1_SRGB:
1742 case PIPE_FORMAT_DXT1_SRGBA:
1743 return V_008F14_IMG_DATA_FORMAT_BC1;
1744 case PIPE_FORMAT_DXT3_RGBA:
1745 case PIPE_FORMAT_DXT3_SRGBA:
1746 return V_008F14_IMG_DATA_FORMAT_BC2;
1747 case PIPE_FORMAT_DXT5_RGBA:
1748 case PIPE_FORMAT_DXT5_SRGBA:
1749 return V_008F14_IMG_DATA_FORMAT_BC3;
1750 default:
1751 goto out_unknown;
1752 }
1753 }
1754
1755 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1756 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1757 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1758 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1759 }
1760
1761 /* R8G8Bx_SNORM - TODO CxV8U8 */
1762
1763 /* hw cannot support mixed formats (except depth/stencil, since only
1764 * depth is read).*/
1765 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1766 goto out_unknown;
1767
1768 /* See whether the components are of the same size. */
1769 for (i = 1; i < desc->nr_channels; i++) {
1770 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1771 }
1772
1773 /* Non-uniform formats. */
1774 if (!uniform) {
1775 switch(desc->nr_channels) {
1776 case 3:
1777 if (desc->channel[0].size == 5 &&
1778 desc->channel[1].size == 6 &&
1779 desc->channel[2].size == 5) {
1780 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1781 }
1782 goto out_unknown;
1783 case 4:
1784 if (desc->channel[0].size == 5 &&
1785 desc->channel[1].size == 5 &&
1786 desc->channel[2].size == 5 &&
1787 desc->channel[3].size == 1) {
1788 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1789 }
1790 if (desc->channel[0].size == 1 &&
1791 desc->channel[1].size == 5 &&
1792 desc->channel[2].size == 5 &&
1793 desc->channel[3].size == 5) {
1794 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1795 }
1796 if (desc->channel[0].size == 10 &&
1797 desc->channel[1].size == 10 &&
1798 desc->channel[2].size == 10 &&
1799 desc->channel[3].size == 2) {
1800 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1801 }
1802 goto out_unknown;
1803 }
1804 goto out_unknown;
1805 }
1806
1807 if (first_non_void < 0 || first_non_void > 3)
1808 goto out_unknown;
1809
1810 /* uniform formats */
1811 switch (desc->channel[first_non_void].size) {
1812 case 4:
1813 switch (desc->nr_channels) {
1814 #if 0 /* Not supported for render targets */
1815 case 2:
1816 return V_008F14_IMG_DATA_FORMAT_4_4;
1817 #endif
1818 case 4:
1819 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1820 }
1821 break;
1822 case 8:
1823 switch (desc->nr_channels) {
1824 case 1:
1825 return V_008F14_IMG_DATA_FORMAT_8;
1826 case 2:
1827 return V_008F14_IMG_DATA_FORMAT_8_8;
1828 case 4:
1829 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1830 }
1831 break;
1832 case 16:
1833 switch (desc->nr_channels) {
1834 case 1:
1835 return V_008F14_IMG_DATA_FORMAT_16;
1836 case 2:
1837 return V_008F14_IMG_DATA_FORMAT_16_16;
1838 case 4:
1839 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1840 }
1841 break;
1842 case 32:
1843 switch (desc->nr_channels) {
1844 case 1:
1845 return V_008F14_IMG_DATA_FORMAT_32;
1846 case 2:
1847 return V_008F14_IMG_DATA_FORMAT_32_32;
1848 #if 0 /* Not supported for render targets */
1849 case 3:
1850 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1851 #endif
1852 case 4:
1853 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1854 }
1855 }
1856
1857 out_unknown:
1858 return ~0;
1859 }
1860
1861 static unsigned si_tex_wrap(unsigned wrap)
1862 {
1863 switch (wrap) {
1864 default:
1865 case PIPE_TEX_WRAP_REPEAT:
1866 return V_008F30_SQ_TEX_WRAP;
1867 case PIPE_TEX_WRAP_CLAMP:
1868 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1869 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1870 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1871 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1872 return V_008F30_SQ_TEX_CLAMP_BORDER;
1873 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1874 return V_008F30_SQ_TEX_MIRROR;
1875 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1876 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1877 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1878 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1879 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1880 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1881 }
1882 }
1883
1884 static unsigned si_tex_mipfilter(unsigned filter)
1885 {
1886 switch (filter) {
1887 case PIPE_TEX_MIPFILTER_NEAREST:
1888 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1889 case PIPE_TEX_MIPFILTER_LINEAR:
1890 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1891 default:
1892 case PIPE_TEX_MIPFILTER_NONE:
1893 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1894 }
1895 }
1896
1897 static unsigned si_tex_compare(unsigned compare)
1898 {
1899 switch (compare) {
1900 default:
1901 case PIPE_FUNC_NEVER:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1903 case PIPE_FUNC_LESS:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1905 case PIPE_FUNC_EQUAL:
1906 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1907 case PIPE_FUNC_LEQUAL:
1908 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1909 case PIPE_FUNC_GREATER:
1910 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1911 case PIPE_FUNC_NOTEQUAL:
1912 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1913 case PIPE_FUNC_GEQUAL:
1914 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1915 case PIPE_FUNC_ALWAYS:
1916 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1917 }
1918 }
1919
1920 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1921 unsigned view_target, unsigned nr_samples)
1922 {
1923 unsigned res_target = tex->buffer.b.b.target;
1924
1925 if (view_target == PIPE_TEXTURE_CUBE ||
1926 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1927 res_target = view_target;
1928 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1929 else if (res_target == PIPE_TEXTURE_CUBE ||
1930 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1931 res_target = PIPE_TEXTURE_2D_ARRAY;
1932
1933 /* GFX9 allocates 1D textures as 2D. */
1934 if ((res_target == PIPE_TEXTURE_1D ||
1935 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1936 sscreen->info.chip_class >= GFX9 &&
1937 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1938 if (res_target == PIPE_TEXTURE_1D)
1939 res_target = PIPE_TEXTURE_2D;
1940 else
1941 res_target = PIPE_TEXTURE_2D_ARRAY;
1942 }
1943
1944 switch (res_target) {
1945 default:
1946 case PIPE_TEXTURE_1D:
1947 return V_008F1C_SQ_RSRC_IMG_1D;
1948 case PIPE_TEXTURE_1D_ARRAY:
1949 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1950 case PIPE_TEXTURE_2D:
1951 case PIPE_TEXTURE_RECT:
1952 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1953 V_008F1C_SQ_RSRC_IMG_2D;
1954 case PIPE_TEXTURE_2D_ARRAY:
1955 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1956 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1957 case PIPE_TEXTURE_3D:
1958 return V_008F1C_SQ_RSRC_IMG_3D;
1959 case PIPE_TEXTURE_CUBE:
1960 case PIPE_TEXTURE_CUBE_ARRAY:
1961 return V_008F1C_SQ_RSRC_IMG_CUBE;
1962 }
1963 }
1964
1965 /*
1966 * Format support testing
1967 */
1968
1969 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1970 {
1971 const struct util_format_description *desc = util_format_description(format);
1972 if (!desc)
1973 return false;
1974
1975 return si_translate_texformat(screen, format, desc,
1976 util_format_get_first_non_void_channel(format)) != ~0U;
1977 }
1978
1979 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1980 const struct util_format_description *desc,
1981 int first_non_void)
1982 {
1983 int i;
1984
1985 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1986 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1987
1988 assert(first_non_void >= 0);
1989
1990 if (desc->nr_channels == 4 &&
1991 desc->channel[0].size == 10 &&
1992 desc->channel[1].size == 10 &&
1993 desc->channel[2].size == 10 &&
1994 desc->channel[3].size == 2)
1995 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1996
1997 /* See whether the components are of the same size. */
1998 for (i = 0; i < desc->nr_channels; i++) {
1999 if (desc->channel[first_non_void].size != desc->channel[i].size)
2000 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2001 }
2002
2003 switch (desc->channel[first_non_void].size) {
2004 case 8:
2005 switch (desc->nr_channels) {
2006 case 1:
2007 case 3: /* 3 loads */
2008 return V_008F0C_BUF_DATA_FORMAT_8;
2009 case 2:
2010 return V_008F0C_BUF_DATA_FORMAT_8_8;
2011 case 4:
2012 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2013 }
2014 break;
2015 case 16:
2016 switch (desc->nr_channels) {
2017 case 1:
2018 case 3: /* 3 loads */
2019 return V_008F0C_BUF_DATA_FORMAT_16;
2020 case 2:
2021 return V_008F0C_BUF_DATA_FORMAT_16_16;
2022 case 4:
2023 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2024 }
2025 break;
2026 case 32:
2027 switch (desc->nr_channels) {
2028 case 1:
2029 return V_008F0C_BUF_DATA_FORMAT_32;
2030 case 2:
2031 return V_008F0C_BUF_DATA_FORMAT_32_32;
2032 case 3:
2033 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2034 case 4:
2035 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2036 }
2037 break;
2038 case 64:
2039 /* Legacy double formats. */
2040 switch (desc->nr_channels) {
2041 case 1: /* 1 load */
2042 return V_008F0C_BUF_DATA_FORMAT_32_32;
2043 case 2: /* 1 load */
2044 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2045 case 3: /* 3 loads */
2046 return V_008F0C_BUF_DATA_FORMAT_32_32;
2047 case 4: /* 2 loads */
2048 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2049 }
2050 break;
2051 }
2052
2053 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2054 }
2055
2056 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2057 const struct util_format_description *desc,
2058 int first_non_void)
2059 {
2060 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2061 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2062
2063 assert(first_non_void >= 0);
2064
2065 switch (desc->channel[first_non_void].type) {
2066 case UTIL_FORMAT_TYPE_SIGNED:
2067 case UTIL_FORMAT_TYPE_FIXED:
2068 if (desc->channel[first_non_void].size >= 32 ||
2069 desc->channel[first_non_void].pure_integer)
2070 return V_008F0C_BUF_NUM_FORMAT_SINT;
2071 else if (desc->channel[first_non_void].normalized)
2072 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2073 else
2074 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2075 break;
2076 case UTIL_FORMAT_TYPE_UNSIGNED:
2077 if (desc->channel[first_non_void].size >= 32 ||
2078 desc->channel[first_non_void].pure_integer)
2079 return V_008F0C_BUF_NUM_FORMAT_UINT;
2080 else if (desc->channel[first_non_void].normalized)
2081 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2082 else
2083 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2084 break;
2085 case UTIL_FORMAT_TYPE_FLOAT:
2086 default:
2087 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2088 }
2089 }
2090
2091 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2092 enum pipe_format format,
2093 unsigned usage)
2094 {
2095 const struct util_format_description *desc;
2096 int first_non_void;
2097 unsigned data_format;
2098
2099 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2100 PIPE_BIND_SAMPLER_VIEW |
2101 PIPE_BIND_VERTEX_BUFFER)) == 0);
2102
2103 desc = util_format_description(format);
2104 if (!desc)
2105 return 0;
2106
2107 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2108 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2109 * for read-only access (with caveats surrounding bounds checks), but
2110 * obviously fails for write access which we have to implement for
2111 * shader images. Luckily, OpenGL doesn't expect this to be supported
2112 * anyway, and so the only impact is on PBO uploads / downloads, which
2113 * shouldn't be expected to be fast for GL_RGB anyway.
2114 */
2115 if (desc->block.bits == 3 * 8 ||
2116 desc->block.bits == 3 * 16) {
2117 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2118 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2119 if (!usage)
2120 return 0;
2121 }
2122 }
2123
2124 first_non_void = util_format_get_first_non_void_channel(format);
2125 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2126 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2127 return 0;
2128
2129 return usage;
2130 }
2131
2132 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2133 {
2134 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2135 si_translate_colorswap(format, false) != ~0U;
2136 }
2137
2138 static bool si_is_zs_format_supported(enum pipe_format format)
2139 {
2140 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2141 }
2142
2143 static boolean si_is_format_supported(struct pipe_screen *screen,
2144 enum pipe_format format,
2145 enum pipe_texture_target target,
2146 unsigned sample_count,
2147 unsigned storage_sample_count,
2148 unsigned usage)
2149 {
2150 struct si_screen *sscreen = (struct si_screen *)screen;
2151 unsigned retval = 0;
2152
2153 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2154 PRINT_ERR("r600: unsupported texture type %d\n", target);
2155 return false;
2156 }
2157
2158 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2159 return false;
2160
2161 if (sample_count > 1) {
2162 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2163 return false;
2164
2165 if (usage & PIPE_BIND_SHADER_IMAGE)
2166 return false;
2167
2168 /* Only power-of-two sample counts are supported. */
2169 if (!util_is_power_of_two_or_zero(sample_count) ||
2170 !util_is_power_of_two_or_zero(storage_sample_count))
2171 return false;
2172
2173 /* MSAA support without framebuffer attachments. */
2174 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2175 return true;
2176
2177 if (!sscreen->info.has_eqaa_surface_allocator ||
2178 util_format_is_depth_or_stencil(format)) {
2179 /* Color without EQAA or depth/stencil. */
2180 if (sample_count > 8 ||
2181 sample_count != storage_sample_count)
2182 return false;
2183 } else {
2184 /* Color with EQAA. */
2185 if (sample_count > 16 ||
2186 storage_sample_count > 8)
2187 return false;
2188 }
2189 }
2190
2191 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2192 PIPE_BIND_SHADER_IMAGE)) {
2193 if (target == PIPE_BUFFER) {
2194 retval |= si_is_vertex_format_supported(
2195 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2196 PIPE_BIND_SHADER_IMAGE));
2197 } else {
2198 if (si_is_sampler_format_supported(screen, format))
2199 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2200 PIPE_BIND_SHADER_IMAGE);
2201 }
2202 }
2203
2204 if ((usage & (PIPE_BIND_RENDER_TARGET |
2205 PIPE_BIND_DISPLAY_TARGET |
2206 PIPE_BIND_SCANOUT |
2207 PIPE_BIND_SHARED |
2208 PIPE_BIND_BLENDABLE)) &&
2209 si_is_colorbuffer_format_supported(format)) {
2210 retval |= usage &
2211 (PIPE_BIND_RENDER_TARGET |
2212 PIPE_BIND_DISPLAY_TARGET |
2213 PIPE_BIND_SCANOUT |
2214 PIPE_BIND_SHARED);
2215 if (!util_format_is_pure_integer(format) &&
2216 !util_format_is_depth_or_stencil(format))
2217 retval |= usage & PIPE_BIND_BLENDABLE;
2218 }
2219
2220 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2221 si_is_zs_format_supported(format)) {
2222 retval |= PIPE_BIND_DEPTH_STENCIL;
2223 }
2224
2225 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2226 retval |= si_is_vertex_format_supported(screen, format,
2227 PIPE_BIND_VERTEX_BUFFER);
2228 }
2229
2230 if ((usage & PIPE_BIND_LINEAR) &&
2231 !util_format_is_compressed(format) &&
2232 !(usage & PIPE_BIND_DEPTH_STENCIL))
2233 retval |= PIPE_BIND_LINEAR;
2234
2235 return retval == usage;
2236 }
2237
2238 /*
2239 * framebuffer handling
2240 */
2241
2242 static void si_choose_spi_color_formats(struct si_surface *surf,
2243 unsigned format, unsigned swap,
2244 unsigned ntype, bool is_depth)
2245 {
2246 /* Alpha is needed for alpha-to-coverage.
2247 * Blending may be with or without alpha.
2248 */
2249 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2250 unsigned alpha = 0; /* exports alpha, but may not support blending */
2251 unsigned blend = 0; /* supports blending, but may not export alpha */
2252 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2253
2254 /* Choose the SPI color formats. These are required values for RB+.
2255 * Other chips have multiple choices, though they are not necessarily better.
2256 */
2257 switch (format) {
2258 case V_028C70_COLOR_5_6_5:
2259 case V_028C70_COLOR_1_5_5_5:
2260 case V_028C70_COLOR_5_5_5_1:
2261 case V_028C70_COLOR_4_4_4_4:
2262 case V_028C70_COLOR_10_11_11:
2263 case V_028C70_COLOR_11_11_10:
2264 case V_028C70_COLOR_8:
2265 case V_028C70_COLOR_8_8:
2266 case V_028C70_COLOR_8_8_8_8:
2267 case V_028C70_COLOR_10_10_10_2:
2268 case V_028C70_COLOR_2_10_10_10:
2269 if (ntype == V_028C70_NUMBER_UINT)
2270 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2271 else if (ntype == V_028C70_NUMBER_SINT)
2272 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2273 else
2274 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2275 break;
2276
2277 case V_028C70_COLOR_16:
2278 case V_028C70_COLOR_16_16:
2279 case V_028C70_COLOR_16_16_16_16:
2280 if (ntype == V_028C70_NUMBER_UNORM ||
2281 ntype == V_028C70_NUMBER_SNORM) {
2282 /* UNORM16 and SNORM16 don't support blending */
2283 if (ntype == V_028C70_NUMBER_UNORM)
2284 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2285 else
2286 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2287
2288 /* Use 32 bits per channel for blending. */
2289 if (format == V_028C70_COLOR_16) {
2290 if (swap == V_028C70_SWAP_STD) { /* R */
2291 blend = V_028714_SPI_SHADER_32_R;
2292 blend_alpha = V_028714_SPI_SHADER_32_AR;
2293 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2294 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2295 else
2296 assert(0);
2297 } else if (format == V_028C70_COLOR_16_16) {
2298 if (swap == V_028C70_SWAP_STD) { /* RG */
2299 blend = V_028714_SPI_SHADER_32_GR;
2300 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2301 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2302 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2303 else
2304 assert(0);
2305 } else /* 16_16_16_16 */
2306 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2307 } else if (ntype == V_028C70_NUMBER_UINT)
2308 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2309 else if (ntype == V_028C70_NUMBER_SINT)
2310 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2311 else if (ntype == V_028C70_NUMBER_FLOAT)
2312 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2313 else
2314 assert(0);
2315 break;
2316
2317 case V_028C70_COLOR_32:
2318 if (swap == V_028C70_SWAP_STD) { /* R */
2319 blend = normal = V_028714_SPI_SHADER_32_R;
2320 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2321 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2322 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2323 else
2324 assert(0);
2325 break;
2326
2327 case V_028C70_COLOR_32_32:
2328 if (swap == V_028C70_SWAP_STD) { /* RG */
2329 blend = normal = V_028714_SPI_SHADER_32_GR;
2330 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2331 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2332 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2333 else
2334 assert(0);
2335 break;
2336
2337 case V_028C70_COLOR_32_32_32_32:
2338 case V_028C70_COLOR_8_24:
2339 case V_028C70_COLOR_24_8:
2340 case V_028C70_COLOR_X24_8_32_FLOAT:
2341 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2342 break;
2343
2344 default:
2345 assert(0);
2346 return;
2347 }
2348
2349 /* The DB->CB copy needs 32_ABGR. */
2350 if (is_depth)
2351 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2352
2353 surf->spi_shader_col_format = normal;
2354 surf->spi_shader_col_format_alpha = alpha;
2355 surf->spi_shader_col_format_blend = blend;
2356 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2357 }
2358
2359 static void si_initialize_color_surface(struct si_context *sctx,
2360 struct si_surface *surf)
2361 {
2362 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2363 unsigned color_info, color_attrib;
2364 unsigned format, swap, ntype, endian;
2365 const struct util_format_description *desc;
2366 int firstchan;
2367 unsigned blend_clamp = 0, blend_bypass = 0;
2368
2369 desc = util_format_description(surf->base.format);
2370 for (firstchan = 0; firstchan < 4; firstchan++) {
2371 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2372 break;
2373 }
2374 }
2375 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2376 ntype = V_028C70_NUMBER_FLOAT;
2377 } else {
2378 ntype = V_028C70_NUMBER_UNORM;
2379 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2380 ntype = V_028C70_NUMBER_SRGB;
2381 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2382 if (desc->channel[firstchan].pure_integer) {
2383 ntype = V_028C70_NUMBER_SINT;
2384 } else {
2385 assert(desc->channel[firstchan].normalized);
2386 ntype = V_028C70_NUMBER_SNORM;
2387 }
2388 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2389 if (desc->channel[firstchan].pure_integer) {
2390 ntype = V_028C70_NUMBER_UINT;
2391 } else {
2392 assert(desc->channel[firstchan].normalized);
2393 ntype = V_028C70_NUMBER_UNORM;
2394 }
2395 }
2396 }
2397
2398 format = si_translate_colorformat(surf->base.format);
2399 if (format == V_028C70_COLOR_INVALID) {
2400 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2401 }
2402 assert(format != V_028C70_COLOR_INVALID);
2403 swap = si_translate_colorswap(surf->base.format, false);
2404 endian = si_colorformat_endian_swap(format);
2405
2406 /* blend clamp should be set for all NORM/SRGB types */
2407 if (ntype == V_028C70_NUMBER_UNORM ||
2408 ntype == V_028C70_NUMBER_SNORM ||
2409 ntype == V_028C70_NUMBER_SRGB)
2410 blend_clamp = 1;
2411
2412 /* set blend bypass according to docs if SINT/UINT or
2413 8/24 COLOR variants */
2414 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2415 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2416 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2417 blend_clamp = 0;
2418 blend_bypass = 1;
2419 }
2420
2421 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2422 if (format == V_028C70_COLOR_8 ||
2423 format == V_028C70_COLOR_8_8 ||
2424 format == V_028C70_COLOR_8_8_8_8)
2425 surf->color_is_int8 = true;
2426 else if (format == V_028C70_COLOR_10_10_10_2 ||
2427 format == V_028C70_COLOR_2_10_10_10)
2428 surf->color_is_int10 = true;
2429 }
2430
2431 color_info = S_028C70_FORMAT(format) |
2432 S_028C70_COMP_SWAP(swap) |
2433 S_028C70_BLEND_CLAMP(blend_clamp) |
2434 S_028C70_BLEND_BYPASS(blend_bypass) |
2435 S_028C70_SIMPLE_FLOAT(1) |
2436 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2437 ntype != V_028C70_NUMBER_SNORM &&
2438 ntype != V_028C70_NUMBER_SRGB &&
2439 format != V_028C70_COLOR_8_24 &&
2440 format != V_028C70_COLOR_24_8) |
2441 S_028C70_NUMBER_TYPE(ntype) |
2442 S_028C70_ENDIAN(endian);
2443
2444 /* Intensity is implemented as Red, so treat it that way. */
2445 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2446 util_format_is_intensity(surf->base.format));
2447
2448 if (tex->buffer.b.b.nr_samples > 1) {
2449 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2450 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2451
2452 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2453 S_028C74_NUM_FRAGMENTS(log_fragments);
2454
2455 if (tex->surface.fmask_size) {
2456 color_info |= S_028C70_COMPRESSION(1);
2457 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2458
2459 if (sctx->chip_class == SI) {
2460 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2461 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2462 }
2463 }
2464 }
2465
2466 if (sctx->chip_class >= VI) {
2467 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2468 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2469
2470 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2471 64 for APU because all of our APUs to date use DIMMs which have
2472 a request granularity size of 64B while all other chips have a
2473 32B request size */
2474 if (!sctx->screen->info.has_dedicated_vram)
2475 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2476
2477 if (tex->buffer.b.b.nr_storage_samples > 1) {
2478 if (tex->surface.bpe == 1)
2479 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2480 else if (tex->surface.bpe == 2)
2481 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2482 }
2483
2484 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2485 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2486 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2487 }
2488
2489 /* This must be set for fast clear to work without FMASK. */
2490 if (!tex->surface.fmask_size && sctx->chip_class == SI) {
2491 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2492 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2493 }
2494
2495 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2496 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2497
2498 if (sctx->chip_class >= GFX9) {
2499 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2500
2501 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2502 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2503 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2504 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2505 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2506 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2507 }
2508
2509 surf->cb_color_view = color_view;
2510 surf->cb_color_info = color_info;
2511 surf->cb_color_attrib = color_attrib;
2512
2513 /* Determine pixel shader export format */
2514 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2515
2516 surf->color_initialized = true;
2517 }
2518
2519 static void si_init_depth_surface(struct si_context *sctx,
2520 struct si_surface *surf)
2521 {
2522 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2523 unsigned level = surf->base.u.tex.level;
2524 unsigned format, stencil_format;
2525 uint32_t z_info, s_info;
2526
2527 format = si_translate_dbformat(tex->db_render_format);
2528 stencil_format = tex->surface.has_stencil ?
2529 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2530
2531 assert(format != V_028040_Z_INVALID);
2532 if (format == V_028040_Z_INVALID)
2533 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2534
2535 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2536 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2537 surf->db_htile_data_base = 0;
2538 surf->db_htile_surface = 0;
2539
2540 if (sctx->chip_class >= GFX9) {
2541 assert(tex->surface.u.gfx9.surf_offset == 0);
2542 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2543 surf->db_stencil_base = (tex->buffer.gpu_address +
2544 tex->surface.u.gfx9.stencil_offset) >> 8;
2545 z_info = S_028038_FORMAT(format) |
2546 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2547 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2548 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2549 s_info = S_02803C_FORMAT(stencil_format) |
2550 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2551 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2552 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2553 surf->db_depth_view |= S_028008_MIPID(level);
2554 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2555 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2556
2557 if (si_htile_enabled(tex, level)) {
2558 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2559 S_028038_ALLOW_EXPCLEAR(1);
2560
2561 if (tex->tc_compatible_htile) {
2562 unsigned max_zplanes = 4;
2563
2564 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2565 tex->buffer.b.b.nr_samples > 1)
2566 max_zplanes = 2;
2567
2568 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2569 S_028038_ITERATE_FLUSH(1);
2570 s_info |= S_02803C_ITERATE_FLUSH(1);
2571 }
2572
2573 if (tex->surface.has_stencil) {
2574 /* Stencil buffer workaround ported from the SI-CI-VI code.
2575 * See that for explanation.
2576 */
2577 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2578 } else {
2579 /* Use all HTILE for depth if there's no stencil. */
2580 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2581 }
2582
2583 surf->db_htile_data_base = (tex->buffer.gpu_address +
2584 tex->htile_offset) >> 8;
2585 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2586 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2587 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2588 }
2589 } else {
2590 /* SI-CI-VI */
2591 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2592
2593 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2594
2595 surf->db_depth_base = (tex->buffer.gpu_address +
2596 tex->surface.u.legacy.level[level].offset) >> 8;
2597 surf->db_stencil_base = (tex->buffer.gpu_address +
2598 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2599
2600 z_info = S_028040_FORMAT(format) |
2601 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2602 s_info = S_028044_FORMAT(stencil_format);
2603 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2604
2605 if (sctx->chip_class >= CIK) {
2606 struct radeon_info *info = &sctx->screen->info;
2607 unsigned index = tex->surface.u.legacy.tiling_index[level];
2608 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2609 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2610 unsigned tile_mode = info->si_tile_mode_array[index];
2611 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2612 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2613
2614 surf->db_depth_info |=
2615 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2616 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2617 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2618 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2619 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2620 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2621 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2622 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2623 } else {
2624 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2625 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2626 tile_mode_index = si_tile_mode_index(tex, level, true);
2627 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2628 }
2629
2630 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2631 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2632 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2633 levelinfo->nblk_y) / 64 - 1);
2634
2635 if (si_htile_enabled(tex, level)) {
2636 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2637 S_028040_ALLOW_EXPCLEAR(1);
2638
2639 if (tex->surface.has_stencil) {
2640 /* Workaround: For a not yet understood reason, the
2641 * combination of MSAA, fast stencil clear and stencil
2642 * decompress messes with subsequent stencil buffer
2643 * uses. Problem was reproduced on Verde, Bonaire,
2644 * Tonga, and Carrizo.
2645 *
2646 * Disabling EXPCLEAR works around the problem.
2647 *
2648 * Check piglit's arb_texture_multisample-stencil-clear
2649 * test if you want to try changing this.
2650 */
2651 if (tex->buffer.b.b.nr_samples <= 1)
2652 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2653 } else if (!tex->tc_compatible_htile) {
2654 /* Use all of the htile_buffer for depth if there's no stencil.
2655 * This must not be set when TC-compatible HTILE is enabled
2656 * due to a hw bug.
2657 */
2658 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2659 }
2660
2661 surf->db_htile_data_base = (tex->buffer.gpu_address +
2662 tex->htile_offset) >> 8;
2663 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2664
2665 if (tex->tc_compatible_htile) {
2666 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2667
2668 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2669 if (tex->buffer.b.b.nr_samples <= 1)
2670 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2671 else if (tex->buffer.b.b.nr_samples <= 4)
2672 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2673 else
2674 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2675 }
2676 }
2677 }
2678
2679 surf->db_z_info = z_info;
2680 surf->db_stencil_info = s_info;
2681
2682 surf->depth_initialized = true;
2683 }
2684
2685 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2686 {
2687 if (sctx->decompression_enabled)
2688 return;
2689
2690 if (sctx->framebuffer.state.zsbuf) {
2691 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2692 struct si_texture *tex = (struct si_texture *)surf->texture;
2693
2694 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2695
2696 if (tex->surface.has_stencil)
2697 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2698 }
2699
2700 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2701 while (compressed_cb_mask) {
2702 unsigned i = u_bit_scan(&compressed_cb_mask);
2703 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2704 struct si_texture *tex = (struct si_texture*)surf->texture;
2705
2706 if (tex->surface.fmask_size)
2707 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2708 if (tex->dcc_gather_statistics)
2709 tex->separate_dcc_dirty = true;
2710 }
2711 }
2712
2713 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2714 {
2715 for (int i = 0; i < state->nr_cbufs; ++i) {
2716 struct si_surface *surf = NULL;
2717 struct si_texture *tex;
2718
2719 if (!state->cbufs[i])
2720 continue;
2721 surf = (struct si_surface*)state->cbufs[i];
2722 tex = (struct si_texture*)surf->base.texture;
2723
2724 p_atomic_dec(&tex->framebuffers_bound);
2725 }
2726 }
2727
2728 static void si_set_framebuffer_state(struct pipe_context *ctx,
2729 const struct pipe_framebuffer_state *state)
2730 {
2731 struct si_context *sctx = (struct si_context *)ctx;
2732 struct si_surface *surf = NULL;
2733 struct si_texture *tex;
2734 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2735 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2736 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2737 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2738 bool old_has_stencil =
2739 old_has_zsbuf &&
2740 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2741 bool unbound = false;
2742 int i;
2743
2744 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2745 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2746 * We could implement the full workaround here, but it's a useless case.
2747 */
2748 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2749 unreachable("the framebuffer shouldn't have zero area");
2750 return;
2751 }
2752
2753 si_update_fb_dirtiness_after_rendering(sctx);
2754
2755 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2756 if (!sctx->framebuffer.state.cbufs[i])
2757 continue;
2758
2759 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2760 if (tex->dcc_gather_statistics)
2761 vi_separate_dcc_stop_query(sctx, tex);
2762 }
2763
2764 /* Disable DCC if the formats are incompatible. */
2765 for (i = 0; i < state->nr_cbufs; i++) {
2766 if (!state->cbufs[i])
2767 continue;
2768
2769 surf = (struct si_surface*)state->cbufs[i];
2770 tex = (struct si_texture*)surf->base.texture;
2771
2772 if (!surf->dcc_incompatible)
2773 continue;
2774
2775 /* Since the DCC decompression calls back into set_framebuffer-
2776 * _state, we need to unbind the framebuffer, so that
2777 * vi_separate_dcc_stop_query isn't called twice with the same
2778 * color buffer.
2779 */
2780 if (!unbound) {
2781 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2782 unbound = true;
2783 }
2784
2785 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2786 if (!si_texture_disable_dcc(sctx, tex))
2787 si_decompress_dcc(sctx, tex);
2788
2789 surf->dcc_incompatible = false;
2790 }
2791
2792 /* Only flush TC when changing the framebuffer state, because
2793 * the only client not using TC that can change textures is
2794 * the framebuffer.
2795 *
2796 * Wait for compute shaders because of possible transitions:
2797 * - FB write -> shader read
2798 * - shader write -> FB read
2799 *
2800 * DB caches are flushed on demand (using si_decompress_textures).
2801 *
2802 * When MSAA is enabled, CB and TC caches are flushed on demand
2803 * (after FMASK decompression). Shader write -> FB read transitions
2804 * cannot happen for MSAA textures, because MSAA shader images are
2805 * not supported.
2806 *
2807 * Only flush and wait for CB if there is actually a bound color buffer.
2808 */
2809 if (sctx->framebuffer.uncompressed_cb_mask)
2810 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2811 sctx->framebuffer.CB_has_shader_readable_metadata);
2812
2813 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2814
2815 /* u_blitter doesn't invoke depth decompression when it does multiple
2816 * blits in a row, but the only case when it matters for DB is when
2817 * doing generate_mipmap. So here we flush DB manually between
2818 * individual generate_mipmap blits.
2819 * Note that lower mipmap levels aren't compressed.
2820 */
2821 if (sctx->generate_mipmap_for_depth) {
2822 si_make_DB_shader_coherent(sctx, 1, false,
2823 sctx->framebuffer.DB_has_shader_readable_metadata);
2824 } else if (sctx->chip_class == GFX9) {
2825 /* It appears that DB metadata "leaks" in a sequence of:
2826 * - depth clear
2827 * - DCC decompress for shader image writes (with DB disabled)
2828 * - render with DEPTH_BEFORE_SHADER=1
2829 * Flushing DB metadata works around the problem.
2830 */
2831 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2832 }
2833
2834 /* Take the maximum of the old and new count. If the new count is lower,
2835 * dirtying is needed to disable the unbound colorbuffers.
2836 */
2837 sctx->framebuffer.dirty_cbufs |=
2838 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2839 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2840
2841 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2842 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2843
2844 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2845 sctx->framebuffer.spi_shader_col_format = 0;
2846 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2847 sctx->framebuffer.spi_shader_col_format_blend = 0;
2848 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2849 sctx->framebuffer.color_is_int8 = 0;
2850 sctx->framebuffer.color_is_int10 = 0;
2851
2852 sctx->framebuffer.compressed_cb_mask = 0;
2853 sctx->framebuffer.uncompressed_cb_mask = 0;
2854 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2855 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2856 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2857 sctx->framebuffer.any_dst_linear = false;
2858 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2859 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2860 unsigned num_bpp64_colorbufs = 0;
2861
2862 for (i = 0; i < state->nr_cbufs; i++) {
2863 if (!state->cbufs[i])
2864 continue;
2865
2866 surf = (struct si_surface*)state->cbufs[i];
2867 tex = (struct si_texture*)surf->base.texture;
2868
2869 if (!surf->color_initialized) {
2870 si_initialize_color_surface(sctx, surf);
2871 }
2872
2873 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2874 sctx->framebuffer.spi_shader_col_format |=
2875 surf->spi_shader_col_format << (i * 4);
2876 sctx->framebuffer.spi_shader_col_format_alpha |=
2877 surf->spi_shader_col_format_alpha << (i * 4);
2878 sctx->framebuffer.spi_shader_col_format_blend |=
2879 surf->spi_shader_col_format_blend << (i * 4);
2880 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2881 surf->spi_shader_col_format_blend_alpha << (i * 4);
2882
2883 if (surf->color_is_int8)
2884 sctx->framebuffer.color_is_int8 |= 1 << i;
2885 if (surf->color_is_int10)
2886 sctx->framebuffer.color_is_int10 |= 1 << i;
2887
2888 if (tex->surface.fmask_size)
2889 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2890 else
2891 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2892
2893 /* Don't update nr_color_samples for non-AA buffers.
2894 * (e.g. destination of MSAA resolve)
2895 */
2896 if (tex->buffer.b.b.nr_samples >= 2 &&
2897 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2898 sctx->framebuffer.nr_color_samples =
2899 MIN2(sctx->framebuffer.nr_color_samples,
2900 tex->buffer.b.b.nr_storage_samples);
2901 sctx->framebuffer.nr_color_samples =
2902 MAX2(1, sctx->framebuffer.nr_color_samples);
2903 }
2904
2905 if (tex->surface.is_linear)
2906 sctx->framebuffer.any_dst_linear = true;
2907 if (tex->surface.bpe >= 8)
2908 num_bpp64_colorbufs++;
2909
2910 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2911 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2912
2913 si_context_add_resource_size(sctx, surf->base.texture);
2914
2915 p_atomic_inc(&tex->framebuffers_bound);
2916
2917 if (tex->dcc_gather_statistics) {
2918 /* Dirty tracking must be enabled for DCC usage analysis. */
2919 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2920 vi_separate_dcc_start_query(sctx, tex);
2921 }
2922 }
2923
2924 /* For optimal DCC performance. */
2925 if (sctx->chip_class == VI)
2926 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2927 else if (num_bpp64_colorbufs >= 5)
2928 sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
2929 else
2930 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2931
2932 struct si_texture *zstex = NULL;
2933
2934 if (state->zsbuf) {
2935 surf = (struct si_surface*)state->zsbuf;
2936 zstex = (struct si_texture*)surf->base.texture;
2937
2938 if (!surf->depth_initialized) {
2939 si_init_depth_surface(sctx, surf);
2940 }
2941
2942 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2943 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2944
2945 si_context_add_resource_size(sctx, surf->base.texture);
2946 }
2947
2948 si_update_ps_colorbuf0_slot(sctx);
2949 si_update_poly_offset_state(sctx);
2950 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2951 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2952
2953 if (sctx->screen->dpbb_allowed)
2954 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2955
2956 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2957 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2958
2959 if (sctx->screen->has_out_of_order_rast &&
2960 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2961 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2962 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2963 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2964
2965 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2966 struct pipe_constant_buffer constbuf = {0};
2967
2968 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2969 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2970
2971 constbuf.buffer = sctx->sample_pos_buffer;
2972
2973 /* Set sample locations as fragment shader constants. */
2974 switch (sctx->framebuffer.nr_samples) {
2975 case 1:
2976 constbuf.buffer_offset = 0;
2977 break;
2978 case 2:
2979 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
2980 (ubyte*)sctx->sample_positions.x1;
2981 break;
2982 case 4:
2983 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
2984 (ubyte*)sctx->sample_positions.x1;
2985 break;
2986 case 8:
2987 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
2988 (ubyte*)sctx->sample_positions.x1;
2989 break;
2990 case 16:
2991 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
2992 (ubyte*)sctx->sample_positions.x1;
2993 break;
2994 default:
2995 PRINT_ERR("Requested an invalid number of samples %i.\n",
2996 sctx->framebuffer.nr_samples);
2997 assert(0);
2998 }
2999 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3000 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3001
3002 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3003 }
3004
3005 sctx->do_update_shaders = true;
3006
3007 if (!sctx->decompression_enabled) {
3008 /* Prevent textures decompression when the framebuffer state
3009 * changes come from the decompression passes themselves.
3010 */
3011 sctx->need_check_render_feedback = true;
3012 }
3013 }
3014
3015 static void si_emit_framebuffer_state(struct si_context *sctx)
3016 {
3017 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3018 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3019 unsigned i, nr_cbufs = state->nr_cbufs;
3020 struct si_texture *tex = NULL;
3021 struct si_surface *cb = NULL;
3022 unsigned cb_color_info = 0;
3023
3024 /* Colorbuffers. */
3025 for (i = 0; i < nr_cbufs; i++) {
3026 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3027 unsigned cb_color_attrib;
3028
3029 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3030 continue;
3031
3032 cb = (struct si_surface*)state->cbufs[i];
3033 if (!cb) {
3034 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3035 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3036 continue;
3037 }
3038
3039 tex = (struct si_texture *)cb->base.texture;
3040 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3041 &tex->buffer, RADEON_USAGE_READWRITE,
3042 tex->buffer.b.b.nr_samples > 1 ?
3043 RADEON_PRIO_COLOR_BUFFER_MSAA :
3044 RADEON_PRIO_COLOR_BUFFER);
3045
3046 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3047 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3048 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3049 RADEON_PRIO_SEPARATE_META);
3050 }
3051
3052 if (tex->dcc_separate_buffer)
3053 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3054 tex->dcc_separate_buffer,
3055 RADEON_USAGE_READWRITE,
3056 RADEON_PRIO_SEPARATE_META);
3057
3058 /* Compute mutable surface parameters. */
3059 cb_color_base = tex->buffer.gpu_address >> 8;
3060 cb_color_fmask = 0;
3061 cb_color_cmask = tex->cmask_base_address_reg;
3062 cb_dcc_base = 0;
3063 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3064 cb_color_attrib = cb->cb_color_attrib;
3065
3066 if (cb->base.u.tex.level > 0)
3067 cb_color_info &= C_028C70_FAST_CLEAR;
3068
3069 if (tex->surface.fmask_size) {
3070 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3071 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3072 }
3073
3074 /* Set up DCC. */
3075 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3076 bool is_msaa_resolve_dst = state->cbufs[0] &&
3077 state->cbufs[0]->texture->nr_samples > 1 &&
3078 state->cbufs[1] == &cb->base &&
3079 state->cbufs[1]->texture->nr_samples <= 1;
3080
3081 if (!is_msaa_resolve_dst)
3082 cb_color_info |= S_028C70_DCC_ENABLE(1);
3083
3084 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3085 tex->dcc_offset) >> 8;
3086 cb_dcc_base |= tex->surface.tile_swizzle;
3087 }
3088
3089 if (sctx->chip_class >= GFX9) {
3090 struct gfx9_surf_meta_flags meta;
3091
3092 if (tex->dcc_offset)
3093 meta = tex->surface.u.gfx9.dcc;
3094 else
3095 meta = tex->surface.u.gfx9.cmask;
3096
3097 /* Set mutable surface parameters. */
3098 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3099 cb_color_base |= tex->surface.tile_swizzle;
3100 if (!tex->surface.fmask_size)
3101 cb_color_fmask = cb_color_base;
3102 if (cb->base.u.tex.level > 0)
3103 cb_color_cmask = cb_color_base;
3104 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3105 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3106 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3107 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3108
3109 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3110 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3111 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3112 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3113 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3114 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3115 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3116 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3117 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3118 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3119 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3120 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3121 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3122 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3123 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3124 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3125
3126 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3127 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3128 } else {
3129 /* Compute mutable surface parameters (SI-CI-VI). */
3130 const struct legacy_surf_level *level_info =
3131 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3132 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3133 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3134
3135 cb_color_base += level_info->offset >> 8;
3136 /* Only macrotiled modes can set tile swizzle. */
3137 if (level_info->mode == RADEON_SURF_MODE_2D)
3138 cb_color_base |= tex->surface.tile_swizzle;
3139
3140 if (!tex->surface.fmask_size)
3141 cb_color_fmask = cb_color_base;
3142 if (cb->base.u.tex.level > 0)
3143 cb_color_cmask = cb_color_base;
3144 if (cb_dcc_base)
3145 cb_dcc_base += level_info->dcc_offset >> 8;
3146
3147 pitch_tile_max = level_info->nblk_x / 8 - 1;
3148 slice_tile_max = level_info->nblk_x *
3149 level_info->nblk_y / 64 - 1;
3150 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3151
3152 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3153 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3154 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3155
3156 if (tex->surface.fmask_size) {
3157 if (sctx->chip_class >= CIK)
3158 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3159 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3160 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3161 } else {
3162 /* This must be set for fast clear to work without FMASK. */
3163 if (sctx->chip_class >= CIK)
3164 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3165 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3166 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3167 }
3168
3169 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3170 sctx->chip_class >= VI ? 14 : 13);
3171 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3172 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3173 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3174 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3175 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3176 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3177 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3178 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3179 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3180 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3181 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3182 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3183 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3184
3185 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3186 radeon_emit(cs, cb_dcc_base);
3187 }
3188 }
3189 for (; i < 8 ; i++)
3190 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3191 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3192
3193 /* ZS buffer. */
3194 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3195 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3196 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3197
3198 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3199 &tex->buffer, RADEON_USAGE_READWRITE,
3200 zb->base.texture->nr_samples > 1 ?
3201 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3202 RADEON_PRIO_DEPTH_BUFFER);
3203
3204 if (sctx->chip_class >= GFX9) {
3205 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3206 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3207 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3208 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3209
3210 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3211 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3212 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3213 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3214 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3215 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3216 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3217 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3218 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3219 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3220 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3221 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3222
3223 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3224 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3225 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3226 } else {
3227 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3228
3229 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3230 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3231 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3232 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3233 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3234 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3235 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3236 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3237 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3238 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3239 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3240 }
3241
3242 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3243 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3244 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3245
3246 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3247 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3248 } else if (sctx->framebuffer.dirty_zsbuf) {
3249 if (sctx->chip_class >= GFX9)
3250 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3251 else
3252 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3253
3254 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3255 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3256 }
3257
3258 /* Framebuffer dimensions. */
3259 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3260 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3261 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3262
3263 if (sctx->screen->dfsm_allowed) {
3264 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3265 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3266 }
3267
3268 sctx->framebuffer.dirty_cbufs = 0;
3269 sctx->framebuffer.dirty_zsbuf = false;
3270 }
3271
3272 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3273 {
3274 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3275 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3276 unsigned nr_samples = sctx->framebuffer.nr_samples;
3277 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3278
3279 /* Smoothing (only possible with nr_samples == 1) uses the same
3280 * sample locations as the MSAA it simulates.
3281 */
3282 if (nr_samples <= 1 && sctx->smoothing_enabled)
3283 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3284
3285 /* On Polaris, the small primitive filter uses the sample locations
3286 * even when MSAA is off, so we need to make sure they're set to 0.
3287 */
3288 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3289 nr_samples != sctx->sample_locs_num_samples) {
3290 sctx->sample_locs_num_samples = nr_samples;
3291 si_emit_sample_locations(cs, nr_samples);
3292 }
3293
3294 if (sctx->family >= CHIP_POLARIS10) {
3295 unsigned small_prim_filter_cntl =
3296 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3297 /* line bug */
3298 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3299
3300 /* The alternative of setting sample locations to 0 would
3301 * require a DB flush to avoid Z errors, see
3302 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3303 */
3304 if (has_msaa_sample_loc_bug &&
3305 sctx->framebuffer.nr_samples > 1 &&
3306 !rs->multisample_enable)
3307 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3308
3309 radeon_opt_set_context_reg(sctx,
3310 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3311 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3312 small_prim_filter_cntl);
3313 }
3314
3315 /* The exclusion bits can be set to improve rasterization efficiency
3316 * if no sample lies on the pixel boundary (-8 sample offset).
3317 */
3318 bool exclusion = sctx->chip_class >= CIK &&
3319 (!rs->multisample_enable || nr_samples != 16);
3320 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3321 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3322 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3323 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3324 }
3325
3326 static bool si_out_of_order_rasterization(struct si_context *sctx)
3327 {
3328 struct si_state_blend *blend = sctx->queued.named.blend;
3329 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3330
3331 if (!sctx->screen->has_out_of_order_rast)
3332 return false;
3333
3334 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3335
3336 if (blend) {
3337 colormask &= blend->cb_target_enabled_4bit;
3338 } else {
3339 colormask = 0;
3340 }
3341
3342 /* Conservative: No logic op. */
3343 if (colormask && blend->logicop_enable)
3344 return false;
3345
3346 struct si_dsa_order_invariance dsa_order_invariant = {
3347 .zs = true, .pass_set = true, .pass_last = false
3348 };
3349
3350 if (sctx->framebuffer.state.zsbuf) {
3351 struct si_texture *zstex =
3352 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3353 bool has_stencil = zstex->surface.has_stencil;
3354 dsa_order_invariant = dsa->order_invariance[has_stencil];
3355 if (!dsa_order_invariant.zs)
3356 return false;
3357
3358 /* The set of PS invocations is always order invariant,
3359 * except when early Z/S tests are requested. */
3360 if (sctx->ps_shader.cso &&
3361 sctx->ps_shader.cso->info.writes_memory &&
3362 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3363 !dsa_order_invariant.pass_set)
3364 return false;
3365
3366 if (sctx->num_perfect_occlusion_queries != 0 &&
3367 !dsa_order_invariant.pass_set)
3368 return false;
3369 }
3370
3371 if (!colormask)
3372 return true;
3373
3374 unsigned blendmask = colormask & blend->blend_enable_4bit;
3375
3376 if (blendmask) {
3377 /* Only commutative blending. */
3378 if (blendmask & ~blend->commutative_4bit)
3379 return false;
3380
3381 if (!dsa_order_invariant.pass_set)
3382 return false;
3383 }
3384
3385 if (colormask & ~blendmask) {
3386 if (!dsa_order_invariant.pass_last)
3387 return false;
3388 }
3389
3390 return true;
3391 }
3392
3393 static void si_emit_msaa_config(struct si_context *sctx)
3394 {
3395 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3396 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3397 /* 33% faster rendering to linear color buffers */
3398 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3399 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3400 unsigned sc_mode_cntl_1 =
3401 S_028A4C_WALK_SIZE(dst_is_linear) |
3402 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3403 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3404 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3405 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3406 /* always 1: */
3407 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3408 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3409 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3410 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3411 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3412 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3413 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3414 S_028804_INCOHERENT_EQAA_READS(1) |
3415 S_028804_INTERPOLATE_COMP_Z(1) |
3416 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3417 unsigned coverage_samples, color_samples, z_samples;
3418
3419 /* S: Coverage samples (up to 16x):
3420 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3421 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3422 *
3423 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3424 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3425 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3426 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3427 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3428 * # Z samples).
3429 *
3430 * F: Color samples (up to 8x, must be <= coverage samples):
3431 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3432 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3433 *
3434 * Can be anything between coverage and color samples:
3435 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3436 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3437 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3438 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3439 * # All are currently set the same as coverage samples.
3440 *
3441 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3442 * flag for undefined color samples. A shader-based resolve must handle unknowns
3443 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3444 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3445 * useful. The CB resolve always drops unknowns.
3446 *
3447 * Sensible AA configurations:
3448 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3449 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3450 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3451 * EQAA 8s 8z 8f = 8x MSAA
3452 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3453 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3454 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3455 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3456 * EQAA 4s 4z 4f = 4x MSAA
3457 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3458 * EQAA 2s 2z 2f = 2x MSAA
3459 */
3460 if (sctx->framebuffer.nr_samples > 1) {
3461 coverage_samples = sctx->framebuffer.nr_samples;
3462 color_samples = sctx->framebuffer.nr_color_samples;
3463
3464 if (sctx->framebuffer.state.zsbuf) {
3465 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3466 z_samples = MAX2(1, z_samples);
3467 } else {
3468 z_samples = coverage_samples;
3469 }
3470 } else if (sctx->smoothing_enabled) {
3471 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3472 } else {
3473 coverage_samples = color_samples = z_samples = 1;
3474 }
3475
3476 /* Required by OpenGL line rasterization.
3477 *
3478 * TODO: We should also enable perpendicular endcaps for AA lines,
3479 * but that requires implementing line stippling in the pixel
3480 * shader. SC can only do line stippling with axis-aligned
3481 * endcaps.
3482 */
3483 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3484 unsigned sc_aa_config = 0;
3485
3486 if (coverage_samples > 1) {
3487 /* distance from the pixel center, indexed by log2(nr_samples) */
3488 static unsigned max_dist[] = {
3489 0, /* unused */
3490 4, /* 2x MSAA */
3491 6, /* 4x MSAA */
3492 7, /* 8x MSAA */
3493 8, /* 16x MSAA */
3494 };
3495 unsigned log_samples = util_logbase2(coverage_samples);
3496 unsigned log_z_samples = util_logbase2(z_samples);
3497 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3498 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3499
3500 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3501 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3502 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3503 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3504
3505 if (sctx->framebuffer.nr_samples > 1) {
3506 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3507 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3508 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3509 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3510 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3511 } else if (sctx->smoothing_enabled) {
3512 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3513 }
3514 }
3515
3516 unsigned initial_cdw = cs->current.cdw;
3517
3518 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3519 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3520 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3521 sc_aa_config);
3522 /* R_028804_DB_EQAA */
3523 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3524 db_eqaa);
3525 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3526 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3527 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3528
3529 if (initial_cdw != cs->current.cdw) {
3530 sctx->context_roll_counter++;
3531
3532 /* GFX9: Flush DFSM when the AA mode changes. */
3533 if (sctx->screen->dfsm_allowed) {
3534 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3535 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3536 }
3537 }
3538 }
3539
3540 void si_update_ps_iter_samples(struct si_context *sctx)
3541 {
3542 if (sctx->framebuffer.nr_samples > 1)
3543 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3544 if (sctx->screen->dpbb_allowed)
3545 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3546 }
3547
3548 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3549 {
3550 struct si_context *sctx = (struct si_context *)ctx;
3551
3552 /* The hardware can only do sample shading with 2^n samples. */
3553 min_samples = util_next_power_of_two(min_samples);
3554
3555 if (sctx->ps_iter_samples == min_samples)
3556 return;
3557
3558 sctx->ps_iter_samples = min_samples;
3559 sctx->do_update_shaders = true;
3560
3561 si_update_ps_iter_samples(sctx);
3562 }
3563
3564 /*
3565 * Samplers
3566 */
3567
3568 /**
3569 * Build the sampler view descriptor for a buffer texture.
3570 * @param state 256-bit descriptor; only the high 128 bits are filled in
3571 */
3572 void
3573 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3574 enum pipe_format format,
3575 unsigned offset, unsigned size,
3576 uint32_t *state)
3577 {
3578 const struct util_format_description *desc;
3579 int first_non_void;
3580 unsigned stride;
3581 unsigned num_records;
3582 unsigned num_format, data_format;
3583
3584 desc = util_format_description(format);
3585 first_non_void = util_format_get_first_non_void_channel(format);
3586 stride = desc->block.bits / 8;
3587 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3588 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3589
3590 num_records = size / stride;
3591 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3592
3593 /* The NUM_RECORDS field has a different meaning depending on the chip,
3594 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3595 *
3596 * SI-CIK:
3597 * - If STRIDE == 0, it's in byte units.
3598 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3599 *
3600 * VI:
3601 * - For SMEM and STRIDE == 0, it's in byte units.
3602 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3603 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3604 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3605 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3606 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3607 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3608 * That way the same descriptor can be used by both SMEM and VMEM.
3609 *
3610 * GFX9:
3611 * - For SMEM and STRIDE == 0, it's in byte units.
3612 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3613 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3614 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3615 */
3616 if (screen->info.chip_class >= GFX9)
3617 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3618 * from STRIDE to bytes. This works around it by setting
3619 * NUM_RECORDS to at least the size of one element, so that
3620 * the first element is readable when IDXEN == 0.
3621 *
3622 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3623 * IDXEN is enforced?
3624 */
3625 num_records = num_records ? MAX2(num_records, stride) : 0;
3626 else if (screen->info.chip_class == VI)
3627 num_records *= stride;
3628
3629 state[4] = 0;
3630 state[5] = S_008F04_STRIDE(stride);
3631 state[6] = num_records;
3632 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3633 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3634 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3635 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3636 S_008F0C_NUM_FORMAT(num_format) |
3637 S_008F0C_DATA_FORMAT(data_format);
3638 }
3639
3640 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3641 {
3642 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3643
3644 if (swizzle[3] == PIPE_SWIZZLE_X) {
3645 /* For the pre-defined border color values (white, opaque
3646 * black, transparent black), the only thing that matters is
3647 * that the alpha channel winds up in the correct place
3648 * (because the RGB channels are all the same) so either of
3649 * these enumerations will work.
3650 */
3651 if (swizzle[2] == PIPE_SWIZZLE_Y)
3652 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3653 else
3654 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3655 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3656 if (swizzle[1] == PIPE_SWIZZLE_Y)
3657 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3658 else
3659 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3660 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3661 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3662 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3663 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3664 }
3665
3666 return bc_swizzle;
3667 }
3668
3669 /**
3670 * Build the sampler view descriptor for a texture.
3671 */
3672 void
3673 si_make_texture_descriptor(struct si_screen *screen,
3674 struct si_texture *tex,
3675 bool sampler,
3676 enum pipe_texture_target target,
3677 enum pipe_format pipe_format,
3678 const unsigned char state_swizzle[4],
3679 unsigned first_level, unsigned last_level,
3680 unsigned first_layer, unsigned last_layer,
3681 unsigned width, unsigned height, unsigned depth,
3682 uint32_t *state,
3683 uint32_t *fmask_state)
3684 {
3685 struct pipe_resource *res = &tex->buffer.b.b;
3686 const struct util_format_description *desc;
3687 unsigned char swizzle[4];
3688 int first_non_void;
3689 unsigned num_format, data_format, type, num_samples;
3690 uint64_t va;
3691
3692 desc = util_format_description(pipe_format);
3693
3694 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3695 MAX2(1, res->nr_samples) :
3696 MAX2(1, res->nr_storage_samples);
3697
3698 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3699 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3700 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3701 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3702
3703 switch (pipe_format) {
3704 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3705 case PIPE_FORMAT_X32_S8X24_UINT:
3706 case PIPE_FORMAT_X8Z24_UNORM:
3707 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3708 break;
3709 case PIPE_FORMAT_X24S8_UINT:
3710 /*
3711 * X24S8 is implemented as an 8_8_8_8 data format, to
3712 * fix texture gathers. This affects at least
3713 * GL45-CTS.texture_cube_map_array.sampling on VI.
3714 */
3715 if (screen->info.chip_class <= VI)
3716 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3717 else
3718 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3719 break;
3720 default:
3721 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3722 }
3723 } else {
3724 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3725 }
3726
3727 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3728
3729 switch (pipe_format) {
3730 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3731 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3732 break;
3733 default:
3734 if (first_non_void < 0) {
3735 if (util_format_is_compressed(pipe_format)) {
3736 switch (pipe_format) {
3737 case PIPE_FORMAT_DXT1_SRGB:
3738 case PIPE_FORMAT_DXT1_SRGBA:
3739 case PIPE_FORMAT_DXT3_SRGBA:
3740 case PIPE_FORMAT_DXT5_SRGBA:
3741 case PIPE_FORMAT_BPTC_SRGBA:
3742 case PIPE_FORMAT_ETC2_SRGB8:
3743 case PIPE_FORMAT_ETC2_SRGB8A1:
3744 case PIPE_FORMAT_ETC2_SRGBA8:
3745 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3746 break;
3747 case PIPE_FORMAT_RGTC1_SNORM:
3748 case PIPE_FORMAT_LATC1_SNORM:
3749 case PIPE_FORMAT_RGTC2_SNORM:
3750 case PIPE_FORMAT_LATC2_SNORM:
3751 case PIPE_FORMAT_ETC2_R11_SNORM:
3752 case PIPE_FORMAT_ETC2_RG11_SNORM:
3753 /* implies float, so use SNORM/UNORM to determine
3754 whether data is signed or not */
3755 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3756 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3757 break;
3758 default:
3759 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3760 break;
3761 }
3762 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3763 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3764 } else {
3765 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3766 }
3767 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3768 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3769 } else {
3770 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3771
3772 switch (desc->channel[first_non_void].type) {
3773 case UTIL_FORMAT_TYPE_FLOAT:
3774 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3775 break;
3776 case UTIL_FORMAT_TYPE_SIGNED:
3777 if (desc->channel[first_non_void].normalized)
3778 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3779 else if (desc->channel[first_non_void].pure_integer)
3780 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3781 else
3782 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3783 break;
3784 case UTIL_FORMAT_TYPE_UNSIGNED:
3785 if (desc->channel[first_non_void].normalized)
3786 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3787 else if (desc->channel[first_non_void].pure_integer)
3788 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3789 else
3790 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3791 }
3792 }
3793 }
3794
3795 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3796 if (data_format == ~0) {
3797 data_format = 0;
3798 }
3799
3800 /* S8 with Z32 HTILE needs a special format. */
3801 if (screen->info.chip_class >= GFX9 &&
3802 pipe_format == PIPE_FORMAT_S8_UINT &&
3803 tex->tc_compatible_htile)
3804 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3805
3806 if (!sampler &&
3807 (res->target == PIPE_TEXTURE_CUBE ||
3808 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3809 (screen->info.chip_class <= VI &&
3810 res->target == PIPE_TEXTURE_3D))) {
3811 /* For the purpose of shader images, treat cube maps and 3D
3812 * textures as 2D arrays. For 3D textures, the address
3813 * calculations for mipmaps are different, so we rely on the
3814 * caller to effectively disable mipmaps.
3815 */
3816 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3817
3818 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3819 } else {
3820 type = si_tex_dim(screen, tex, target, num_samples);
3821 }
3822
3823 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3824 height = 1;
3825 depth = res->array_size;
3826 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3827 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3828 if (sampler || res->target != PIPE_TEXTURE_3D)
3829 depth = res->array_size;
3830 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3831 depth = res->array_size / 6;
3832
3833 state[0] = 0;
3834 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3835 S_008F14_NUM_FORMAT_GFX6(num_format));
3836 state[2] = (S_008F18_WIDTH(width - 1) |
3837 S_008F18_HEIGHT(height - 1) |
3838 S_008F18_PERF_MOD(4));
3839 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3840 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3841 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3842 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3843 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3844 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3845 util_logbase2(num_samples) :
3846 last_level) |
3847 S_008F1C_TYPE(type));
3848 state[4] = 0;
3849 state[5] = S_008F24_BASE_ARRAY(first_layer);
3850 state[6] = 0;
3851 state[7] = 0;
3852
3853 if (screen->info.chip_class >= GFX9) {
3854 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3855
3856 /* Depth is the the last accessible layer on Gfx9.
3857 * The hw doesn't need to know the total number of layers.
3858 */
3859 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3860 state[4] |= S_008F20_DEPTH(depth - 1);
3861 else
3862 state[4] |= S_008F20_DEPTH(last_layer);
3863
3864 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3865 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3866 util_logbase2(num_samples) :
3867 tex->buffer.b.b.last_level);
3868 } else {
3869 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3870 state[4] |= S_008F20_DEPTH(depth - 1);
3871 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3872 }
3873
3874 if (tex->dcc_offset) {
3875 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3876 } else {
3877 /* The last dword is unused by hw. The shader uses it to clear
3878 * bits in the first dword of sampler state.
3879 */
3880 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3881 if (first_level == last_level)
3882 state[7] = C_008F30_MAX_ANISO_RATIO;
3883 else
3884 state[7] = 0xffffffff;
3885 }
3886 }
3887
3888 /* Initialize the sampler view for FMASK. */
3889 if (tex->surface.fmask_size) {
3890 uint32_t data_format, num_format;
3891
3892 va = tex->buffer.gpu_address + tex->fmask_offset;
3893
3894 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3895 if (screen->info.chip_class >= GFX9) {
3896 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3897 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3898 case FMASK(2,1):
3899 num_format = V_008F14_IMG_FMASK_8_2_1;
3900 break;
3901 case FMASK(2,2):
3902 num_format = V_008F14_IMG_FMASK_8_2_2;
3903 break;
3904 case FMASK(4,1):
3905 num_format = V_008F14_IMG_FMASK_8_4_1;
3906 break;
3907 case FMASK(4,2):
3908 num_format = V_008F14_IMG_FMASK_8_4_2;
3909 break;
3910 case FMASK(4,4):
3911 num_format = V_008F14_IMG_FMASK_8_4_4;
3912 break;
3913 case FMASK(8,1):
3914 num_format = V_008F14_IMG_FMASK_8_8_1;
3915 break;
3916 case FMASK(8,2):
3917 num_format = V_008F14_IMG_FMASK_16_8_2;
3918 break;
3919 case FMASK(8,4):
3920 num_format = V_008F14_IMG_FMASK_32_8_4;
3921 break;
3922 case FMASK(8,8):
3923 num_format = V_008F14_IMG_FMASK_32_8_8;
3924 break;
3925 case FMASK(16,1):
3926 num_format = V_008F14_IMG_FMASK_16_16_1;
3927 break;
3928 case FMASK(16,2):
3929 num_format = V_008F14_IMG_FMASK_32_16_2;
3930 break;
3931 case FMASK(16,4):
3932 num_format = V_008F14_IMG_FMASK_64_16_4;
3933 break;
3934 case FMASK(16,8):
3935 num_format = V_008F14_IMG_FMASK_64_16_8;
3936 break;
3937 default:
3938 unreachable("invalid nr_samples");
3939 }
3940 } else {
3941 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3942 case FMASK(2,1):
3943 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3944 break;
3945 case FMASK(2,2):
3946 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3947 break;
3948 case FMASK(4,1):
3949 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3950 break;
3951 case FMASK(4,2):
3952 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3953 break;
3954 case FMASK(4,4):
3955 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3956 break;
3957 case FMASK(8,1):
3958 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3959 break;
3960 case FMASK(8,2):
3961 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3962 break;
3963 case FMASK(8,4):
3964 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3965 break;
3966 case FMASK(8,8):
3967 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3968 break;
3969 case FMASK(16,1):
3970 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3971 break;
3972 case FMASK(16,2):
3973 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3974 break;
3975 case FMASK(16,4):
3976 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3977 break;
3978 case FMASK(16,8):
3979 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3980 break;
3981 default:
3982 unreachable("invalid nr_samples");
3983 }
3984 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3985 }
3986 #undef FMASK
3987
3988 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3989 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3990 S_008F14_DATA_FORMAT_GFX6(data_format) |
3991 S_008F14_NUM_FORMAT_GFX6(num_format);
3992 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3993 S_008F18_HEIGHT(height - 1);
3994 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3995 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3996 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3997 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3998 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3999 fmask_state[4] = 0;
4000 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4001 fmask_state[6] = 0;
4002 fmask_state[7] = 0;
4003
4004 if (screen->info.chip_class >= GFX9) {
4005 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4006 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4007 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
4008 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4009 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4010 } else {
4011 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4012 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4013 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4014 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4015 }
4016 }
4017 }
4018
4019 /**
4020 * Create a sampler view.
4021 *
4022 * @param ctx context
4023 * @param texture texture
4024 * @param state sampler view template
4025 * @param width0 width0 override (for compressed textures as int)
4026 * @param height0 height0 override (for compressed textures as int)
4027 * @param force_level set the base address to the level (for compressed textures)
4028 */
4029 struct pipe_sampler_view *
4030 si_create_sampler_view_custom(struct pipe_context *ctx,
4031 struct pipe_resource *texture,
4032 const struct pipe_sampler_view *state,
4033 unsigned width0, unsigned height0,
4034 unsigned force_level)
4035 {
4036 struct si_context *sctx = (struct si_context*)ctx;
4037 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4038 struct si_texture *tex = (struct si_texture*)texture;
4039 unsigned base_level, first_level, last_level;
4040 unsigned char state_swizzle[4];
4041 unsigned height, depth, width;
4042 unsigned last_layer = state->u.tex.last_layer;
4043 enum pipe_format pipe_format;
4044 const struct legacy_surf_level *surflevel;
4045
4046 if (!view)
4047 return NULL;
4048
4049 /* initialize base object */
4050 view->base = *state;
4051 view->base.texture = NULL;
4052 view->base.reference.count = 1;
4053 view->base.context = ctx;
4054
4055 assert(texture);
4056 pipe_resource_reference(&view->base.texture, texture);
4057
4058 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4059 state->format == PIPE_FORMAT_S8X24_UINT ||
4060 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4061 state->format == PIPE_FORMAT_S8_UINT)
4062 view->is_stencil_sampler = true;
4063
4064 /* Buffer resource. */
4065 if (texture->target == PIPE_BUFFER) {
4066 si_make_buffer_descriptor(sctx->screen,
4067 r600_resource(texture),
4068 state->format,
4069 state->u.buf.offset,
4070 state->u.buf.size,
4071 view->state);
4072 return &view->base;
4073 }
4074
4075 state_swizzle[0] = state->swizzle_r;
4076 state_swizzle[1] = state->swizzle_g;
4077 state_swizzle[2] = state->swizzle_b;
4078 state_swizzle[3] = state->swizzle_a;
4079
4080 base_level = 0;
4081 first_level = state->u.tex.first_level;
4082 last_level = state->u.tex.last_level;
4083 width = width0;
4084 height = height0;
4085 depth = texture->depth0;
4086
4087 if (sctx->chip_class <= VI && force_level) {
4088 assert(force_level == first_level &&
4089 force_level == last_level);
4090 base_level = force_level;
4091 first_level = 0;
4092 last_level = 0;
4093 width = u_minify(width, force_level);
4094 height = u_minify(height, force_level);
4095 depth = u_minify(depth, force_level);
4096 }
4097
4098 /* This is not needed if state trackers set last_layer correctly. */
4099 if (state->target == PIPE_TEXTURE_1D ||
4100 state->target == PIPE_TEXTURE_2D ||
4101 state->target == PIPE_TEXTURE_RECT ||
4102 state->target == PIPE_TEXTURE_CUBE)
4103 last_layer = state->u.tex.first_layer;
4104
4105 /* Texturing with separate depth and stencil. */
4106 pipe_format = state->format;
4107
4108 /* Depth/stencil texturing sometimes needs separate texture. */
4109 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4110 if (!tex->flushed_depth_texture &&
4111 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4112 pipe_resource_reference(&view->base.texture, NULL);
4113 FREE(view);
4114 return NULL;
4115 }
4116
4117 assert(tex->flushed_depth_texture);
4118
4119 /* Override format for the case where the flushed texture
4120 * contains only Z or only S.
4121 */
4122 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4123 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4124
4125 tex = tex->flushed_depth_texture;
4126 }
4127
4128 surflevel = tex->surface.u.legacy.level;
4129
4130 if (tex->db_compatible) {
4131 if (!view->is_stencil_sampler)
4132 pipe_format = tex->db_render_format;
4133
4134 switch (pipe_format) {
4135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4136 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4137 break;
4138 case PIPE_FORMAT_X8Z24_UNORM:
4139 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4140 /* Z24 is always stored like this for DB
4141 * compatibility.
4142 */
4143 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4144 break;
4145 case PIPE_FORMAT_X24S8_UINT:
4146 case PIPE_FORMAT_S8X24_UINT:
4147 case PIPE_FORMAT_X32_S8X24_UINT:
4148 pipe_format = PIPE_FORMAT_S8_UINT;
4149 surflevel = tex->surface.u.legacy.stencil_level;
4150 break;
4151 default:;
4152 }
4153 }
4154
4155 view->dcc_incompatible =
4156 vi_dcc_formats_are_incompatible(texture,
4157 state->u.tex.first_level,
4158 state->format);
4159
4160 si_make_texture_descriptor(sctx->screen, tex, true,
4161 state->target, pipe_format, state_swizzle,
4162 first_level, last_level,
4163 state->u.tex.first_layer, last_layer,
4164 width, height, depth,
4165 view->state, view->fmask_state);
4166
4167 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4168 view->is_integer =
4169 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4170 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4171 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4172 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4173 view->base_level_info = &surflevel[base_level];
4174 view->base_level = base_level;
4175 view->block_width = util_format_get_blockwidth(pipe_format);
4176 return &view->base;
4177 }
4178
4179 static struct pipe_sampler_view *
4180 si_create_sampler_view(struct pipe_context *ctx,
4181 struct pipe_resource *texture,
4182 const struct pipe_sampler_view *state)
4183 {
4184 return si_create_sampler_view_custom(ctx, texture, state,
4185 texture ? texture->width0 : 0,
4186 texture ? texture->height0 : 0, 0);
4187 }
4188
4189 static void si_sampler_view_destroy(struct pipe_context *ctx,
4190 struct pipe_sampler_view *state)
4191 {
4192 struct si_sampler_view *view = (struct si_sampler_view *)state;
4193
4194 pipe_resource_reference(&state->texture, NULL);
4195 FREE(view);
4196 }
4197
4198 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4199 {
4200 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4201 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4202 (linear_filter &&
4203 (wrap == PIPE_TEX_WRAP_CLAMP ||
4204 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4205 }
4206
4207 static uint32_t si_translate_border_color(struct si_context *sctx,
4208 const struct pipe_sampler_state *state,
4209 const union pipe_color_union *color,
4210 bool is_integer)
4211 {
4212 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4213 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4214
4215 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4216 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4217 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4218 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4219
4220 #define simple_border_types(elt) \
4221 do { \
4222 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4223 color->elt[2] == 0 && color->elt[3] == 0) \
4224 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4225 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4226 color->elt[2] == 0 && color->elt[3] == 1) \
4227 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4228 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4229 color->elt[2] == 1 && color->elt[3] == 1) \
4230 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4231 } while (false)
4232
4233 if (is_integer)
4234 simple_border_types(ui);
4235 else
4236 simple_border_types(f);
4237
4238 #undef simple_border_types
4239
4240 int i;
4241
4242 /* Check if the border has been uploaded already. */
4243 for (i = 0; i < sctx->border_color_count; i++)
4244 if (memcmp(&sctx->border_color_table[i], color,
4245 sizeof(*color)) == 0)
4246 break;
4247
4248 if (i >= SI_MAX_BORDER_COLORS) {
4249 /* Getting 4096 unique border colors is very unlikely. */
4250 fprintf(stderr, "radeonsi: The border color table is full. "
4251 "Any new border colors will be just black. "
4252 "Please file a bug.\n");
4253 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4254 }
4255
4256 if (i == sctx->border_color_count) {
4257 /* Upload a new border color. */
4258 memcpy(&sctx->border_color_table[i], color,
4259 sizeof(*color));
4260 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4261 color, sizeof(*color));
4262 sctx->border_color_count++;
4263 }
4264
4265 return S_008F3C_BORDER_COLOR_PTR(i) |
4266 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4267 }
4268
4269 static inline int S_FIXED(float value, unsigned frac_bits)
4270 {
4271 return value * (1 << frac_bits);
4272 }
4273
4274 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4275 {
4276 if (filter == PIPE_TEX_FILTER_LINEAR)
4277 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4278 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4279 else
4280 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4281 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4282 }
4283
4284 static inline unsigned si_tex_aniso_filter(unsigned filter)
4285 {
4286 if (filter < 2)
4287 return 0;
4288 if (filter < 4)
4289 return 1;
4290 if (filter < 8)
4291 return 2;
4292 if (filter < 16)
4293 return 3;
4294 return 4;
4295 }
4296
4297 static void *si_create_sampler_state(struct pipe_context *ctx,
4298 const struct pipe_sampler_state *state)
4299 {
4300 struct si_context *sctx = (struct si_context *)ctx;
4301 struct si_screen *sscreen = sctx->screen;
4302 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4303 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4304 : state->max_anisotropy;
4305 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4306 union pipe_color_union clamped_border_color;
4307
4308 if (!rstate) {
4309 return NULL;
4310 }
4311
4312 #ifdef DEBUG
4313 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4314 #endif
4315 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4316 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4317 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4318 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4319 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4320 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4321 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4322 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4323 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4324 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4325 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4326 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4327 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4328 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4329 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4330 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4331 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4332 S_008F38_MIP_POINT_PRECLAMP(0) |
4333 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4334 S_008F38_FILTER_PREC_FIX(1) |
4335 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4336 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4337
4338 /* Create sampler resource for integer textures. */
4339 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4340 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4341
4342 /* Create sampler resource for upgraded depth textures. */
4343 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4344
4345 for (unsigned i = 0; i < 4; ++i) {
4346 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4347 * when the border color is 1.0. */
4348 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4349 }
4350
4351 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4352 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4353 else
4354 rstate->upgraded_depth_val[3] =
4355 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4356 S_008F3C_UPGRADED_DEPTH(1);
4357
4358 return rstate;
4359 }
4360
4361 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4362 {
4363 struct si_context *sctx = (struct si_context *)ctx;
4364
4365 if (sctx->sample_mask == (uint16_t)sample_mask)
4366 return;
4367
4368 sctx->sample_mask = sample_mask;
4369 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4370 }
4371
4372 static void si_emit_sample_mask(struct si_context *sctx)
4373 {
4374 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4375 unsigned mask = sctx->sample_mask;
4376
4377 /* Needed for line and polygon smoothing as well as for the Polaris
4378 * small primitive filter. We expect the state tracker to take care of
4379 * this for us.
4380 */
4381 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4382 (mask & 1 && sctx->blitter->running));
4383
4384 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4385 radeon_emit(cs, mask | (mask << 16));
4386 radeon_emit(cs, mask | (mask << 16));
4387 }
4388
4389 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4390 {
4391 #ifdef DEBUG
4392 struct si_sampler_state *s = state;
4393
4394 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4395 s->magic = 0;
4396 #endif
4397 free(state);
4398 }
4399
4400 /*
4401 * Vertex elements & buffers
4402 */
4403
4404 struct util_fast_udiv_info32 {
4405 unsigned multiplier; /* the "magic number" multiplier */
4406 unsigned pre_shift; /* shift for the dividend before multiplying */
4407 unsigned post_shift; /* shift for the dividend after multiplying */
4408 int increment; /* 0 or 1; if set then increment the numerator, using one of
4409 the two strategies */
4410 };
4411
4412 static struct util_fast_udiv_info32
4413 util_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4414 {
4415 struct util_fast_udiv_info info =
4416 util_compute_fast_udiv_info(D, num_bits, 32);
4417
4418 struct util_fast_udiv_info32 result = {
4419 info.multiplier,
4420 info.pre_shift,
4421 info.post_shift,
4422 info.increment,
4423 };
4424 return result;
4425 }
4426
4427 static void *si_create_vertex_elements(struct pipe_context *ctx,
4428 unsigned count,
4429 const struct pipe_vertex_element *elements)
4430 {
4431 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4432 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4433 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4434 struct util_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4435 STATIC_ASSERT(sizeof(struct util_fast_udiv_info32) == 16);
4436 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4437 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4438 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4439 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4440 int i;
4441
4442 assert(count <= SI_MAX_ATTRIBS);
4443 if (!v)
4444 return NULL;
4445
4446 v->count = count;
4447 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4448
4449 for (i = 0; i < count; ++i) {
4450 const struct util_format_description *desc;
4451 const struct util_format_channel_description *channel;
4452 unsigned data_format, num_format;
4453 int first_non_void;
4454 unsigned vbo_index = elements[i].vertex_buffer_index;
4455 unsigned char swizzle[4];
4456
4457 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4458 FREE(v);
4459 return NULL;
4460 }
4461
4462 unsigned instance_divisor = elements[i].instance_divisor;
4463 if (instance_divisor) {
4464 v->uses_instance_divisors = true;
4465
4466 if (instance_divisor == 1) {
4467 v->instance_divisor_is_one |= 1u << i;
4468 } else {
4469 v->instance_divisor_is_fetched |= 1u << i;
4470 divisor_factors[i] =
4471 util_compute_fast_udiv_info32(instance_divisor, 32);
4472 }
4473 }
4474
4475 if (!used[vbo_index]) {
4476 v->first_vb_use_mask |= 1 << i;
4477 used[vbo_index] = true;
4478 }
4479
4480 desc = util_format_description(elements[i].src_format);
4481 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4482 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4483 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4484 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4485 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4486
4487 v->format_size[i] = desc->block.bits / 8;
4488 v->src_offset[i] = elements[i].src_offset;
4489 v->vertex_buffer_index[i] = vbo_index;
4490
4491 /* The hardware always treats the 2-bit alpha channel as
4492 * unsigned, so a shader workaround is needed. The affected
4493 * chips are VI and older except Stoney (GFX8.1).
4494 */
4495 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4496 sscreen->info.chip_class <= VI &&
4497 sscreen->info.family != CHIP_STONEY) {
4498 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4499 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4500 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4501 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4502 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4503 /* This isn't actually used in OpenGL. */
4504 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4505 }
4506 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4507 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4508 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4509 else
4510 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4511 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4512 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4513 if (channel->normalized) {
4514 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4515 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4516 else
4517 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4518 } else {
4519 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4520 }
4521 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4522 if (channel->normalized) {
4523 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4524 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4525 else
4526 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4527 } else {
4528 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4529 }
4530 }
4531 } else if (channel && channel->size == 64 &&
4532 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4533 switch (desc->nr_channels) {
4534 case 1:
4535 case 2:
4536 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4537 swizzle[0] = PIPE_SWIZZLE_X;
4538 swizzle[1] = PIPE_SWIZZLE_Y;
4539 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4540 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4541 break;
4542 case 3:
4543 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4544 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4545 swizzle[1] = PIPE_SWIZZLE_Y;
4546 swizzle[2] = PIPE_SWIZZLE_0;
4547 swizzle[3] = PIPE_SWIZZLE_0;
4548 break;
4549 case 4:
4550 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4551 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4552 swizzle[1] = PIPE_SWIZZLE_Y;
4553 swizzle[2] = PIPE_SWIZZLE_Z;
4554 swizzle[3] = PIPE_SWIZZLE_W;
4555 break;
4556 default:
4557 assert(0);
4558 }
4559 } else if (channel && desc->nr_channels == 3) {
4560 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4561
4562 if (channel->size == 8) {
4563 if (channel->pure_integer)
4564 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4565 else
4566 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4567 } else if (channel->size == 16) {
4568 if (channel->pure_integer)
4569 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4570 else
4571 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4572 }
4573 }
4574
4575 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4576 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4577 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4578 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4579 S_008F0C_NUM_FORMAT(num_format) |
4580 S_008F0C_DATA_FORMAT(data_format);
4581 }
4582
4583 if (v->instance_divisor_is_fetched) {
4584 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4585
4586 v->instance_divisor_factor_buffer =
4587 (struct r600_resource*)
4588 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4589 num_divisors * sizeof(divisor_factors[0]));
4590 if (!v->instance_divisor_factor_buffer) {
4591 FREE(v);
4592 return NULL;
4593 }
4594 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4595 NULL, PIPE_TRANSFER_WRITE);
4596 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4597 }
4598 return v;
4599 }
4600
4601 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4602 {
4603 struct si_context *sctx = (struct si_context *)ctx;
4604 struct si_vertex_elements *old = sctx->vertex_elements;
4605 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4606
4607 sctx->vertex_elements = v;
4608 sctx->vertex_buffers_dirty = true;
4609
4610 if (v &&
4611 (!old ||
4612 old->count != v->count ||
4613 old->uses_instance_divisors != v->uses_instance_divisors ||
4614 v->uses_instance_divisors || /* we don't check which divisors changed */
4615 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4616 sctx->do_update_shaders = true;
4617
4618 if (v && v->instance_divisor_is_fetched) {
4619 struct pipe_constant_buffer cb;
4620
4621 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4622 cb.user_buffer = NULL;
4623 cb.buffer_offset = 0;
4624 cb.buffer_size = 0xffffffff;
4625 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4626 }
4627 }
4628
4629 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4630 {
4631 struct si_context *sctx = (struct si_context *)ctx;
4632 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4633
4634 if (sctx->vertex_elements == state)
4635 sctx->vertex_elements = NULL;
4636 r600_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4637 FREE(state);
4638 }
4639
4640 static void si_set_vertex_buffers(struct pipe_context *ctx,
4641 unsigned start_slot, unsigned count,
4642 const struct pipe_vertex_buffer *buffers)
4643 {
4644 struct si_context *sctx = (struct si_context *)ctx;
4645 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4646 int i;
4647
4648 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4649
4650 if (buffers) {
4651 for (i = 0; i < count; i++) {
4652 const struct pipe_vertex_buffer *src = buffers + i;
4653 struct pipe_vertex_buffer *dsti = dst + i;
4654 struct pipe_resource *buf = src->buffer.resource;
4655
4656 pipe_resource_reference(&dsti->buffer.resource, buf);
4657 dsti->buffer_offset = src->buffer_offset;
4658 dsti->stride = src->stride;
4659 si_context_add_resource_size(sctx, buf);
4660 if (buf)
4661 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4662 }
4663 } else {
4664 for (i = 0; i < count; i++) {
4665 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4666 }
4667 }
4668 sctx->vertex_buffers_dirty = true;
4669 }
4670
4671 /*
4672 * Misc
4673 */
4674
4675 static void si_set_tess_state(struct pipe_context *ctx,
4676 const float default_outer_level[4],
4677 const float default_inner_level[2])
4678 {
4679 struct si_context *sctx = (struct si_context *)ctx;
4680 struct pipe_constant_buffer cb;
4681 float array[8];
4682
4683 memcpy(array, default_outer_level, sizeof(float) * 4);
4684 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4685
4686 cb.buffer = NULL;
4687 cb.user_buffer = NULL;
4688 cb.buffer_size = sizeof(array);
4689
4690 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4691 (void*)array, sizeof(array),
4692 &cb.buffer_offset);
4693
4694 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4695 pipe_resource_reference(&cb.buffer, NULL);
4696 }
4697
4698 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4699 {
4700 struct si_context *sctx = (struct si_context *)ctx;
4701
4702 si_update_fb_dirtiness_after_rendering(sctx);
4703
4704 /* Multisample surfaces are flushed in si_decompress_textures. */
4705 if (sctx->framebuffer.uncompressed_cb_mask)
4706 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4707 sctx->framebuffer.CB_has_shader_readable_metadata);
4708 }
4709
4710 /* This only ensures coherency for shader image/buffer stores. */
4711 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4712 {
4713 struct si_context *sctx = (struct si_context *)ctx;
4714
4715 /* Subsequent commands must wait for all shader invocations to
4716 * complete. */
4717 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4718 SI_CONTEXT_CS_PARTIAL_FLUSH;
4719
4720 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4721 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4722 SI_CONTEXT_INV_VMEM_L1;
4723
4724 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4725 PIPE_BARRIER_SHADER_BUFFER |
4726 PIPE_BARRIER_TEXTURE |
4727 PIPE_BARRIER_IMAGE |
4728 PIPE_BARRIER_STREAMOUT_BUFFER |
4729 PIPE_BARRIER_GLOBAL_BUFFER)) {
4730 /* As far as I can tell, L1 contents are written back to L2
4731 * automatically at end of shader, but the contents of other
4732 * L1 caches might still be stale. */
4733 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4734 }
4735
4736 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4737 /* Indices are read through TC L2 since VI.
4738 * L1 isn't used.
4739 */
4740 if (sctx->screen->info.chip_class <= CIK)
4741 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4742 }
4743
4744 /* MSAA color, any depth and any stencil are flushed in
4745 * si_decompress_textures when needed.
4746 */
4747 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4748 sctx->framebuffer.uncompressed_cb_mask) {
4749 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4750
4751 if (sctx->chip_class <= VI)
4752 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4753 }
4754
4755 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4756 if (sctx->screen->info.chip_class <= VI &&
4757 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4758 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4759 }
4760
4761 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4762 {
4763 struct pipe_blend_state blend;
4764
4765 memset(&blend, 0, sizeof(blend));
4766 blend.independent_blend_enable = true;
4767 blend.rt[0].colormask = 0xf;
4768 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4769 }
4770
4771 static void si_init_config(struct si_context *sctx);
4772
4773 void si_init_state_functions(struct si_context *sctx)
4774 {
4775 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4776 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4777 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4778 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4779 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4780 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4781 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4782 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4783 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4784 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4785 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4786
4787 sctx->b.create_blend_state = si_create_blend_state;
4788 sctx->b.bind_blend_state = si_bind_blend_state;
4789 sctx->b.delete_blend_state = si_delete_blend_state;
4790 sctx->b.set_blend_color = si_set_blend_color;
4791
4792 sctx->b.create_rasterizer_state = si_create_rs_state;
4793 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4794 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4795
4796 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4797 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4798 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4799
4800 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4801 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4802 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4803 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4804 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4805
4806 sctx->b.set_clip_state = si_set_clip_state;
4807 sctx->b.set_stencil_ref = si_set_stencil_ref;
4808
4809 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4810
4811 sctx->b.create_sampler_state = si_create_sampler_state;
4812 sctx->b.delete_sampler_state = si_delete_sampler_state;
4813
4814 sctx->b.create_sampler_view = si_create_sampler_view;
4815 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4816
4817 sctx->b.set_sample_mask = si_set_sample_mask;
4818
4819 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4820 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4821 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4822 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4823
4824 sctx->b.texture_barrier = si_texture_barrier;
4825 sctx->b.memory_barrier = si_memory_barrier;
4826 sctx->b.set_min_samples = si_set_min_samples;
4827 sctx->b.set_tess_state = si_set_tess_state;
4828
4829 sctx->b.set_active_query_state = si_set_active_query_state;
4830
4831 sctx->b.draw_vbo = si_draw_vbo;
4832
4833 si_init_config(sctx);
4834 }
4835
4836 void si_init_screen_state_functions(struct si_screen *sscreen)
4837 {
4838 sscreen->b.is_format_supported = si_is_format_supported;
4839 }
4840
4841 static void si_set_grbm_gfx_index(struct si_context *sctx,
4842 struct si_pm4_state *pm4, unsigned value)
4843 {
4844 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4845 R_00802C_GRBM_GFX_INDEX;
4846 si_pm4_set_reg(pm4, reg, value);
4847 }
4848
4849 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4850 struct si_pm4_state *pm4, unsigned se)
4851 {
4852 assert(se == ~0 || se < sctx->screen->info.max_se);
4853 si_set_grbm_gfx_index(sctx, pm4,
4854 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4855 S_030800_SE_INDEX(se)) |
4856 S_030800_SH_BROADCAST_WRITES(1) |
4857 S_030800_INSTANCE_BROADCAST_WRITES(1));
4858 }
4859
4860 static void
4861 si_write_harvested_raster_configs(struct si_context *sctx,
4862 struct si_pm4_state *pm4,
4863 unsigned raster_config,
4864 unsigned raster_config_1)
4865 {
4866 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4867 unsigned raster_config_se[4];
4868 unsigned se;
4869
4870 ac_get_harvested_configs(&sctx->screen->info,
4871 raster_config,
4872 &raster_config_1,
4873 raster_config_se);
4874
4875 for (se = 0; se < num_se; se++) {
4876 si_set_grbm_gfx_index_se(sctx, pm4, se);
4877 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4878 }
4879 si_set_grbm_gfx_index(sctx, pm4, ~0);
4880
4881 if (sctx->chip_class >= CIK) {
4882 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4883 }
4884 }
4885
4886 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4887 {
4888 struct si_screen *sscreen = sctx->screen;
4889 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4890 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4891 unsigned raster_config = sscreen->pa_sc_raster_config;
4892 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4893
4894 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4895 /* Always use the default config when all backends are enabled
4896 * (or when we failed to determine the enabled backends).
4897 */
4898 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4899 raster_config);
4900 if (sctx->chip_class >= CIK)
4901 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4902 raster_config_1);
4903 } else {
4904 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4905 }
4906 }
4907
4908 static void si_init_config(struct si_context *sctx)
4909 {
4910 struct si_screen *sscreen = sctx->screen;
4911 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4912 bool has_clear_state = sscreen->has_clear_state;
4913 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4914
4915 /* SI, radeon kernel disabled CLEAR_STATE. */
4916 assert(has_clear_state || sscreen->info.chip_class == SI ||
4917 sscreen->info.drm_major != 3);
4918
4919 if (!pm4)
4920 return;
4921
4922 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4923 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4924 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4925 si_pm4_cmd_end(pm4, false);
4926
4927 if (has_clear_state) {
4928 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4929 si_pm4_cmd_add(pm4, 0);
4930 si_pm4_cmd_end(pm4, false);
4931 }
4932
4933 if (sctx->chip_class <= VI)
4934 si_set_raster_config(sctx, pm4);
4935
4936 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4937 if (!has_clear_state)
4938 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4939
4940 /* FIXME calculate these values somehow ??? */
4941 if (sctx->chip_class <= VI) {
4942 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4943 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4944 }
4945
4946 if (!has_clear_state) {
4947 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4948 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4949 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4950 }
4951
4952 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4953 if (!has_clear_state)
4954 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4955 if (sctx->chip_class < CIK)
4956 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4957 S_008A14_CLIP_VTX_REORDER_ENA(1));
4958
4959 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4960 * I don't know why. Deduced by trial and error.
4961 */
4962 if (sctx->chip_class <= CIK) {
4963 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4964 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4965 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4966 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4967 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4968 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4969 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4970 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4971 }
4972
4973 if (!has_clear_state) {
4974 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4975 S_028230_ER_TRI(0xA) |
4976 S_028230_ER_POINT(0xA) |
4977 S_028230_ER_RECT(0xA) |
4978 /* Required by DX10_DIAMOND_TEST_ENA: */
4979 S_028230_ER_LINE_LR(0x1A) |
4980 S_028230_ER_LINE_RL(0x26) |
4981 S_028230_ER_LINE_TB(0xA) |
4982 S_028230_ER_LINE_BT(0xA));
4983 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4984 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4985 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4986 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4987 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4988 }
4989
4990 if (sctx->chip_class >= GFX9) {
4991 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4992 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4993 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4994 } else {
4995 /* These registers, when written, also overwrite the CLEAR_STATE
4996 * context, so we can't rely on CLEAR_STATE setting them.
4997 * It would be an issue if there was another UMD changing them.
4998 */
4999 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5000 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5001 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5002 }
5003
5004 if (sctx->chip_class >= CIK) {
5005 if (sctx->chip_class >= GFX9) {
5006 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5007 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5008 } else {
5009 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5010 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5011 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5012 S_00B41C_WAVE_LIMIT(0x3F));
5013 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5014 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5015
5016 /* If this is 0, Bonaire can hang even if GS isn't being used.
5017 * Other chips are unaffected. These are suboptimal values,
5018 * but we don't use on-chip GS.
5019 */
5020 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5021 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5022 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5023 }
5024 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5025 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5026
5027 /* Compute LATE_ALLOC_VS.LIMIT. */
5028 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5029 unsigned late_alloc_limit; /* The limit is per SH. */
5030
5031 if (sctx->family == CHIP_KABINI) {
5032 late_alloc_limit = 0; /* Potential hang on Kabini. */
5033 } else if (num_cu_per_sh <= 4) {
5034 /* Too few available compute units per SH. Disallowing
5035 * VS to run on one CU could hurt us more than late VS
5036 * allocation would help.
5037 *
5038 * 2 is the highest safe number that allows us to keep
5039 * all CUs enabled.
5040 */
5041 late_alloc_limit = 2;
5042 } else {
5043 /* This is a good initial value, allowing 1 late_alloc
5044 * wave per SIMD on num_cu - 2.
5045 */
5046 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5047
5048 /* The limit is 0-based, so 0 means 1. */
5049 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5050 late_alloc_limit -= 1;
5051 }
5052
5053 /* VS can't execute on one CU if the limit is > 2. */
5054 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5055 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5056 S_00B118_WAVE_LIMIT(0x3F));
5057 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5058 S_00B11C_LIMIT(late_alloc_limit));
5059 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5060 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5061 }
5062
5063 if (sctx->chip_class >= VI) {
5064 unsigned vgt_tess_distribution;
5065
5066 vgt_tess_distribution =
5067 S_028B50_ACCUM_ISOLINE(32) |
5068 S_028B50_ACCUM_TRI(11) |
5069 S_028B50_ACCUM_QUAD(11) |
5070 S_028B50_DONUT_SPLIT(16);
5071
5072 /* Testing with Unigine Heaven extreme tesselation yielded best results
5073 * with TRAP_SPLIT = 3.
5074 */
5075 if (sctx->family == CHIP_FIJI ||
5076 sctx->family >= CHIP_POLARIS10)
5077 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5078
5079 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5080 } else if (!has_clear_state) {
5081 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5082 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5083 }
5084
5085 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5086 if (sctx->chip_class >= CIK) {
5087 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5088 S_028084_ADDRESS(border_color_va >> 40));
5089 }
5090 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5091 RADEON_PRIO_BORDER_COLORS);
5092
5093 if (sctx->chip_class >= GFX9) {
5094 unsigned num_se = sscreen->info.max_se;
5095 unsigned pc_lines = 0;
5096
5097 switch (sctx->family) {
5098 case CHIP_VEGA10:
5099 case CHIP_VEGA12:
5100 case CHIP_VEGA20:
5101 pc_lines = 4096;
5102 break;
5103 case CHIP_RAVEN:
5104 case CHIP_RAVEN2:
5105 pc_lines = 1024;
5106 break;
5107 default:
5108 assert(0);
5109 }
5110
5111 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5112 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5113 S_028C48_MAX_PRIM_PER_BATCH(1023));
5114 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5115 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5116 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5117 }
5118
5119 si_pm4_upload_indirect_buffer(sctx, pm4);
5120 sctx->init_config = pm4;
5121 }