radeonsi: kill point size VS output if it's not used by the rasterizer
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "si_query.h"
27 #include "sid.h"
28 #include "util/fast_idiv_by_const.h"
29 #include "util/format/u_format.h"
30 #include "util/format/u_format_s3tc.h"
31 #include "util/u_dual_blend.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_blend.h"
36
37 #include "gfx10_format_table.h"
38
39 static unsigned si_map_swizzle(unsigned swizzle)
40 {
41 switch (swizzle) {
42 case PIPE_SWIZZLE_Y:
43 return V_008F0C_SQ_SEL_Y;
44 case PIPE_SWIZZLE_Z:
45 return V_008F0C_SQ_SEL_Z;
46 case PIPE_SWIZZLE_W:
47 return V_008F0C_SQ_SEL_W;
48 case PIPE_SWIZZLE_0:
49 return V_008F0C_SQ_SEL_0;
50 case PIPE_SWIZZLE_1:
51 return V_008F0C_SQ_SEL_1;
52 default: /* PIPE_SWIZZLE_X */
53 return V_008F0C_SQ_SEL_X;
54 }
55 }
56
57 /* 12.4 fixed-point */
58 static unsigned si_pack_float_12p4(float x)
59 {
60 return x <= 0 ? 0 : x >= 4096 ? 0xffff : x * 16;
61 }
62
63 /*
64 * Inferred framebuffer and blender state.
65 *
66 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
67 * if there is not enough PS outputs.
68 */
69 static void si_emit_cb_render_state(struct si_context *sctx)
70 {
71 struct radeon_cmdbuf *cs = sctx->gfx_cs;
72 struct si_state_blend *blend = sctx->queued.named.blend;
73 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
74 * but you never know. */
75 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_mask;
76 unsigned i;
77
78 /* Avoid a hang that happens when dual source blending is enabled
79 * but there is not enough color outputs. This is undefined behavior,
80 * so disable color writes completely.
81 *
82 * Reproducible with Unigine Heaven 4.0 and drirc missing.
83 */
84 if (blend->dual_src_blend && sctx->ps_shader.cso &&
85 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
86 cb_target_mask = 0;
87
88 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
89 * I think we don't have to do anything between IBs.
90 */
91 if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask) {
92 sctx->last_cb_target_mask = cb_target_mask;
93
94 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
95 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
96 }
97
98 unsigned initial_cdw = cs->current.cdw;
99 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
100 cb_target_mask);
101
102 if (sctx->chip_class >= GFX8) {
103 /* DCC MSAA workaround.
104 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
105 * COMBINER_DISABLE, but that would be more complicated.
106 */
107 bool oc_disable =
108 blend->dcc_msaa_corruption_4bit & cb_target_mask && sctx->framebuffer.nr_samples >= 2;
109 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
110
111 radeon_opt_set_context_reg(
112 sctx, R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
113 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
114 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
115 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
116 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->info.has_dcc_constant_encode));
117 }
118
119 /* RB+ register settings. */
120 if (sctx->screen->info.rbplus_allowed) {
121 unsigned spi_shader_col_format =
122 sctx->ps_shader.cso ? sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format
123 : 0;
124 unsigned sx_ps_downconvert = 0;
125 unsigned sx_blend_opt_epsilon = 0;
126 unsigned sx_blend_opt_control = 0;
127
128 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
129 struct si_surface *surf = (struct si_surface *)sctx->framebuffer.state.cbufs[i];
130 unsigned format, swap, spi_format, colormask;
131 bool has_alpha, has_rgb;
132
133 if (!surf) {
134 /* If the color buffer is not set, the driver sets 32_R
135 * as the SPI color format, because the hw doesn't allow
136 * holes between color outputs, so also set this to
137 * enable RB+.
138 */
139 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
140 continue;
141 }
142
143 format = G_028C70_FORMAT(surf->cb_color_info);
144 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
145 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
146 colormask = (cb_target_mask >> (i * 4)) & 0xf;
147
148 /* Set if RGB and A are present. */
149 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
150
151 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 ||
152 format == V_028C70_COLOR_32)
153 has_rgb = !has_alpha;
154 else
155 has_rgb = true;
156
157 /* Check the colormask and export format. */
158 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
159 has_rgb = false;
160 if (!(colormask & PIPE_MASK_A))
161 has_alpha = false;
162
163 if (spi_format == V_028714_SPI_SHADER_ZERO) {
164 has_rgb = false;
165 has_alpha = false;
166 }
167
168 /* Disable value checking for disabled channels. */
169 if (!has_rgb)
170 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
171 if (!has_alpha)
172 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
173
174 /* Enable down-conversion for 32bpp and smaller formats. */
175 switch (format) {
176 case V_028C70_COLOR_8:
177 case V_028C70_COLOR_8_8:
178 case V_028C70_COLOR_8_8_8_8:
179 /* For 1 and 2-channel formats, use the superset thereof. */
180 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
181 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
182 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
183 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
184 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
185 }
186 break;
187
188 case V_028C70_COLOR_5_6_5:
189 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_1_5_5_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_4_4_4_4:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_32:
210 if (swap == V_028C70_SWAP_STD && spi_format == V_028714_SPI_SHADER_32_R)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
212 else if (swap == V_028C70_SWAP_ALT_REV && spi_format == V_028714_SPI_SHADER_32_AR)
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
214 break;
215
216 case V_028C70_COLOR_16:
217 case V_028C70_COLOR_16_16:
218 /* For 1-channel formats, use the superset thereof. */
219 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
220 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
221 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
222 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
223 if (swap == V_028C70_SWAP_STD || swap == V_028C70_SWAP_STD_REV)
224 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
225 else
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
227 }
228 break;
229
230 case V_028C70_COLOR_10_11_11:
231 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
233 break;
234
235 case V_028C70_COLOR_2_10_10_10:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_5_9_9_9:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4);
245 break;
246 }
247 }
248
249 /* If there are no color outputs, the first color export is
250 * always enabled as 32_R, so also set this to enable RB+.
251 */
252 if (!sx_ps_downconvert)
253 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
254
255 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
256 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
257 sx_ps_downconvert, sx_blend_opt_epsilon, sx_blend_opt_control);
258 }
259 if (initial_cdw != cs->current.cdw)
260 sctx->context_roll = true;
261 }
262
263 /*
264 * Blender functions
265 */
266
267 static uint32_t si_translate_blend_function(int blend_func)
268 {
269 switch (blend_func) {
270 case PIPE_BLEND_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case PIPE_BLEND_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case PIPE_BLEND_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case PIPE_BLEND_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case PIPE_BLEND_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 PRINT_ERR("Unknown blend function %d\n", blend_func);
282 assert(0);
283 break;
284 }
285 return 0;
286 }
287
288 static uint32_t si_translate_blend_factor(int blend_fact)
289 {
290 switch (blend_fact) {
291 case PIPE_BLENDFACTOR_ONE:
292 return V_028780_BLEND_ONE;
293 case PIPE_BLENDFACTOR_SRC_COLOR:
294 return V_028780_BLEND_SRC_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA:
296 return V_028780_BLEND_SRC_ALPHA;
297 case PIPE_BLENDFACTOR_DST_ALPHA:
298 return V_028780_BLEND_DST_ALPHA;
299 case PIPE_BLENDFACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE;
303 case PIPE_BLENDFACTOR_CONST_COLOR:
304 return V_028780_BLEND_CONSTANT_COLOR;
305 case PIPE_BLENDFACTOR_CONST_ALPHA:
306 return V_028780_BLEND_CONSTANT_ALPHA;
307 case PIPE_BLENDFACTOR_ZERO:
308 return V_028780_BLEND_ZERO;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA:
324 return V_028780_BLEND_SRC1_ALPHA;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
326 return V_028780_BLEND_INV_SRC1_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
331 assert(0);
332 break;
333 }
334 return 0;
335 }
336
337 static uint32_t si_translate_blend_opt_function(int blend_func)
338 {
339 switch (blend_func) {
340 case PIPE_BLEND_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case PIPE_BLEND_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case PIPE_BLEND_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case PIPE_BLEND_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case PIPE_BLEND_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
356 {
357 switch (blend_fact) {
358 case PIPE_BLENDFACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case PIPE_BLENDFACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case PIPE_BLENDFACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 static void si_blend_check_commutativity(struct si_screen *sscreen, struct si_state_blend *blend,
381 enum pipe_blend_func func, enum pipe_blendfactor src,
382 enum pipe_blendfactor dst, unsigned chanmask)
383 {
384 /* Src factor is allowed when it does not depend on Dst */
385 static const uint32_t src_allowed =
386 (1u << PIPE_BLENDFACTOR_ONE) | (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
387 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
388 (1u << PIPE_BLENDFACTOR_CONST_COLOR) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
389 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
390 (1u << PIPE_BLENDFACTOR_ZERO) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
393 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
394
395 if (dst == PIPE_BLENDFACTOR_ONE && (src_allowed & (1u << src))) {
396 /* Addition is commutative, but floating point addition isn't
397 * associative: subtle changes can be introduced via different
398 * rounding.
399 *
400 * Out-of-order is also non-deterministic, which means that
401 * this breaks OpenGL invariance requirements. So only enable
402 * out-of-order additive blending if explicitly allowed by a
403 * setting.
404 */
405 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
406 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
407 blend->commutative_4bit |= chanmask;
408 }
409 }
410
411 /**
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
414 */
415 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor, unsigned *dst_factor,
416 unsigned expected_dst, unsigned replacement_src)
417 {
418 if (*src_factor == expected_dst && *dst_factor == PIPE_BLENDFACTOR_ZERO) {
419 *src_factor = PIPE_BLENDFACTOR_ZERO;
420 *dst_factor = replacement_src;
421
422 /* Commuting the operands requires reversing subtractions. */
423 if (*func == PIPE_BLEND_SUBTRACT)
424 *func = PIPE_BLEND_REVERSE_SUBTRACT;
425 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
426 *func = PIPE_BLEND_SUBTRACT;
427 }
428 }
429
430 static void *si_create_blend_state_mode(struct pipe_context *ctx,
431 const struct pipe_blend_state *state, unsigned mode)
432 {
433 struct si_context *sctx = (struct si_context *)ctx;
434 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
435 struct si_pm4_state *pm4 = &blend->pm4;
436 uint32_t sx_mrt_blend_opt[8] = {0};
437 uint32_t color_control = 0;
438 bool logicop_enable = state->logicop_enable && state->logicop_func != PIPE_LOGICOP_COPY;
439
440 if (!blend)
441 return NULL;
442
443 blend->alpha_to_coverage = state->alpha_to_coverage;
444 blend->alpha_to_one = state->alpha_to_one;
445 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
446 blend->logicop_enable = logicop_enable;
447
448 unsigned num_shader_outputs = state->max_rt + 1; /* estimate */
449 if (blend->dual_src_blend)
450 num_shader_outputs = MAX2(num_shader_outputs, 2);
451
452 if (logicop_enable) {
453 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
454 } else {
455 color_control |= S_028808_ROP3(0xcc);
456 }
457
458 if (state->alpha_to_coverage && state->alpha_to_coverage_dither) {
459 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
460 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
461 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
462 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
463 S_028B70_OFFSET_ROUND(1));
464 } else {
465 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
466 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
467 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
468 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
469 S_028B70_OFFSET_ROUND(0));
470 }
471
472 if (state->alpha_to_coverage)
473 blend->need_src_alpha_4bit |= 0xf;
474
475 blend->cb_target_mask = 0;
476 blend->cb_target_enabled_4bit = 0;
477
478 for (int i = 0; i < num_shader_outputs; i++) {
479 /* state->rt entries > 0 only written if independent blending */
480 const int j = state->independent_blend_enable ? i : 0;
481
482 unsigned eqRGB = state->rt[j].rgb_func;
483 unsigned srcRGB = state->rt[j].rgb_src_factor;
484 unsigned dstRGB = state->rt[j].rgb_dst_factor;
485 unsigned eqA = state->rt[j].alpha_func;
486 unsigned srcA = state->rt[j].alpha_src_factor;
487 unsigned dstA = state->rt[j].alpha_dst_factor;
488
489 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
490 unsigned blend_cntl = 0;
491
492 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
493 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
494
495 /* Only set dual source blending for MRT0 to avoid a hang. */
496 if (i >= 1 && blend->dual_src_blend) {
497 /* Vulkan does this for dual source blending. */
498 if (i == 1)
499 blend_cntl |= S_028780_ENABLE(1);
500
501 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
502 continue;
503 }
504
505 /* Only addition and subtraction equations are supported with
506 * dual source blending.
507 */
508 if (blend->dual_src_blend && (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
509 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
510 assert(!"Unsupported equation for dual source blending");
511 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
512 continue;
513 }
514
515 /* cb_render_state will disable unused ones */
516 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
517 if (state->rt[j].colormask)
518 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
519
520 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
521 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
522 continue;
523 }
524
525 si_blend_check_commutativity(sctx->screen, blend, eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
526 si_blend_check_commutativity(sctx->screen, blend, eqA, srcA, dstA, 0x8 << (4 * i));
527
528 /* Blending optimizations for RB+.
529 * These transformations don't change the behavior.
530 *
531 * First, get rid of DST in the blend factors:
532 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
533 */
534 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, PIPE_BLENDFACTOR_DST_COLOR,
535 PIPE_BLENDFACTOR_SRC_COLOR);
536 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_COLOR,
537 PIPE_BLENDFACTOR_SRC_COLOR);
538 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_ALPHA,
539 PIPE_BLENDFACTOR_SRC_ALPHA);
540
541 /* Look up the ideal settings from tables. */
542 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
543 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
544 srcA_opt = si_translate_blend_opt_factor(srcA, true);
545 dstA_opt = si_translate_blend_opt_factor(dstA, true);
546
547 /* Handle interdependencies. */
548 if (util_blend_factor_uses_dest(srcRGB, false))
549 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
550 if (util_blend_factor_uses_dest(srcA, false))
551 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
552
553 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
554 (dstRGB == PIPE_BLENDFACTOR_ZERO || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
555 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
556 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
557
558 /* Set the final value. */
559 sx_mrt_blend_opt[i] = S_028760_COLOR_SRC_OPT(srcRGB_opt) |
560 S_028760_COLOR_DST_OPT(dstRGB_opt) |
561 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
562 S_028760_ALPHA_SRC_OPT(srcA_opt) | S_028760_ALPHA_DST_OPT(dstA_opt) |
563 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
564
565 /* Set blend state. */
566 blend_cntl |= S_028780_ENABLE(1);
567 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
568 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
569 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
570
571 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
572 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
573 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
574 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
575 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
576 }
577 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
578
579 blend->blend_enable_4bit |= 0xfu << (i * 4);
580
581 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10)
582 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
583
584 /* This is only important for formats without alpha. */
585 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
586 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
587 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
588 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
589 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
590 }
591
592 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10 && logicop_enable)
593 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
594
595 if (blend->cb_target_mask) {
596 color_control |= S_028808_MODE(mode);
597 } else {
598 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
599 }
600
601 if (sctx->screen->info.rbplus_allowed) {
602 /* Disable RB+ blend optimizations for dual source blending.
603 * Vulkan does this.
604 */
605 if (blend->dual_src_blend) {
606 for (int i = 0; i < num_shader_outputs; i++) {
607 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
608 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
609 }
610 }
611
612 for (int i = 0; i < num_shader_outputs; i++)
613 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
614
615 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
616 if (blend->dual_src_blend || logicop_enable || mode == V_028808_CB_RESOLVE)
617 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
618 }
619
620 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
621 return blend;
622 }
623
624 static void *si_create_blend_state(struct pipe_context *ctx, const struct pipe_blend_state *state)
625 {
626 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
627 }
628
629 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
630 {
631 struct si_context *sctx = (struct si_context *)ctx;
632 struct si_state_blend *old_blend = sctx->queued.named.blend;
633 struct si_state_blend *blend = (struct si_state_blend *)state;
634
635 if (!blend)
636 blend = (struct si_state_blend *)sctx->noop_blend;
637
638 si_pm4_bind_state(sctx, blend, blend);
639
640 if (old_blend->cb_target_mask != blend->cb_target_mask ||
641 old_blend->dual_src_blend != blend->dual_src_blend ||
642 (old_blend->dcc_msaa_corruption_4bit != blend->dcc_msaa_corruption_4bit &&
643 sctx->framebuffer.nr_samples >= 2 && sctx->screen->dcc_msaa_allowed))
644 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
645
646 if (old_blend->cb_target_mask != blend->cb_target_mask ||
647 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
648 old_blend->alpha_to_one != blend->alpha_to_one ||
649 old_blend->dual_src_blend != blend->dual_src_blend ||
650 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
651 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
652 sctx->do_update_shaders = true;
653
654 if (sctx->screen->dpbb_allowed &&
655 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
656 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
657 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
658 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
659
660 if (sctx->screen->has_out_of_order_rast &&
661 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
662 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
663 old_blend->commutative_4bit != blend->commutative_4bit ||
664 old_blend->logicop_enable != blend->logicop_enable)))
665 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
666 }
667
668 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
669 {
670 struct si_context *sctx = (struct si_context *)ctx;
671
672 if (sctx->queued.named.blend == state)
673 si_bind_blend_state(ctx, sctx->noop_blend);
674
675 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
676 }
677
678 static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state)
679 {
680 struct si_context *sctx = (struct si_context *)ctx;
681 static const struct pipe_blend_color zeros;
682
683 sctx->blend_color.state = *state;
684 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
685 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
686 }
687
688 static void si_emit_blend_color(struct si_context *sctx)
689 {
690 struct radeon_cmdbuf *cs = sctx->gfx_cs;
691
692 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
693 radeon_emit_array(cs, (uint32_t *)sctx->blend_color.state.color, 4);
694 }
695
696 /*
697 * Clipping
698 */
699
700 static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state)
701 {
702 struct si_context *sctx = (struct si_context *)ctx;
703 struct pipe_constant_buffer cb;
704 static const struct pipe_clip_state zeros;
705
706 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
707 return;
708
709 sctx->clip_state.state = *state;
710 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
711 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
712
713 cb.buffer = NULL;
714 cb.user_buffer = state->ucp;
715 cb.buffer_offset = 0;
716 cb.buffer_size = 4 * 4 * 8;
717 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
718 pipe_resource_reference(&cb.buffer, NULL);
719 }
720
721 static void si_emit_clip_state(struct si_context *sctx)
722 {
723 struct radeon_cmdbuf *cs = sctx->gfx_cs;
724
725 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6 * 4);
726 radeon_emit_array(cs, (uint32_t *)sctx->clip_state.state.ucp, 6 * 4);
727 }
728
729 static void si_emit_clip_regs(struct si_context *sctx)
730 {
731 struct si_shader *vs = si_get_vs_state(sctx);
732 struct si_shader_selector *vs_sel = vs->selector;
733 struct si_shader_info *info = &vs_sel->info;
734 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
735 bool window_space = info->stage == MESA_SHADER_VERTEX ?
736 info->base.vs.window_space_position : 0;
737 unsigned clipdist_mask = vs_sel->clipdist_mask;
738 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
739 unsigned culldist_mask = vs_sel->culldist_mask;
740 unsigned total_mask;
741
742 if (vs->key.opt.clip_disable) {
743 assert(!info->base.cull_distance_array_size);
744 clipdist_mask = 0;
745 culldist_mask = 0;
746 }
747 total_mask = clipdist_mask | culldist_mask;
748
749 /* Clip distances on points have no effect, so need to be implemented
750 * as cull distances. This applies for the clipvertex case as well.
751 *
752 * Setting this for primitives other than points should have no adverse
753 * effects.
754 */
755 clipdist_mask &= rs->clip_plane_enable;
756 culldist_mask |= clipdist_mask;
757
758 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
759 unsigned pa_cl_cntl = S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
760 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
761 S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->chip_class >= GFX10_3) |
762 S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->chip_class >= GFX10_3) |
763 clipdist_mask | (culldist_mask << 8);
764
765 if (sctx->chip_class >= GFX10) {
766 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
767 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL, pa_cl_cntl,
768 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
769 } else {
770 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL__CL,
771 vs_sel->pa_cl_vs_out_cntl | pa_cl_cntl);
772 }
773 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
774 rs->pa_cl_clip_cntl | ucp_mask | S_028810_CLIP_DISABLE(window_space));
775
776 if (initial_cdw != sctx->gfx_cs->current.cdw)
777 sctx->context_roll = true;
778 }
779
780 /*
781 * inferred state between framebuffer and rasterizer
782 */
783 static void si_update_poly_offset_state(struct si_context *sctx)
784 {
785 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
786
787 if (!rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
788 si_pm4_bind_state(sctx, poly_offset, NULL);
789 return;
790 }
791
792 /* Use the user format, not db_render_format, so that the polygon
793 * offset behaves as expected by applications.
794 */
795 switch (sctx->framebuffer.state.zsbuf->texture->format) {
796 case PIPE_FORMAT_Z16_UNORM:
797 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
798 break;
799 default: /* 24-bit */
800 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
801 break;
802 case PIPE_FORMAT_Z32_FLOAT:
803 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
804 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
805 break;
806 }
807 }
808
809 /*
810 * Rasterizer
811 */
812
813 static uint32_t si_translate_fill(uint32_t func)
814 {
815 switch (func) {
816 case PIPE_POLYGON_MODE_FILL:
817 return V_028814_X_DRAW_TRIANGLES;
818 case PIPE_POLYGON_MODE_LINE:
819 return V_028814_X_DRAW_LINES;
820 case PIPE_POLYGON_MODE_POINT:
821 return V_028814_X_DRAW_POINTS;
822 default:
823 assert(0);
824 return V_028814_X_DRAW_POINTS;
825 }
826 }
827
828 static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rasterizer_state *state)
829 {
830 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
831 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
832 struct si_pm4_state *pm4 = &rs->pm4;
833 unsigned tmp, i;
834 float psize_min, psize_max;
835
836 if (!rs) {
837 return NULL;
838 }
839
840 if (!state->front_ccw) {
841 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
842 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
843 } else {
844 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
845 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
846 }
847 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
848 rs->provoking_vertex_first = state->flatshade_first;
849 rs->scissor_enable = state->scissor;
850 rs->clip_halfz = state->clip_halfz;
851 rs->two_side = state->light_twoside;
852 rs->multisample_enable = state->multisample;
853 rs->force_persample_interp = state->force_persample_interp;
854 rs->clip_plane_enable = state->clip_plane_enable;
855 rs->half_pixel_center = state->half_pixel_center;
856 rs->line_stipple_enable = state->line_stipple_enable;
857 rs->poly_stipple_enable = state->poly_stipple_enable;
858 rs->line_smooth = state->line_smooth;
859 rs->line_width = state->line_width;
860 rs->poly_smooth = state->poly_smooth;
861 rs->uses_poly_offset = state->offset_point || state->offset_line || state->offset_tri;
862 rs->clamp_fragment_color = state->clamp_fragment_color;
863 rs->clamp_vertex_color = state->clamp_vertex_color;
864 rs->flatshade = state->flatshade;
865 rs->flatshade_first = state->flatshade_first;
866 rs->sprite_coord_enable = state->sprite_coord_enable;
867 rs->rasterizer_discard = state->rasterizer_discard;
868 rs->polygon_mode_enabled =
869 (state->fill_front != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_FRONT)) ||
870 (state->fill_back != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_BACK));
871 rs->polygon_mode_is_lines =
872 (state->fill_front == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_FRONT)) ||
873 (state->fill_back == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_BACK));
874 rs->polygon_mode_is_points =
875 (state->fill_front == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_FRONT)) ||
876 (state->fill_back == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_BACK));
877 rs->pa_sc_line_stipple = state->line_stipple_enable
878 ? S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
879 S_028A0C_REPEAT_COUNT(state->line_stipple_factor)
880 : 0;
881 rs->pa_cl_clip_cntl = S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
882 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
883 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
884 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
885 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
886
887 si_pm4_set_reg(
888 pm4, R_0286D4_SPI_INTERP_CONTROL_0,
889 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
890 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
891 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
892 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
893 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
894 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
895
896 /* point size 12.4 fixed point */
897 tmp = (unsigned)(state->point_size * 8.0);
898 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
899
900 if (state->point_size_per_vertex) {
901 psize_min = util_get_min_point_size(state);
902 psize_max = SI_MAX_POINT_SIZE;
903 } else {
904 /* Force the point size to be as if the vertex output was disabled. */
905 psize_min = state->point_size;
906 psize_max = state->point_size;
907 }
908 rs->max_point_size = psize_max;
909
910 /* Divide by two, because 0.5 = 1 pixel. */
911 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
912 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min / 2)) |
913 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max / 2)));
914
915 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
916 S_028A08_WIDTH(si_pack_float_12p4(state->line_width / 2)));
917 si_pm4_set_reg(
918 pm4, R_028A48_PA_SC_MODE_CNTL_0,
919 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
920 S_028A48_MSAA_ENABLE(state->multisample || state->poly_smooth || state->line_smooth) |
921 S_028A48_VPORT_SCISSOR_ENABLE(1) |
922 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
923
924 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
925 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
926 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
927 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
928 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
929 S_028814_FACE(!state->front_ccw) |
930 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
931 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
932 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
933 S_028814_POLY_MODE(rs->polygon_mode_enabled) |
934 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
935 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
936
937 if (!rs->uses_poly_offset)
938 return rs;
939
940 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
941 if (!rs->pm4_poly_offset) {
942 FREE(rs);
943 return NULL;
944 }
945
946 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
947 for (i = 0; i < 3; i++) {
948 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
949 float offset_units = state->offset_units;
950 float offset_scale = state->offset_scale * 16.0f;
951 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
952
953 if (!state->offset_units_unscaled) {
954 switch (i) {
955 case 0: /* 16-bit zbuffer */
956 offset_units *= 4.0f;
957 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
958 break;
959 case 1: /* 24-bit zbuffer */
960 offset_units *= 2.0f;
961 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
962 break;
963 case 2: /* 32-bit zbuffer */
964 offset_units *= 1.0f;
965 pa_su_poly_offset_db_fmt_cntl =
966 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
967 break;
968 }
969 }
970
971 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale));
972 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
973 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale));
974 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
975 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, pa_su_poly_offset_db_fmt_cntl);
976 }
977
978 return rs;
979 }
980
981 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
982 {
983 struct si_context *sctx = (struct si_context *)ctx;
984 struct si_state_rasterizer *old_rs = (struct si_state_rasterizer *)sctx->queued.named.rasterizer;
985 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
986
987 if (!rs)
988 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
989
990 if (old_rs->multisample_enable != rs->multisample_enable) {
991 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
992
993 /* Update the small primitive filter workaround if necessary. */
994 if (sctx->screen->info.has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1)
995 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
996 }
997
998 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
999 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1000
1001 si_pm4_bind_state(sctx, rasterizer, rs);
1002 si_update_poly_offset_state(sctx);
1003
1004 if (old_rs->scissor_enable != rs->scissor_enable)
1005 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1006
1007 if (old_rs->line_width != rs->line_width || old_rs->max_point_size != rs->max_point_size ||
1008 old_rs->half_pixel_center != rs->half_pixel_center)
1009 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1010
1011 if (old_rs->clip_halfz != rs->clip_halfz)
1012 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1013
1014 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1015 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1016 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1017
1018 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1019 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1020 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1021 old_rs->flatshade != rs->flatshade || old_rs->two_side != rs->two_side ||
1022 old_rs->multisample_enable != rs->multisample_enable ||
1023 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1024 old_rs->poly_smooth != rs->poly_smooth || old_rs->line_smooth != rs->line_smooth ||
1025 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1026 old_rs->force_persample_interp != rs->force_persample_interp ||
1027 old_rs->polygon_mode_is_points != rs->polygon_mode_is_points)
1028 sctx->do_update_shaders = true;
1029 }
1030
1031 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1032 {
1033 struct si_context *sctx = (struct si_context *)ctx;
1034 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1035
1036 if (sctx->queued.named.rasterizer == state)
1037 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1038
1039 FREE(rs->pm4_poly_offset);
1040 si_pm4_delete_state(sctx, rasterizer, rs);
1041 }
1042
1043 /*
1044 * infeered state between dsa and stencil ref
1045 */
1046 static void si_emit_stencil_ref(struct si_context *sctx)
1047 {
1048 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1049 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1050 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1051
1052 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1053 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1054 S_028430_STENCILMASK(dsa->valuemask[0]) |
1055 S_028430_STENCILWRITEMASK(dsa->writemask[0]) | S_028430_STENCILOPVAL(1));
1056 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1057 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1058 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1059 S_028434_STENCILOPVAL_BF(1));
1060 }
1061
1062 static void si_set_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref *state)
1063 {
1064 struct si_context *sctx = (struct si_context *)ctx;
1065
1066 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1067 return;
1068
1069 sctx->stencil_ref.state = *state;
1070 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1071 }
1072
1073 /*
1074 * DSA
1075 */
1076
1077 static uint32_t si_translate_stencil_op(int s_op)
1078 {
1079 switch (s_op) {
1080 case PIPE_STENCIL_OP_KEEP:
1081 return V_02842C_STENCIL_KEEP;
1082 case PIPE_STENCIL_OP_ZERO:
1083 return V_02842C_STENCIL_ZERO;
1084 case PIPE_STENCIL_OP_REPLACE:
1085 return V_02842C_STENCIL_REPLACE_TEST;
1086 case PIPE_STENCIL_OP_INCR:
1087 return V_02842C_STENCIL_ADD_CLAMP;
1088 case PIPE_STENCIL_OP_DECR:
1089 return V_02842C_STENCIL_SUB_CLAMP;
1090 case PIPE_STENCIL_OP_INCR_WRAP:
1091 return V_02842C_STENCIL_ADD_WRAP;
1092 case PIPE_STENCIL_OP_DECR_WRAP:
1093 return V_02842C_STENCIL_SUB_WRAP;
1094 case PIPE_STENCIL_OP_INVERT:
1095 return V_02842C_STENCIL_INVERT;
1096 default:
1097 PRINT_ERR("Unknown stencil op %d", s_op);
1098 assert(0);
1099 break;
1100 }
1101 return 0;
1102 }
1103
1104 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1105 {
1106 return s->enabled && s->writemask &&
1107 (s->fail_op != PIPE_STENCIL_OP_KEEP || s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1108 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1109 }
1110
1111 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1112 {
1113 /* REPLACE is normally order invariant, except when the stencil
1114 * reference value is written by the fragment shader. Tracking this
1115 * interaction does not seem worth the effort, so be conservative. */
1116 return op != PIPE_STENCIL_OP_INCR && op != PIPE_STENCIL_OP_DECR && op != PIPE_STENCIL_OP_REPLACE;
1117 }
1118
1119 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1120 * invariant in the sense that the set of passing fragments as well as the
1121 * final stencil buffer result does not depend on the order of fragments. */
1122 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1123 {
1124 return !state->enabled || !state->writemask ||
1125 /* The following assumes that Z writes are disabled. */
1126 (state->func == PIPE_FUNC_ALWAYS && si_order_invariant_stencil_op(state->zpass_op) &&
1127 si_order_invariant_stencil_op(state->zfail_op)) ||
1128 (state->func == PIPE_FUNC_NEVER && si_order_invariant_stencil_op(state->fail_op));
1129 }
1130
1131 static void *si_create_dsa_state(struct pipe_context *ctx,
1132 const struct pipe_depth_stencil_alpha_state *state)
1133 {
1134 struct si_context *sctx = (struct si_context *)ctx;
1135 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1136 struct si_pm4_state *pm4 = &dsa->pm4;
1137 unsigned db_depth_control;
1138 uint32_t db_stencil_control = 0;
1139
1140 if (!dsa) {
1141 return NULL;
1142 }
1143
1144 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1145 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1146 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1147 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1148
1149 db_depth_control =
1150 S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1151 S_028800_ZFUNC(state->depth.func) | S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1152
1153 /* stencil */
1154 if (state->stencil[0].enabled) {
1155 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1156 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1157 db_stencil_control |=
1158 S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1159 db_stencil_control |=
1160 S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1161 db_stencil_control |=
1162 S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1163
1164 if (state->stencil[1].enabled) {
1165 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1166 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1167 db_stencil_control |=
1168 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1169 db_stencil_control |=
1170 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1171 db_stencil_control |=
1172 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1173 }
1174 }
1175
1176 /* alpha */
1177 if (state->alpha.enabled) {
1178 dsa->alpha_func = state->alpha.func;
1179
1180 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1181 fui(state->alpha.ref_value));
1182 } else {
1183 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1184 }
1185
1186 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1187 if (state->stencil[0].enabled)
1188 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1189 if (state->depth.bounds_test) {
1190 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1191 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1192 }
1193
1194 dsa->depth_enabled = state->depth.enabled;
1195 dsa->depth_write_enabled = state->depth.enabled && state->depth.writemask;
1196 dsa->stencil_enabled = state->stencil[0].enabled;
1197 dsa->stencil_write_enabled =
1198 state->stencil[0].enabled &&
1199 (si_dsa_writes_stencil(&state->stencil[0]) || si_dsa_writes_stencil(&state->stencil[1]));
1200 dsa->db_can_write = dsa->depth_write_enabled || dsa->stencil_write_enabled;
1201
1202 bool zfunc_is_ordered =
1203 state->depth.func == PIPE_FUNC_NEVER || state->depth.func == PIPE_FUNC_LESS ||
1204 state->depth.func == PIPE_FUNC_LEQUAL || state->depth.func == PIPE_FUNC_GREATER ||
1205 state->depth.func == PIPE_FUNC_GEQUAL;
1206
1207 bool nozwrite_and_order_invariant_stencil =
1208 !dsa->db_can_write ||
1209 (!dsa->depth_write_enabled && si_order_invariant_stencil_state(&state->stencil[0]) &&
1210 si_order_invariant_stencil_state(&state->stencil[1]));
1211
1212 dsa->order_invariance[1].zs =
1213 nozwrite_and_order_invariant_stencil || (!dsa->stencil_write_enabled && zfunc_is_ordered);
1214 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1215
1216 dsa->order_invariance[1].pass_set =
1217 nozwrite_and_order_invariant_stencil ||
1218 (!dsa->stencil_write_enabled &&
1219 (state->depth.func == PIPE_FUNC_ALWAYS || state->depth.func == PIPE_FUNC_NEVER));
1220 dsa->order_invariance[0].pass_set =
1221 !dsa->depth_write_enabled ||
1222 (state->depth.func == PIPE_FUNC_ALWAYS || state->depth.func == PIPE_FUNC_NEVER);
1223
1224 dsa->order_invariance[1].pass_last = sctx->screen->assume_no_z_fights &&
1225 !dsa->stencil_write_enabled && dsa->depth_write_enabled &&
1226 zfunc_is_ordered;
1227 dsa->order_invariance[0].pass_last =
1228 sctx->screen->assume_no_z_fights && dsa->depth_write_enabled && zfunc_is_ordered;
1229
1230 return dsa;
1231 }
1232
1233 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1234 {
1235 struct si_context *sctx = (struct si_context *)ctx;
1236 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1237 struct si_state_dsa *dsa = state;
1238
1239 if (!dsa)
1240 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1241
1242 si_pm4_bind_state(sctx, dsa, dsa);
1243
1244 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1245 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1246 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1247 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1248 }
1249
1250 if (old_dsa->alpha_func != dsa->alpha_func)
1251 sctx->do_update_shaders = true;
1252
1253 if (sctx->screen->dpbb_allowed && ((old_dsa->depth_enabled != dsa->depth_enabled ||
1254 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1255 old_dsa->db_can_write != dsa->db_can_write)))
1256 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1257
1258 if (sctx->screen->has_out_of_order_rast &&
1259 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1260 sizeof(old_dsa->order_invariance))))
1261 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1262 }
1263
1264 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1265 {
1266 struct si_context *sctx = (struct si_context *)ctx;
1267
1268 if (sctx->queued.named.dsa == state)
1269 si_bind_dsa_state(ctx, sctx->noop_dsa);
1270
1271 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1272 }
1273
1274 static void *si_create_db_flush_dsa(struct si_context *sctx)
1275 {
1276 struct pipe_depth_stencil_alpha_state dsa = {};
1277
1278 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1279 }
1280
1281 /* DB RENDER STATE */
1282
1283 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1284 {
1285 struct si_context *sctx = (struct si_context *)ctx;
1286
1287 /* Pipeline stat & streamout queries. */
1288 if (enable) {
1289 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1290 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1291 } else {
1292 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1293 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1294 }
1295
1296 /* Occlusion queries. */
1297 if (sctx->occlusion_queries_disabled != !enable) {
1298 sctx->occlusion_queries_disabled = !enable;
1299 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1300 }
1301 }
1302
1303 void si_set_occlusion_query_state(struct si_context *sctx, bool old_perfect_enable)
1304 {
1305 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1306
1307 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1308
1309 if (perfect_enable != old_perfect_enable)
1310 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1311 }
1312
1313 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1314 {
1315 st->saved_compute = sctx->cs_shader_state.program;
1316
1317 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1318 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1319
1320 st->saved_ssbo_writable_mask = 0;
1321
1322 for (unsigned i = 0; i < 3; i++) {
1323 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1324 (1u << si_get_shaderbuf_slot(i)))
1325 st->saved_ssbo_writable_mask |= 1 << i;
1326 }
1327 }
1328
1329 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1330 {
1331 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1332
1333 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1334 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1335
1336 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1337 st->saved_ssbo_writable_mask);
1338 for (unsigned i = 0; i < 3; ++i)
1339 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1340 }
1341
1342 static void si_emit_db_render_state(struct si_context *sctx)
1343 {
1344 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1345 unsigned db_shader_control, db_render_control, db_count_control;
1346 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1347
1348 /* DB_RENDER_CONTROL */
1349 if (sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled) {
1350 db_render_control = S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1351 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1352 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1353 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1354 db_render_control = S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1355 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1356 } else {
1357 db_render_control = S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1358 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1359 }
1360
1361 /* DB_COUNT_CONTROL (occlusion queries) */
1362 if (sctx->num_occlusion_queries > 0 && !sctx->occlusion_queries_disabled) {
1363 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1364 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1365
1366 if (sctx->chip_class >= GFX7) {
1367 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1368
1369 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1370 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1371 S_028004_SAMPLE_RATE(log_sample_rate) | S_028004_ZPASS_ENABLE(1) |
1372 S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
1373 } else {
1374 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1375 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1376 }
1377 } else {
1378 /* Disable occlusion queries. */
1379 if (sctx->chip_class >= GFX7) {
1380 db_count_control = 0;
1381 } else {
1382 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1383 }
1384 }
1385
1386 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1387 db_render_control, db_count_control);
1388
1389 /* DB_RENDER_OVERRIDE2 */
1390 radeon_opt_set_context_reg(
1391 sctx, R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
1392 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1393 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1394 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
1395 S_028010_CENTROID_COMPUTATION_MODE(sctx->chip_class >= GFX10_3 ? 2 : 0));
1396
1397 db_shader_control = sctx->ps_db_shader_control;
1398
1399 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1400 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1401 db_shader_control &= C_02880C_Z_ORDER;
1402 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1403 }
1404
1405 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1406 if (!rs->multisample_enable)
1407 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1408
1409 if (sctx->screen->info.has_rbplus && !sctx->screen->info.rbplus_allowed)
1410 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1411
1412 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1413 db_shader_control);
1414
1415 if (initial_cdw != sctx->gfx_cs->current.cdw)
1416 sctx->context_roll = true;
1417 }
1418
1419 /*
1420 * format translation
1421 */
1422 static uint32_t si_translate_colorformat(enum chip_class chip_class,
1423 enum pipe_format format)
1424 {
1425 const struct util_format_description *desc = util_format_description(format);
1426 if (!desc)
1427 return V_028C70_COLOR_INVALID;
1428
1429 #define HAS_SIZE(x, y, z, w) \
1430 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1431 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1432
1433 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1434 return V_028C70_COLOR_10_11_11;
1435
1436 if (chip_class >= GFX10_3 &&
1437 format == PIPE_FORMAT_R9G9B9E5_FLOAT) /* isn't plain */
1438 return V_028C70_COLOR_5_9_9_9;
1439
1440 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1441 return V_028C70_COLOR_INVALID;
1442
1443 /* hw cannot support mixed formats (except depth/stencil, since
1444 * stencil is not written to). */
1445 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1446 return V_028C70_COLOR_INVALID;
1447
1448 switch (desc->nr_channels) {
1449 case 1:
1450 switch (desc->channel[0].size) {
1451 case 8:
1452 return V_028C70_COLOR_8;
1453 case 16:
1454 return V_028C70_COLOR_16;
1455 case 32:
1456 return V_028C70_COLOR_32;
1457 }
1458 break;
1459 case 2:
1460 if (desc->channel[0].size == desc->channel[1].size) {
1461 switch (desc->channel[0].size) {
1462 case 8:
1463 return V_028C70_COLOR_8_8;
1464 case 16:
1465 return V_028C70_COLOR_16_16;
1466 case 32:
1467 return V_028C70_COLOR_32_32;
1468 }
1469 } else if (HAS_SIZE(8, 24, 0, 0)) {
1470 return V_028C70_COLOR_24_8;
1471 } else if (HAS_SIZE(24, 8, 0, 0)) {
1472 return V_028C70_COLOR_8_24;
1473 }
1474 break;
1475 case 3:
1476 if (HAS_SIZE(5, 6, 5, 0)) {
1477 return V_028C70_COLOR_5_6_5;
1478 } else if (HAS_SIZE(32, 8, 24, 0)) {
1479 return V_028C70_COLOR_X24_8_32_FLOAT;
1480 }
1481 break;
1482 case 4:
1483 if (desc->channel[0].size == desc->channel[1].size &&
1484 desc->channel[0].size == desc->channel[2].size &&
1485 desc->channel[0].size == desc->channel[3].size) {
1486 switch (desc->channel[0].size) {
1487 case 4:
1488 return V_028C70_COLOR_4_4_4_4;
1489 case 8:
1490 return V_028C70_COLOR_8_8_8_8;
1491 case 16:
1492 return V_028C70_COLOR_16_16_16_16;
1493 case 32:
1494 return V_028C70_COLOR_32_32_32_32;
1495 }
1496 } else if (HAS_SIZE(5, 5, 5, 1)) {
1497 return V_028C70_COLOR_1_5_5_5;
1498 } else if (HAS_SIZE(1, 5, 5, 5)) {
1499 return V_028C70_COLOR_5_5_5_1;
1500 } else if (HAS_SIZE(10, 10, 10, 2)) {
1501 return V_028C70_COLOR_2_10_10_10;
1502 }
1503 break;
1504 }
1505 return V_028C70_COLOR_INVALID;
1506 }
1507
1508 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1509 {
1510 if (SI_BIG_ENDIAN) {
1511 switch (colorformat) {
1512 /* 8-bit buffers. */
1513 case V_028C70_COLOR_8:
1514 return V_028C70_ENDIAN_NONE;
1515
1516 /* 16-bit buffers. */
1517 case V_028C70_COLOR_5_6_5:
1518 case V_028C70_COLOR_1_5_5_5:
1519 case V_028C70_COLOR_4_4_4_4:
1520 case V_028C70_COLOR_16:
1521 case V_028C70_COLOR_8_8:
1522 return V_028C70_ENDIAN_8IN16;
1523
1524 /* 32-bit buffers. */
1525 case V_028C70_COLOR_8_8_8_8:
1526 case V_028C70_COLOR_2_10_10_10:
1527 case V_028C70_COLOR_8_24:
1528 case V_028C70_COLOR_24_8:
1529 case V_028C70_COLOR_16_16:
1530 return V_028C70_ENDIAN_8IN32;
1531
1532 /* 64-bit buffers. */
1533 case V_028C70_COLOR_16_16_16_16:
1534 return V_028C70_ENDIAN_8IN16;
1535
1536 case V_028C70_COLOR_32_32:
1537 return V_028C70_ENDIAN_8IN32;
1538
1539 /* 128-bit buffers. */
1540 case V_028C70_COLOR_32_32_32_32:
1541 return V_028C70_ENDIAN_8IN32;
1542 default:
1543 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1544 }
1545 } else {
1546 return V_028C70_ENDIAN_NONE;
1547 }
1548 }
1549
1550 static uint32_t si_translate_dbformat(enum pipe_format format)
1551 {
1552 switch (format) {
1553 case PIPE_FORMAT_Z16_UNORM:
1554 return V_028040_Z_16;
1555 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1556 case PIPE_FORMAT_X8Z24_UNORM:
1557 case PIPE_FORMAT_Z24X8_UNORM:
1558 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1559 return V_028040_Z_24; /* deprecated on AMD GCN */
1560 case PIPE_FORMAT_Z32_FLOAT:
1561 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1562 return V_028040_Z_32_FLOAT;
1563 default:
1564 return V_028040_Z_INVALID;
1565 }
1566 }
1567
1568 /*
1569 * Texture translation
1570 */
1571
1572 static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
1573 const struct util_format_description *desc,
1574 int first_non_void)
1575 {
1576 struct si_screen *sscreen = (struct si_screen *)screen;
1577 bool uniform = true;
1578 int i;
1579
1580 assert(sscreen->info.chip_class <= GFX9);
1581
1582 /* Colorspace (return non-RGB formats directly). */
1583 switch (desc->colorspace) {
1584 /* Depth stencil formats */
1585 case UTIL_FORMAT_COLORSPACE_ZS:
1586 switch (format) {
1587 case PIPE_FORMAT_Z16_UNORM:
1588 return V_008F14_IMG_DATA_FORMAT_16;
1589 case PIPE_FORMAT_X24S8_UINT:
1590 case PIPE_FORMAT_S8X24_UINT:
1591 /*
1592 * Implemented as an 8_8_8_8 data format to fix texture
1593 * gathers in stencil sampling. This affects at least
1594 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1595 */
1596 if (sscreen->info.chip_class <= GFX8)
1597 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1598
1599 if (format == PIPE_FORMAT_X24S8_UINT)
1600 return V_008F14_IMG_DATA_FORMAT_8_24;
1601 else
1602 return V_008F14_IMG_DATA_FORMAT_24_8;
1603 case PIPE_FORMAT_Z24X8_UNORM:
1604 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1605 return V_008F14_IMG_DATA_FORMAT_8_24;
1606 case PIPE_FORMAT_X8Z24_UNORM:
1607 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1608 return V_008F14_IMG_DATA_FORMAT_24_8;
1609 case PIPE_FORMAT_S8_UINT:
1610 return V_008F14_IMG_DATA_FORMAT_8;
1611 case PIPE_FORMAT_Z32_FLOAT:
1612 return V_008F14_IMG_DATA_FORMAT_32;
1613 case PIPE_FORMAT_X32_S8X24_UINT:
1614 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1615 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1616 default:
1617 goto out_unknown;
1618 }
1619
1620 case UTIL_FORMAT_COLORSPACE_YUV:
1621 goto out_unknown; /* TODO */
1622
1623 case UTIL_FORMAT_COLORSPACE_SRGB:
1624 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1625 goto out_unknown;
1626 break;
1627
1628 default:
1629 break;
1630 }
1631
1632 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1633 if (!sscreen->info.has_format_bc1_through_bc7)
1634 goto out_unknown;
1635
1636 switch (format) {
1637 case PIPE_FORMAT_RGTC1_SNORM:
1638 case PIPE_FORMAT_LATC1_SNORM:
1639 case PIPE_FORMAT_RGTC1_UNORM:
1640 case PIPE_FORMAT_LATC1_UNORM:
1641 return V_008F14_IMG_DATA_FORMAT_BC4;
1642 case PIPE_FORMAT_RGTC2_SNORM:
1643 case PIPE_FORMAT_LATC2_SNORM:
1644 case PIPE_FORMAT_RGTC2_UNORM:
1645 case PIPE_FORMAT_LATC2_UNORM:
1646 return V_008F14_IMG_DATA_FORMAT_BC5;
1647 default:
1648 goto out_unknown;
1649 }
1650 }
1651
1652 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1653 (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA10 ||
1654 sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2)) {
1655 switch (format) {
1656 case PIPE_FORMAT_ETC1_RGB8:
1657 case PIPE_FORMAT_ETC2_RGB8:
1658 case PIPE_FORMAT_ETC2_SRGB8:
1659 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1660 case PIPE_FORMAT_ETC2_RGB8A1:
1661 case PIPE_FORMAT_ETC2_SRGB8A1:
1662 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1663 case PIPE_FORMAT_ETC2_RGBA8:
1664 case PIPE_FORMAT_ETC2_SRGBA8:
1665 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1666 case PIPE_FORMAT_ETC2_R11_UNORM:
1667 case PIPE_FORMAT_ETC2_R11_SNORM:
1668 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1669 case PIPE_FORMAT_ETC2_RG11_UNORM:
1670 case PIPE_FORMAT_ETC2_RG11_SNORM:
1671 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1672 default:
1673 goto out_unknown;
1674 }
1675 }
1676
1677 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1678 if (!sscreen->info.has_format_bc1_through_bc7)
1679 goto out_unknown;
1680
1681 switch (format) {
1682 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1683 case PIPE_FORMAT_BPTC_SRGBA:
1684 return V_008F14_IMG_DATA_FORMAT_BC7;
1685 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1686 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1687 return V_008F14_IMG_DATA_FORMAT_BC6;
1688 default:
1689 goto out_unknown;
1690 }
1691 }
1692
1693 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1694 switch (format) {
1695 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1696 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1697 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1698 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1699 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1700 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1701 default:
1702 goto out_unknown;
1703 }
1704 }
1705
1706 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1707 if (!sscreen->info.has_format_bc1_through_bc7)
1708 goto out_unknown;
1709
1710 switch (format) {
1711 case PIPE_FORMAT_DXT1_RGB:
1712 case PIPE_FORMAT_DXT1_RGBA:
1713 case PIPE_FORMAT_DXT1_SRGB:
1714 case PIPE_FORMAT_DXT1_SRGBA:
1715 return V_008F14_IMG_DATA_FORMAT_BC1;
1716 case PIPE_FORMAT_DXT3_RGBA:
1717 case PIPE_FORMAT_DXT3_SRGBA:
1718 return V_008F14_IMG_DATA_FORMAT_BC2;
1719 case PIPE_FORMAT_DXT5_RGBA:
1720 case PIPE_FORMAT_DXT5_SRGBA:
1721 return V_008F14_IMG_DATA_FORMAT_BC3;
1722 default:
1723 goto out_unknown;
1724 }
1725 }
1726
1727 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1728 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1729 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1730 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1731 }
1732
1733 /* R8G8Bx_SNORM - TODO CxV8U8 */
1734
1735 /* hw cannot support mixed formats (except depth/stencil, since only
1736 * depth is read).*/
1737 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1738 goto out_unknown;
1739
1740 /* See whether the components are of the same size. */
1741 for (i = 1; i < desc->nr_channels; i++) {
1742 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1743 }
1744
1745 /* Non-uniform formats. */
1746 if (!uniform) {
1747 switch (desc->nr_channels) {
1748 case 3:
1749 if (desc->channel[0].size == 5 && desc->channel[1].size == 6 &&
1750 desc->channel[2].size == 5) {
1751 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1752 }
1753 goto out_unknown;
1754 case 4:
1755 if (desc->channel[0].size == 5 && desc->channel[1].size == 5 &&
1756 desc->channel[2].size == 5 && desc->channel[3].size == 1) {
1757 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1758 }
1759 if (desc->channel[0].size == 1 && desc->channel[1].size == 5 &&
1760 desc->channel[2].size == 5 && desc->channel[3].size == 5) {
1761 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1762 }
1763 if (desc->channel[0].size == 10 && desc->channel[1].size == 10 &&
1764 desc->channel[2].size == 10 && desc->channel[3].size == 2) {
1765 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1766 }
1767 goto out_unknown;
1768 }
1769 goto out_unknown;
1770 }
1771
1772 if (first_non_void < 0 || first_non_void > 3)
1773 goto out_unknown;
1774
1775 /* uniform formats */
1776 switch (desc->channel[first_non_void].size) {
1777 case 4:
1778 switch (desc->nr_channels) {
1779 #if 0 /* Not supported for render targets */
1780 case 2:
1781 return V_008F14_IMG_DATA_FORMAT_4_4;
1782 #endif
1783 case 4:
1784 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1785 }
1786 break;
1787 case 8:
1788 switch (desc->nr_channels) {
1789 case 1:
1790 return V_008F14_IMG_DATA_FORMAT_8;
1791 case 2:
1792 return V_008F14_IMG_DATA_FORMAT_8_8;
1793 case 4:
1794 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1795 }
1796 break;
1797 case 16:
1798 switch (desc->nr_channels) {
1799 case 1:
1800 return V_008F14_IMG_DATA_FORMAT_16;
1801 case 2:
1802 return V_008F14_IMG_DATA_FORMAT_16_16;
1803 case 4:
1804 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1805 }
1806 break;
1807 case 32:
1808 switch (desc->nr_channels) {
1809 case 1:
1810 return V_008F14_IMG_DATA_FORMAT_32;
1811 case 2:
1812 return V_008F14_IMG_DATA_FORMAT_32_32;
1813 #if 0 /* Not supported for render targets */
1814 case 3:
1815 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1816 #endif
1817 case 4:
1818 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1819 }
1820 }
1821
1822 out_unknown:
1823 return ~0;
1824 }
1825
1826 static unsigned si_tex_wrap(unsigned wrap)
1827 {
1828 switch (wrap) {
1829 default:
1830 case PIPE_TEX_WRAP_REPEAT:
1831 return V_008F30_SQ_TEX_WRAP;
1832 case PIPE_TEX_WRAP_CLAMP:
1833 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1834 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1835 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1836 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1837 return V_008F30_SQ_TEX_CLAMP_BORDER;
1838 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1839 return V_008F30_SQ_TEX_MIRROR;
1840 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1841 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1842 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1843 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1844 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1845 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1846 }
1847 }
1848
1849 static unsigned si_tex_mipfilter(unsigned filter)
1850 {
1851 switch (filter) {
1852 case PIPE_TEX_MIPFILTER_NEAREST:
1853 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1854 case PIPE_TEX_MIPFILTER_LINEAR:
1855 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1856 default:
1857 case PIPE_TEX_MIPFILTER_NONE:
1858 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1859 }
1860 }
1861
1862 static unsigned si_tex_compare(unsigned compare)
1863 {
1864 switch (compare) {
1865 default:
1866 case PIPE_FUNC_NEVER:
1867 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1868 case PIPE_FUNC_LESS:
1869 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1870 case PIPE_FUNC_EQUAL:
1871 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1872 case PIPE_FUNC_LEQUAL:
1873 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1874 case PIPE_FUNC_GREATER:
1875 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1876 case PIPE_FUNC_NOTEQUAL:
1877 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1878 case PIPE_FUNC_GEQUAL:
1879 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1880 case PIPE_FUNC_ALWAYS:
1881 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1882 }
1883 }
1884
1885 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, unsigned view_target,
1886 unsigned nr_samples)
1887 {
1888 unsigned res_target = tex->buffer.b.b.target;
1889
1890 if (view_target == PIPE_TEXTURE_CUBE || view_target == PIPE_TEXTURE_CUBE_ARRAY)
1891 res_target = view_target;
1892 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1893 else if (res_target == PIPE_TEXTURE_CUBE || res_target == PIPE_TEXTURE_CUBE_ARRAY)
1894 res_target = PIPE_TEXTURE_2D_ARRAY;
1895
1896 /* GFX9 allocates 1D textures as 2D. */
1897 if ((res_target == PIPE_TEXTURE_1D || res_target == PIPE_TEXTURE_1D_ARRAY) &&
1898 sscreen->info.chip_class == GFX9 &&
1899 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1900 if (res_target == PIPE_TEXTURE_1D)
1901 res_target = PIPE_TEXTURE_2D;
1902 else
1903 res_target = PIPE_TEXTURE_2D_ARRAY;
1904 }
1905
1906 switch (res_target) {
1907 default:
1908 case PIPE_TEXTURE_1D:
1909 return V_008F1C_SQ_RSRC_IMG_1D;
1910 case PIPE_TEXTURE_1D_ARRAY:
1911 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1912 case PIPE_TEXTURE_2D:
1913 case PIPE_TEXTURE_RECT:
1914 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : V_008F1C_SQ_RSRC_IMG_2D;
1915 case PIPE_TEXTURE_2D_ARRAY:
1916 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1917 case PIPE_TEXTURE_3D:
1918 return V_008F1C_SQ_RSRC_IMG_3D;
1919 case PIPE_TEXTURE_CUBE:
1920 case PIPE_TEXTURE_CUBE_ARRAY:
1921 return V_008F1C_SQ_RSRC_IMG_CUBE;
1922 }
1923 }
1924
1925 /*
1926 * Format support testing
1927 */
1928
1929 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1930 {
1931 struct si_screen *sscreen = (struct si_screen *)screen;
1932
1933 if (sscreen->info.chip_class >= GFX10) {
1934 const struct gfx10_format *fmt = &gfx10_format_table[format];
1935 if (!fmt->img_format || fmt->buffers_only)
1936 return false;
1937 return true;
1938 }
1939
1940 const struct util_format_description *desc = util_format_description(format);
1941 if (!desc)
1942 return false;
1943
1944 return si_translate_texformat(screen, format, desc,
1945 util_format_get_first_non_void_channel(format)) != ~0U;
1946 }
1947
1948 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1949 const struct util_format_description *desc,
1950 int first_non_void)
1951 {
1952 int i;
1953
1954 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
1955
1956 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1957 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1958
1959 assert(first_non_void >= 0);
1960
1961 if (desc->nr_channels == 4 && desc->channel[0].size == 10 && desc->channel[1].size == 10 &&
1962 desc->channel[2].size == 10 && desc->channel[3].size == 2)
1963 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1964
1965 /* See whether the components are of the same size. */
1966 for (i = 0; i < desc->nr_channels; i++) {
1967 if (desc->channel[first_non_void].size != desc->channel[i].size)
1968 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1969 }
1970
1971 switch (desc->channel[first_non_void].size) {
1972 case 8:
1973 switch (desc->nr_channels) {
1974 case 1:
1975 case 3: /* 3 loads */
1976 return V_008F0C_BUF_DATA_FORMAT_8;
1977 case 2:
1978 return V_008F0C_BUF_DATA_FORMAT_8_8;
1979 case 4:
1980 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1981 }
1982 break;
1983 case 16:
1984 switch (desc->nr_channels) {
1985 case 1:
1986 case 3: /* 3 loads */
1987 return V_008F0C_BUF_DATA_FORMAT_16;
1988 case 2:
1989 return V_008F0C_BUF_DATA_FORMAT_16_16;
1990 case 4:
1991 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1992 }
1993 break;
1994 case 32:
1995 switch (desc->nr_channels) {
1996 case 1:
1997 return V_008F0C_BUF_DATA_FORMAT_32;
1998 case 2:
1999 return V_008F0C_BUF_DATA_FORMAT_32_32;
2000 case 3:
2001 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2002 case 4:
2003 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2004 }
2005 break;
2006 case 64:
2007 /* Legacy double formats. */
2008 switch (desc->nr_channels) {
2009 case 1: /* 1 load */
2010 return V_008F0C_BUF_DATA_FORMAT_32_32;
2011 case 2: /* 1 load */
2012 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2013 case 3: /* 3 loads */
2014 return V_008F0C_BUF_DATA_FORMAT_32_32;
2015 case 4: /* 2 loads */
2016 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2017 }
2018 break;
2019 }
2020
2021 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2022 }
2023
2024 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2025 const struct util_format_description *desc,
2026 int first_non_void)
2027 {
2028 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2029
2030 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2031 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2032
2033 assert(first_non_void >= 0);
2034
2035 switch (desc->channel[first_non_void].type) {
2036 case UTIL_FORMAT_TYPE_SIGNED:
2037 case UTIL_FORMAT_TYPE_FIXED:
2038 if (desc->channel[first_non_void].size >= 32 || desc->channel[first_non_void].pure_integer)
2039 return V_008F0C_BUF_NUM_FORMAT_SINT;
2040 else if (desc->channel[first_non_void].normalized)
2041 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2042 else
2043 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2044 break;
2045 case UTIL_FORMAT_TYPE_UNSIGNED:
2046 if (desc->channel[first_non_void].size >= 32 || desc->channel[first_non_void].pure_integer)
2047 return V_008F0C_BUF_NUM_FORMAT_UINT;
2048 else if (desc->channel[first_non_void].normalized)
2049 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2050 else
2051 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2052 break;
2053 case UTIL_FORMAT_TYPE_FLOAT:
2054 default:
2055 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2056 }
2057 }
2058
2059 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format,
2060 unsigned usage)
2061 {
2062 struct si_screen *sscreen = (struct si_screen *)screen;
2063 const struct util_format_description *desc;
2064 int first_non_void;
2065 unsigned data_format;
2066
2067 assert((usage & ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_VERTEX_BUFFER)) ==
2068 0);
2069
2070 desc = util_format_description(format);
2071 if (!desc)
2072 return 0;
2073
2074 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2075 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2076 * for read-only access (with caveats surrounding bounds checks), but
2077 * obviously fails for write access which we have to implement for
2078 * shader images. Luckily, OpenGL doesn't expect this to be supported
2079 * anyway, and so the only impact is on PBO uploads / downloads, which
2080 * shouldn't be expected to be fast for GL_RGB anyway.
2081 */
2082 if (desc->block.bits == 3 * 8 || desc->block.bits == 3 * 16) {
2083 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2084 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2085 if (!usage)
2086 return 0;
2087 }
2088 }
2089
2090 if (sscreen->info.chip_class >= GFX10) {
2091 const struct gfx10_format *fmt = &gfx10_format_table[format];
2092 if (!fmt->img_format || fmt->img_format >= 128)
2093 return 0;
2094 return usage;
2095 }
2096
2097 first_non_void = util_format_get_first_non_void_channel(format);
2098 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2099 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2100 return 0;
2101
2102 return usage;
2103 }
2104
2105 static bool si_is_colorbuffer_format_supported(enum chip_class chip_class,
2106 enum pipe_format format)
2107 {
2108 return si_translate_colorformat(chip_class, format) != V_028C70_COLOR_INVALID &&
2109 si_translate_colorswap(format, false) != ~0U;
2110 }
2111
2112 static bool si_is_zs_format_supported(enum pipe_format format)
2113 {
2114 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2115 }
2116
2117 static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
2118 enum pipe_texture_target target, unsigned sample_count,
2119 unsigned storage_sample_count, unsigned usage)
2120 {
2121 struct si_screen *sscreen = (struct si_screen *)screen;
2122 unsigned retval = 0;
2123
2124 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2125 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2126 return false;
2127 }
2128
2129 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2130 return false;
2131
2132 if (sample_count > 1) {
2133 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2134 return false;
2135
2136 /* Only power-of-two sample counts are supported. */
2137 if (!util_is_power_of_two_or_zero(sample_count) ||
2138 !util_is_power_of_two_or_zero(storage_sample_count))
2139 return false;
2140
2141 /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
2142 * so don't expose 16 samples there.
2143 */
2144 const unsigned max_eqaa_samples = sscreen->info.num_render_backends == 1 ? 8 : 16;
2145 const unsigned max_samples = 8;
2146
2147 /* MSAA support without framebuffer attachments. */
2148 if (format == PIPE_FORMAT_NONE && sample_count <= max_eqaa_samples)
2149 return true;
2150
2151 if (!sscreen->info.has_eqaa_surface_allocator || util_format_is_depth_or_stencil(format)) {
2152 /* Color without EQAA or depth/stencil. */
2153 if (sample_count > max_samples || sample_count != storage_sample_count)
2154 return false;
2155 } else {
2156 /* Color with EQAA. */
2157 if (sample_count > max_eqaa_samples || storage_sample_count > max_samples)
2158 return false;
2159 }
2160 }
2161
2162 if (usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) {
2163 if (target == PIPE_BUFFER) {
2164 retval |= si_is_vertex_format_supported(
2165 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE));
2166 } else {
2167 if (si_is_sampler_format_supported(screen, format))
2168 retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
2169 }
2170 }
2171
2172 if ((usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2173 PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) &&
2174 si_is_colorbuffer_format_supported(sscreen->info.chip_class, format)) {
2175 retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2176 PIPE_BIND_SHARED);
2177 if (!util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format))
2178 retval |= usage & PIPE_BIND_BLENDABLE;
2179 }
2180
2181 if ((usage & PIPE_BIND_DEPTH_STENCIL) && si_is_zs_format_supported(format)) {
2182 retval |= PIPE_BIND_DEPTH_STENCIL;
2183 }
2184
2185 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2186 retval |= si_is_vertex_format_supported(screen, format, PIPE_BIND_VERTEX_BUFFER);
2187 }
2188
2189 if ((usage & PIPE_BIND_LINEAR) && !util_format_is_compressed(format) &&
2190 !(usage & PIPE_BIND_DEPTH_STENCIL))
2191 retval |= PIPE_BIND_LINEAR;
2192
2193 return retval == usage;
2194 }
2195
2196 /*
2197 * framebuffer handling
2198 */
2199
2200 static void si_choose_spi_color_formats(struct si_surface *surf, unsigned format, unsigned swap,
2201 unsigned ntype, bool is_depth)
2202 {
2203 struct ac_spi_color_formats formats = {};
2204
2205 ac_choose_spi_color_formats(format, swap, ntype, is_depth, &formats);
2206
2207 surf->spi_shader_col_format = formats.normal;
2208 surf->spi_shader_col_format_alpha = formats.alpha;
2209 surf->spi_shader_col_format_blend = formats.blend;
2210 surf->spi_shader_col_format_blend_alpha = formats.blend_alpha;
2211 }
2212
2213 static void si_initialize_color_surface(struct si_context *sctx, struct si_surface *surf)
2214 {
2215 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2216 unsigned color_info, color_attrib;
2217 unsigned format, swap, ntype, endian;
2218 const struct util_format_description *desc;
2219 int firstchan;
2220 unsigned blend_clamp = 0, blend_bypass = 0;
2221
2222 desc = util_format_description(surf->base.format);
2223 for (firstchan = 0; firstchan < 4; firstchan++) {
2224 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2225 break;
2226 }
2227 }
2228 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2229 ntype = V_028C70_NUMBER_FLOAT;
2230 } else {
2231 ntype = V_028C70_NUMBER_UNORM;
2232 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2233 ntype = V_028C70_NUMBER_SRGB;
2234 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2235 if (desc->channel[firstchan].pure_integer) {
2236 ntype = V_028C70_NUMBER_SINT;
2237 } else {
2238 assert(desc->channel[firstchan].normalized);
2239 ntype = V_028C70_NUMBER_SNORM;
2240 }
2241 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2242 if (desc->channel[firstchan].pure_integer) {
2243 ntype = V_028C70_NUMBER_UINT;
2244 } else {
2245 assert(desc->channel[firstchan].normalized);
2246 ntype = V_028C70_NUMBER_UNORM;
2247 }
2248 }
2249 }
2250
2251 format = si_translate_colorformat(sctx->chip_class, surf->base.format);
2252 if (format == V_028C70_COLOR_INVALID) {
2253 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2254 }
2255 assert(format != V_028C70_COLOR_INVALID);
2256 swap = si_translate_colorswap(surf->base.format, false);
2257 endian = si_colorformat_endian_swap(format);
2258
2259 /* blend clamp should be set for all NORM/SRGB types */
2260 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
2261 ntype == V_028C70_NUMBER_SRGB)
2262 blend_clamp = 1;
2263
2264 /* set blend bypass according to docs if SINT/UINT or
2265 8/24 COLOR variants */
2266 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2267 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2268 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2269 blend_clamp = 0;
2270 blend_bypass = 1;
2271 }
2272
2273 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2274 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_8_8 ||
2275 format == V_028C70_COLOR_8_8_8_8)
2276 surf->color_is_int8 = true;
2277 else if (format == V_028C70_COLOR_10_10_10_2 || format == V_028C70_COLOR_2_10_10_10)
2278 surf->color_is_int10 = true;
2279 }
2280
2281 color_info =
2282 S_028C70_FORMAT(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) |
2283 S_028C70_BLEND_BYPASS(blend_bypass) | S_028C70_SIMPLE_FLOAT(1) |
2284 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM && ntype != V_028C70_NUMBER_SNORM &&
2285 ntype != V_028C70_NUMBER_SRGB && format != V_028C70_COLOR_8_24 &&
2286 format != V_028C70_COLOR_24_8) |
2287 S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian);
2288
2289 /* Intensity is implemented as Red, so treat it that way. */
2290 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2291 util_format_is_intensity(surf->base.format));
2292
2293 if (tex->buffer.b.b.nr_samples > 1) {
2294 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2295 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2296
2297 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS(log_fragments);
2298
2299 if (tex->surface.fmask_offset) {
2300 color_info |= S_028C70_COMPRESSION(1);
2301 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2302
2303 if (sctx->chip_class == GFX6) {
2304 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2305 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2306 }
2307 }
2308 }
2309
2310 if (sctx->chip_class >= GFX10) {
2311 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2312
2313 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2314 64 for APU because all of our APUs to date use DIMMs which have
2315 a request granularity size of 64B while all other chips have a
2316 32B request size */
2317 if (!sctx->screen->info.has_dedicated_vram)
2318 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2319
2320 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2321 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.dcc.max_compressed_block_size) |
2322 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2323 S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.dcc.independent_64B_blocks) |
2324 S_028C78_INDEPENDENT_128B_BLOCKS(tex->surface.u.gfx9.dcc.independent_128B_blocks);
2325 } else if (sctx->chip_class >= GFX8) {
2326 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2327 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2328
2329 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2330 64 for APU because all of our APUs to date use DIMMs which have
2331 a request granularity size of 64B while all other chips have a
2332 32B request size */
2333 if (!sctx->screen->info.has_dedicated_vram)
2334 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2335
2336 if (tex->buffer.b.b.nr_storage_samples > 1) {
2337 if (tex->surface.bpe == 1)
2338 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2339 else if (tex->surface.bpe == 2)
2340 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2341 }
2342
2343 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2344 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2345 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2346 }
2347
2348 /* This must be set for fast clear to work without FMASK. */
2349 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2350 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2351 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2352 }
2353
2354 /* GFX10 field has the same base shift as the GFX6 field */
2355 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2356 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2357 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2358
2359 if (sctx->chip_class >= GFX10) {
2360 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2361
2362 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2363 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2364 S_028EE0_RESOURCE_LEVEL(1);
2365 } else if (sctx->chip_class == GFX9) {
2366 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2367 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2368 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2369 }
2370
2371 if (sctx->chip_class >= GFX9) {
2372 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2373 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2374 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2375 }
2376
2377 surf->cb_color_view = color_view;
2378 surf->cb_color_info = color_info;
2379 surf->cb_color_attrib = color_attrib;
2380
2381 /* Determine pixel shader export format */
2382 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2383
2384 surf->color_initialized = true;
2385 }
2386
2387 static void si_init_depth_surface(struct si_context *sctx, struct si_surface *surf)
2388 {
2389 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2390 unsigned level = surf->base.u.tex.level;
2391 unsigned format, stencil_format;
2392 uint32_t z_info, s_info;
2393
2394 format = si_translate_dbformat(tex->db_render_format);
2395 stencil_format = tex->surface.has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2396
2397 assert(format != V_028040_Z_INVALID);
2398 if (format == V_028040_Z_INVALID)
2399 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2400
2401 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2402 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2403 surf->db_htile_data_base = 0;
2404 surf->db_htile_surface = 0;
2405
2406 if (sctx->chip_class >= GFX10) {
2407 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2408 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2409 }
2410
2411 if (sctx->chip_class >= GFX9) {
2412 assert(tex->surface.u.gfx9.surf_offset == 0);
2413 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2414 surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.stencil_offset) >> 8;
2415 z_info = S_028038_FORMAT(format) |
2416 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2417 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2418 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2419 s_info = S_02803C_FORMAT(stencil_format) |
2420 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2421
2422 if (sctx->chip_class == GFX9) {
2423 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2424 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2425 }
2426 surf->db_depth_view |= S_028008_MIPID(level);
2427 surf->db_depth_size =
2428 S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) | S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2429
2430 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2431 z_info |= S_028038_TILE_SURFACE_ENABLE(1) | S_028038_ALLOW_EXPCLEAR(1);
2432
2433 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2434 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2435 * See that for explanation.
2436 */
2437 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2438 } else {
2439 /* Use all HTILE for depth if there's no stencil. */
2440 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2441 }
2442
2443 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8;
2444 surf->db_htile_surface =
2445 S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
2446 if (sctx->chip_class == GFX9) {
2447 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
2448 }
2449 }
2450 } else {
2451 /* GFX6-GFX8 */
2452 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2453
2454 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2455
2456 surf->db_depth_base =
2457 (tex->buffer.gpu_address + tex->surface.u.legacy.level[level].offset) >> 8;
2458 surf->db_stencil_base =
2459 (tex->buffer.gpu_address + tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2460
2461 z_info =
2462 S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2463 s_info = S_028044_FORMAT(stencil_format);
2464 surf->db_depth_info = 0;
2465
2466 if (sctx->chip_class >= GFX7) {
2467 struct radeon_info *info = &sctx->screen->info;
2468 unsigned index = tex->surface.u.legacy.tiling_index[level];
2469 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2470 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2471 unsigned tile_mode = info->si_tile_mode_array[index];
2472 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2473 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2474
2475 surf->db_depth_info |= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2476 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2477 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2478 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2479 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2480 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2481 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2482 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2483 } else {
2484 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2485 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2486 tile_mode_index = si_tile_mode_index(tex, level, true);
2487 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2488 }
2489
2490 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2491 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2492 surf->db_depth_slice =
2493 S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * levelinfo->nblk_y) / 64 - 1);
2494
2495 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2496 z_info |= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1);
2497
2498 if (tex->surface.has_stencil) {
2499 /* Workaround: For a not yet understood reason, the
2500 * combination of MSAA, fast stencil clear and stencil
2501 * decompress messes with subsequent stencil buffer
2502 * uses. Problem was reproduced on Verde, Bonaire,
2503 * Tonga, and Carrizo.
2504 *
2505 * Disabling EXPCLEAR works around the problem.
2506 *
2507 * Check piglit's arb_texture_multisample-stencil-clear
2508 * test if you want to try changing this.
2509 */
2510 if (tex->buffer.b.b.nr_samples <= 1)
2511 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2512 }
2513
2514 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8;
2515 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2516 }
2517 }
2518
2519 surf->db_z_info = z_info;
2520 surf->db_stencil_info = s_info;
2521
2522 surf->depth_initialized = true;
2523 }
2524
2525 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2526 {
2527 if (sctx->decompression_enabled)
2528 return;
2529
2530 if (sctx->framebuffer.state.zsbuf) {
2531 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2532 struct si_texture *tex = (struct si_texture *)surf->texture;
2533
2534 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2535
2536 if (tex->surface.has_stencil)
2537 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2538 }
2539
2540 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2541 while (compressed_cb_mask) {
2542 unsigned i = u_bit_scan(&compressed_cb_mask);
2543 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2544 struct si_texture *tex = (struct si_texture *)surf->texture;
2545
2546 if (tex->surface.fmask_offset) {
2547 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2548 tex->fmask_is_identity = false;
2549 }
2550 if (tex->dcc_gather_statistics)
2551 tex->separate_dcc_dirty = true;
2552 }
2553 }
2554
2555 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2556 {
2557 for (int i = 0; i < state->nr_cbufs; ++i) {
2558 struct si_surface *surf = NULL;
2559 struct si_texture *tex;
2560
2561 if (!state->cbufs[i])
2562 continue;
2563 surf = (struct si_surface *)state->cbufs[i];
2564 tex = (struct si_texture *)surf->base.texture;
2565
2566 p_atomic_dec(&tex->framebuffers_bound);
2567 }
2568 }
2569
2570 static void si_set_framebuffer_state(struct pipe_context *ctx,
2571 const struct pipe_framebuffer_state *state)
2572 {
2573 struct si_context *sctx = (struct si_context *)ctx;
2574 struct si_surface *surf = NULL;
2575 struct si_texture *tex;
2576 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2577 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2578 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2579 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2580 bool old_has_stencil =
2581 old_has_zsbuf &&
2582 ((struct si_texture *)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2583 bool unbound = false;
2584 int i;
2585
2586 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2587 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2588 * We could implement the full workaround here, but it's a useless case.
2589 */
2590 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2591 unreachable("the framebuffer shouldn't have zero area");
2592 return;
2593 }
2594
2595 si_update_fb_dirtiness_after_rendering(sctx);
2596
2597 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2598 if (!sctx->framebuffer.state.cbufs[i])
2599 continue;
2600
2601 tex = (struct si_texture *)sctx->framebuffer.state.cbufs[i]->texture;
2602 if (tex->dcc_gather_statistics)
2603 vi_separate_dcc_stop_query(sctx, tex);
2604 }
2605
2606 /* Disable DCC if the formats are incompatible. */
2607 for (i = 0; i < state->nr_cbufs; i++) {
2608 if (!state->cbufs[i])
2609 continue;
2610
2611 surf = (struct si_surface *)state->cbufs[i];
2612 tex = (struct si_texture *)surf->base.texture;
2613
2614 if (!surf->dcc_incompatible)
2615 continue;
2616
2617 /* Since the DCC decompression calls back into set_framebuffer-
2618 * _state, we need to unbind the framebuffer, so that
2619 * vi_separate_dcc_stop_query isn't called twice with the same
2620 * color buffer.
2621 */
2622 if (!unbound) {
2623 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2624 unbound = true;
2625 }
2626
2627 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2628 if (!si_texture_disable_dcc(sctx, tex))
2629 si_decompress_dcc(sctx, tex);
2630
2631 surf->dcc_incompatible = false;
2632 }
2633
2634 /* Only flush TC when changing the framebuffer state, because
2635 * the only client not using TC that can change textures is
2636 * the framebuffer.
2637 *
2638 * Wait for compute shaders because of possible transitions:
2639 * - FB write -> shader read
2640 * - shader write -> FB read
2641 *
2642 * DB caches are flushed on demand (using si_decompress_textures).
2643 *
2644 * When MSAA is enabled, CB and TC caches are flushed on demand
2645 * (after FMASK decompression). Shader write -> FB read transitions
2646 * cannot happen for MSAA textures, because MSAA shader images are
2647 * not supported.
2648 *
2649 * Only flush and wait for CB if there is actually a bound color buffer.
2650 */
2651 if (sctx->framebuffer.uncompressed_cb_mask) {
2652 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2653 sctx->framebuffer.CB_has_shader_readable_metadata,
2654 sctx->framebuffer.all_DCC_pipe_aligned);
2655 }
2656
2657 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2658
2659 /* u_blitter doesn't invoke depth decompression when it does multiple
2660 * blits in a row, but the only case when it matters for DB is when
2661 * doing generate_mipmap. So here we flush DB manually between
2662 * individual generate_mipmap blits.
2663 * Note that lower mipmap levels aren't compressed.
2664 */
2665 if (sctx->generate_mipmap_for_depth) {
2666 si_make_DB_shader_coherent(sctx, 1, false, sctx->framebuffer.DB_has_shader_readable_metadata);
2667 } else if (sctx->chip_class == GFX9) {
2668 /* It appears that DB metadata "leaks" in a sequence of:
2669 * - depth clear
2670 * - DCC decompress for shader image writes (with DB disabled)
2671 * - render with DEPTH_BEFORE_SHADER=1
2672 * Flushing DB metadata works around the problem.
2673 */
2674 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2675 }
2676
2677 /* Take the maximum of the old and new count. If the new count is lower,
2678 * dirtying is needed to disable the unbound colorbuffers.
2679 */
2680 sctx->framebuffer.dirty_cbufs |=
2681 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2682 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2683
2684 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2685 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2686
2687 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2688 sctx->framebuffer.spi_shader_col_format = 0;
2689 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2690 sctx->framebuffer.spi_shader_col_format_blend = 0;
2691 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2692 sctx->framebuffer.color_is_int8 = 0;
2693 sctx->framebuffer.color_is_int10 = 0;
2694
2695 sctx->framebuffer.compressed_cb_mask = 0;
2696 sctx->framebuffer.uncompressed_cb_mask = 0;
2697 sctx->framebuffer.displayable_dcc_cb_mask = 0;
2698 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2699 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2700 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2701 sctx->framebuffer.any_dst_linear = false;
2702 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2703 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2704 sctx->framebuffer.all_DCC_pipe_aligned = true;
2705 sctx->framebuffer.min_bytes_per_pixel = 0;
2706 sctx->framebuffer.color_big_page = true;
2707 sctx->framebuffer.zs_big_page = true;
2708
2709 for (i = 0; i < state->nr_cbufs; i++) {
2710 if (!state->cbufs[i])
2711 continue;
2712
2713 surf = (struct si_surface *)state->cbufs[i];
2714 tex = (struct si_texture *)surf->base.texture;
2715
2716 if (!surf->color_initialized) {
2717 si_initialize_color_surface(sctx, surf);
2718 }
2719
2720 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2721 sctx->framebuffer.spi_shader_col_format |= surf->spi_shader_col_format << (i * 4);
2722 sctx->framebuffer.spi_shader_col_format_alpha |= surf->spi_shader_col_format_alpha << (i * 4);
2723 sctx->framebuffer.spi_shader_col_format_blend |= surf->spi_shader_col_format_blend << (i * 4);
2724 sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
2725 << (i * 4);
2726
2727 sctx->framebuffer.color_big_page &=
2728 tex->buffer.bo_alignment % (64 * 1024) == 0;
2729
2730 if (surf->color_is_int8)
2731 sctx->framebuffer.color_is_int8 |= 1 << i;
2732 if (surf->color_is_int10)
2733 sctx->framebuffer.color_is_int10 |= 1 << i;
2734
2735 if (tex->surface.fmask_offset)
2736 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2737 else
2738 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2739
2740 if (tex->surface.display_dcc_offset)
2741 sctx->framebuffer.displayable_dcc_cb_mask |= 1 << i;
2742
2743 /* Don't update nr_color_samples for non-AA buffers.
2744 * (e.g. destination of MSAA resolve)
2745 */
2746 if (tex->buffer.b.b.nr_samples >= 2 &&
2747 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2748 sctx->framebuffer.nr_color_samples =
2749 MIN2(sctx->framebuffer.nr_color_samples, tex->buffer.b.b.nr_storage_samples);
2750 sctx->framebuffer.nr_color_samples = MAX2(1, sctx->framebuffer.nr_color_samples);
2751 }
2752
2753 if (tex->surface.is_linear)
2754 sctx->framebuffer.any_dst_linear = true;
2755
2756 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2757 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2758
2759 if (sctx->chip_class >= GFX9 && !tex->surface.u.gfx9.dcc.pipe_aligned)
2760 sctx->framebuffer.all_DCC_pipe_aligned = false;
2761 }
2762
2763 si_context_add_resource_size(sctx, surf->base.texture);
2764
2765 p_atomic_inc(&tex->framebuffers_bound);
2766
2767 if (tex->dcc_gather_statistics) {
2768 /* Dirty tracking must be enabled for DCC usage analysis. */
2769 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2770 vi_separate_dcc_start_query(sctx, tex);
2771 }
2772
2773 /* Update the minimum but don't keep 0. */
2774 if (!sctx->framebuffer.min_bytes_per_pixel ||
2775 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2776 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
2777 }
2778
2779 /* For optimal DCC performance. */
2780 if (sctx->chip_class >= GFX10)
2781 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2782 else
2783 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2784
2785 struct si_texture *zstex = NULL;
2786
2787 if (state->zsbuf) {
2788 surf = (struct si_surface *)state->zsbuf;
2789 zstex = (struct si_texture *)surf->base.texture;
2790
2791 if (!surf->depth_initialized) {
2792 si_init_depth_surface(sctx, surf);
2793 }
2794
2795 sctx->framebuffer.zs_big_page = zstex->buffer.bo_alignment % (64 * 1024) == 0;
2796
2797 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
2798 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2799
2800 si_context_add_resource_size(sctx, surf->base.texture);
2801
2802 /* Update the minimum but don't keep 0. */
2803 if (!sctx->framebuffer.min_bytes_per_pixel ||
2804 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2805 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
2806 }
2807
2808 si_update_ps_colorbuf0_slot(sctx);
2809 si_update_poly_offset_state(sctx);
2810 si_update_ngg_small_prim_precision(sctx);
2811 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2812 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2813
2814 if (sctx->screen->dpbb_allowed)
2815 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2816
2817 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2818 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2819
2820 if (sctx->screen->has_out_of_order_rast &&
2821 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2822 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2823 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2824 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2825
2826 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2827 struct pipe_constant_buffer constbuf = {0};
2828
2829 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2830 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2831
2832 constbuf.buffer = sctx->sample_pos_buffer;
2833
2834 /* Set sample locations as fragment shader constants. */
2835 switch (sctx->framebuffer.nr_samples) {
2836 case 1:
2837 constbuf.buffer_offset = 0;
2838 break;
2839 case 2:
2840 constbuf.buffer_offset =
2841 (ubyte *)sctx->sample_positions.x2 - (ubyte *)sctx->sample_positions.x1;
2842 break;
2843 case 4:
2844 constbuf.buffer_offset =
2845 (ubyte *)sctx->sample_positions.x4 - (ubyte *)sctx->sample_positions.x1;
2846 break;
2847 case 8:
2848 constbuf.buffer_offset =
2849 (ubyte *)sctx->sample_positions.x8 - (ubyte *)sctx->sample_positions.x1;
2850 break;
2851 case 16:
2852 constbuf.buffer_offset =
2853 (ubyte *)sctx->sample_positions.x16 - (ubyte *)sctx->sample_positions.x1;
2854 break;
2855 default:
2856 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx->framebuffer.nr_samples);
2857 assert(0);
2858 }
2859 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2860 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2861
2862 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2863 }
2864
2865 sctx->do_update_shaders = true;
2866
2867 if (!sctx->decompression_enabled) {
2868 /* Prevent textures decompression when the framebuffer state
2869 * changes come from the decompression passes themselves.
2870 */
2871 sctx->need_check_render_feedback = true;
2872 }
2873 }
2874
2875 static void si_emit_framebuffer_state(struct si_context *sctx)
2876 {
2877 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2878 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2879 unsigned i, nr_cbufs = state->nr_cbufs;
2880 struct si_texture *tex = NULL;
2881 struct si_surface *cb = NULL;
2882 unsigned cb_color_info = 0;
2883
2884 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
2885 unsigned meta_write_policy, meta_read_policy;
2886 /* TODO: investigate whether LRU improves performance on other chips too */
2887 if (sctx->screen->info.num_render_backends <= 4) {
2888 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
2889 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
2890 } else {
2891 meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
2892 meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
2893 }
2894
2895 /* Colorbuffers. */
2896 for (i = 0; i < nr_cbufs; i++) {
2897 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2898 unsigned cb_color_attrib;
2899
2900 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2901 continue;
2902
2903 cb = (struct si_surface *)state->cbufs[i];
2904 if (!cb) {
2905 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2906 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2907 continue;
2908 }
2909
2910 tex = (struct si_texture *)cb->base.texture;
2911 radeon_add_to_buffer_list(
2912 sctx, sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE,
2913 tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER);
2914
2915 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
2916 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, tex->cmask_buffer, RADEON_USAGE_READWRITE,
2917 RADEON_PRIO_SEPARATE_META);
2918 }
2919
2920 if (tex->dcc_separate_buffer)
2921 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, tex->dcc_separate_buffer,
2922 RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
2923
2924 /* Compute mutable surface parameters. */
2925 cb_color_base = tex->buffer.gpu_address >> 8;
2926 cb_color_fmask = 0;
2927 cb_color_cmask = tex->cmask_base_address_reg;
2928 cb_dcc_base = 0;
2929 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2930 cb_color_attrib = cb->cb_color_attrib;
2931
2932 if (cb->base.u.tex.level > 0)
2933 cb_color_info &= C_028C70_FAST_CLEAR;
2934
2935 if (tex->surface.fmask_offset) {
2936 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
2937 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
2938 }
2939
2940 /* Set up DCC. */
2941 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2942 bool is_msaa_resolve_dst = state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
2943 state->cbufs[1] == &cb->base &&
2944 state->cbufs[1]->texture->nr_samples <= 1;
2945
2946 if (!is_msaa_resolve_dst)
2947 cb_color_info |= S_028C70_DCC_ENABLE(1);
2948
2949 cb_dcc_base =
2950 ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset) >>
2951