projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
amd/common/gfx10: add register JSON
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 static unsigned si_map_swizzle(unsigned swizzle)
38 {
39 switch (swizzle) {
40 case PIPE_SWIZZLE_Y:
41 return V_008F0C_SQ_SEL_Y;
42 case PIPE_SWIZZLE_Z:
43 return V_008F0C_SQ_SEL_Z;
44 case PIPE_SWIZZLE_W:
45 return V_008F0C_SQ_SEL_W;
46 case PIPE_SWIZZLE_0:
47 return V_008F0C_SQ_SEL_0;
48 case PIPE_SWIZZLE_1:
49 return V_008F0C_SQ_SEL_1;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X;
52 }
53 }
54
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x)
57 {
58 return x <= 0 ? 0 :
59 x >= 4096 ? 0xffff : x * 16;
60 }
61
62 /*
63 * Inferred framebuffer and blender state.
64 *
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
67 */
68 static void si_emit_cb_render_state(struct si_context *sctx)
69 {
70 struct radeon_cmdbuf *cs = sctx->gfx_cs;
71 struct si_state_blend *blend = sctx->queued.named.blend;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
75 unsigned i;
76
77 if (blend)
78 cb_target_mask &= blend->cb_target_mask;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend && blend->dual_src_blend &&
87 sctx->ps_shader.cso &&
88 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
89 cb_target_mask = 0;
90
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
93 */
94 if (sctx->screen->dfsm_allowed &&
95 sctx->last_cb_target_mask != cb_target_mask) {
96 sctx->last_cb_target_mask = cb_target_mask;
97
98 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
99 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
100 }
101
102 unsigned initial_cdw = cs->current.cdw;
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
104 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
105
106 if (sctx->chip_class >= GFX8) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
110 */
111 bool oc_disable = (sctx->chip_class == GFX8 ||
112 sctx->chip_class == GFX9) &&
113 blend &&
114 blend->blend_enable_4bit & cb_target_mask &&
115 sctx->framebuffer.nr_samples >= 2;
116 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
117
118 radeon_opt_set_context_reg(
119 sctx, R_028424_CB_DCC_CONTROL,
120 SI_TRACKED_CB_DCC_CONTROL,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
125 }
126
127 /* RB+ register settings. */
128 if (sctx->screen->rbplus_allowed) {
129 unsigned spi_shader_col_format =
130 sctx->ps_shader.cso ?
131 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
132 unsigned sx_ps_downconvert = 0;
133 unsigned sx_blend_opt_epsilon = 0;
134 unsigned sx_blend_opt_control = 0;
135
136 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
137 struct si_surface *surf =
138 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
139 unsigned format, swap, spi_format, colormask;
140 bool has_alpha, has_rgb;
141
142 if (!surf)
143 continue;
144
145 format = G_028C70_FORMAT(surf->cb_color_info);
146 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
147 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
148 colormask = (cb_target_mask >> (i * 4)) & 0xf;
149
150 /* Set if RGB and A are present. */
151 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
152
153 if (format == V_028C70_COLOR_8 ||
154 format == V_028C70_COLOR_16 ||
155 format == V_028C70_COLOR_32)
156 has_rgb = !has_alpha;
157 else
158 has_rgb = true;
159
160 /* Check the colormask and export format. */
161 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
162 has_rgb = false;
163 if (!(colormask & PIPE_MASK_A))
164 has_alpha = false;
165
166 if (spi_format == V_028714_SPI_SHADER_ZERO) {
167 has_rgb = false;
168 has_alpha = false;
169 }
170
171 /* Disable value checking for disabled channels. */
172 if (!has_rgb)
173 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
174 if (!has_alpha)
175 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
176
177 /* Enable down-conversion for 32bpp and smaller formats. */
178 switch (format) {
179 case V_028C70_COLOR_8:
180 case V_028C70_COLOR_8_8:
181 case V_028C70_COLOR_8_8_8_8:
182 /* For 1 and 2-channel formats, use the superset thereof. */
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
185 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_5_6_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_1_5_5_5:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_4_4_4_4:
206 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
208 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
209 }
210 break;
211
212 case V_028C70_COLOR_32:
213 if (swap == V_028C70_SWAP_STD &&
214 spi_format == V_028714_SPI_SHADER_32_R)
215 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
216 else if (swap == V_028C70_SWAP_ALT_REV &&
217 spi_format == V_028714_SPI_SHADER_32_AR)
218 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
219 break;
220
221 case V_028C70_COLOR_16:
222 case V_028C70_COLOR_16_16:
223 /* For 1-channel formats, use the superset thereof. */
224 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
227 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
228 if (swap == V_028C70_SWAP_STD ||
229 swap == V_028C70_SWAP_STD_REV)
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
231 else
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_10_11_11:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
240 }
241 break;
242
243 case V_028C70_COLOR_2_10_10_10:
244 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
246 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
247 }
248 break;
249 }
250 }
251
252 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
253 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
254 SI_TRACKED_SX_PS_DOWNCONVERT,
255 sx_ps_downconvert, sx_blend_opt_epsilon,
256 sx_blend_opt_control);
257 }
258 if (initial_cdw != cs->current.cdw)
259 sctx->context_roll = true;
260 }
261
262 /*
263 * Blender functions
264 */
265
266 static uint32_t si_translate_blend_function(int blend_func)
267 {
268 switch (blend_func) {
269 case PIPE_BLEND_ADD:
270 return V_028780_COMB_DST_PLUS_SRC;
271 case PIPE_BLEND_SUBTRACT:
272 return V_028780_COMB_SRC_MINUS_DST;
273 case PIPE_BLEND_REVERSE_SUBTRACT:
274 return V_028780_COMB_DST_MINUS_SRC;
275 case PIPE_BLEND_MIN:
276 return V_028780_COMB_MIN_DST_SRC;
277 case PIPE_BLEND_MAX:
278 return V_028780_COMB_MAX_DST_SRC;
279 default:
280 PRINT_ERR("Unknown blend function %d\n", blend_func);
281 assert(0);
282 break;
283 }
284 return 0;
285 }
286
287 static uint32_t si_translate_blend_factor(int blend_fact)
288 {
289 switch (blend_fact) {
290 case PIPE_BLENDFACTOR_ONE:
291 return V_028780_BLEND_ONE;
292 case PIPE_BLENDFACTOR_SRC_COLOR:
293 return V_028780_BLEND_SRC_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA:
295 return V_028780_BLEND_SRC_ALPHA;
296 case PIPE_BLENDFACTOR_DST_ALPHA:
297 return V_028780_BLEND_DST_ALPHA;
298 case PIPE_BLENDFACTOR_DST_COLOR:
299 return V_028780_BLEND_DST_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
301 return V_028780_BLEND_SRC_ALPHA_SATURATE;
302 case PIPE_BLENDFACTOR_CONST_COLOR:
303 return V_028780_BLEND_CONSTANT_COLOR;
304 case PIPE_BLENDFACTOR_CONST_ALPHA:
305 return V_028780_BLEND_CONSTANT_ALPHA;
306 case PIPE_BLENDFACTOR_ZERO:
307 return V_028780_BLEND_ZERO;
308 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
309 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
310 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
311 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
312 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_COLOR:
315 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
316 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_SRC1_COLOR:
321 return V_028780_BLEND_SRC1_COLOR;
322 case PIPE_BLENDFACTOR_SRC1_ALPHA:
323 return V_028780_BLEND_SRC1_ALPHA;
324 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
325 return V_028780_BLEND_INV_SRC1_COLOR;
326 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
327 return V_028780_BLEND_INV_SRC1_ALPHA;
328 default:
329 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
330 assert(0);
331 break;
332 }
333 return 0;
334 }
335
336 static uint32_t si_translate_blend_opt_function(int blend_func)
337 {
338 switch (blend_func) {
339 case PIPE_BLEND_ADD:
340 return V_028760_OPT_COMB_ADD;
341 case PIPE_BLEND_SUBTRACT:
342 return V_028760_OPT_COMB_SUBTRACT;
343 case PIPE_BLEND_REVERSE_SUBTRACT:
344 return V_028760_OPT_COMB_REVSUBTRACT;
345 case PIPE_BLEND_MIN:
346 return V_028760_OPT_COMB_MIN;
347 case PIPE_BLEND_MAX:
348 return V_028760_OPT_COMB_MAX;
349 default:
350 return V_028760_OPT_COMB_BLEND_DISABLED;
351 }
352 }
353
354 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
355 {
356 switch (blend_fact) {
357 case PIPE_BLENDFACTOR_ZERO:
358 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
359 case PIPE_BLENDFACTOR_ONE:
360 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
361 case PIPE_BLENDFACTOR_SRC_COLOR:
362 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
363 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
364 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
365 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
366 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
367 case PIPE_BLENDFACTOR_SRC_ALPHA:
368 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
369 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
371 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
372 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
373 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
374 default:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
376 }
377 }
378
379 static void si_blend_check_commutativity(struct si_screen *sscreen,
380 struct si_state_blend *blend,
381 enum pipe_blend_func func,
382 enum pipe_blendfactor src,
383 enum pipe_blendfactor dst,
384 unsigned chanmask)
385 {
386 /* Src factor is allowed when it does not depend on Dst */
387 static const uint32_t src_allowed =
388 (1u << PIPE_BLENDFACTOR_ONE) |
389 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
392 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
393 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
394 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
395 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
396 (1u << PIPE_BLENDFACTOR_ZERO) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
399 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
401 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
403
404 if (dst == PIPE_BLENDFACTOR_ONE &&
405 (src_allowed & (1u << src))) {
406 /* Addition is commutative, but floating point addition isn't
407 * associative: subtle changes can be introduced via different
408 * rounding.
409 *
410 * Out-of-order is also non-deterministic, which means that
411 * this breaks OpenGL invariance requirements. So only enable
412 * out-of-order additive blending if explicitly allowed by a
413 * setting.
414 */
415 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
416 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
417 blend->commutative_4bit |= chanmask;
418 }
419 }
420
421 /**
422 * Get rid of DST in the blend factors by commuting the operands:
423 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
424 */
425 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
426 unsigned *dst_factor, unsigned expected_dst,
427 unsigned replacement_src)
428 {
429 if (*src_factor == expected_dst &&
430 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
431 *src_factor = PIPE_BLENDFACTOR_ZERO;
432 *dst_factor = replacement_src;
433
434 /* Commuting the operands requires reversing subtractions. */
435 if (*func == PIPE_BLEND_SUBTRACT)
436 *func = PIPE_BLEND_REVERSE_SUBTRACT;
437 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
438 *func = PIPE_BLEND_SUBTRACT;
439 }
440 }
441
442 static bool si_blend_factor_uses_dst(unsigned factor)
443 {
444 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
445 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
446 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
447 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
448 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
449 }
450
451 static void *si_create_blend_state_mode(struct pipe_context *ctx,
452 const struct pipe_blend_state *state,
453 unsigned mode)
454 {
455 struct si_context *sctx = (struct si_context*)ctx;
456 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
457 struct si_pm4_state *pm4 = &blend->pm4;
458 uint32_t sx_mrt_blend_opt[8] = {0};
459 uint32_t color_control = 0;
460
461 if (!blend)
462 return NULL;
463
464 blend->alpha_to_coverage = state->alpha_to_coverage;
465 blend->alpha_to_one = state->alpha_to_one;
466 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
467 blend->logicop_enable = state->logicop_enable;
468
469 if (state->logicop_enable) {
470 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
471 } else {
472 color_control |= S_028808_ROP3(0xcc);
473 }
474
475 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
476 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
477 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
478 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
479 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
480 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
481 S_028B70_OFFSET_ROUND(1));
482
483 if (state->alpha_to_coverage)
484 blend->need_src_alpha_4bit |= 0xf;
485
486 blend->cb_target_mask = 0;
487 blend->cb_target_enabled_4bit = 0;
488
489 for (int i = 0; i < 8; i++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j = state->independent_blend_enable ? i : 0;
492
493 unsigned eqRGB = state->rt[j].rgb_func;
494 unsigned srcRGB = state->rt[j].rgb_src_factor;
495 unsigned dstRGB = state->rt[j].rgb_dst_factor;
496 unsigned eqA = state->rt[j].alpha_func;
497 unsigned srcA = state->rt[j].alpha_src_factor;
498 unsigned dstA = state->rt[j].alpha_dst_factor;
499
500 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
501 unsigned blend_cntl = 0;
502
503 sx_mrt_blend_opt[i] =
504 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
505 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
506
507 /* Only set dual source blending for MRT0 to avoid a hang. */
508 if (i >= 1 && blend->dual_src_blend) {
509 /* Vulkan does this for dual source blending. */
510 if (i == 1)
511 blend_cntl |= S_028780_ENABLE(1);
512
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
514 continue;
515 }
516
517 /* Only addition and subtraction equations are supported with
518 * dual source blending.
519 */
520 if (blend->dual_src_blend &&
521 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
522 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
523 assert(!"Unsupported equation for dual source blending");
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
525 continue;
526 }
527
528 /* cb_render_state will disable unused ones */
529 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
530 if (state->rt[j].colormask)
531 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
532
533 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
534 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
535 continue;
536 }
537
538 si_blend_check_commutativity(sctx->screen, blend,
539 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
540 si_blend_check_commutativity(sctx->screen, blend,
541 eqA, srcA, dstA, 0x8 << (4 * i));
542
543 /* Blending optimizations for RB+.
544 * These transformations don't change the behavior.
545 *
546 * First, get rid of DST in the blend factors:
547 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
548 */
549 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
550 PIPE_BLENDFACTOR_DST_COLOR,
551 PIPE_BLENDFACTOR_SRC_COLOR);
552 si_blend_remove_dst(&eqA, &srcA, &dstA,
553 PIPE_BLENDFACTOR_DST_COLOR,
554 PIPE_BLENDFACTOR_SRC_COLOR);
555 si_blend_remove_dst(&eqA, &srcA, &dstA,
556 PIPE_BLENDFACTOR_DST_ALPHA,
557 PIPE_BLENDFACTOR_SRC_ALPHA);
558
559 /* Look up the ideal settings from tables. */
560 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
561 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
562 srcA_opt = si_translate_blend_opt_factor(srcA, true);
563 dstA_opt = si_translate_blend_opt_factor(dstA, true);
564
565 /* Handle interdependencies. */
566 if (si_blend_factor_uses_dst(srcRGB))
567 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
568 if (si_blend_factor_uses_dst(srcA))
569 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
570
571 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
572 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
573 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
574 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
575 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
576
577 /* Set the final value. */
578 sx_mrt_blend_opt[i] =
579 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
580 S_028760_COLOR_DST_OPT(dstRGB_opt) |
581 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
582 S_028760_ALPHA_SRC_OPT(srcA_opt) |
583 S_028760_ALPHA_DST_OPT(dstA_opt) |
584 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
585
586 /* Set blend state. */
587 blend_cntl |= S_028780_ENABLE(1);
588 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
589 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
590 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
591
592 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
593 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
594 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
595 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
596 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
597 }
598 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
599
600 blend->blend_enable_4bit |= 0xfu << (i * 4);
601
602 /* This is only important for formats without alpha. */
603 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
604 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
605 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
606 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
607 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
608 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
609 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
610 }
611
612 if (blend->cb_target_mask) {
613 color_control |= S_028808_MODE(mode);
614 } else {
615 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
616 }
617
618 if (sctx->screen->rbplus_allowed) {
619 /* Disable RB+ blend optimizations for dual source blending.
620 * Vulkan does this.
621 */
622 if (blend->dual_src_blend) {
623 for (int i = 0; i < 8; i++) {
624 sx_mrt_blend_opt[i] =
625 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
626 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
627 }
628 }
629
630 for (int i = 0; i < 8; i++)
631 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
632 sx_mrt_blend_opt[i]);
633
634 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
635 if (blend->dual_src_blend || state->logicop_enable ||
636 mode == V_028808_CB_RESOLVE)
637 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
638 }
639
640 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
641 return blend;
642 }
643
644 static void *si_create_blend_state(struct pipe_context *ctx,
645 const struct pipe_blend_state *state)
646 {
647 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
648 }
649
650 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
651 {
652 struct si_context *sctx = (struct si_context *)ctx;
653 struct si_state_blend *old_blend = sctx->queued.named.blend;
654 struct si_state_blend *blend = (struct si_state_blend *)state;
655
656 if (!state)
657 return;
658
659 si_pm4_bind_state(sctx, blend, state);
660
661 if (!old_blend ||
662 old_blend->cb_target_mask != blend->cb_target_mask ||
663 old_blend->dual_src_blend != blend->dual_src_blend ||
664 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
665 sctx->framebuffer.nr_samples >= 2 &&
666 sctx->screen->dcc_msaa_allowed))
667 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
668
669 if (!old_blend ||
670 old_blend->cb_target_mask != blend->cb_target_mask ||
671 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
672 old_blend->alpha_to_one != blend->alpha_to_one ||
673 old_blend->dual_src_blend != blend->dual_src_blend ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
676 sctx->do_update_shaders = true;
677
678 if (sctx->screen->dpbb_allowed &&
679 (!old_blend ||
680 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
681 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
682 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
683 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
684
685 if (sctx->screen->has_out_of_order_rast &&
686 (!old_blend ||
687 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
688 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
689 old_blend->commutative_4bit != blend->commutative_4bit ||
690 old_blend->logicop_enable != blend->logicop_enable)))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
692 }
693
694 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
698 }
699
700 static void si_set_blend_color(struct pipe_context *ctx,
701 const struct pipe_blend_color *state)
702 {
703 struct si_context *sctx = (struct si_context *)ctx;
704 static const struct pipe_blend_color zeros;
705
706 sctx->blend_color.state = *state;
707 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
708 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
709 }
710
711 static void si_emit_blend_color(struct si_context *sctx)
712 {
713 struct radeon_cmdbuf *cs = sctx->gfx_cs;
714
715 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
716 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
717 }
718
719 /*
720 * Clipping
721 */
722
723 static void si_set_clip_state(struct pipe_context *ctx,
724 const struct pipe_clip_state *state)
725 {
726 struct si_context *sctx = (struct si_context *)ctx;
727 struct pipe_constant_buffer cb;
728 static const struct pipe_clip_state zeros;
729
730 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
731 return;
732
733 sctx->clip_state.state = *state;
734 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
735 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
736
737 cb.buffer = NULL;
738 cb.user_buffer = state->ucp;
739 cb.buffer_offset = 0;
740 cb.buffer_size = 4*4*8;
741 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
742 pipe_resource_reference(&cb.buffer, NULL);
743 }
744
745 static void si_emit_clip_state(struct si_context *sctx)
746 {
747 struct radeon_cmdbuf *cs = sctx->gfx_cs;
748
749 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
750 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
751 }
752
753 static void si_emit_clip_regs(struct si_context *sctx)
754 {
755 struct si_shader *vs = si_get_vs_state(sctx);
756 struct si_shader_selector *vs_sel = vs->selector;
757 struct tgsi_shader_info *info = &vs_sel->info;
758 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
759 unsigned window_space =
760 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
761 unsigned clipdist_mask = vs_sel->clipdist_mask;
762 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
763 unsigned culldist_mask = vs_sel->culldist_mask;
764 unsigned total_mask;
765
766 if (vs->key.opt.clip_disable) {
767 assert(!info->culldist_writemask);
768 clipdist_mask = 0;
769 culldist_mask = 0;
770 }
771 total_mask = clipdist_mask | culldist_mask;
772
773 /* Clip distances on points have no effect, so need to be implemented
774 * as cull distances. This applies for the clipvertex case as well.
775 *
776 * Setting this for primitives other than points should have no adverse
777 * effects.
778 */
779 clipdist_mask &= rs->clip_plane_enable;
780 culldist_mask |= clipdist_mask;
781
782 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
783 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
784 SI_TRACKED_PA_CL_VS_OUT_CNTL,
785 vs_sel->pa_cl_vs_out_cntl |
786 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
787 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
788 clipdist_mask | (culldist_mask << 8));
789 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
790 SI_TRACKED_PA_CL_CLIP_CNTL,
791 rs->pa_cl_clip_cntl |
792 ucp_mask |
793 S_028810_CLIP_DISABLE(window_space));
794
795 if (initial_cdw != sctx->gfx_cs->current.cdw)
796 sctx->context_roll = true;
797 }
798
799 /*
800 * inferred state between framebuffer and rasterizer
801 */
802 static void si_update_poly_offset_state(struct si_context *sctx)
803 {
804 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
805
806 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
807 si_pm4_bind_state(sctx, poly_offset, NULL);
808 return;
809 }
810
811 /* Use the user format, not db_render_format, so that the polygon
812 * offset behaves as expected by applications.
813 */
814 switch (sctx->framebuffer.state.zsbuf->texture->format) {
815 case PIPE_FORMAT_Z16_UNORM:
816 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
817 break;
818 default: /* 24-bit */
819 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
820 break;
821 case PIPE_FORMAT_Z32_FLOAT:
822 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
823 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
824 break;
825 }
826 }
827
828 /*
829 * Rasterizer
830 */
831
832 static uint32_t si_translate_fill(uint32_t func)
833 {
834 switch(func) {
835 case PIPE_POLYGON_MODE_FILL:
836 return V_028814_X_DRAW_TRIANGLES;
837 case PIPE_POLYGON_MODE_LINE:
838 return V_028814_X_DRAW_LINES;
839 case PIPE_POLYGON_MODE_POINT:
840 return V_028814_X_DRAW_POINTS;
841 default:
842 assert(0);
843 return V_028814_X_DRAW_POINTS;
844 }
845 }
846
847 static void *si_create_rs_state(struct pipe_context *ctx,
848 const struct pipe_rasterizer_state *state)
849 {
850 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
851 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
852 struct si_pm4_state *pm4 = &rs->pm4;
853 unsigned tmp, i;
854 float psize_min, psize_max;
855
856 if (!rs) {
857 return NULL;
858 }
859
860 if (!state->front_ccw) {
861 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
862 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
863 } else {
864 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
865 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
866 }
867 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
868 rs->provoking_vertex_first = state->flatshade_first;
869 rs->scissor_enable = state->scissor;
870 rs->clip_halfz = state->clip_halfz;
871 rs->two_side = state->light_twoside;
872 rs->multisample_enable = state->multisample;
873 rs->force_persample_interp = state->force_persample_interp;
874 rs->clip_plane_enable = state->clip_plane_enable;
875 rs->half_pixel_center = state->half_pixel_center;
876 rs->line_stipple_enable = state->line_stipple_enable;
877 rs->poly_stipple_enable = state->poly_stipple_enable;
878 rs->line_smooth = state->line_smooth;
879 rs->line_width = state->line_width;
880 rs->poly_smooth = state->poly_smooth;
881 rs->uses_poly_offset = state->offset_point || state->offset_line ||
882 state->offset_tri;
883 rs->clamp_fragment_color = state->clamp_fragment_color;
884 rs->clamp_vertex_color = state->clamp_vertex_color;
885 rs->flatshade = state->flatshade;
886 rs->sprite_coord_enable = state->sprite_coord_enable;
887 rs->rasterizer_discard = state->rasterizer_discard;
888 rs->pa_sc_line_stipple = state->line_stipple_enable ?
889 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
890 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
891 rs->pa_cl_clip_cntl =
892 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
893 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
894 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
895 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
896 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
897
898 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
899 S_0286D4_FLAT_SHADE_ENA(1) |
900 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
901 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
902 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
903 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
904 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
905 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
906
907 /* point size 12.4 fixed point */
908 tmp = (unsigned)(state->point_size * 8.0);
909 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
910
911 if (state->point_size_per_vertex) {
912 psize_min = util_get_min_point_size(state);
913 psize_max = SI_MAX_POINT_SIZE;
914 } else {
915 /* Force the point size to be as if the vertex output was disabled. */
916 psize_min = state->point_size;
917 psize_max = state->point_size;
918 }
919 rs->max_point_size = psize_max;
920
921 /* Divide by two, because 0.5 = 1 pixel. */
922 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
923 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
924 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
925
926 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
927 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
928 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
929 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
930 S_028A48_MSAA_ENABLE(state->multisample ||
931 state->poly_smooth ||
932 state->line_smooth) |
933 S_028A48_VPORT_SCISSOR_ENABLE(1) |
934 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
935
936 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
937 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
938 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
939 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
940 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
941 S_028814_FACE(!state->front_ccw) |
942 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
943 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
944 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
945 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
946 state->fill_back != PIPE_POLYGON_MODE_FILL) |
947 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
948 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
949
950 if (!rs->uses_poly_offset)
951 return rs;
952
953 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
954 if (!rs->pm4_poly_offset) {
955 FREE(rs);
956 return NULL;
957 }
958
959 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
960 for (i = 0; i < 3; i++) {
961 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
962 float offset_units = state->offset_units;
963 float offset_scale = state->offset_scale * 16.0f;
964 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
965
966 if (!state->offset_units_unscaled) {
967 switch (i) {
968 case 0: /* 16-bit zbuffer */
969 offset_units *= 4.0f;
970 pa_su_poly_offset_db_fmt_cntl =
971 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
972 break;
973 case 1: /* 24-bit zbuffer */
974 offset_units *= 2.0f;
975 pa_su_poly_offset_db_fmt_cntl =
976 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
977 break;
978 case 2: /* 32-bit zbuffer */
979 offset_units *= 1.0f;
980 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
981 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
982 break;
983 }
984 }
985
986 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
987 fui(offset_scale));
988 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
989 fui(offset_units));
990 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
991 fui(offset_scale));
992 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
993 fui(offset_units));
994 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
995 pa_su_poly_offset_db_fmt_cntl);
996 }
997
998 return rs;
999 }
1000
1001 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1002 {
1003 struct si_context *sctx = (struct si_context *)ctx;
1004 struct si_state_rasterizer *old_rs =
1005 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1006 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1007
1008 if (!state)
1009 return;
1010
1011 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1012 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1013
1014 /* Update the small primitive filter workaround if necessary. */
1015 if (sctx->screen->has_msaa_sample_loc_bug &&
1016 sctx->framebuffer.nr_samples > 1)
1017 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1018 }
1019
1020 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1021 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1022
1023 si_pm4_bind_state(sctx, rasterizer, rs);
1024 si_update_poly_offset_state(sctx);
1025
1026 if (!old_rs ||
1027 old_rs->scissor_enable != rs->scissor_enable)
1028 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1029
1030 if (!old_rs ||
1031 old_rs->line_width != rs->line_width ||
1032 old_rs->max_point_size != rs->max_point_size ||
1033 old_rs->half_pixel_center != rs->half_pixel_center)
1034 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1035
1036 if (!old_rs ||
1037 old_rs->clip_halfz != rs->clip_halfz)
1038 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1039
1040 if (!old_rs ||
1041 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1042 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1043 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1044
1045 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1046 rs->line_stipple_enable;
1047
1048 if (!old_rs ||
1049 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1050 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1051 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1052 old_rs->flatshade != rs->flatshade ||
1053 old_rs->two_side != rs->two_side ||
1054 old_rs->multisample_enable != rs->multisample_enable ||
1055 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1056 old_rs->poly_smooth != rs->poly_smooth ||
1057 old_rs->line_smooth != rs->line_smooth ||
1058 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1059 old_rs->force_persample_interp != rs->force_persample_interp)
1060 sctx->do_update_shaders = true;
1061 }
1062
1063 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1064 {
1065 struct si_context *sctx = (struct si_context *)ctx;
1066 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1067
1068 if (sctx->queued.named.rasterizer == state)
1069 si_pm4_bind_state(sctx, poly_offset, NULL);
1070
1071 FREE(rs->pm4_poly_offset);
1072 si_pm4_delete_state(sctx, rasterizer, rs);
1073 }
1074
1075 /*
1076 * infeered state between dsa and stencil ref
1077 */
1078 static void si_emit_stencil_ref(struct si_context *sctx)
1079 {
1080 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1081 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1082 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1083
1084 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1085 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1086 S_028430_STENCILMASK(dsa->valuemask[0]) |
1087 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1088 S_028430_STENCILOPVAL(1));
1089 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1090 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1091 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1092 S_028434_STENCILOPVAL_BF(1));
1093 }
1094
1095 static void si_set_stencil_ref(struct pipe_context *ctx,
1096 const struct pipe_stencil_ref *state)
1097 {
1098 struct si_context *sctx = (struct si_context *)ctx;
1099
1100 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1101 return;
1102
1103 sctx->stencil_ref.state = *state;
1104 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1105 }
1106
1107
1108 /*
1109 * DSA
1110 */
1111
1112 static uint32_t si_translate_stencil_op(int s_op)
1113 {
1114 switch (s_op) {
1115 case PIPE_STENCIL_OP_KEEP:
1116 return V_02842C_STENCIL_KEEP;
1117 case PIPE_STENCIL_OP_ZERO:
1118 return V_02842C_STENCIL_ZERO;
1119 case PIPE_STENCIL_OP_REPLACE:
1120 return V_02842C_STENCIL_REPLACE_TEST;
1121 case PIPE_STENCIL_OP_INCR:
1122 return V_02842C_STENCIL_ADD_CLAMP;
1123 case PIPE_STENCIL_OP_DECR:
1124 return V_02842C_STENCIL_SUB_CLAMP;
1125 case PIPE_STENCIL_OP_INCR_WRAP:
1126 return V_02842C_STENCIL_ADD_WRAP;
1127 case PIPE_STENCIL_OP_DECR_WRAP:
1128 return V_02842C_STENCIL_SUB_WRAP;
1129 case PIPE_STENCIL_OP_INVERT:
1130 return V_02842C_STENCIL_INVERT;
1131 default:
1132 PRINT_ERR("Unknown stencil op %d", s_op);
1133 assert(0);
1134 break;
1135 }
1136 return 0;
1137 }
1138
1139 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1140 {
1141 return s->enabled && s->writemask &&
1142 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1143 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1144 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1145 }
1146
1147 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1148 {
1149 /* REPLACE is normally order invariant, except when the stencil
1150 * reference value is written by the fragment shader. Tracking this
1151 * interaction does not seem worth the effort, so be conservative. */
1152 return op != PIPE_STENCIL_OP_INCR &&
1153 op != PIPE_STENCIL_OP_DECR &&
1154 op != PIPE_STENCIL_OP_REPLACE;
1155 }
1156
1157 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1158 * invariant in the sense that the set of passing fragments as well as the
1159 * final stencil buffer result does not depend on the order of fragments. */
1160 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1161 {
1162 return !state->enabled || !state->writemask ||
1163 /* The following assumes that Z writes are disabled. */
1164 (state->func == PIPE_FUNC_ALWAYS &&
1165 si_order_invariant_stencil_op(state->zpass_op) &&
1166 si_order_invariant_stencil_op(state->zfail_op)) ||
1167 (state->func == PIPE_FUNC_NEVER &&
1168 si_order_invariant_stencil_op(state->fail_op));
1169 }
1170
1171 static void *si_create_dsa_state(struct pipe_context *ctx,
1172 const struct pipe_depth_stencil_alpha_state *state)
1173 {
1174 struct si_context *sctx = (struct si_context *)ctx;
1175 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1176 struct si_pm4_state *pm4 = &dsa->pm4;
1177 unsigned db_depth_control;
1178 uint32_t db_stencil_control = 0;
1179
1180 if (!dsa) {
1181 return NULL;
1182 }
1183
1184 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1185 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1186 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1187 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1188
1189 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1190 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1191 S_028800_ZFUNC(state->depth.func) |
1192 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1193
1194 /* stencil */
1195 if (state->stencil[0].enabled) {
1196 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1197 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1198 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1199 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1200 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1201
1202 if (state->stencil[1].enabled) {
1203 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1204 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1205 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1206 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1207 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1208 }
1209 }
1210
1211 /* alpha */
1212 if (state->alpha.enabled) {
1213 dsa->alpha_func = state->alpha.func;
1214
1215 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1216 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1217 } else {
1218 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1219 }
1220
1221 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1222 if (state->stencil[0].enabled)
1223 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1224 if (state->depth.bounds_test) {
1225 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1226 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1227 }
1228
1229 dsa->depth_enabled = state->depth.enabled;
1230 dsa->depth_write_enabled = state->depth.enabled &&
1231 state->depth.writemask;
1232 dsa->stencil_enabled = state->stencil[0].enabled;
1233 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1234 (si_dsa_writes_stencil(&state->stencil[0]) ||
1235 si_dsa_writes_stencil(&state->stencil[1]));
1236 dsa->db_can_write = dsa->depth_write_enabled ||
1237 dsa->stencil_write_enabled;
1238
1239 bool zfunc_is_ordered =
1240 state->depth.func == PIPE_FUNC_NEVER ||
1241 state->depth.func == PIPE_FUNC_LESS ||
1242 state->depth.func == PIPE_FUNC_LEQUAL ||
1243 state->depth.func == PIPE_FUNC_GREATER ||
1244 state->depth.func == PIPE_FUNC_GEQUAL;
1245
1246 bool nozwrite_and_order_invariant_stencil =
1247 !dsa->db_can_write ||
1248 (!dsa->depth_write_enabled &&
1249 si_order_invariant_stencil_state(&state->stencil[0]) &&
1250 si_order_invariant_stencil_state(&state->stencil[1]));
1251
1252 dsa->order_invariance[1].zs =
1253 nozwrite_and_order_invariant_stencil ||
1254 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1255 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1256
1257 dsa->order_invariance[1].pass_set =
1258 nozwrite_and_order_invariant_stencil ||
1259 (!dsa->stencil_write_enabled &&
1260 (state->depth.func == PIPE_FUNC_ALWAYS ||
1261 state->depth.func == PIPE_FUNC_NEVER));
1262 dsa->order_invariance[0].pass_set =
1263 !dsa->depth_write_enabled ||
1264 (state->depth.func == PIPE_FUNC_ALWAYS ||
1265 state->depth.func == PIPE_FUNC_NEVER);
1266
1267 dsa->order_invariance[1].pass_last =
1268 sctx->screen->assume_no_z_fights &&
1269 !dsa->stencil_write_enabled &&
1270 dsa->depth_write_enabled && zfunc_is_ordered;
1271 dsa->order_invariance[0].pass_last =
1272 sctx->screen->assume_no_z_fights &&
1273 dsa->depth_write_enabled && zfunc_is_ordered;
1274
1275 return dsa;
1276 }
1277
1278 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1279 {
1280 struct si_context *sctx = (struct si_context *)ctx;
1281 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1282 struct si_state_dsa *dsa = state;
1283
1284 if (!state)
1285 return;
1286
1287 si_pm4_bind_state(sctx, dsa, dsa);
1288
1289 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1290 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1291 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1292 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1293 }
1294
1295 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1296 sctx->do_update_shaders = true;
1297
1298 if (sctx->screen->dpbb_allowed &&
1299 (!old_dsa ||
1300 (old_dsa->depth_enabled != dsa->depth_enabled ||
1301 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1302 old_dsa->db_can_write != dsa->db_can_write)))
1303 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1304
1305 if (sctx->screen->has_out_of_order_rast &&
1306 (!old_dsa ||
1307 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1308 sizeof(old_dsa->order_invariance))))
1309 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1310 }
1311
1312 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1313 {
1314 struct si_context *sctx = (struct si_context *)ctx;
1315 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1316 }
1317
1318 static void *si_create_db_flush_dsa(struct si_context *sctx)
1319 {
1320 struct pipe_depth_stencil_alpha_state dsa = {};
1321
1322 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1323 }
1324
1325 /* DB RENDER STATE */
1326
1327 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1328 {
1329 struct si_context *sctx = (struct si_context*)ctx;
1330
1331 /* Pipeline stat & streamout queries. */
1332 if (enable) {
1333 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1334 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1335 } else {
1336 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1337 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1338 }
1339
1340 /* Occlusion queries. */
1341 if (sctx->occlusion_queries_disabled != !enable) {
1342 sctx->occlusion_queries_disabled = !enable;
1343 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1344 }
1345 }
1346
1347 void si_set_occlusion_query_state(struct si_context *sctx,
1348 bool old_perfect_enable)
1349 {
1350 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1351
1352 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1353
1354 if (perfect_enable != old_perfect_enable)
1355 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1356 }
1357
1358 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1359 {
1360 st->saved_compute = sctx->cs_shader_state.program;
1361
1362 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1363 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1364
1365 st->saved_ssbo_writable_mask = 0;
1366
1367 for (unsigned i = 0; i < 3; i++) {
1368 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1369 (1u << si_get_shaderbuf_slot(i)))
1370 st->saved_ssbo_writable_mask |= 1 << i;
1371 }
1372 }
1373
1374 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1375 {
1376 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1377
1378 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1379 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1380
1381 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1382 st->saved_ssbo_writable_mask);
1383 for (unsigned i = 0; i < 3; ++i)
1384 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1385 }
1386
1387 static void si_emit_db_render_state(struct si_context *sctx)
1388 {
1389 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1390 unsigned db_shader_control, db_render_control, db_count_control;
1391 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1392
1393 /* DB_RENDER_CONTROL */
1394 if (sctx->dbcb_depth_copy_enabled ||
1395 sctx->dbcb_stencil_copy_enabled) {
1396 db_render_control =
1397 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1398 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1399 S_028000_COPY_CENTROID(1) |
1400 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1401 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1402 db_render_control =
1403 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1404 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1405 } else {
1406 db_render_control =
1407 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1408 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1409 }
1410
1411 /* DB_COUNT_CONTROL (occlusion queries) */
1412 if (sctx->num_occlusion_queries > 0 &&
1413 !sctx->occlusion_queries_disabled) {
1414 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1415
1416 if (sctx->chip_class >= GFX7) {
1417 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1418
1419 /* Stoney doesn't increment occlusion query counters
1420 * if the sample rate is 16x. Use 8x sample rate instead.
1421 */
1422 if (sctx->family == CHIP_STONEY)
1423 log_sample_rate = MIN2(log_sample_rate, 3);
1424
1425 db_count_control =
1426 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1427 S_028004_SAMPLE_RATE(log_sample_rate) |
1428 S_028004_ZPASS_ENABLE(1) |
1429 S_028004_SLICE_EVEN_ENABLE(1) |
1430 S_028004_SLICE_ODD_ENABLE(1);
1431 } else {
1432 db_count_control =
1433 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1434 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1435 }
1436 } else {
1437 /* Disable occlusion queries. */
1438 if (sctx->chip_class >= GFX7) {
1439 db_count_control = 0;
1440 } else {
1441 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1442 }
1443 }
1444
1445 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1446 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1447 db_count_control);
1448
1449 /* DB_RENDER_OVERRIDE2 */
1450 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1451 SI_TRACKED_DB_RENDER_OVERRIDE2,
1452 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1453 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1454 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1455
1456 db_shader_control = sctx->ps_db_shader_control;
1457
1458 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1459 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1460 db_shader_control &= C_02880C_Z_ORDER;
1461 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1462 }
1463
1464 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1465 if (!rs->multisample_enable)
1466 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1467
1468 if (sctx->screen->has_rbplus &&
1469 !sctx->screen->rbplus_allowed)
1470 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1471
1472 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1473 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1474
1475 if (initial_cdw != sctx->gfx_cs->current.cdw)
1476 sctx->context_roll = true;
1477 }
1478
1479 /*
1480 * format translation
1481 */
1482 static uint32_t si_translate_colorformat(enum pipe_format format)
1483 {
1484 const struct util_format_description *desc = util_format_description(format);
1485 if (!desc)
1486 return V_028C70_COLOR_INVALID;
1487
1488 #define HAS_SIZE(x,y,z,w) \
1489 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1490 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1491
1492 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1493 return V_028C70_COLOR_10_11_11;
1494
1495 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1496 return V_028C70_COLOR_INVALID;
1497
1498 /* hw cannot support mixed formats (except depth/stencil, since
1499 * stencil is not written to). */
1500 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1501 return V_028C70_COLOR_INVALID;
1502
1503 switch (desc->nr_channels) {
1504 case 1:
1505 switch (desc->channel[0].size) {
1506 case 8:
1507 return V_028C70_COLOR_8;
1508 case 16:
1509 return V_028C70_COLOR_16;
1510 case 32:
1511 return V_028C70_COLOR_32;
1512 }
1513 break;
1514 case 2:
1515 if (desc->channel[0].size == desc->channel[1].size) {
1516 switch (desc->channel[0].size) {
1517 case 8:
1518 return V_028C70_COLOR_8_8;
1519 case 16:
1520 return V_028C70_COLOR_16_16;
1521 case 32:
1522 return V_028C70_COLOR_32_32;
1523 }
1524 } else if (HAS_SIZE(8,24,0,0)) {
1525 return V_028C70_COLOR_24_8;
1526 } else if (HAS_SIZE(24,8,0,0)) {
1527 return V_028C70_COLOR_8_24;
1528 }
1529 break;
1530 case 3:
1531 if (HAS_SIZE(5,6,5,0)) {
1532 return V_028C70_COLOR_5_6_5;
1533 } else if (HAS_SIZE(32,8,24,0)) {
1534 return V_028C70_COLOR_X24_8_32_FLOAT;
1535 }
1536 break;
1537 case 4:
1538 if (desc->channel[0].size == desc->channel[1].size &&
1539 desc->channel[0].size == desc->channel[2].size &&
1540 desc->channel[0].size == desc->channel[3].size) {
1541 switch (desc->channel[0].size) {
1542 case 4:
1543 return V_028C70_COLOR_4_4_4_4;
1544 case 8:
1545 return V_028C70_COLOR_8_8_8_8;
1546 case 16:
1547 return V_028C70_COLOR_16_16_16_16;
1548 case 32:
1549 return V_028C70_COLOR_32_32_32_32;
1550 }
1551 } else if (HAS_SIZE(5,5,5,1)) {
1552 return V_028C70_COLOR_1_5_5_5;
1553 } else if (HAS_SIZE(1,5,5,5)) {
1554 return V_028C70_COLOR_5_5_5_1;
1555 } else if (HAS_SIZE(10,10,10,2)) {
1556 return V_028C70_COLOR_2_10_10_10;
1557 }
1558 break;
1559 }
1560 return V_028C70_COLOR_INVALID;
1561 }
1562
1563 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1564 {
1565 if (SI_BIG_ENDIAN) {
1566 switch(colorformat) {
1567 /* 8-bit buffers. */
1568 case V_028C70_COLOR_8:
1569 return V_028C70_ENDIAN_NONE;
1570
1571 /* 16-bit buffers. */
1572 case V_028C70_COLOR_5_6_5:
1573 case V_028C70_COLOR_1_5_5_5:
1574 case V_028C70_COLOR_4_4_4_4:
1575 case V_028C70_COLOR_16:
1576 case V_028C70_COLOR_8_8:
1577 return V_028C70_ENDIAN_8IN16;
1578
1579 /* 32-bit buffers. */
1580 case V_028C70_COLOR_8_8_8_8:
1581 case V_028C70_COLOR_2_10_10_10:
1582 case V_028C70_COLOR_8_24:
1583 case V_028C70_COLOR_24_8:
1584 case V_028C70_COLOR_16_16:
1585 return V_028C70_ENDIAN_8IN32;
1586
1587 /* 64-bit buffers. */
1588 case V_028C70_COLOR_16_16_16_16:
1589 return V_028C70_ENDIAN_8IN16;
1590
1591 case V_028C70_COLOR_32_32:
1592 return V_028C70_ENDIAN_8IN32;
1593
1594 /* 128-bit buffers. */
1595 case V_028C70_COLOR_32_32_32_32:
1596 return V_028C70_ENDIAN_8IN32;
1597 default:
1598 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1599 }
1600 } else {
1601 return V_028C70_ENDIAN_NONE;
1602 }
1603 }
1604
1605 static uint32_t si_translate_dbformat(enum pipe_format format)
1606 {
1607 switch (format) {
1608 case PIPE_FORMAT_Z16_UNORM:
1609 return V_028040_Z_16;
1610 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1611 case PIPE_FORMAT_X8Z24_UNORM:
1612 case PIPE_FORMAT_Z24X8_UNORM:
1613 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1614 return V_028040_Z_24; /* deprecated on AMD GCN */
1615 case PIPE_FORMAT_Z32_FLOAT:
1616 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1617 return V_028040_Z_32_FLOAT;
1618 default:
1619 return V_028040_Z_INVALID;
1620 }
1621 }
1622
1623 /*
1624 * Texture translation
1625 */
1626
1627 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1628 enum pipe_format format,
1629 const struct util_format_description *desc,
1630 int first_non_void)
1631 {
1632 struct si_screen *sscreen = (struct si_screen*)screen;
1633 bool uniform = true;
1634 int i;
1635
1636 assert(sscreen->info.chip_class <= GFX9);
1637
1638 /* Colorspace (return non-RGB formats directly). */
1639 switch (desc->colorspace) {
1640 /* Depth stencil formats */
1641 case UTIL_FORMAT_COLORSPACE_ZS:
1642 switch (format) {
1643 case PIPE_FORMAT_Z16_UNORM:
1644 return V_008F14_IMG_DATA_FORMAT_16;
1645 case PIPE_FORMAT_X24S8_UINT:
1646 case PIPE_FORMAT_S8X24_UINT:
1647 /*
1648 * Implemented as an 8_8_8_8 data format to fix texture
1649 * gathers in stencil sampling. This affects at least
1650 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1651 */
1652 if (sscreen->info.chip_class <= GFX8)
1653 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1654
1655 if (format == PIPE_FORMAT_X24S8_UINT)
1656 return V_008F14_IMG_DATA_FORMAT_8_24;
1657 else
1658 return V_008F14_IMG_DATA_FORMAT_24_8;
1659 case PIPE_FORMAT_Z24X8_UNORM:
1660 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1661 return V_008F14_IMG_DATA_FORMAT_8_24;
1662 case PIPE_FORMAT_X8Z24_UNORM:
1663 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1664 return V_008F14_IMG_DATA_FORMAT_24_8;
1665 case PIPE_FORMAT_S8_UINT:
1666 return V_008F14_IMG_DATA_FORMAT_8;
1667 case PIPE_FORMAT_Z32_FLOAT:
1668 return V_008F14_IMG_DATA_FORMAT_32;
1669 case PIPE_FORMAT_X32_S8X24_UINT:
1670 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1671 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1672 default:
1673 goto out_unknown;
1674 }
1675
1676 case UTIL_FORMAT_COLORSPACE_YUV:
1677 goto out_unknown; /* TODO */
1678
1679 case UTIL_FORMAT_COLORSPACE_SRGB:
1680 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1681 goto out_unknown;
1682 break;
1683
1684 default:
1685 break;
1686 }
1687
1688 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1689 if (!sscreen->info.has_format_bc1_through_bc7)
1690 goto out_unknown;
1691
1692 switch (format) {
1693 case PIPE_FORMAT_RGTC1_SNORM:
1694 case PIPE_FORMAT_LATC1_SNORM:
1695 case PIPE_FORMAT_RGTC1_UNORM:
1696 case PIPE_FORMAT_LATC1_UNORM:
1697 return V_008F14_IMG_DATA_FORMAT_BC4;
1698 case PIPE_FORMAT_RGTC2_SNORM:
1699 case PIPE_FORMAT_LATC2_SNORM:
1700 case PIPE_FORMAT_RGTC2_UNORM:
1701 case PIPE_FORMAT_LATC2_UNORM:
1702 return V_008F14_IMG_DATA_FORMAT_BC5;
1703 default:
1704 goto out_unknown;
1705 }
1706 }
1707
1708 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1709 (sscreen->info.family == CHIP_STONEY ||
1710 sscreen->info.family == CHIP_VEGA10 ||
1711 sscreen->info.family == CHIP_RAVEN)) {
1712 switch (format) {
1713 case PIPE_FORMAT_ETC1_RGB8:
1714 case PIPE_FORMAT_ETC2_RGB8:
1715 case PIPE_FORMAT_ETC2_SRGB8:
1716 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1717 case PIPE_FORMAT_ETC2_RGB8A1:
1718 case PIPE_FORMAT_ETC2_SRGB8A1:
1719 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1720 case PIPE_FORMAT_ETC2_RGBA8:
1721 case PIPE_FORMAT_ETC2_SRGBA8:
1722 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1723 case PIPE_FORMAT_ETC2_R11_UNORM:
1724 case PIPE_FORMAT_ETC2_R11_SNORM:
1725 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1726 case PIPE_FORMAT_ETC2_RG11_UNORM:
1727 case PIPE_FORMAT_ETC2_RG11_SNORM:
1728 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1729 default:
1730 goto out_unknown;
1731 }
1732 }
1733
1734 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1735 if (!sscreen->info.has_format_bc1_through_bc7)
1736 goto out_unknown;
1737
1738 switch (format) {
1739 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1740 case PIPE_FORMAT_BPTC_SRGBA:
1741 return V_008F14_IMG_DATA_FORMAT_BC7;
1742 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1743 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1744 return V_008F14_IMG_DATA_FORMAT_BC6;
1745 default:
1746 goto out_unknown;
1747 }
1748 }
1749
1750 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1751 switch (format) {
1752 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1753 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1754 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1755 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1756 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1757 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1758 default:
1759 goto out_unknown;
1760 }
1761 }
1762
1763 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1764 if (!sscreen->info.has_format_bc1_through_bc7)
1765 goto out_unknown;
1766
1767 switch (format) {
1768 case PIPE_FORMAT_DXT1_RGB:
1769 case PIPE_FORMAT_DXT1_RGBA:
1770 case PIPE_FORMAT_DXT1_SRGB:
1771 case PIPE_FORMAT_DXT1_SRGBA:
1772 return V_008F14_IMG_DATA_FORMAT_BC1;
1773 case PIPE_FORMAT_DXT3_RGBA:
1774 case PIPE_FORMAT_DXT3_SRGBA:
1775 return V_008F14_IMG_DATA_FORMAT_BC2;
1776 case PIPE_FORMAT_DXT5_RGBA:
1777 case PIPE_FORMAT_DXT5_SRGBA:
1778 return V_008F14_IMG_DATA_FORMAT_BC3;
1779 default:
1780 goto out_unknown;
1781 }
1782 }
1783
1784 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1785 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1786 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1787 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1788 }
1789
1790 /* R8G8Bx_SNORM - TODO CxV8U8 */
1791
1792 /* hw cannot support mixed formats (except depth/stencil, since only
1793 * depth is read).*/
1794 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1795 goto out_unknown;
1796
1797 /* See whether the components are of the same size. */
1798 for (i = 1; i < desc->nr_channels; i++) {
1799 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1800 }
1801
1802 /* Non-uniform formats. */
1803 if (!uniform) {
1804 switch(desc->nr_channels) {
1805 case 3:
1806 if (desc->channel[0].size == 5 &&
1807 desc->channel[1].size == 6 &&
1808 desc->channel[2].size == 5) {
1809 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1810 }
1811 goto out_unknown;
1812 case 4:
1813 if (desc->channel[0].size == 5 &&
1814 desc->channel[1].size == 5 &&
1815 desc->channel[2].size == 5 &&
1816 desc->channel[3].size == 1) {
1817 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1818 }
1819 if (desc->channel[0].size == 1 &&
1820 desc->channel[1].size == 5 &&
1821 desc->channel[2].size == 5 &&
1822 desc->channel[3].size == 5) {
1823 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1824 }
1825 if (desc->channel[0].size == 10 &&
1826 desc->channel[1].size == 10 &&
1827 desc->channel[2].size == 10 &&
1828 desc->channel[3].size == 2) {
1829 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1830 }
1831 goto out_unknown;
1832 }
1833 goto out_unknown;
1834 }
1835
1836 if (first_non_void < 0 || first_non_void > 3)
1837 goto out_unknown;
1838
1839 /* uniform formats */
1840 switch (desc->channel[first_non_void].size) {
1841 case 4:
1842 switch (desc->nr_channels) {
1843 #if 0 /* Not supported for render targets */
1844 case 2:
1845 return V_008F14_IMG_DATA_FORMAT_4_4;
1846 #endif
1847 case 4:
1848 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1849 }
1850 break;
1851 case 8:
1852 switch (desc->nr_channels) {
1853 case 1:
1854 return V_008F14_IMG_DATA_FORMAT_8;
1855 case 2:
1856 return V_008F14_IMG_DATA_FORMAT_8_8;
1857 case 4:
1858 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1859 }
1860 break;
1861 case 16:
1862 switch (desc->nr_channels) {
1863 case 1:
1864 return V_008F14_IMG_DATA_FORMAT_16;
1865 case 2:
1866 return V_008F14_IMG_DATA_FORMAT_16_16;
1867 case 4:
1868 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1869 }
1870 break;
1871 case 32:
1872 switch (desc->nr_channels) {
1873 case 1:
1874 return V_008F14_IMG_DATA_FORMAT_32;
1875 case 2:
1876 return V_008F14_IMG_DATA_FORMAT_32_32;
1877 #if 0 /* Not supported for render targets */
1878 case 3:
1879 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1880 #endif
1881 case 4:
1882 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1883 }
1884 }
1885
1886 out_unknown:
1887 return ~0;
1888 }
1889
1890 static unsigned si_tex_wrap(unsigned wrap)
1891 {
1892 switch (wrap) {
1893 default:
1894 case PIPE_TEX_WRAP_REPEAT:
1895 return V_008F30_SQ_TEX_WRAP;
1896 case PIPE_TEX_WRAP_CLAMP:
1897 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1898 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1899 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1900 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1901 return V_008F30_SQ_TEX_CLAMP_BORDER;
1902 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1903 return V_008F30_SQ_TEX_MIRROR;
1904 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1905 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1906 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1907 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1908 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1909 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1910 }
1911 }
1912
1913 static unsigned si_tex_mipfilter(unsigned filter)
1914 {
1915 switch (filter) {
1916 case PIPE_TEX_MIPFILTER_NEAREST:
1917 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1918 case PIPE_TEX_MIPFILTER_LINEAR:
1919 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1920 default:
1921 case PIPE_TEX_MIPFILTER_NONE:
1922 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1923 }
1924 }
1925
1926 static unsigned si_tex_compare(unsigned compare)
1927 {
1928 switch (compare) {
1929 default:
1930 case PIPE_FUNC_NEVER:
1931 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1932 case PIPE_FUNC_LESS:
1933 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1934 case PIPE_FUNC_EQUAL:
1935 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1936 case PIPE_FUNC_LEQUAL:
1937 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1938 case PIPE_FUNC_GREATER:
1939 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1940 case PIPE_FUNC_NOTEQUAL:
1941 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1942 case PIPE_FUNC_GEQUAL:
1943 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1944 case PIPE_FUNC_ALWAYS:
1945 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1946 }
1947 }
1948
1949 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1950 unsigned view_target, unsigned nr_samples)
1951 {
1952 unsigned res_target = tex->buffer.b.b.target;
1953
1954 if (view_target == PIPE_TEXTURE_CUBE ||
1955 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1956 res_target = view_target;
1957 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1958 else if (res_target == PIPE_TEXTURE_CUBE ||
1959 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1960 res_target = PIPE_TEXTURE_2D_ARRAY;
1961
1962 /* GFX9 allocates 1D textures as 2D. */
1963 if ((res_target == PIPE_TEXTURE_1D ||
1964 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1965 sscreen->info.chip_class >= GFX9 &&
1966 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1967 if (res_target == PIPE_TEXTURE_1D)
1968 res_target = PIPE_TEXTURE_2D;
1969 else
1970 res_target = PIPE_TEXTURE_2D_ARRAY;
1971 }
1972
1973 switch (res_target) {
1974 default:
1975 case PIPE_TEXTURE_1D:
1976 return V_008F1C_SQ_RSRC_IMG_1D;
1977 case PIPE_TEXTURE_1D_ARRAY:
1978 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1979 case PIPE_TEXTURE_2D:
1980 case PIPE_TEXTURE_RECT:
1981 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1982 V_008F1C_SQ_RSRC_IMG_2D;
1983 case PIPE_TEXTURE_2D_ARRAY:
1984 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1985 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1986 case PIPE_TEXTURE_3D:
1987 return V_008F1C_SQ_RSRC_IMG_3D;
1988 case PIPE_TEXTURE_CUBE:
1989 case PIPE_TEXTURE_CUBE_ARRAY:
1990 return V_008F1C_SQ_RSRC_IMG_CUBE;
1991 }
1992 }
1993
1994 /*
1995 * Format support testing
1996 */
1997
1998 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1999 {
2000 const struct util_format_description *desc = util_format_description(format);
2001 if (!desc)
2002 return false;
2003
2004 return si_translate_texformat(screen, format, desc,
2005 util_format_get_first_non_void_channel(format)) != ~0U;
2006 }
2007
2008 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2009 const struct util_format_description *desc,
2010 int first_non_void)
2011 {
2012 int i;
2013
2014 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2015
2016 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2017 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2018
2019 assert(first_non_void >= 0);
2020
2021 if (desc->nr_channels == 4 &&
2022 desc->channel[0].size == 10 &&
2023 desc->channel[1].size == 10 &&
2024 desc->channel[2].size == 10 &&
2025 desc->channel[3].size == 2)
2026 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2027
2028 /* See whether the components are of the same size. */
2029 for (i = 0; i < desc->nr_channels; i++) {
2030 if (desc->channel[first_non_void].size != desc->channel[i].size)
2031 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2032 }
2033
2034 switch (desc->channel[first_non_void].size) {
2035 case 8:
2036 switch (desc->nr_channels) {
2037 case 1:
2038 case 3: /* 3 loads */
2039 return V_008F0C_BUF_DATA_FORMAT_8;
2040 case 2:
2041 return V_008F0C_BUF_DATA_FORMAT_8_8;
2042 case 4:
2043 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2044 }
2045 break;
2046 case 16:
2047 switch (desc->nr_channels) {
2048 case 1:
2049 case 3: /* 3 loads */
2050 return V_008F0C_BUF_DATA_FORMAT_16;
2051 case 2:
2052 return V_008F0C_BUF_DATA_FORMAT_16_16;
2053 case 4:
2054 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2055 }
2056 break;
2057 case 32:
2058 switch (desc->nr_channels) {
2059 case 1:
2060 return V_008F0C_BUF_DATA_FORMAT_32;
2061 case 2:
2062 return V_008F0C_BUF_DATA_FORMAT_32_32;
2063 case 3:
2064 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2065 case 4:
2066 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2067 }
2068 break;
2069 case 64:
2070 /* Legacy double formats. */
2071 switch (desc->nr_channels) {
2072 case 1: /* 1 load */
2073 return V_008F0C_BUF_DATA_FORMAT_32_32;
2074 case 2: /* 1 load */
2075 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2076 case 3: /* 3 loads */
2077 return V_008F0C_BUF_DATA_FORMAT_32_32;
2078 case 4: /* 2 loads */
2079 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2080 }
2081 break;
2082 }
2083
2084 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2085 }
2086
2087 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2088 const struct util_format_description *desc,
2089 int first_non_void)
2090 {
2091 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2092
2093 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2094 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2095
2096 assert(first_non_void >= 0);
2097
2098 switch (desc->channel[first_non_void].type) {
2099 case UTIL_FORMAT_TYPE_SIGNED:
2100 case UTIL_FORMAT_TYPE_FIXED:
2101 if (desc->channel[first_non_void].size >= 32 ||
2102 desc->channel[first_non_void].pure_integer)
2103 return V_008F0C_BUF_NUM_FORMAT_SINT;
2104 else if (desc->channel[first_non_void].normalized)
2105 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2106 else
2107 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2108 break;
2109 case UTIL_FORMAT_TYPE_UNSIGNED:
2110 if (desc->channel[first_non_void].size >= 32 ||
2111 desc->channel[first_non_void].pure_integer)
2112 return V_008F0C_BUF_NUM_FORMAT_UINT;
2113 else if (desc->channel[first_non_void].normalized)
2114 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2115 else
2116 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2117 break;
2118 case UTIL_FORMAT_TYPE_FLOAT:
2119 default:
2120 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2121 }
2122 }
2123
2124 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2125 enum pipe_format format,
2126 unsigned usage)
2127 {
2128 const struct util_format_description *desc;
2129 int first_non_void;
2130 unsigned data_format;
2131
2132 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2133 PIPE_BIND_SAMPLER_VIEW |
2134 PIPE_BIND_VERTEX_BUFFER)) == 0);
2135
2136 desc = util_format_description(format);
2137 if (!desc)
2138 return 0;
2139
2140 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2141 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2142 * for read-only access (with caveats surrounding bounds checks), but
2143 * obviously fails for write access which we have to implement for
2144 * shader images. Luckily, OpenGL doesn't expect this to be supported
2145 * anyway, and so the only impact is on PBO uploads / downloads, which
2146 * shouldn't be expected to be fast for GL_RGB anyway.
2147 */
2148 if (desc->block.bits == 3 * 8 ||
2149 desc->block.bits == 3 * 16) {
2150 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2151 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2152 if (!usage)
2153 return 0;
2154 }
2155 }
2156
2157 first_non_void = util_format_get_first_non_void_channel(format);
2158 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2159 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2160 return 0;
2161
2162 return usage;
2163 }
2164
2165 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2166 {
2167 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2168 si_translate_colorswap(format, false) != ~0U;
2169 }
2170
2171 static bool si_is_zs_format_supported(enum pipe_format format)
2172 {
2173 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2174 }
2175
2176 static boolean si_is_format_supported(struct pipe_screen *screen,
2177 enum pipe_format format,
2178 enum pipe_texture_target target,
2179 unsigned sample_count,
2180 unsigned storage_sample_count,
2181 unsigned usage)
2182 {
2183 struct si_screen *sscreen = (struct si_screen *)screen;
2184 unsigned retval = 0;
2185
2186 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2187 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2188 return false;
2189 }
2190
2191 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2192 return false;
2193
2194 if (sample_count > 1) {
2195 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2196 return false;
2197
2198 if (usage & PIPE_BIND_SHADER_IMAGE)
2199 return false;
2200
2201 /* Only power-of-two sample counts are supported. */
2202 if (!util_is_power_of_two_or_zero(sample_count) ||
2203 !util_is_power_of_two_or_zero(storage_sample_count))
2204 return false;
2205
2206 /* MSAA support without framebuffer attachments. */
2207 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2208 return true;
2209
2210 if (!sscreen->info.has_eqaa_surface_allocator ||
2211 util_format_is_depth_or_stencil(format)) {
2212 /* Color without EQAA or depth/stencil. */
2213 if (sample_count > 8 ||
2214 sample_count != storage_sample_count)
2215 return false;
2216 } else {
2217 /* Color with EQAA. */
2218 if (sample_count > 16 ||
2219 storage_sample_count > 8)
2220 return false;
2221 }
2222 }
2223
2224 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2225 PIPE_BIND_SHADER_IMAGE)) {
2226 if (target == PIPE_BUFFER) {
2227 retval |= si_is_vertex_format_supported(
2228 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2229 PIPE_BIND_SHADER_IMAGE));
2230 } else {
2231 if (si_is_sampler_format_supported(screen, format))
2232 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2233 PIPE_BIND_SHADER_IMAGE);
2234 }
2235 }
2236
2237 if ((usage & (PIPE_BIND_RENDER_TARGET |
2238 PIPE_BIND_DISPLAY_TARGET |
2239 PIPE_BIND_SCANOUT |
2240 PIPE_BIND_SHARED |
2241 PIPE_BIND_BLENDABLE)) &&
2242 si_is_colorbuffer_format_supported(format)) {
2243 retval |= usage &
2244 (PIPE_BIND_RENDER_TARGET |
2245 PIPE_BIND_DISPLAY_TARGET |
2246 PIPE_BIND_SCANOUT |
2247 PIPE_BIND_SHARED);
2248 if (!util_format_is_pure_integer(format) &&
2249 !util_format_is_depth_or_stencil(format))
2250 retval |= usage & PIPE_BIND_BLENDABLE;
2251 }
2252
2253 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2254 si_is_zs_format_supported(format)) {
2255 retval |= PIPE_BIND_DEPTH_STENCIL;
2256 }
2257
2258 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2259 retval |= si_is_vertex_format_supported(screen, format,
2260 PIPE_BIND_VERTEX_BUFFER);
2261 }
2262
2263 if ((usage & PIPE_BIND_LINEAR) &&
2264 !util_format_is_compressed(format) &&
2265 !(usage & PIPE_BIND_DEPTH_STENCIL))
2266 retval |= PIPE_BIND_LINEAR;
2267
2268 return retval == usage;
2269 }
2270
2271 /*
2272 * framebuffer handling
2273 */
2274
2275 static void si_choose_spi_color_formats(struct si_surface *surf,
2276 unsigned format, unsigned swap,
2277 unsigned ntype, bool is_depth)
2278 {
2279 /* Alpha is needed for alpha-to-coverage.
2280 * Blending may be with or without alpha.
2281 */
2282 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2283 unsigned alpha = 0; /* exports alpha, but may not support blending */
2284 unsigned blend = 0; /* supports blending, but may not export alpha */
2285 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2286
2287 /* Choose the SPI color formats. These are required values for RB+.
2288 * Other chips have multiple choices, though they are not necessarily better.
2289 */
2290 switch (format) {
2291 case V_028C70_COLOR_5_6_5:
2292 case V_028C70_COLOR_1_5_5_5:
2293 case V_028C70_COLOR_5_5_5_1:
2294 case V_028C70_COLOR_4_4_4_4:
2295 case V_028C70_COLOR_10_11_11:
2296 case V_028C70_COLOR_11_11_10:
2297 case V_028C70_COLOR_8:
2298 case V_028C70_COLOR_8_8:
2299 case V_028C70_COLOR_8_8_8_8:
2300 case V_028C70_COLOR_10_10_10_2:
2301 case V_028C70_COLOR_2_10_10_10:
2302 if (ntype == V_028C70_NUMBER_UINT)
2303 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2304 else if (ntype == V_028C70_NUMBER_SINT)
2305 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2306 else
2307 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2308 break;
2309
2310 case V_028C70_COLOR_16:
2311 case V_028C70_COLOR_16_16:
2312 case V_028C70_COLOR_16_16_16_16:
2313 if (ntype == V_028C70_NUMBER_UNORM ||
2314 ntype == V_028C70_NUMBER_SNORM) {
2315 /* UNORM16 and SNORM16 don't support blending */
2316 if (ntype == V_028C70_NUMBER_UNORM)
2317 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2318 else
2319 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2320
2321 /* Use 32 bits per channel for blending. */
2322 if (format == V_028C70_COLOR_16) {
2323 if (swap == V_028C70_SWAP_STD) { /* R */
2324 blend = V_028714_SPI_SHADER_32_R;
2325 blend_alpha = V_028714_SPI_SHADER_32_AR;
2326 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2327 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2328 else
2329 assert(0);
2330 } else if (format == V_028C70_COLOR_16_16) {
2331 if (swap == V_028C70_SWAP_STD) { /* RG */
2332 blend = V_028714_SPI_SHADER_32_GR;
2333 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2334 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2335 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2336 else
2337 assert(0);
2338 } else /* 16_16_16_16 */
2339 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2340 } else if (ntype == V_028C70_NUMBER_UINT)
2341 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2342 else if (ntype == V_028C70_NUMBER_SINT)
2343 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2344 else if (ntype == V_028C70_NUMBER_FLOAT)
2345 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2346 else
2347 assert(0);
2348 break;
2349
2350 case V_028C70_COLOR_32:
2351 if (swap == V_028C70_SWAP_STD) { /* R */
2352 blend = normal = V_028714_SPI_SHADER_32_R;
2353 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2354 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2355 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2356 else
2357 assert(0);
2358 break;
2359
2360 case V_028C70_COLOR_32_32:
2361 if (swap == V_028C70_SWAP_STD) { /* RG */
2362 blend = normal = V_028714_SPI_SHADER_32_GR;
2363 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2364 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2365 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2366 else
2367 assert(0);
2368 break;
2369
2370 case V_028C70_COLOR_32_32_32_32:
2371 case V_028C70_COLOR_8_24:
2372 case V_028C70_COLOR_24_8:
2373 case V_028C70_COLOR_X24_8_32_FLOAT:
2374 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2375 break;
2376
2377 default:
2378 assert(0);
2379 return;
2380 }
2381
2382 /* The DB->CB copy needs 32_ABGR. */
2383 if (is_depth)
2384 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2385
2386 surf->spi_shader_col_format = normal;
2387 surf->spi_shader_col_format_alpha = alpha;
2388 surf->spi_shader_col_format_blend = blend;
2389 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2390 }
2391
2392 static void si_initialize_color_surface(struct si_context *sctx,
2393 struct si_surface *surf)
2394 {
2395 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2396 unsigned color_info, color_attrib;
2397 unsigned format, swap, ntype, endian;
2398 const struct util_format_description *desc;
2399 int firstchan;
2400 unsigned blend_clamp = 0, blend_bypass = 0;
2401
2402 desc = util_format_description(surf->base.format);
2403 for (firstchan = 0; firstchan < 4; firstchan++) {
2404 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2405 break;
2406 }
2407 }
2408 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2409 ntype = V_028C70_NUMBER_FLOAT;
2410 } else {
2411 ntype = V_028C70_NUMBER_UNORM;
2412 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2413 ntype = V_028C70_NUMBER_SRGB;
2414 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2415 if (desc->channel[firstchan].pure_integer) {
2416 ntype = V_028C70_NUMBER_SINT;
2417 } else {
2418 assert(desc->channel[firstchan].normalized);
2419 ntype = V_028C70_NUMBER_SNORM;
2420 }
2421 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2422 if (desc->channel[firstchan].pure_integer) {
2423 ntype = V_028C70_NUMBER_UINT;
2424 } else {
2425 assert(desc->channel[firstchan].normalized);
2426 ntype = V_028C70_NUMBER_UNORM;
2427 }
2428 }
2429 }
2430
2431 format = si_translate_colorformat(surf->base.format);
2432 if (format == V_028C70_COLOR_INVALID) {
2433 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2434 }
2435 assert(format != V_028C70_COLOR_INVALID);
2436 swap = si_translate_colorswap(surf->base.format, false);
2437 endian = si_colorformat_endian_swap(format);
2438
2439 /* blend clamp should be set for all NORM/SRGB types */
2440 if (ntype == V_028C70_NUMBER_UNORM ||
2441 ntype == V_028C70_NUMBER_SNORM ||
2442 ntype == V_028C70_NUMBER_SRGB)
2443 blend_clamp = 1;
2444
2445 /* set blend bypass according to docs if SINT/UINT or
2446 8/24 COLOR variants */
2447 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2448 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2449 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2450 blend_clamp = 0;
2451 blend_bypass = 1;
2452 }
2453
2454 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2455 if (format == V_028C70_COLOR_8 ||
2456 format == V_028C70_COLOR_8_8 ||
2457 format == V_028C70_COLOR_8_8_8_8)
2458 surf->color_is_int8 = true;
2459 else if (format == V_028C70_COLOR_10_10_10_2 ||
2460 format == V_028C70_COLOR_2_10_10_10)
2461 surf->color_is_int10 = true;
2462 }
2463
2464 color_info = S_028C70_FORMAT(format) |
2465 S_028C70_COMP_SWAP(swap) |
2466 S_028C70_BLEND_CLAMP(blend_clamp) |
2467 S_028C70_BLEND_BYPASS(blend_bypass) |
2468 S_028C70_SIMPLE_FLOAT(1) |
2469 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2470 ntype != V_028C70_NUMBER_SNORM &&
2471 ntype != V_028C70_NUMBER_SRGB &&
2472 format != V_028C70_COLOR_8_24 &&
2473 format != V_028C70_COLOR_24_8) |
2474 S_028C70_NUMBER_TYPE(ntype) |
2475 S_028C70_ENDIAN(endian);
2476
2477 /* Intensity is implemented as Red, so treat it that way. */
2478 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2479 util_format_is_intensity(surf->base.format));
2480
2481 if (tex->buffer.b.b.nr_samples > 1) {
2482 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2483 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2484
2485 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2486 S_028C74_NUM_FRAGMENTS(log_fragments);
2487
2488 if (tex->fmask_offset) {
2489 color_info |= S_028C70_COMPRESSION(1);
2490 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2491
2492 if (sctx->chip_class == GFX6) {
2493 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2494 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2495 }
2496 }
2497 }
2498
2499 if (sctx->chip_class >= GFX8) {
2500 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2501 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2502
2503 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2504 64 for APU because all of our APUs to date use DIMMs which have
2505 a request granularity size of 64B while all other chips have a
2506 32B request size */
2507 if (!sctx->screen->info.has_dedicated_vram)
2508 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2509
2510 if (tex->buffer.b.b.nr_storage_samples > 1) {
2511 if (tex->surface.bpe == 1)
2512 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2513 else if (tex->surface.bpe == 2)
2514 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2515 }
2516
2517 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2518 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2519 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2520 }
2521
2522 /* This must be set for fast clear to work without FMASK. */
2523 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2524 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2525 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2526 }
2527
2528 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2529 S_028C6C_SLICE_MAX_GFX6(surf->base.u.tex.last_layer);
2530
2531 if (sctx->chip_class >= GFX9) {
2532 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2533
2534 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2535 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2536 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2537 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2538 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2539 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2540 }
2541
2542 surf->cb_color_view = color_view;
2543 surf->cb_color_info = color_info;
2544 surf->cb_color_attrib = color_attrib;
2545
2546 /* Determine pixel shader export format */
2547 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2548
2549 surf->color_initialized = true;
2550 }
2551
2552 static void si_init_depth_surface(struct si_context *sctx,
2553 struct si_surface *surf)
2554 {
2555 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2556 unsigned level = surf->base.u.tex.level;
2557 unsigned format, stencil_format;
2558 uint32_t z_info, s_info;
2559
2560 format = si_translate_dbformat(tex->db_render_format);
2561 stencil_format = tex->surface.has_stencil ?
2562 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2563
2564 assert(format != V_028040_Z_INVALID);
2565 if (format == V_028040_Z_INVALID)
2566 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2567
2568 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2569 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2570 surf->db_htile_data_base = 0;
2571 surf->db_htile_surface = 0;
2572
2573 if (sctx->chip_class >= GFX9) {
2574 assert(tex->surface.u.gfx9.surf_offset == 0);
2575 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2576 surf->db_stencil_base = (tex->buffer.gpu_address +
2577 tex->surface.u.gfx9.stencil_offset) >> 8;
2578 z_info = S_028038_FORMAT(format) |
2579 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2580 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2581 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2582 s_info = S_02803C_FORMAT(stencil_format) |
2583 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2584 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2585 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2586 surf->db_depth_view |= S_028008_MIPID(level);
2587 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2588 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2589
2590 if (si_htile_enabled(tex, level)) {
2591 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2592 S_028038_ALLOW_EXPCLEAR(1);
2593
2594 if (tex->tc_compatible_htile) {
2595 unsigned max_zplanes = 4;
2596
2597 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2598 tex->buffer.b.b.nr_samples > 1)
2599 max_zplanes = 2;
2600
2601 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2602 S_028038_ITERATE_FLUSH(1);
2603 s_info |= S_02803C_ITERATE_FLUSH(1);
2604 }
2605
2606 if (tex->surface.has_stencil) {
2607 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2608 * See that for explanation.
2609 */
2610 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2611 } else {
2612 /* Use all HTILE for depth if there's no stencil. */
2613 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2614 }
2615
2616 surf->db_htile_data_base = (tex->buffer.gpu_address +
2617 tex->htile_offset) >> 8;
2618 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2619 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2620 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2621 }
2622 } else {
2623 /* GFX6-GFX8 */
2624 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2625
2626 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2627
2628 surf->db_depth_base = (tex->buffer.gpu_address +
2629 tex->surface.u.legacy.level[level].offset) >> 8;
2630 surf->db_stencil_base = (tex->buffer.gpu_address +
2631 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2632
2633 z_info = S_028040_FORMAT(format) |
2634 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2635 s_info = S_028044_FORMAT(stencil_format);
2636 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2637
2638 if (sctx->chip_class >= GFX7) {
2639 struct radeon_info *info = &sctx->screen->info;
2640 unsigned index = tex->surface.u.legacy.tiling_index[level];
2641 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2642 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2643 unsigned tile_mode = info->si_tile_mode_array[index];
2644 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2645 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2646
2647 surf->db_depth_info |=
2648 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2649 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2650 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2651 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2652 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2653 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2654 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2655 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2656 } else {
2657 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2658 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2659 tile_mode_index = si_tile_mode_index(tex, level, true);
2660 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2661 }
2662
2663 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2664 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2665 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2666 levelinfo->nblk_y) / 64 - 1);
2667
2668 if (si_htile_enabled(tex, level)) {
2669 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2670 S_028040_ALLOW_EXPCLEAR(1);
2671
2672 if (tex->surface.has_stencil) {
2673 /* Workaround: For a not yet understood reason, the
2674 * combination of MSAA, fast stencil clear and stencil
2675 * decompress messes with subsequent stencil buffer
2676 * uses. Problem was reproduced on Verde, Bonaire,
2677 * Tonga, and Carrizo.
2678 *
2679 * Disabling EXPCLEAR works around the problem.
2680 *
2681 * Check piglit's arb_texture_multisample-stencil-clear
2682 * test if you want to try changing this.
2683 */
2684 if (tex->buffer.b.b.nr_samples <= 1)
2685 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2686 } else if (!tex->tc_compatible_htile) {
2687 /* Use all of the htile_buffer for depth if there's no stencil.
2688 * This must not be set when TC-compatible HTILE is enabled
2689 * due to a hw bug.
2690 */
2691 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2692 }
2693
2694 surf->db_htile_data_base = (tex->buffer.gpu_address +
2695 tex->htile_offset) >> 8;
2696 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2697
2698 if (tex->tc_compatible_htile) {
2699 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2700
2701 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2702 if (tex->buffer.b.b.nr_samples <= 1)
2703 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2704 else if (tex->buffer.b.b.nr_samples <= 4)
2705 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2706 else
2707 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2708 }
2709 }
2710 }
2711
2712 surf->db_z_info = z_info;
2713 surf->db_stencil_info = s_info;
2714
2715 surf->depth_initialized = true;
2716 }
2717
2718 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2719 {
2720 if (sctx->decompression_enabled)
2721 return;
2722
2723 if (sctx->framebuffer.state.zsbuf) {
2724 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2725 struct si_texture *tex = (struct si_texture *)surf->texture;
2726
2727 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2728
2729 if (tex->surface.has_stencil)
2730 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2731 }
2732
2733 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2734 while (compressed_cb_mask) {
2735 unsigned i = u_bit_scan(&compressed_cb_mask);
2736 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2737 struct si_texture *tex = (struct si_texture*)surf->texture;
2738
2739 if (tex->fmask_offset)
2740 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2741 if (tex->dcc_gather_statistics)
2742 tex->separate_dcc_dirty = true;
2743 }
2744 }
2745
2746 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2747 {
2748 for (int i = 0; i < state->nr_cbufs; ++i) {
2749 struct si_surface *surf = NULL;
2750 struct si_texture *tex;
2751
2752 if (!state->cbufs[i])
2753 continue;
2754 surf = (struct si_surface*)state->cbufs[i];
2755 tex = (struct si_texture*)surf->base.texture;
2756
2757 p_atomic_dec(&tex->framebuffers_bound);
2758 }
2759 }
2760
2761 static void si_set_framebuffer_state(struct pipe_context *ctx,
2762 const struct pipe_framebuffer_state *state)
2763 {
2764 struct si_context *sctx = (struct si_context *)ctx;
2765 struct si_surface *surf = NULL;
2766 struct si_texture *tex;
2767 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2768 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2769 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2770 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2771 bool old_has_stencil =
2772 old_has_zsbuf &&
2773 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2774 bool unbound = false;
2775 int i;
2776
2777 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2778 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2779 * We could implement the full workaround here, but it's a useless case.
2780 */
2781 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2782 unreachable("the framebuffer shouldn't have zero area");
2783 return;
2784 }
2785
2786 si_update_fb_dirtiness_after_rendering(sctx);
2787
2788 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2789 if (!sctx->framebuffer.state.cbufs[i])
2790 continue;
2791
2792 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2793 if (tex->dcc_gather_statistics)
2794 vi_separate_dcc_stop_query(sctx, tex);
2795 }
2796
2797 /* Disable DCC if the formats are incompatible. */
2798 for (i = 0; i < state->nr_cbufs; i++) {
2799 if (!state->cbufs[i])
2800 continue;
2801
2802 surf = (struct si_surface*)state->cbufs[i];
2803 tex = (struct si_texture*)surf->base.texture;
2804
2805 if (!surf->dcc_incompatible)
2806 continue;
2807
2808 /* Since the DCC decompression calls back into set_framebuffer-
2809 * _state, we need to unbind the framebuffer, so that
2810 * vi_separate_dcc_stop_query isn't called twice with the same
2811 * color buffer.
2812 */
2813 if (!unbound) {
2814 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2815 unbound = true;
2816 }
2817
2818 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2819 if (!si_texture_disable_dcc(sctx, tex))
2820 si_decompress_dcc(sctx, tex);
2821
2822 surf->dcc_incompatible = false;
2823 }
2824
2825 /* Only flush TC when changing the framebuffer state, because
2826 * the only client not using TC that can change textures is
2827 * the framebuffer.
2828 *
2829 * Wait for compute shaders because of possible transitions:
2830 * - FB write -> shader read
2831 * - shader write -> FB read
2832 *
2833 * DB caches are flushed on demand (using si_decompress_textures).
2834 *
2835 * When MSAA is enabled, CB and TC caches are flushed on demand
2836 * (after FMASK decompression). Shader write -> FB read transitions
2837 * cannot happen for MSAA textures, because MSAA shader images are
2838 * not supported.
2839 *
2840 * Only flush and wait for CB if there is actually a bound color buffer.
2841 */
2842 if (sctx->framebuffer.uncompressed_cb_mask) {
2843 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2844 sctx->framebuffer.CB_has_shader_readable_metadata,
2845 sctx->framebuffer.all_DCC_pipe_aligned);
2846 }
2847
2848 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2849
2850 /* u_blitter doesn't invoke depth decompression when it does multiple
2851 * blits in a row, but the only case when it matters for DB is when
2852 * doing generate_mipmap. So here we flush DB manually between
2853 * individual generate_mipmap blits.
2854 * Note that lower mipmap levels aren't compressed.
2855 */
2856 if (sctx->generate_mipmap_for_depth) {
2857 si_make_DB_shader_coherent(sctx, 1, false,
2858 sctx->framebuffer.DB_has_shader_readable_metadata);
2859 } else if (sctx->chip_class == GFX9) {
2860 /* It appears that DB metadata "leaks" in a sequence of:
2861 * - depth clear
2862 * - DCC decompress for shader image writes (with DB disabled)
2863 * - render with DEPTH_BEFORE_SHADER=1
2864 * Flushing DB metadata works around the problem.
2865 */
2866 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2867 }
2868
2869 /* Take the maximum of the old and new count. If the new count is lower,
2870 * dirtying is needed to disable the unbound colorbuffers.
2871 */
2872 sctx->framebuffer.dirty_cbufs |=
2873 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2874 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2875
2876 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2877 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2878
2879 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2880 sctx->framebuffer.spi_shader_col_format = 0;
2881 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2882 sctx->framebuffer.spi_shader_col_format_blend = 0;
2883 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2884 sctx->framebuffer.color_is_int8 = 0;
2885 sctx->framebuffer.color_is_int10 = 0;
2886
2887 sctx->framebuffer.compressed_cb_mask = 0;
2888 sctx->framebuffer.uncompressed_cb_mask = 0;
2889 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2890 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2891 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2892 sctx->framebuffer.any_dst_linear = false;
2893 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2894 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2895 sctx->framebuffer.all_DCC_pipe_aligned = true;
2896 unsigned num_bpp64_colorbufs = 0;
2897
2898 for (i = 0; i < state->nr_cbufs; i++) {
2899 if (!state->cbufs[i])
2900 continue;
2901
2902 surf = (struct si_surface*)state->cbufs[i];
2903 tex = (struct si_texture*)surf->base.texture;
2904
2905 if (!surf->color_initialized) {
2906 si_initialize_color_surface(sctx, surf);
2907 }
2908
2909 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2910 sctx->framebuffer.spi_shader_col_format |=
2911 surf->spi_shader_col_format << (i * 4);
2912 sctx->framebuffer.spi_shader_col_format_alpha |=
2913 surf->spi_shader_col_format_alpha << (i * 4);
2914 sctx->framebuffer.spi_shader_col_format_blend |=
2915 surf->spi_shader_col_format_blend << (i * 4);
2916 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2917 surf->spi_shader_col_format_blend_alpha << (i * 4);
2918
2919 if (surf->color_is_int8)
2920 sctx->framebuffer.color_is_int8 |= 1 << i;
2921 if (surf->color_is_int10)
2922 sctx->framebuffer.color_is_int10 |= 1 << i;
2923
2924 if (tex->fmask_offset)
2925 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2926 else
2927 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2928
2929 /* Don't update nr_color_samples for non-AA buffers.
2930 * (e.g. destination of MSAA resolve)
2931 */
2932 if (tex->buffer.b.b.nr_samples >= 2 &&
2933 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2934 sctx->framebuffer.nr_color_samples =
2935 MIN2(sctx->framebuffer.nr_color_samples,
2936 tex->buffer.b.b.nr_storage_samples);
2937 sctx->framebuffer.nr_color_samples =
2938 MAX2(1, sctx->framebuffer.nr_color_samples);
2939 }
2940
2941 if (tex->surface.is_linear)
2942 sctx->framebuffer.any_dst_linear = true;
2943 if (tex->surface.bpe >= 8)
2944 num_bpp64_colorbufs++;
2945
2946 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2947 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2948
2949 if (sctx->chip_class >= GFX9 &&
2950 !tex->surface.u.gfx9.dcc.pipe_aligned)
2951 sctx->framebuffer.all_DCC_pipe_aligned = false;
2952 }
2953
2954 si_context_add_resource_size(sctx, surf->base.texture);
2955
2956 p_atomic_inc(&tex->framebuffers_bound);
2957
2958 if (tex->dcc_gather_statistics) {
2959 /* Dirty tracking must be enabled for DCC usage analysis. */
2960 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2961 vi_separate_dcc_start_query(sctx, tex);
2962 }
2963 }
2964
2965 /* For optimal DCC performance. */
2966 if (sctx->chip_class == GFX8)
2967 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2968 else if (num_bpp64_colorbufs >= 5)
2969 sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
2970 else
2971 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2972
2973 struct si_texture *zstex = NULL;
2974
2975 if (state->zsbuf) {
2976 surf = (struct si_surface*)state->zsbuf;
2977 zstex = (struct si_texture*)surf->base.texture;
2978
2979 if (!surf->depth_initialized) {
2980 si_init_depth_surface(sctx, surf);
2981 }
2982
2983 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2984 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2985
2986 si_context_add_resource_size(sctx, surf->base.texture);
2987 }
2988
2989 si_update_ps_colorbuf0_slot(sctx);
2990 si_update_poly_offset_state(sctx);
2991 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2992 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2993
2994 if (sctx->screen->dpbb_allowed)
2995 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2996
2997 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2998 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2999
3000 if (sctx->screen->has_out_of_order_rast &&
3001 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3002 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3003 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3004 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3005
3006 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3007 struct pipe_constant_buffer constbuf = {0};
3008
3009 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3010 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3011
3012 constbuf.buffer = sctx->sample_pos_buffer;
3013
3014 /* Set sample locations as fragment shader constants. */
3015 switch (sctx->framebuffer.nr_samples) {
3016 case 1:
3017 constbuf.buffer_offset = 0;
3018 break;
3019 case 2:
3020 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3021 (ubyte*)sctx->sample_positions.x1;
3022 break;
3023 case 4:
3024 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3025 (ubyte*)sctx->sample_positions.x1;
3026 break;
3027 case 8:
3028 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3029 (ubyte*)sctx->sample_positions.x1;
3030 break;
3031 case 16:
3032 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3033 (ubyte*)sctx->sample_positions.x1;
3034 break;
3035 default:
3036 PRINT_ERR("Requested an invalid number of samples %i.\n",
3037 sctx->framebuffer.nr_samples);
3038 assert(0);
3039 }
3040 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3041 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3042
3043 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3044 }
3045
3046 sctx->do_update_shaders = true;
3047
3048 if (!sctx->decompression_enabled) {
3049 /* Prevent textures decompression when the framebuffer state
3050 * changes come from the decompression passes themselves.
3051 */
3052 sctx->need_check_render_feedback = true;
3053 }
3054 }
3055
3056 static void si_emit_framebuffer_state(struct si_context *sctx)
3057 {
3058 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3059 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3060 unsigned i, nr_cbufs = state->nr_cbufs;
3061 struct si_texture *tex = NULL;
3062 struct si_surface *cb = NULL;
3063 unsigned cb_color_info = 0;
3064
3065 /* Colorbuffers. */
3066 for (i = 0; i < nr_cbufs; i++) {
3067 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3068 unsigned cb_color_attrib;
3069
3070 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3071 continue;
3072
3073 cb = (struct si_surface*)state->cbufs[i];
3074 if (!cb) {
3075 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3076 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3077 continue;
3078 }
3079
3080 tex = (struct si_texture *)cb->base.texture;
3081 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3082 &tex->buffer, RADEON_USAGE_READWRITE,
3083 tex->buffer.b.b.nr_samples > 1 ?
3084 RADEON_PRIO_COLOR_BUFFER_MSAA :
3085 RADEON_PRIO_COLOR_BUFFER);
3086
3087 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3088 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3089 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3090 RADEON_PRIO_SEPARATE_META);
3091 }
3092
3093 if (tex->dcc_separate_buffer)
3094 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3095 tex->dcc_separate_buffer,
3096 RADEON_USAGE_READWRITE,
3097 RADEON_PRIO_SEPARATE_META);
3098
3099 /* Compute mutable surface parameters. */
3100 cb_color_base = tex->buffer.gpu_address >> 8;
3101 cb_color_fmask = 0;
3102 cb_color_cmask = tex->cmask_base_address_reg;
3103 cb_dcc_base = 0;
3104 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3105 cb_color_attrib = cb->cb_color_attrib;
3106
3107 if (cb->base.u.tex.level > 0)
3108 cb_color_info &= C_028C70_FAST_CLEAR;
3109
3110 if (tex->fmask_offset) {
3111 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3112 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3113 }
3114
3115 /* Set up DCC. */
3116 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3117 bool is_msaa_resolve_dst = state->cbufs[0] &&
3118 state->cbufs[0]->texture->nr_samples > 1 &&
3119 state->cbufs[1] == &cb->base &&
3120 state->cbufs[1]->texture->nr_samples <= 1;
3121
3122 if (!is_msaa_resolve_dst)
3123 cb_color_info |= S_028C70_DCC_ENABLE(1);
3124
3125 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3126 tex->dcc_offset) >> 8;
3127 cb_dcc_base |= tex->surface.tile_swizzle;
3128 }
3129
3130 if (sctx->chip_class >= GFX9) {
3131 struct gfx9_surf_meta_flags meta;
3132
3133 if (tex->dcc_offset)
3134 meta = tex->surface.u.gfx9.dcc;
3135 else
3136 meta = tex->surface.u.gfx9.cmask;
3137
3138 /* Set mutable surface parameters. */
3139 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3140 cb_color_base |= tex->surface.tile_swizzle;
3141 if (!tex->fmask_offset)
3142 cb_color_fmask = cb_color_base;
3143 if (cb->base.u.tex.level > 0)
3144 cb_color_cmask = cb_color_base;
3145 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3146 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3147 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3148 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3149
3150 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3151 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3152 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3153 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3154 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3155 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3156 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3157 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3158 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3159 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3160 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3161 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3162 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3163 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3164 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3165 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3166
3167 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3168 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3169 } else {
3170 /* Compute mutable surface parameters (GFX6-GFX8). */
3171 const struct legacy_surf_level *level_info =
3172 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3173 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3174 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3175
3176 cb_color_base += level_info->offset >> 8;
3177 /* Only macrotiled modes can set tile swizzle. */
3178 if (level_info->mode == RADEON_SURF_MODE_2D)
3179 cb_color_base |= tex->surface.tile_swizzle;
3180
3181 if (!tex->fmask_offset)
3182 cb_color_fmask = cb_color_base;
3183 if (cb->base.u.tex.level > 0)
3184 cb_color_cmask = cb_color_base;
3185 if (cb_dcc_base)
3186 cb_dcc_base += level_info->dcc_offset >> 8;
3187
3188 pitch_tile_max = level_info->nblk_x / 8 - 1;
3189 slice_tile_max = level_info->nblk_x *
3190 level_info->nblk_y / 64 - 1;
3191 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3192
3193 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3194 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3195 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3196
3197 if (tex->fmask_offset) {
3198 if (sctx->chip_class >= GFX7)
3199 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3200 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3201 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3202 } else {
3203 /* This must be set for fast clear to work without FMASK. */
3204 if (sctx->chip_class >= GFX7)
3205 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3206 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3207 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3208 }
3209
3210 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3211 sctx->chip_class >= GFX8 ? 14 : 13);
3212 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3213 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3214 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3215 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3216 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3217 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3218 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3219 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3220 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3221 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3222 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3223 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3224 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3225
3226 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3227 radeon_emit(cs, cb_dcc_base);
3228 }
3229 }
3230 for (; i < 8 ; i++)
3231 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3232 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3233
3234 /* ZS buffer. */
3235 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3236 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3237 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3238
3239 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3240 &tex->buffer, RADEON_USAGE_READWRITE,
3241 zb->base.texture->nr_samples > 1 ?
3242 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3243 RADEON_PRIO_DEPTH_BUFFER);
3244
3245 if (sctx->chip_class >= GFX9) {
3246 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3247 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3248 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3249 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3250
3251 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3252 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3253 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3254 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3255 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3256 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3257 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3258 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3259 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3260 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3261 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3262 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3263
3264 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3265 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3266 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3267 } else {
3268 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3269
3270 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3271 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3272 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3273 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3274 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3275 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3276 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3277 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3278 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3279 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3280 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3281 }
3282
3283 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3284 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3285 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3286
3287 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3288 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3289 } else if (sctx->framebuffer.dirty_zsbuf) {
3290 if (sctx->chip_class >= GFX9)
3291 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3292 else
3293 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3294
3295 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3296 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3297 }
3298
3299 /* Framebuffer dimensions. */
3300 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3301 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3302 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3303
3304 if (sctx->screen->dfsm_allowed) {
3305 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3306 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3307 }
3308
3309 sctx->framebuffer.dirty_cbufs = 0;
3310 sctx->framebuffer.dirty_zsbuf = false;
3311 }
3312
3313 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3314 {
3315 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3316 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3317 unsigned nr_samples = sctx->framebuffer.nr_samples;
3318 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3319
3320 /* Smoothing (only possible with nr_samples == 1) uses the same
3321 * sample locations as the MSAA it simulates.
3322 */
3323 if (nr_samples <= 1 && sctx->smoothing_enabled)
3324 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3325
3326 /* On Polaris, the small primitive filter uses the sample locations
3327 * even when MSAA is off, so we need to make sure they're set to 0.
3328 */
3329 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3330 nr_samples != sctx->sample_locs_num_samples) {
3331 sctx->sample_locs_num_samples = nr_samples;
3332 si_emit_sample_locations(cs, nr_samples);
3333 }
3334
3335 if (sctx->family >= CHIP_POLARIS10) {
3336 unsigned small_prim_filter_cntl =
3337 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3338 /* line bug */
3339 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3340
3341 /* The alternative of setting sample locations to 0 would
3342 * require a DB flush to avoid Z errors, see
3343 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3344 */
3345 if (has_msaa_sample_loc_bug &&
3346 sctx->framebuffer.nr_samples > 1 &&
3347 !rs->multisample_enable)
3348 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3349
3350 radeon_opt_set_context_reg(sctx,
3351 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3352 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3353 small_prim_filter_cntl);
3354 }
3355
3356 /* The exclusion bits can be set to improve rasterization efficiency
3357 * if no sample lies on the pixel boundary (-8 sample offset).
3358 */
3359 bool exclusion = sctx->chip_class >= GFX7 &&
3360 (!rs->multisample_enable || nr_samples != 16);
3361 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3362 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3363 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3364 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3365 }
3366
3367 static bool si_out_of_order_rasterization(struct si_context *sctx)
3368 {
3369 struct si_state_blend *blend = sctx->queued.named.blend;
3370 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3371
3372 if (!sctx->screen->has_out_of_order_rast)
3373 return false;
3374
3375 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3376
3377 if (blend) {
3378 colormask &= blend->cb_target_enabled_4bit;
3379 } else {
3380 colormask = 0;
3381 }
3382
3383 /* Conservative: No logic op. */
3384 if (colormask && blend->logicop_enable)
3385 return false;
3386
3387 struct si_dsa_order_invariance dsa_order_invariant = {
3388 .zs = true, .pass_set = true, .pass_last = false
3389 };
3390
3391 if (sctx->framebuffer.state.zsbuf) {
3392 struct si_texture *zstex =
3393 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3394 bool has_stencil = zstex->surface.has_stencil;
3395 dsa_order_invariant = dsa->order_invariance[has_stencil];
3396 if (!dsa_order_invariant.zs)
3397 return false;
3398
3399 /* The set of PS invocations is always order invariant,
3400 * except when early Z/S tests are requested. */
3401 if (sctx->ps_shader.cso &&
3402 sctx->ps_shader.cso->info.writes_memory &&
3403 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3404 !dsa_order_invariant.pass_set)
3405 return false;
3406
3407 if (sctx->num_perfect_occlusion_queries != 0 &&
3408 !dsa_order_invariant.pass_set)
3409 return false;
3410 }
3411
3412 if (!colormask)
3413 return true;
3414
3415 unsigned blendmask = colormask & blend->blend_enable_4bit;
3416
3417 if (blendmask) {
3418 /* Only commutative blending. */
3419 if (blendmask & ~blend->commutative_4bit)
3420 return false;
3421
3422 if (!dsa_order_invariant.pass_set)
3423 return false;
3424 }
3425
3426 if (colormask & ~blendmask) {
3427 if (!dsa_order_invariant.pass_last)
3428 return false;
3429 }
3430
3431 return true;
3432 }
3433
3434 static void si_emit_msaa_config(struct si_context *sctx)
3435 {
3436 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3437 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3438 /* 33% faster rendering to linear color buffers */
3439 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3440 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3441 unsigned sc_mode_cntl_1 =
3442 S_028A4C_WALK_SIZE(dst_is_linear) |
3443 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3444 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3445 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3446 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3447 /* always 1: */
3448 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3449 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3450 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3451 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3452 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3453 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3454 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3455 S_028804_INCOHERENT_EQAA_READS(1) |
3456 S_028804_INTERPOLATE_COMP_Z(1) |
3457 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3458 unsigned coverage_samples, color_samples, z_samples;
3459 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3460
3461 /* S: Coverage samples (up to 16x):
3462 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3463 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3464 *
3465 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3466 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3467 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3468 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3469 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3470 * # Z samples).
3471 *
3472 * F: Color samples (up to 8x, must be <= coverage samples):
3473 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3474 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3475 *
3476 * Can be anything between coverage and color samples:
3477 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3478 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3479 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3480 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3481 * # All are currently set the same as coverage samples.
3482 *
3483 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3484 * flag for undefined color samples. A shader-based resolve must handle unknowns
3485 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3486 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3487 * useful. The CB resolve always drops unknowns.
3488 *
3489 * Sensible AA configurations:
3490 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3491 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3492 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3493 * EQAA 8s 8z 8f = 8x MSAA
3494 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3495 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3496 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3497 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3498 * EQAA 4s 4z 4f = 4x MSAA
3499 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3500 * EQAA 2s 2z 2f = 2x MSAA
3501 */
3502 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3503 coverage_samples = sctx->framebuffer.nr_samples;
3504 color_samples = sctx->framebuffer.nr_color_samples;
3505
3506 if (sctx->framebuffer.state.zsbuf) {
3507 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3508 z_samples = MAX2(1, z_samples);
3509 } else {
3510 z_samples = coverage_samples;
3511 }
3512 } else if (sctx->smoothing_enabled) {
3513 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3514 } else {
3515 coverage_samples = color_samples = z_samples = 1;
3516 }
3517
3518 /* Required by OpenGL line rasterization.
3519 *
3520 * TODO: We should also enable perpendicular endcaps for AA lines,
3521 * but that requires implementing line stippling in the pixel
3522 * shader. SC can only do line stippling with axis-aligned
3523 * endcaps.
3524 */
3525 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3526 unsigned sc_aa_config = 0;
3527
3528 if (coverage_samples > 1) {
3529 /* distance from the pixel center, indexed by log2(nr_samples) */
3530 static unsigned max_dist[] = {
3531 0, /* unused */
3532 4, /* 2x MSAA */
3533 6, /* 4x MSAA */
3534 7, /* 8x MSAA */
3535 8, /* 16x MSAA */
3536 };
3537 unsigned log_samples = util_logbase2(coverage_samples);
3538 unsigned log_z_samples = util_logbase2(z_samples);
3539 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3540 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3541
3542 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3543 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3544 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3545 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3546
3547 if (sctx->framebuffer.nr_samples > 1) {
3548 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3549 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3550 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3551 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3552 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3553 } else if (sctx->smoothing_enabled) {
3554 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3555 }
3556 }
3557
3558 unsigned initial_cdw = cs->current.cdw;
3559
3560 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3561 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3562 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3563 sc_aa_config);
3564 /* R_028804_DB_EQAA */
3565 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3566 db_eqaa);
3567 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3568 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3569 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3570
3571 if (initial_cdw != cs->current.cdw) {
3572 sctx->context_roll = true;
3573
3574 /* GFX9: Flush DFSM when the AA mode changes. */
3575 if (sctx->screen->dfsm_allowed) {
3576 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3577 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3578 }
3579 }
3580 }
3581
3582 void si_update_ps_iter_samples(struct si_context *sctx)
3583 {
3584 if (sctx->framebuffer.nr_samples > 1)
3585 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3586 if (sctx->screen->dpbb_allowed)
3587 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3588 }
3589
3590 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3591 {
3592 struct si_context *sctx = (struct si_context *)ctx;
3593
3594 /* The hardware can only do sample shading with 2^n samples. */
3595 min_samples = util_next_power_of_two(min_samples);
3596
3597 if (sctx->ps_iter_samples == min_samples)
3598 return;
3599
3600 sctx->ps_iter_samples = min_samples;
3601 sctx->do_update_shaders = true;
3602
3603 si_update_ps_iter_samples(sctx);
3604 }
3605
3606 /*
3607 * Samplers
3608 */
3609
3610 /**
3611 * Build the sampler view descriptor for a buffer texture.
3612 * @param state 256-bit descriptor; only the high 128 bits are filled in
3613 */
3614 void
3615 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3616 enum pipe_format format,
3617 unsigned offset, unsigned size,
3618 uint32_t *state)
3619 {
3620 const struct util_format_description *desc;
3621 int first_non_void;
3622 unsigned stride;
3623 unsigned num_records;
3624 unsigned num_format, data_format;
3625
3626 desc = util_format_description(format);
3627 first_non_void = util_format_get_first_non_void_channel(format);
3628 stride = desc->block.bits / 8;
3629 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3630 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3631
3632 num_records = size / stride;
3633 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3634
3635 /* The NUM_RECORDS field has a different meaning depending on the chip,
3636 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3637 *
3638 * GFX6-GFX7:
3639 * - If STRIDE == 0, it's in byte units.
3640 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3641 *
3642 * GFX8:
3643 * - For SMEM and STRIDE == 0, it's in byte units.
3644 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3645 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3646 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3647 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3648 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3649 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3650 * That way the same descriptor can be used by both SMEM and VMEM.
3651 *
3652 * GFX9:
3653 * - For SMEM and STRIDE == 0, it's in byte units.
3654 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3655 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3656 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3657 */
3658 if (screen->info.chip_class >= GFX9 && HAVE_LLVM < 0x0800)
3659 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3660 * from STRIDE to bytes. This works around it by setting
3661 * NUM_RECORDS to at least the size of one element, so that
3662 * the first element is readable when IDXEN == 0.
3663 */
3664 num_records = num_records ? MAX2(num_records, stride) : 0;
3665 else if (screen->info.chip_class == GFX8)
3666 num_records *= stride;
3667
3668 state[4] = 0;
3669 state[5] = S_008F04_STRIDE(stride);
3670 state[6] = num_records;
3671 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3672 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3673 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3674 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3675 S_008F0C_NUM_FORMAT(num_format) |
3676 S_008F0C_DATA_FORMAT(data_format);
3677 }
3678
3679 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3680 {
3681 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3682
3683 if (swizzle[3] == PIPE_SWIZZLE_X) {
3684 /* For the pre-defined border color values (white, opaque
3685 * black, transparent black), the only thing that matters is
3686 * that the alpha channel winds up in the correct place
3687 * (because the RGB channels are all the same) so either of
3688 * these enumerations will work.
3689 */
3690 if (swizzle[2] == PIPE_SWIZZLE_Y)
3691 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3692 else
3693 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3694 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3695 if (swizzle[1] == PIPE_SWIZZLE_Y)
3696 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3697 else
3698 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3699 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3700 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3701 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3702 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3703 }
3704
3705 return bc_swizzle;
3706 }
3707
3708 /**
3709 * Build the sampler view descriptor for a texture.
3710 */
3711 void
3712 si_make_texture_descriptor(struct si_screen *screen,
3713 struct si_texture *tex,
3714 bool sampler,
3715 enum pipe_texture_target target,
3716 enum pipe_format pipe_format,
3717 const unsigned char state_swizzle[4],
3718 unsigned first_level, unsigned last_level,
3719 unsigned first_layer, unsigned last_layer,
3720 unsigned width, unsigned height, unsigned depth,
3721 uint32_t *state,
3722 uint32_t *fmask_state)
3723 {
3724 struct pipe_resource *res = &tex->buffer.b.b;
3725 const struct util_format_description *desc;
3726 unsigned char swizzle[4];
3727 int first_non_void;
3728 unsigned num_format, data_format, type, num_samples;
3729 uint64_t va;
3730
3731 desc = util_format_description(pipe_format);
3732
3733 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3734 MAX2(1, res->nr_samples) :
3735 MAX2(1, res->nr_storage_samples);
3736
3737 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3738 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3739 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3740 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3741
3742 switch (pipe_format) {
3743 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3744 case PIPE_FORMAT_X32_S8X24_UINT:
3745 case PIPE_FORMAT_X8Z24_UNORM:
3746 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3747 break;
3748 case PIPE_FORMAT_X24S8_UINT:
3749 /*
3750 * X24S8 is implemented as an 8_8_8_8 data format, to
3751 * fix texture gathers. This affects at least
3752 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3753 */
3754 if (screen->info.chip_class <= GFX8)
3755 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3756 else
3757 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3758 break;
3759 default:
3760 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3761 }
3762 } else {
3763 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3764 }
3765
3766 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3767
3768 switch (pipe_format) {
3769 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3770 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3771 break;
3772 default:
3773 if (first_non_void < 0) {
3774 if (util_format_is_compressed(pipe_format)) {
3775 switch (pipe_format) {
3776 case PIPE_FORMAT_DXT1_SRGB:
3777 case PIPE_FORMAT_DXT1_SRGBA:
3778 case PIPE_FORMAT_DXT3_SRGBA:
3779 case PIPE_FORMAT_DXT5_SRGBA:
3780 case PIPE_FORMAT_BPTC_SRGBA:
3781 case PIPE_FORMAT_ETC2_SRGB8:
3782 case PIPE_FORMAT_ETC2_SRGB8A1:
3783 case PIPE_FORMAT_ETC2_SRGBA8:
3784 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3785 break;
3786 case PIPE_FORMAT_RGTC1_SNORM:
3787 case PIPE_FORMAT_LATC1_SNORM:
3788 case PIPE_FORMAT_RGTC2_SNORM:
3789 case PIPE_FORMAT_LATC2_SNORM:
3790 case PIPE_FORMAT_ETC2_R11_SNORM:
3791 case PIPE_FORMAT_ETC2_RG11_SNORM:
3792 /* implies float, so use SNORM/UNORM to determine
3793 whether data is signed or not */
3794 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3795 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3796 break;
3797 default:
3798 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3799 break;
3800 }
3801 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3802 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3803 } else {
3804 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3805 }
3806 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3807 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3808 } else {
3809 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3810
3811 switch (desc->channel[first_non_void].type) {
3812 case UTIL_FORMAT_TYPE_FLOAT:
3813 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3814 break;
3815 case UTIL_FORMAT_TYPE_SIGNED:
3816 if (desc->channel[first_non_void].normalized)
3817 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3818 else if (desc->channel[first_non_void].pure_integer)
3819 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3820 else
3821 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3822 break;
3823 case UTIL_FORMAT_TYPE_UNSIGNED:
3824 if (desc->channel[first_non_void].normalized)
3825 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3826 else if (desc->channel[first_non_void].pure_integer)
3827 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3828 else
3829 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3830 }
3831 }
3832 }
3833
3834 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3835 if (data_format == ~0) {
3836 data_format = 0;
3837 }
3838
3839 /* S8 with Z32 HTILE needs a special format. */
3840 if (screen->info.chip_class >= GFX9 &&
3841 pipe_format == PIPE_FORMAT_S8_UINT &&
3842 tex->tc_compatible_htile)
3843 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3844
3845 if (!sampler &&
3846 (res->target == PIPE_TEXTURE_CUBE ||
3847 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3848 (screen->info.chip_class <= GFX8 &&
3849 res->target == PIPE_TEXTURE_3D))) {
3850 /* For the purpose of shader images, treat cube maps and 3D
3851 * textures as 2D arrays. For 3D textures, the address
3852 * calculations for mipmaps are different, so we rely on the
3853 * caller to effectively disable mipmaps.
3854 */
3855 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3856
3857 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3858 } else {
3859 type = si_tex_dim(screen, tex, target, num_samples);
3860 }
3861
3862 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3863 height = 1;
3864 depth = res->array_size;
3865 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3866 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3867 if (sampler || res->target != PIPE_TEXTURE_3D)
3868 depth = res->array_size;
3869 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3870 depth = res->array_size / 6;
3871
3872 state[0] = 0;
3873 state[1] = (S_008F14_DATA_FORMAT(data_format) |
3874 S_008F14_NUM_FORMAT(num_format));
3875 state[2] = (S_008F18_WIDTH(width - 1) |
3876 S_008F18_HEIGHT(height - 1) |
3877 S_008F18_PERF_MOD(4));
3878 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3879 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3880 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3881 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3882 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3883 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3884 util_logbase2(num_samples) :
3885 last_level) |
3886 S_008F1C_TYPE(type));
3887 state[4] = 0;
3888 state[5] = S_008F24_BASE_ARRAY(first_layer);
3889 state[6] = 0;
3890 state[7] = 0;
3891
3892 if (screen->info.chip_class >= GFX9) {
3893 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3894
3895 /* Depth is the the last accessible layer on Gfx9.
3896 * The hw doesn't need to know the total number of layers.
3897 */
3898 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3899 state[4] |= S_008F20_DEPTH(depth - 1);
3900 else
3901 state[4] |= S_008F20_DEPTH(last_layer);
3902
3903 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3904 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3905 util_logbase2(num_samples) :
3906 tex->buffer.b.b.last_level);
3907 } else {
3908 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3909 state[4] |= S_008F20_DEPTH(depth - 1);
3910 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3911 }
3912
3913 if (tex->dcc_offset) {
3914 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3915 } else {
3916 /* The last dword is unused by hw. The shader uses it to clear
3917 * bits in the first dword of sampler state.
3918 */
3919 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
3920 if (first_level == last_level)
3921 state[7] = C_008F30_MAX_ANISO_RATIO;
3922 else
3923 state[7] = 0xffffffff;
3924 }
3925 }
3926
3927 /* Initialize the sampler view for FMASK. */
3928 if (tex->fmask_offset) {
3929 uint32_t data_format, num_format;
3930
3931 va = tex->buffer.gpu_address + tex->fmask_offset;
3932
3933 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3934 if (screen->info.chip_class >= GFX9) {
3935 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3936 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3937 case FMASK(2,1):
3938 num_format = V_008F14_IMG_FMASK_8_2_1;
3939 break;
3940 case FMASK(2,2):
3941 num_format = V_008F14_IMG_FMASK_8_2_2;
3942 break;
3943 case FMASK(4,1):
3944 num_format = V_008F14_IMG_FMASK_8_4_1;
3945 break;
3946 case FMASK(4,2):
3947 num_format = V_008F14_IMG_FMASK_8_4_2;
3948 break;
3949 case FMASK(4,4):
3950 num_format = V_008F14_IMG_FMASK_8_4_4;
3951 break;
3952 case FMASK(8,1):
3953 num_format = V_008F14_IMG_FMASK_8_8_1;
3954 break;
3955 case FMASK(8,2):
3956 num_format = V_008F14_IMG_FMASK_16_8_2;
3957 break;
3958 case FMASK(8,4):
3959 num_format = V_008F14_IMG_FMASK_32_8_4;
3960 break;
3961 case FMASK(8,8):
3962 num_format = V_008F14_IMG_FMASK_32_8_8;
3963 break;
3964 case FMASK(16,1):
3965 num_format = V_008F14_IMG_FMASK_16_16_1;
3966 break;
3967 case FMASK(16,2):
3968 num_format = V_008F14_IMG_FMASK_32_16_2;
3969 break;
3970 case FMASK(16,4):
3971 num_format = V_008F14_IMG_FMASK_64_16_4;
3972 break;
3973 case FMASK(16,8):
3974 num_format = V_008F14_IMG_FMASK_64_16_8;
3975 break;
3976 default:
3977 unreachable("invalid nr_samples");
3978 }
3979 } else {
3980 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3981 case FMASK(2,1):
3982 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3983 break;
3984 case FMASK(2,2):
3985 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3986 break;
3987 case FMASK(4,1):
3988 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3989 break;
3990 case FMASK(4,2):
3991 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3992 break;
3993 case FMASK(4,4):
3994 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3995 break;
3996 case FMASK(8,1):
3997 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3998 break;
3999 case FMASK(8,2):
4000 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4001 break;
4002 case FMASK(8,4):
4003 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4004 break;
4005 case FMASK(8,8):
4006 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4007 break;
4008 case FMASK(16,1):
4009 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4010 break;
4011 case FMASK(16,2):
4012 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4013 break;
4014 case FMASK(16,4):
4015 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4016 break;
4017 case FMASK(16,8):
4018 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4019 break;
4020 default:
4021 unreachable("invalid nr_samples");
4022 }
4023 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4024 }
4025 #undef FMASK
4026
4027 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4028 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4029 S_008F14_DATA_FORMAT(data_format) |
4030 S_008F14_NUM_FORMAT(num_format);
4031 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4032 S_008F18_HEIGHT(height - 1);
4033 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4034 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4035 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4036 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4037 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4038 fmask_state[4] = 0;
4039 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4040 fmask_state[6] = 0;
4041 fmask_state[7] = 0;
4042
4043 if (screen->info.chip_class >= GFX9) {
4044 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4045 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4046 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4047 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4048 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4049 } else {
4050 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4051 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4052 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4053 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4054 }
4055 }
4056 }
4057
4058 /**
4059 * Create a sampler view.
4060 *
4061 * @param ctx context
4062 * @param texture texture
4063 * @param state sampler view template
4064 * @param width0 width0 override (for compressed textures as int)
4065 * @param height0 height0 override (for compressed textures as int)
4066 * @param force_level set the base address to the level (for compressed textures)
4067 */
4068 struct pipe_sampler_view *
4069 si_create_sampler_view_custom(struct pipe_context *ctx,
4070 struct pipe_resource *texture,
4071 const struct pipe_sampler_view *state,
4072 unsigned width0, unsigned height0,
4073 unsigned force_level)
4074 {
4075 struct si_context *sctx = (struct si_context*)ctx;
4076 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4077 struct si_texture *tex = (struct si_texture*)texture;
4078 unsigned base_level, first_level, last_level;
4079 unsigned char state_swizzle[4];
4080 unsigned height, depth, width;
4081 unsigned last_layer = state->u.tex.last_layer;
4082 enum pipe_format pipe_format;
4083 const struct legacy_surf_level *surflevel;
4084
4085 if (!view)
4086 return NULL;
4087
4088 /* initialize base object */
4089 view->base = *state;
4090 view->base.texture = NULL;
4091 view->base.reference.count = 1;
4092 view->base.context = ctx;
4093
4094 assert(texture);
4095 pipe_resource_reference(&view->base.texture, texture);
4096
4097 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4098 state->format == PIPE_FORMAT_S8X24_UINT ||
4099 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4100 state->format == PIPE_FORMAT_S8_UINT)
4101 view->is_stencil_sampler = true;
4102
4103 /* Buffer resource. */
4104 if (texture->target == PIPE_BUFFER) {
4105 si_make_buffer_descriptor(sctx->screen,
4106 si_resource(texture),
4107 state->format,
4108 state->u.buf.offset,
4109 state->u.buf.size,
4110 view->state);
4111 return &view->base;
4112 }
4113
4114 state_swizzle[0] = state->swizzle_r;
4115 state_swizzle[1] = state->swizzle_g;
4116 state_swizzle[2] = state->swizzle_b;
4117 state_swizzle[3] = state->swizzle_a;
4118
4119 base_level = 0;
4120 first_level = state->u.tex.first_level;
4121 last_level = state->u.tex.last_level;
4122 width = width0;
4123 height = height0;
4124 depth = texture->depth0;
4125
4126 if (sctx->chip_class <= GFX8 && force_level) {
4127 assert(force_level == first_level &&
4128 force_level == last_level);
4129 base_level = force_level;
4130 first_level = 0;
4131 last_level = 0;
4132 width = u_minify(width, force_level);
4133 height = u_minify(height, force_level);
4134 depth = u_minify(depth, force_level);
4135 }
4136
4137 /* This is not needed if state trackers set last_layer correctly. */
4138 if (state->target == PIPE_TEXTURE_1D ||
4139 state->target == PIPE_TEXTURE_2D ||
4140 state->target == PIPE_TEXTURE_RECT ||
4141 state->target == PIPE_TEXTURE_CUBE)
4142 last_layer = state->u.tex.first_layer;
4143
4144 /* Texturing with separate depth and stencil. */
4145 pipe_format = state->format;
4146
4147 /* Depth/stencil texturing sometimes needs separate texture. */
4148 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4149 if (!tex->flushed_depth_texture &&
4150 !si_init_flushed_depth_texture(ctx, texture)) {
4151 pipe_resource_reference(&view->base.texture, NULL);
4152 FREE(view);
4153 return NULL;
4154 }
4155
4156 assert(tex->flushed_depth_texture);
4157
4158 /* Override format for the case where the flushed texture
4159 * contains only Z or only S.
4160 */
4161 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4162 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4163
4164 tex = tex->flushed_depth_texture;
4165 }
4166
4167 surflevel = tex->surface.u.legacy.level;
4168
4169 if (tex->db_compatible) {
4170 if (!view->is_stencil_sampler)
4171 pipe_format = tex->db_render_format;
4172
4173 switch (pipe_format) {
4174 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4175 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4176 break;
4177 case PIPE_FORMAT_X8Z24_UNORM:
4178 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4179 /* Z24 is always stored like this for DB
4180 * compatibility.
4181 */
4182 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4183 break;
4184 case PIPE_FORMAT_X24S8_UINT:
4185 case PIPE_FORMAT_S8X24_UINT:
4186 case PIPE_FORMAT_X32_S8X24_UINT:
4187 pipe_format = PIPE_FORMAT_S8_UINT;
4188 surflevel = tex->surface.u.legacy.stencil_level;
4189 break;
4190 default:;
4191 }
4192 }
4193
4194 view->dcc_incompatible =
4195 vi_dcc_formats_are_incompatible(texture,
4196 state->u.tex.first_level,
4197 state->format);
4198
4199 si_make_texture_descriptor(sctx->screen, tex, true,
4200 state->target, pipe_format, state_swizzle,
4201 first_level, last_level,
4202 state->u.tex.first_layer, last_layer,
4203 width, height, depth,
4204 view->state, view->fmask_state);
4205
4206 unsigned num_format = G_008F14_NUM_FORMAT(view->state[1]);
4207 view->is_integer =
4208 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4209 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4210 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4211 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4212 view->base_level_info = &surflevel[base_level];
4213 view->base_level = base_level;
4214 view->block_width = util_format_get_blockwidth(pipe_format);
4215 return &view->base;
4216 }
4217
4218 static struct pipe_sampler_view *
4219 si_create_sampler_view(struct pipe_context *ctx,
4220 struct pipe_resource *texture,
4221 const struct pipe_sampler_view *state)
4222 {
4223 return si_create_sampler_view_custom(ctx, texture, state,
4224 texture ? texture->width0 : 0,
4225 texture ? texture->height0 : 0, 0);
4226 }
4227
4228 static void si_sampler_view_destroy(struct pipe_context *ctx,
4229 struct pipe_sampler_view *state)
4230 {
4231 struct si_sampler_view *view = (struct si_sampler_view *)state;
4232
4233 pipe_resource_reference(&state->texture, NULL);
4234 FREE(view);
4235 }
4236
4237 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4238 {
4239 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4240 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4241 (linear_filter &&
4242 (wrap == PIPE_TEX_WRAP_CLAMP ||
4243 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4244 }
4245
4246 static uint32_t si_translate_border_color(struct si_context *sctx,
4247 const struct pipe_sampler_state *state,
4248 const union pipe_color_union *color,
4249 bool is_integer)
4250 {
4251 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4252 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4253
4254 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4255 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4256 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4257 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4258
4259 #define simple_border_types(elt) \
4260 do { \
4261 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4262 color->elt[2] == 0 && color->elt[3] == 0) \
4263 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4264 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4265 color->elt[2] == 0 && color->elt[3] == 1) \
4266 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4267 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4268 color->elt[2] == 1 && color->elt[3] == 1) \
4269 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4270 } while (false)
4271
4272 if (is_integer)
4273 simple_border_types(ui);
4274 else
4275 simple_border_types(f);
4276
4277 #undef simple_border_types
4278
4279 int i;
4280
4281 /* Check if the border has been uploaded already. */
4282 for (i = 0; i < sctx->border_color_count; i++)
4283 if (memcmp(&sctx->border_color_table[i], color,
4284 sizeof(*color)) == 0)
4285 break;
4286
4287 if (i >= SI_MAX_BORDER_COLORS) {
4288 /* Getting 4096 unique border colors is very unlikely. */
4289 fprintf(stderr, "radeonsi: The border color table is full. "
4290 "Any new border colors will be just black. "
4291 "Please file a bug.\n");
4292 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4293 }
4294
4295 if (i == sctx->border_color_count) {
4296 /* Upload a new border color. */
4297 memcpy(&sctx->border_color_table[i], color,
4298 sizeof(*color));
4299 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4300 color, sizeof(*color));
4301 sctx->border_color_count++;
4302 }
4303
4304 return S_008F3C_BORDER_COLOR_PTR(i) |
4305 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4306 }
4307
4308 static inline int S_FIXED(float value, unsigned frac_bits)
4309 {
4310 return value * (1 << frac_bits);
4311 }
4312
4313 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4314 {
4315 if (filter == PIPE_TEX_FILTER_LINEAR)
4316 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4317 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4318 else
4319 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4320 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4321 }
4322
4323 static inline unsigned si_tex_aniso_filter(unsigned filter)
4324 {
4325 if (filter < 2)
4326 return 0;
4327 if (filter < 4)
4328 return 1;
4329 if (filter < 8)
4330 return 2;
4331 if (filter < 16)
4332 return 3;
4333 return 4;
4334 }
4335
4336 static void *si_create_sampler_state(struct pipe_context *ctx,
4337 const struct pipe_sampler_state *state)
4338 {
4339 struct si_context *sctx = (struct si_context *)ctx;
4340 struct si_screen *sscreen = sctx->screen;
4341 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4342 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4343 : state->max_anisotropy;
4344 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4345 union pipe_color_union clamped_border_color;
4346
4347 if (!rstate) {
4348 return NULL;
4349 }
4350
4351 #ifndef NDEBUG
4352 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4353 #endif
4354 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4355 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4356 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4357 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4358 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4359 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4360 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4361 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4362 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4363 S_008F30_COMPAT_MODE(sctx->chip_class >= GFX8));
4364 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4365 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4366 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4367 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4368 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4369 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4370 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4371 S_008F38_MIP_POINT_PRECLAMP(0) |
4372 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4373 S_008F38_FILTER_PREC_FIX(1) |
4374 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8));
4375 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4376
4377 /* Create sampler resource for integer textures. */
4378 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4379 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4380
4381 /* Create sampler resource for upgraded depth textures. */
4382 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4383
4384 for (unsigned i = 0; i < 4; ++i) {
4385 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4386 * when the border color is 1.0. */
4387 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4388 }
4389
4390 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4391 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4392 else
4393 rstate->upgraded_depth_val[3] =
4394 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4395 S_008F3C_UPGRADED_DEPTH(1);
4396
4397 return rstate;
4398 }
4399
4400 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4401 {
4402 struct si_context *sctx = (struct si_context *)ctx;
4403
4404 if (sctx->sample_mask == (uint16_t)sample_mask)
4405 return;
4406
4407 sctx->sample_mask = sample_mask;
4408 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4409 }
4410
4411 static void si_emit_sample_mask(struct si_context *sctx)
4412 {
4413 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4414 unsigned mask = sctx->sample_mask;
4415
4416 /* Needed for line and polygon smoothing as well as for the Polaris
4417 * small primitive filter. We expect the state tracker to take care of
4418 * this for us.
4419 */
4420 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4421 (mask & 1 && sctx->blitter->running));
4422
4423 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4424 radeon_emit(cs, mask | (mask << 16));
4425 radeon_emit(cs, mask | (mask << 16));
4426 }
4427
4428 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4429 {
4430 #ifndef NDEBUG
4431 struct si_sampler_state *s = state;
4432
4433 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4434 s->magic = 0;
4435 #endif
4436 free(state);
4437 }
4438
4439 /*
4440 * Vertex elements & buffers
4441 */
4442
4443 struct si_fast_udiv_info32
4444 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4445 {
4446 struct util_fast_udiv_info info =
4447 util_compute_fast_udiv_info(D, num_bits, 32);
4448
4449 struct si_fast_udiv_info32 result = {
4450 info.multiplier,
4451 info.pre_shift,
4452 info.post_shift,
4453 info.increment,
4454 };
4455 return result;
4456 }
4457
4458 static void *si_create_vertex_elements(struct pipe_context *ctx,
4459 unsigned count,
4460 const struct pipe_vertex_element *elements)
4461 {
4462 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4463 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4464 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4465 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4466 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4467 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4468 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4469 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4470 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4471 int i;
4472
4473 assert(count <= SI_MAX_ATTRIBS);
4474 if (!v)
4475 return NULL;
4476
4477 v->count = count;
4478 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4479
4480 for (i = 0; i < count; ++i) {
4481 const struct util_format_description *desc;
4482 const struct util_format_channel_description *channel;
4483 int first_non_void;
4484 unsigned vbo_index = elements[i].vertex_buffer_index;
4485
4486 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4487 FREE(v);
4488 return NULL;
4489 }
4490
4491 unsigned instance_divisor = elements[i].instance_divisor;
4492 if (instance_divisor) {
4493 v->uses_instance_divisors = true;
4494
4495 if (instance_divisor == 1) {
4496 v->instance_divisor_is_one |= 1u << i;
4497 } else {
4498 v->instance_divisor_is_fetched |= 1u << i;
4499 divisor_factors[i] =
4500 si_compute_fast_udiv_info32(instance_divisor, 32);
4501 }
4502 }
4503
4504 if (!used[vbo_index]) {
4505 v->first_vb_use_mask |= 1 << i;
4506 used[vbo_index] = true;
4507 }
4508
4509 desc = util_format_description(elements[i].src_format);
4510 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4511 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4512
4513 v->format_size[i] = desc->block.bits / 8;
4514 v->src_offset[i] = elements[i].src_offset;
4515 v->vertex_buffer_index[i] = vbo_index;
4516
4517 bool always_fix = false;
4518 union si_vs_fix_fetch fix_fetch;
4519 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4520
4521 fix_fetch.bits = 0;
4522 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4523
4524 if (channel) {
4525 switch (channel->type) {
4526 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4527 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4528 case UTIL_FORMAT_TYPE_SIGNED: {
4529 if (channel->pure_integer)
4530 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4531 else if (channel->normalized)
4532 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4533 else
4534 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4535 break;
4536 }
4537 case UTIL_FORMAT_TYPE_UNSIGNED: {
4538 if (channel->pure_integer)
4539 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4540 else if (channel->normalized)
4541 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4542 else
4543 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4544 break;
4545 }
4546 default: unreachable("bad format type");
4547 }
4548 } else {
4549 switch (elements[i].src_format) {
4550 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4551 default: unreachable("bad other format");
4552 }
4553 }
4554
4555 if (desc->channel[0].size == 10) {
4556 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4557 log_hw_load_size = 2;
4558
4559 /* The hardware always treats the 2-bit alpha channel as
4560 * unsigned, so a shader workaround is needed. The affected
4561 * chips are GFX8 and older except Stoney (GFX8.1).
4562 */
4563 always_fix = sscreen->info.chip_class <= GFX8 &&
4564 sscreen->info.family != CHIP_STONEY &&
4565 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4566 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4567 fix_fetch.u.log_size = 3; /* special encoding */
4568 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4569 log_hw_load_size = 2;
4570 } else {
4571 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4572 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4573
4574 /* Always fix up:
4575 * - doubles (multiple loads + truncate to float)
4576 * - 32-bit requiring a conversion
4577 */
4578 always_fix =
4579 (fix_fetch.u.log_size == 3) ||
4580 (fix_fetch.u.log_size == 2 &&
4581 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4582 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4583 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4584
4585 /* Also fixup 8_8_8 and 16_16_16. */
4586 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4587 always_fix = true;
4588 log_hw_load_size = fix_fetch.u.log_size;
4589 }
4590 }
4591
4592 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4593 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4594 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4595 fix_fetch.u.reverse = 1;
4596 }
4597
4598 /* Force the workaround for unaligned access here already if the
4599 * offset relative to the vertex buffer base is unaligned.
4600 *
4601 * There is a theoretical case in which this is too conservative:
4602 * if the vertex buffer's offset is also unaligned in just the
4603 * right way, we end up with an aligned address after all.
4604 * However, this case should be extremely rare in practice (it
4605 * won't happen in well-behaved applications), and taking it
4606 * into account would complicate the fast path (where everything
4607 * is nicely aligned).
4608 */
4609 bool check_alignment = log_hw_load_size >= 1 && sscreen->info.chip_class == GFX6;
4610 bool opencode = sscreen->options.vs_fetch_always_opencode;
4611
4612 if (check_alignment &&
4613 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4614 opencode = true;
4615
4616 if (always_fix || check_alignment || opencode)
4617 v->fix_fetch[i] = fix_fetch.bits;
4618
4619 if (opencode)
4620 v->fix_fetch_opencode |= 1 << i;
4621 if (opencode || always_fix)
4622 v->fix_fetch_always |= 1 << i;
4623
4624 if (check_alignment && !opencode) {
4625 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
4626
4627 v->fix_fetch_unaligned |= 1 << i;
4628 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
4629 v->vb_alignment_check_mask |= 1 << vbo_index;
4630 }
4631
4632 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
4633 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
4634 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
4635 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
4636
4637 unsigned data_format, num_format;
4638 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4639 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4640 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
4641 S_008F0C_DATA_FORMAT(data_format);
4642 }
4643
4644 if (v->instance_divisor_is_fetched) {
4645 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4646
4647 v->instance_divisor_factor_buffer =
4648 (struct si_resource*)
4649 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4650 num_divisors * sizeof(divisor_factors[0]));
4651 if (!v->instance_divisor_factor_buffer) {
4652 FREE(v);
4653 return NULL;
4654 }
4655 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4656 NULL, PIPE_TRANSFER_WRITE);
4657 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4658 }
4659 return v;
4660 }
4661
4662 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4663 {
4664 struct si_context *sctx = (struct si_context *)ctx;
4665 struct si_vertex_elements *old = sctx->vertex_elements;
4666 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4667
4668 sctx->vertex_elements = v;
4669 sctx->vertex_buffers_dirty = true;
4670
4671 if (v &&
4672 (!old ||
4673 old->count != v->count ||
4674 old->uses_instance_divisors != v->uses_instance_divisors ||
4675 /* we don't check which divisors changed */
4676 v->uses_instance_divisors ||
4677 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
4678 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
4679 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
4680 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
4681 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4682 * functions of fix_fetch and the src_offset alignment.
4683 * If they change and fix_fetch doesn't, it must be due to different
4684 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4685 old->fix_fetch_opencode != v->fix_fetch_opencode ||
4686 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4687 sctx->do_update_shaders = true;
4688
4689 if (v && v->instance_divisor_is_fetched) {
4690 struct pipe_constant_buffer cb;
4691
4692 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4693 cb.user_buffer = NULL;
4694 cb.buffer_offset = 0;
4695 cb.buffer_size = 0xffffffff;
4696 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4697 }
4698 }
4699
4700 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4701 {
4702 struct si_context *sctx = (struct si_context *)ctx;
4703 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4704
4705 if (sctx->vertex_elements == state)
4706 sctx->vertex_elements = NULL;
4707 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4708 FREE(state);
4709 }
4710
4711 static void si_set_vertex_buffers(struct pipe_context *ctx,
4712 unsigned start_slot, unsigned count,
4713 const struct pipe_vertex_buffer *buffers)
4714 {
4715 struct si_context *sctx = (struct si_context *)ctx;
4716 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4717 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
4718 uint32_t unaligned = orig_unaligned;
4719 int i;
4720
4721 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4722
4723 if (buffers) {
4724 for (i = 0; i < count; i++) {
4725 const struct pipe_vertex_buffer *src = buffers + i;
4726 struct pipe_vertex_buffer *dsti = dst + i;
4727 struct pipe_resource *buf = src->buffer.resource;
4728
4729 pipe_resource_reference(&dsti->buffer.resource, buf);
4730 dsti->buffer_offset = src->buffer_offset;
4731 dsti->stride = src->stride;
4732 if (dsti->buffer_offset & 3 || dsti->stride & 3)
4733 unaligned |= 1 << (start_slot + i);
4734 else
4735 unaligned &= ~(1 << (start_slot + i));
4736
4737 si_context_add_resource_size(sctx, buf);
4738 if (buf)
4739 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4740 }
4741 } else {
4742 for (i = 0; i < count; i++) {
4743 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4744 }
4745 unaligned &= ~u_bit_consecutive(start_slot, count);
4746 }
4747 sctx->vertex_buffers_dirty = true;
4748 sctx->vertex_buffer_unaligned = unaligned;
4749
4750 /* Check whether alignment may have changed in a way that requires
4751 * shader changes. This check is conservative: a vertex buffer can only
4752 * trigger a shader change if the misalignment amount changes (e.g.
4753 * from byte-aligned to short-aligned), but we only keep track of
4754 * whether buffers are at least dword-aligned, since that should always
4755 * be the case in well-behaved applications anyway.
4756 */
4757 if (sctx->vertex_elements &&
4758 (sctx->vertex_elements->vb_alignment_check_mask &
4759 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
4760 sctx->do_update_shaders = true;
4761 }
4762
4763 /*
4764 * Misc
4765 */
4766
4767 static void si_set_tess_state(struct pipe_context *ctx,
4768 const float default_outer_level[4],
4769 const float default_inner_level[2])
4770 {
4771 struct si_context *sctx = (struct si_context *)ctx;
4772 struct pipe_constant_buffer cb;
4773 float array[8];
4774
4775 memcpy(array, default_outer_level, sizeof(float) * 4);
4776 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4777
4778 cb.buffer = NULL;
4779 cb.user_buffer = NULL;
4780 cb.buffer_size = sizeof(array);
4781
4782 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
4783 (void*)array, sizeof(array),
4784 &cb.buffer_offset);
4785
4786 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4787 pipe_resource_reference(&cb.buffer, NULL);
4788 }
4789
4790 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4791 {
4792 struct si_context *sctx = (struct si_context *)ctx;
4793
4794 si_update_fb_dirtiness_after_rendering(sctx);
4795
4796 /* Multisample surfaces are flushed in si_decompress_textures. */
4797 if (sctx->framebuffer.uncompressed_cb_mask) {
4798 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4799 sctx->framebuffer.CB_has_shader_readable_metadata,
4800 sctx->framebuffer.all_DCC_pipe_aligned);
4801 }
4802 }
4803
4804 /* This only ensures coherency for shader image/buffer stores. */
4805 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4806 {
4807 struct si_context *sctx = (struct si_context *)ctx;
4808
4809 if (!(flags & ~PIPE_BARRIER_UPDATE))
4810 return;
4811
4812 /* Subsequent commands must wait for all shader invocations to
4813 * complete. */
4814 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4815 SI_CONTEXT_CS_PARTIAL_FLUSH;
4816
4817 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4818 sctx->flags |= SI_CONTEXT_INV_SCACHE |
4819 SI_CONTEXT_INV_VCACHE;
4820
4821 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4822 PIPE_BARRIER_SHADER_BUFFER |
4823 PIPE_BARRIER_TEXTURE |
4824 PIPE_BARRIER_IMAGE |
4825 PIPE_BARRIER_STREAMOUT_BUFFER |
4826 PIPE_BARRIER_GLOBAL_BUFFER)) {
4827 /* As far as I can tell, L1 contents are written back to L2
4828 * automatically at end of shader, but the contents of other
4829 * L1 caches might still be stale. */
4830 sctx->flags |= SI_CONTEXT_INV_VCACHE;
4831 }
4832
4833 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4834 /* Indices are read through TC L2 since GFX8.
4835 * L1 isn't used.
4836 */
4837 if (sctx->screen->info.chip_class <= GFX7)
4838 sctx->flags |= SI_CONTEXT_WB_L2;
4839 }
4840
4841 /* MSAA color, any depth and any stencil are flushed in
4842 * si_decompress_textures when needed.
4843 */
4844 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4845 sctx->framebuffer.uncompressed_cb_mask) {
4846 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4847
4848 if (sctx->chip_class <= GFX8)
4849 sctx->flags |= SI_CONTEXT_WB_L2;
4850 }
4851
4852 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4853 if (sctx->screen->info.chip_class <= GFX8 &&
4854 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4855 sctx->flags |= SI_CONTEXT_WB_L2;
4856 }
4857
4858 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4859 {
4860 struct pipe_blend_state blend;
4861
4862 memset(&blend, 0, sizeof(blend));
4863 blend.independent_blend_enable = true;
4864 blend.rt[0].colormask = 0xf;
4865 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4866 }
4867
4868 static void si_init_config(struct si_context *sctx);
4869
4870 void si_init_state_compute_functions(struct si_context *sctx)
4871 {
4872 sctx->b.create_sampler_state = si_create_sampler_state;
4873 sctx->b.delete_sampler_state = si_delete_sampler_state;
4874 sctx->b.create_sampler_view = si_create_sampler_view;
4875 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4876 sctx->b.memory_barrier = si_memory_barrier;
4877 }
4878
4879 void si_init_state_functions(struct si_context *sctx)
4880 {
4881 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4882 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4883 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4884 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4885 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4886 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4887 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4888 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4889 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4890 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4891 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4892
4893 sctx->b.create_blend_state = si_create_blend_state;
4894 sctx->b.bind_blend_state = si_bind_blend_state;
4895 sctx->b.delete_blend_state = si_delete_blend_state;
4896 sctx->b.set_blend_color = si_set_blend_color;
4897
4898 sctx->b.create_rasterizer_state = si_create_rs_state;
4899 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4900 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4901
4902 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4903 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4904 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4905
4906 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4907 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4908 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4909 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4910 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4911
4912 sctx->b.set_clip_state = si_set_clip_state;
4913 sctx->b.set_stencil_ref = si_set_stencil_ref;
4914
4915 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4916
4917 sctx->b.set_sample_mask = si_set_sample_mask;
4918
4919 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4920 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4921 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4922 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4923
4924 sctx->b.texture_barrier = si_texture_barrier;
4925 sctx->b.set_min_samples = si_set_min_samples;
4926 sctx->b.set_tess_state = si_set_tess_state;
4927
4928 sctx->b.set_active_query_state = si_set_active_query_state;
4929
4930 si_init_config(sctx);
4931 }
4932
4933 void si_init_screen_state_functions(struct si_screen *sscreen)
4934 {
4935 sscreen->b.is_format_supported = si_is_format_supported;
4936 }
4937
4938 static void si_set_grbm_gfx_index(struct si_context *sctx,
4939 struct si_pm4_state *pm4, unsigned value)
4940 {
4941 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
4942 R_00802C_GRBM_GFX_INDEX;
4943 si_pm4_set_reg(pm4, reg, value);
4944 }
4945
4946 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4947 struct si_pm4_state *pm4, unsigned se)
4948 {
4949 assert(se == ~0 || se < sctx->screen->info.max_se);
4950 si_set_grbm_gfx_index(sctx, pm4,
4951 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4952 S_030800_SE_INDEX(se)) |
4953 S_030800_SH_BROADCAST_WRITES(1) |
4954 S_030800_INSTANCE_BROADCAST_WRITES(1));
4955 }
4956
4957 static void
4958 si_write_harvested_raster_configs(struct si_context *sctx,
4959 struct si_pm4_state *pm4,
4960 unsigned raster_config,
4961 unsigned raster_config_1)
4962 {
4963 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4964 unsigned raster_config_se[4];
4965 unsigned se;
4966
4967 ac_get_harvested_configs(&sctx->screen->info,
4968 raster_config,
4969 &raster_config_1,
4970 raster_config_se);
4971
4972 for (se = 0; se < num_se; se++) {
4973 si_set_grbm_gfx_index_se(sctx, pm4, se);
4974 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4975 }
4976 si_set_grbm_gfx_index(sctx, pm4, ~0);
4977
4978 if (sctx->chip_class >= GFX7) {
4979 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4980 }
4981 }
4982
4983 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4984 {
4985 struct si_screen *sscreen = sctx->screen;
4986 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4987 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4988 unsigned raster_config = sscreen->pa_sc_raster_config;
4989 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4990
4991 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4992 /* Always use the default config when all backends are enabled
4993 * (or when we failed to determine the enabled backends).
4994 */
4995 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4996 raster_config);
4997 if (sctx->chip_class >= GFX7)
4998 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4999 raster_config_1);
5000 } else {
5001 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5002 }
5003 }
5004
5005 static void si_init_config(struct si_context *sctx)
5006 {
5007 struct si_screen *sscreen = sctx->screen;
5008 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5009 bool has_clear_state = sscreen->has_clear_state;
5010 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5011
5012 /* GFX6, radeon kernel disabled CLEAR_STATE. */
5013 assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
5014 !sscreen->info.is_amdgpu);
5015
5016 if (!pm4)
5017 return;
5018
5019 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5020 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5021 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5022 si_pm4_cmd_end(pm4, false);
5023
5024 if (has_clear_state) {
5025 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5026 si_pm4_cmd_add(pm4, 0);
5027 si_pm4_cmd_end(pm4, false);
5028 }
5029
5030 if (sctx->chip_class <= GFX8)
5031 si_set_raster_config(sctx, pm4);
5032
5033 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5034 if (!has_clear_state)
5035 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5036
5037 /* FIXME calculate these values somehow ??? */
5038 if (sctx->chip_class <= GFX8) {
5039 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5040 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5041 }
5042
5043 if (!has_clear_state) {
5044 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5045 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5046 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5047 }
5048
5049 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5050 if (!has_clear_state)
5051 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5052 if (sctx->chip_class < GFX7)
5053 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5054 S_008A14_CLIP_VTX_REORDER_ENA(1));
5055
5056 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5057 * I don't know why. Deduced by trial and error.
5058 */
5059 if (sctx->chip_class <= GFX7) {
5060 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5061 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5062 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5063 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5064 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5065 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5066 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5067 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5068 }
5069
5070 if (!has_clear_state) {
5071 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5072 S_028230_ER_TRI(0xA) |
5073 S_028230_ER_POINT(0xA) |
5074 S_028230_ER_RECT(0xA) |
5075 /* Required by DX10_DIAMOND_TEST_ENA: */
5076 S_028230_ER_LINE_LR(0x1A) |
5077 S_028230_ER_LINE_RL(0x26) |
5078 S_028230_ER_LINE_TB(0xA) |
5079 S_028230_ER_LINE_BT(0xA));
5080 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5081 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5082 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5083 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5084 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5085 }
5086
5087 if (sctx->chip_class >= GFX9) {
5088 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5089 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5090 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5091 } else {
5092 /* These registers, when written, also overwrite the CLEAR_STATE
5093 * context, so we can't rely on CLEAR_STATE setting them.
5094 * It would be an issue if there was another UMD changing them.
5095 */
5096 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5097 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5098 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5099 }
5100
5101 if (sctx->chip_class >= GFX7) {
5102 if (sctx->chip_class >= GFX9) {
5103 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5104 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5105 } else {
5106 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5107 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5108 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5109 S_00B41C_WAVE_LIMIT(0x3F));
5110 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5111 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5112
5113 /* If this is 0, Bonaire can hang even if GS isn't being used.
5114 * Other chips are unaffected. These are suboptimal values,
5115 * but we don't use on-chip GS.
5116 */
5117 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5118 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5119 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5120 }
5121 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5122 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5123
5124 /* Compute LATE_ALLOC_VS.LIMIT. */
5125 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5126 unsigned late_alloc_limit; /* The limit is per SH. */
5127
5128 if (sctx->family == CHIP_KABINI) {
5129 late_alloc_limit = 0; /* Potential hang on Kabini. */
5130 } else if (num_cu_per_sh <= 4) {
5131 /* Too few available compute units per SH. Disallowing
5132 * VS to run on one CU could hurt us more than late VS
5133 * allocation would help.
5134 *
5135 * 2 is the highest safe number that allows us to keep
5136 * all CUs enabled.
5137 */
5138 late_alloc_limit = 2;
5139 } else {
5140 /* This is a good initial value, allowing 1 late_alloc
5141 * wave per SIMD on num_cu - 2.
5142 */
5143 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5144
5145 /* The limit is 0-based, so 0 means 1. */
5146 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5147 late_alloc_limit -= 1;
5148 }
5149
5150 /* VS can't execute on one CU if the limit is > 2. */
5151 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5152 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5153 S_00B118_WAVE_LIMIT(0x3F));
5154 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5155 S_00B11C_LIMIT(late_alloc_limit));
5156 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5157 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5158 }
5159
5160 if (sctx->chip_class >= GFX8) {
5161 unsigned vgt_tess_distribution;
5162
5163 vgt_tess_distribution =
5164 S_028B50_ACCUM_ISOLINE(32) |
5165 S_028B50_ACCUM_TRI(11) |
5166 S_028B50_ACCUM_QUAD(11) |
5167 S_028B50_DONUT_SPLIT(16);
5168
5169 /* Testing with Unigine Heaven extreme tesselation yielded best results
5170 * with TRAP_SPLIT = 3.
5171 */
5172 if (sctx->family == CHIP_FIJI ||
5173 sctx->family >= CHIP_POLARIS10)
5174 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5175
5176 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5177 } else if (!has_clear_state) {
5178 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5179 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5180 }
5181
5182 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5183 if (sctx->chip_class >= GFX7) {
5184 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5185 S_028084_ADDRESS(border_color_va >> 40));
5186 }
5187 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5188 RADEON_PRIO_BORDER_COLORS);
5189
5190 if (sctx->chip_class >= GFX9) {
5191 unsigned num_se = sscreen->info.max_se;
5192 unsigned pc_lines = 0;
5193
5194 switch (sctx->family) {
5195 case CHIP_VEGA10:
5196 case CHIP_VEGA12:
5197 case CHIP_VEGA20:
5198 pc_lines = 4096;
5199 break;
5200 case CHIP_RAVEN:
5201 case CHIP_RAVEN2:
5202 pc_lines = 1024;
5203 break;
5204 default:
5205 assert(0);
5206 }
5207
5208 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5209 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5210 S_028C48_MAX_PRIM_PER_BATCH(1023));
5211 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5212 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5213 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5214 }
5215
5216 si_pm4_upload_indirect_buffer(sctx, pm4);
5217 sctx->init_config = pm4;
5218 }