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gallium: new, unified pipe_context::set_sampler_views() function
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "radeonsi_pipe.h"
37 #include "radeonsi_shader.h"
38 #include "si_state.h"
39 #include "../radeon/r600_cs.h"
40 #include "sid.h"
41
42 static uint32_t cik_num_banks(uint32_t nbanks)
43 {
44 switch (nbanks) {
45 case 2:
46 return V_02803C_ADDR_SURF_2_BANK;
47 case 4:
48 return V_02803C_ADDR_SURF_4_BANK;
49 case 8:
50 default:
51 return V_02803C_ADDR_SURF_8_BANK;
52 case 16:
53 return V_02803C_ADDR_SURF_16_BANK;
54 }
55 }
56
57
58 static unsigned cik_tile_split(unsigned tile_split)
59 {
60 switch (tile_split) {
61 case 64:
62 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
63 break;
64 case 128:
65 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
66 break;
67 case 256:
68 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
69 break;
70 case 512:
71 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
72 break;
73 default:
74 case 1024:
75 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
76 break;
77 case 2048:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
79 break;
80 case 4096:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
82 break;
83 }
84 return tile_split;
85 }
86
87 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
88 {
89 switch (macro_tile_aspect) {
90 default:
91 case 1:
92 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
93 break;
94 case 2:
95 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
96 break;
97 case 4:
98 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
99 break;
100 case 8:
101 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
102 break;
103 }
104 return macro_tile_aspect;
105 }
106
107 static unsigned cik_bank_wh(unsigned bankwh)
108 {
109 switch (bankwh) {
110 default:
111 case 1:
112 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
113 break;
114 case 2:
115 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
116 break;
117 case 4:
118 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
119 break;
120 case 8:
121 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
122 break;
123 }
124 return bankwh;
125 }
126
127 static unsigned cik_db_pipe_config(unsigned tile_pipes,
128 unsigned num_rbs)
129 {
130 unsigned pipe_config;
131
132 switch (tile_pipes) {
133 case 8:
134 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
135 break;
136 case 4:
137 default:
138 if (num_rbs == 4)
139 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
140 else
141 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
142 break;
143 case 2:
144 pipe_config = V_02803C_ADDR_SURF_P2;
145 break;
146 }
147 return pipe_config;
148 }
149
150 /*
151 * inferred framebuffer and blender state
152 */
153 static void si_update_fb_blend_state(struct r600_context *rctx)
154 {
155 struct si_pm4_state *pm4;
156 struct si_state_blend *blend = rctx->queued.named.blend;
157 uint32_t mask;
158
159 if (blend == NULL)
160 return;
161
162 pm4 = si_pm4_alloc_state(rctx);
163 if (pm4 == NULL)
164 return;
165
166 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
167 mask &= blend->cb_target_mask;
168 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
169
170 si_pm4_set_state(rctx, fb_blend, pm4);
171 }
172
173 /*
174 * Blender functions
175 */
176
177 static uint32_t si_translate_blend_function(int blend_func)
178 {
179 switch (blend_func) {
180 case PIPE_BLEND_ADD:
181 return V_028780_COMB_DST_PLUS_SRC;
182 case PIPE_BLEND_SUBTRACT:
183 return V_028780_COMB_SRC_MINUS_DST;
184 case PIPE_BLEND_REVERSE_SUBTRACT:
185 return V_028780_COMB_DST_MINUS_SRC;
186 case PIPE_BLEND_MIN:
187 return V_028780_COMB_MIN_DST_SRC;
188 case PIPE_BLEND_MAX:
189 return V_028780_COMB_MAX_DST_SRC;
190 default:
191 R600_ERR("Unknown blend function %d\n", blend_func);
192 assert(0);
193 break;
194 }
195 return 0;
196 }
197
198 static uint32_t si_translate_blend_factor(int blend_fact)
199 {
200 switch (blend_fact) {
201 case PIPE_BLENDFACTOR_ONE:
202 return V_028780_BLEND_ONE;
203 case PIPE_BLENDFACTOR_SRC_COLOR:
204 return V_028780_BLEND_SRC_COLOR;
205 case PIPE_BLENDFACTOR_SRC_ALPHA:
206 return V_028780_BLEND_SRC_ALPHA;
207 case PIPE_BLENDFACTOR_DST_ALPHA:
208 return V_028780_BLEND_DST_ALPHA;
209 case PIPE_BLENDFACTOR_DST_COLOR:
210 return V_028780_BLEND_DST_COLOR;
211 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
212 return V_028780_BLEND_SRC_ALPHA_SATURATE;
213 case PIPE_BLENDFACTOR_CONST_COLOR:
214 return V_028780_BLEND_CONSTANT_COLOR;
215 case PIPE_BLENDFACTOR_CONST_ALPHA:
216 return V_028780_BLEND_CONSTANT_ALPHA;
217 case PIPE_BLENDFACTOR_ZERO:
218 return V_028780_BLEND_ZERO;
219 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
220 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
221 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
222 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
223 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
224 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
225 case PIPE_BLENDFACTOR_INV_DST_COLOR:
226 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
227 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
228 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
229 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
230 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
231 case PIPE_BLENDFACTOR_SRC1_COLOR:
232 return V_028780_BLEND_SRC1_COLOR;
233 case PIPE_BLENDFACTOR_SRC1_ALPHA:
234 return V_028780_BLEND_SRC1_ALPHA;
235 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
236 return V_028780_BLEND_INV_SRC1_COLOR;
237 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
238 return V_028780_BLEND_INV_SRC1_ALPHA;
239 default:
240 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
241 assert(0);
242 break;
243 }
244 return 0;
245 }
246
247 static void *si_create_blend_state_mode(struct pipe_context *ctx,
248 const struct pipe_blend_state *state,
249 unsigned mode)
250 {
251 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
252 struct si_pm4_state *pm4 = &blend->pm4;
253
254 uint32_t color_control;
255
256 if (blend == NULL)
257 return NULL;
258
259 blend->alpha_to_one = state->alpha_to_one;
260
261 color_control = S_028808_MODE(mode);
262 if (state->logicop_enable) {
263 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
264 } else {
265 color_control |= S_028808_ROP3(0xcc);
266 }
267 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
268
269 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
270 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
271 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
272 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
275
276 blend->cb_target_mask = 0;
277 for (int i = 0; i < 8; i++) {
278 /* state->rt entries > 0 only written if independent blending */
279 const int j = state->independent_blend_enable ? i : 0;
280
281 unsigned eqRGB = state->rt[j].rgb_func;
282 unsigned srcRGB = state->rt[j].rgb_src_factor;
283 unsigned dstRGB = state->rt[j].rgb_dst_factor;
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287
288 unsigned blend_cntl = 0;
289
290 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
291 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
292
293 if (!state->rt[j].blend_enable) {
294 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
295 continue;
296 }
297
298 blend_cntl |= S_028780_ENABLE(1);
299 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
300 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
301 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
302
303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
304 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
305 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
306 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
307 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
308 }
309 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
310 }
311
312 return blend;
313 }
314
315 static void *si_create_blend_state(struct pipe_context *ctx,
316 const struct pipe_blend_state *state)
317 {
318 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
319 }
320
321 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_context *rctx = (struct r600_context *)ctx;
324 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
325 si_update_fb_blend_state(rctx);
326 }
327
328 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
329 {
330 struct r600_context *rctx = (struct r600_context *)ctx;
331 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
332 }
333
334 static void si_set_blend_color(struct pipe_context *ctx,
335 const struct pipe_blend_color *state)
336 {
337 struct r600_context *rctx = (struct r600_context *)ctx;
338 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
339
340 if (pm4 == NULL)
341 return;
342
343 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
344 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
345 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
346 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
347
348 si_pm4_set_state(rctx, blend_color, pm4);
349 }
350
351 /*
352 * Clipping, scissors and viewport
353 */
354
355 static void si_set_clip_state(struct pipe_context *ctx,
356 const struct pipe_clip_state *state)
357 {
358 struct r600_context *rctx = (struct r600_context *)ctx;
359 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
360 struct pipe_constant_buffer cb;
361
362 if (pm4 == NULL)
363 return;
364
365 for (int i = 0; i < 6; i++) {
366 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
367 fui(state->ucp[i][0]));
368 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
369 fui(state->ucp[i][1]));
370 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
371 fui(state->ucp[i][2]));
372 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
373 fui(state->ucp[i][3]));
374 }
375
376 cb.buffer = NULL;
377 cb.user_buffer = state->ucp;
378 cb.buffer_offset = 0;
379 cb.buffer_size = 4*4*8;
380 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
381 pipe_resource_reference(&cb.buffer, NULL);
382
383 si_pm4_set_state(rctx, clip, pm4);
384 }
385
386 static void si_set_scissor_states(struct pipe_context *ctx,
387 unsigned start_slot,
388 unsigned num_scissors,
389 const struct pipe_scissor_state *state)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
393 uint32_t tl, br;
394
395 if (pm4 == NULL)
396 return;
397
398 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
399 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
400 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
401 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
402 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
403 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
404 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
405 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
406 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
407 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
408
409 si_pm4_set_state(rctx, scissor, pm4);
410 }
411
412 static void si_set_viewport_states(struct pipe_context *ctx,
413 unsigned start_slot,
414 unsigned num_viewports,
415 const struct pipe_viewport_state *state)
416 {
417 struct r600_context *rctx = (struct r600_context *)ctx;
418 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
419 struct si_pm4_state *pm4 = &viewport->pm4;
420
421 if (viewport == NULL)
422 return;
423
424 viewport->viewport = *state;
425 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
426 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
427 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
428 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
429 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
430 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
431 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
432 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
433 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
434
435 si_pm4_set_state(rctx, viewport, viewport);
436 }
437
438 /*
439 * inferred state between framebuffer and rasterizer
440 */
441 static void si_update_fb_rs_state(struct r600_context *rctx)
442 {
443 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
444 struct si_pm4_state *pm4;
445 unsigned offset_db_fmt_cntl = 0, depth;
446 float offset_units;
447
448 if (!rs || !rctx->framebuffer.zsbuf)
449 return;
450
451 offset_units = rctx->queued.named.rasterizer->offset_units;
452 switch (rctx->framebuffer.zsbuf->texture->format) {
453 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
454 case PIPE_FORMAT_X8Z24_UNORM:
455 case PIPE_FORMAT_Z24X8_UNORM:
456 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
457 depth = -24;
458 offset_units *= 2.0f;
459 break;
460 case PIPE_FORMAT_Z32_FLOAT:
461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
462 depth = -23;
463 offset_units *= 1.0f;
464 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
465 break;
466 case PIPE_FORMAT_Z16_UNORM:
467 depth = -16;
468 offset_units *= 4.0f;
469 break;
470 default:
471 return;
472 }
473
474 pm4 = si_pm4_alloc_state(rctx);
475
476 if (pm4 == NULL)
477 return;
478
479 /* FIXME some of those reg can be computed with cso */
480 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
481 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
482 fui(rctx->queued.named.rasterizer->offset_scale));
483 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
484 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
485 fui(rctx->queued.named.rasterizer->offset_scale));
486 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
487 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
488
489 si_pm4_set_state(rctx, fb_rs, pm4);
490 }
491
492 /*
493 * Rasterizer
494 */
495
496 static uint32_t si_translate_fill(uint32_t func)
497 {
498 switch(func) {
499 case PIPE_POLYGON_MODE_FILL:
500 return V_028814_X_DRAW_TRIANGLES;
501 case PIPE_POLYGON_MODE_LINE:
502 return V_028814_X_DRAW_LINES;
503 case PIPE_POLYGON_MODE_POINT:
504 return V_028814_X_DRAW_POINTS;
505 default:
506 assert(0);
507 return V_028814_X_DRAW_POINTS;
508 }
509 }
510
511 static void *si_create_rs_state(struct pipe_context *ctx,
512 const struct pipe_rasterizer_state *state)
513 {
514 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
515 struct si_pm4_state *pm4 = &rs->pm4;
516 unsigned tmp;
517 unsigned prov_vtx = 1, polygon_dual_mode;
518 unsigned clip_rule;
519 float psize_min, psize_max;
520
521 if (rs == NULL) {
522 return NULL;
523 }
524
525 rs->two_side = state->light_twoside;
526 rs->multisample_enable = state->multisample;
527 rs->clip_plane_enable = state->clip_plane_enable;
528
529 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
530 state->fill_back != PIPE_POLYGON_MODE_FILL);
531
532 if (state->flatshade_first)
533 prov_vtx = 0;
534
535 rs->flatshade = state->flatshade;
536 rs->sprite_coord_enable = state->sprite_coord_enable;
537 rs->pa_sc_line_stipple = state->line_stipple_enable ?
538 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
539 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
540 rs->pa_su_sc_mode_cntl =
541 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
542 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
543 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
544 S_028814_FACE(!state->front_ccw) |
545 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
546 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
547 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
548 S_028814_POLY_MODE(polygon_dual_mode) |
549 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
551 rs->pa_cl_clip_cntl =
552 S_028810_PS_UCP_MODE(3) |
553 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
554 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
555 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
556 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
557
558 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
559
560 /* offset */
561 rs->offset_units = state->offset_units;
562 rs->offset_scale = state->offset_scale * 12.0f;
563
564 tmp = S_0286D4_FLAT_SHADE_ENA(1);
565 if (state->sprite_coord_enable) {
566 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
567 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
568 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
569 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
570 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
571 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
572 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
573 }
574 }
575 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
576
577 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
578 /* point size 12.4 fixed point */
579 tmp = (unsigned)(state->point_size * 8.0);
580 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
581
582 if (state->point_size_per_vertex) {
583 psize_min = util_get_min_point_size(state);
584 psize_max = 8192;
585 } else {
586 /* Force the point size to be as if the vertex output was disabled. */
587 psize_min = state->point_size;
588 psize_max = state->point_size;
589 }
590 /* Divide by two, because 0.5 = 1 pixel. */
591 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
592 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
593 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
594
595 tmp = (unsigned)state->line_width * 8;
596 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
597 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
598 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
599 S_028A48_MSAA_ENABLE(state->multisample));
600
601 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
602 S_028BE4_PIX_CENTER(state->half_pixel_center) |
603 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
604 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
605 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
606 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
607 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
608
609 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
610 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
611
612 return rs;
613 }
614
615 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
616 {
617 struct r600_context *rctx = (struct r600_context *)ctx;
618 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
619
620 if (state == NULL)
621 return;
622
623 // TODO
624 rctx->sprite_coord_enable = rs->sprite_coord_enable;
625 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
626 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
627
628 si_pm4_bind_state(rctx, rasterizer, rs);
629 si_update_fb_rs_state(rctx);
630 }
631
632 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
633 {
634 struct r600_context *rctx = (struct r600_context *)ctx;
635 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
636 }
637
638 /*
639 * infeered state between dsa and stencil ref
640 */
641 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
642 {
643 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
644 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
645 struct si_state_dsa *dsa = rctx->queued.named.dsa;
646
647 if (pm4 == NULL)
648 return;
649
650 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
651 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
652 S_028430_STENCILMASK(dsa->valuemask[0]) |
653 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
654 S_028430_STENCILOPVAL(1));
655 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
656 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
657 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
658 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
659 S_028434_STENCILOPVAL_BF(1));
660
661 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
662 }
663
664 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
665 const struct pipe_stencil_ref *state)
666 {
667 struct r600_context *rctx = (struct r600_context *)ctx;
668 rctx->stencil_ref = *state;
669 si_update_dsa_stencil_ref(rctx);
670 }
671
672
673 /*
674 * DSA
675 */
676
677 static uint32_t si_translate_stencil_op(int s_op)
678 {
679 switch (s_op) {
680 case PIPE_STENCIL_OP_KEEP:
681 return V_02842C_STENCIL_KEEP;
682 case PIPE_STENCIL_OP_ZERO:
683 return V_02842C_STENCIL_ZERO;
684 case PIPE_STENCIL_OP_REPLACE:
685 return V_02842C_STENCIL_REPLACE_TEST;
686 case PIPE_STENCIL_OP_INCR:
687 return V_02842C_STENCIL_ADD_CLAMP;
688 case PIPE_STENCIL_OP_DECR:
689 return V_02842C_STENCIL_SUB_CLAMP;
690 case PIPE_STENCIL_OP_INCR_WRAP:
691 return V_02842C_STENCIL_ADD_WRAP;
692 case PIPE_STENCIL_OP_DECR_WRAP:
693 return V_02842C_STENCIL_SUB_WRAP;
694 case PIPE_STENCIL_OP_INVERT:
695 return V_02842C_STENCIL_INVERT;
696 default:
697 R600_ERR("Unknown stencil op %d", s_op);
698 assert(0);
699 break;
700 }
701 return 0;
702 }
703
704 static void *si_create_dsa_state(struct pipe_context *ctx,
705 const struct pipe_depth_stencil_alpha_state *state)
706 {
707 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
708 struct si_pm4_state *pm4 = &dsa->pm4;
709 unsigned db_depth_control;
710 unsigned db_render_override, db_render_control;
711 uint32_t db_stencil_control = 0;
712
713 if (dsa == NULL) {
714 return NULL;
715 }
716
717 dsa->valuemask[0] = state->stencil[0].valuemask;
718 dsa->valuemask[1] = state->stencil[1].valuemask;
719 dsa->writemask[0] = state->stencil[0].writemask;
720 dsa->writemask[1] = state->stencil[1].writemask;
721
722 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
723 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
724 S_028800_ZFUNC(state->depth.func);
725
726 /* stencil */
727 if (state->stencil[0].enabled) {
728 db_depth_control |= S_028800_STENCIL_ENABLE(1);
729 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
730 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
731 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
732 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
733
734 if (state->stencil[1].enabled) {
735 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
736 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
737 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
738 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
739 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
740 }
741 }
742
743 /* alpha */
744 if (state->alpha.enabled) {
745 dsa->alpha_func = state->alpha.func;
746 dsa->alpha_ref = state->alpha.ref_value;
747
748 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
749 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
750 } else {
751 dsa->alpha_func = PIPE_FUNC_ALWAYS;
752 }
753
754 /* misc */
755 db_render_control = 0;
756 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
757 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
758 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
759 /* TODO db_render_override depends on query */
760 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
761 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
762 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
763 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
764 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
765 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
766 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
767 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
768 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
769 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
770 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
771 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
772 dsa->db_render_override = db_render_override;
773
774 return dsa;
775 }
776
777 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
778 {
779 struct r600_context *rctx = (struct r600_context *)ctx;
780 struct si_state_dsa *dsa = state;
781
782 if (state == NULL)
783 return;
784
785 si_pm4_bind_state(rctx, dsa, dsa);
786 si_update_dsa_stencil_ref(rctx);
787 }
788
789 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
790 {
791 struct r600_context *rctx = (struct r600_context *)ctx;
792 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
793 }
794
795 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
796 bool copy_stencil, int sample)
797 {
798 struct pipe_depth_stencil_alpha_state dsa;
799 struct si_state_dsa *state;
800
801 memset(&dsa, 0, sizeof(dsa));
802
803 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
804 if (copy_depth || copy_stencil) {
805 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
806 S_028000_DEPTH_COPY(copy_depth) |
807 S_028000_STENCIL_COPY(copy_stencil) |
808 S_028000_COPY_CENTROID(1) |
809 S_028000_COPY_SAMPLE(sample));
810 } else {
811 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
812 S_028000_DEPTH_COMPRESS_DISABLE(1) |
813 S_028000_STENCIL_COMPRESS_DISABLE(1));
814 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
815 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
816 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
817 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
818 S_02800C_DISABLE_TILE_RATE_TILES(1));
819 }
820
821 return state;
822 }
823
824 /*
825 * format translation
826 */
827 static uint32_t si_translate_colorformat(enum pipe_format format)
828 {
829 const struct util_format_description *desc = util_format_description(format);
830
831 #define HAS_SIZE(x,y,z,w) \
832 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
833 desc->channel[2].size == (z) && desc->channel[3].size == (w))
834
835 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
836 return V_028C70_COLOR_10_11_11;
837
838 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
839 return V_028C70_COLOR_INVALID;
840
841 switch (desc->nr_channels) {
842 case 1:
843 switch (desc->channel[0].size) {
844 case 8:
845 return V_028C70_COLOR_8;
846 case 16:
847 return V_028C70_COLOR_16;
848 case 32:
849 return V_028C70_COLOR_32;
850 }
851 break;
852 case 2:
853 if (desc->channel[0].size == desc->channel[1].size) {
854 switch (desc->channel[0].size) {
855 case 8:
856 return V_028C70_COLOR_8_8;
857 case 16:
858 return V_028C70_COLOR_16_16;
859 case 32:
860 return V_028C70_COLOR_32_32;
861 }
862 } else if (HAS_SIZE(8,24,0,0)) {
863 return V_028C70_COLOR_24_8;
864 } else if (HAS_SIZE(24,8,0,0)) {
865 return V_028C70_COLOR_8_24;
866 }
867 break;
868 case 3:
869 if (HAS_SIZE(5,6,5,0)) {
870 return V_028C70_COLOR_5_6_5;
871 } else if (HAS_SIZE(32,8,24,0)) {
872 return V_028C70_COLOR_X24_8_32_FLOAT;
873 }
874 break;
875 case 4:
876 if (desc->channel[0].size == desc->channel[1].size &&
877 desc->channel[0].size == desc->channel[2].size &&
878 desc->channel[0].size == desc->channel[3].size) {
879 switch (desc->channel[0].size) {
880 case 4:
881 return V_028C70_COLOR_4_4_4_4;
882 case 8:
883 return V_028C70_COLOR_8_8_8_8;
884 case 16:
885 return V_028C70_COLOR_16_16_16_16;
886 case 32:
887 return V_028C70_COLOR_32_32_32_32;
888 }
889 } else if (HAS_SIZE(5,5,5,1)) {
890 return V_028C70_COLOR_1_5_5_5;
891 } else if (HAS_SIZE(10,10,10,2)) {
892 return V_028C70_COLOR_2_10_10_10;
893 }
894 break;
895 }
896 return V_028C70_COLOR_INVALID;
897 }
898
899 static uint32_t si_translate_colorswap(enum pipe_format format)
900 {
901 const struct util_format_description *desc = util_format_description(format);
902
903 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
904
905 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
906 return V_028C70_SWAP_STD;
907
908 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
909 return ~0;
910
911 switch (desc->nr_channels) {
912 case 1:
913 if (HAS_SWIZZLE(0,X))
914 return V_028C70_SWAP_STD; /* X___ */
915 else if (HAS_SWIZZLE(3,X))
916 return V_028C70_SWAP_ALT_REV; /* ___X */
917 break;
918 case 2:
919 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
920 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
921 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
922 return V_028C70_SWAP_STD; /* XY__ */
923 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
924 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
925 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
926 return V_028C70_SWAP_STD_REV; /* YX__ */
927 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
928 return V_028C70_SWAP_ALT; /* X__Y */
929 break;
930 case 3:
931 if (HAS_SWIZZLE(0,X))
932 return V_028C70_SWAP_STD; /* XYZ */
933 else if (HAS_SWIZZLE(0,Z))
934 return V_028C70_SWAP_STD_REV; /* ZYX */
935 break;
936 case 4:
937 /* check the middle channels, the 1st and 4th channel can be NONE */
938 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
939 return V_028C70_SWAP_STD; /* XYZW */
940 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
941 return V_028C70_SWAP_STD_REV; /* WZYX */
942 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
943 return V_028C70_SWAP_ALT; /* ZYXW */
944 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
945 return V_028C70_SWAP_ALT_REV; /* WXYZ */
946 break;
947 }
948 return ~0U;
949 }
950
951 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
952 {
953 if (R600_BIG_ENDIAN) {
954 switch(colorformat) {
955 /* 8-bit buffers. */
956 case V_028C70_COLOR_8:
957 return V_028C70_ENDIAN_NONE;
958
959 /* 16-bit buffers. */
960 case V_028C70_COLOR_5_6_5:
961 case V_028C70_COLOR_1_5_5_5:
962 case V_028C70_COLOR_4_4_4_4:
963 case V_028C70_COLOR_16:
964 case V_028C70_COLOR_8_8:
965 return V_028C70_ENDIAN_8IN16;
966
967 /* 32-bit buffers. */
968 case V_028C70_COLOR_8_8_8_8:
969 case V_028C70_COLOR_2_10_10_10:
970 case V_028C70_COLOR_8_24:
971 case V_028C70_COLOR_24_8:
972 case V_028C70_COLOR_16_16:
973 return V_028C70_ENDIAN_8IN32;
974
975 /* 64-bit buffers. */
976 case V_028C70_COLOR_16_16_16_16:
977 return V_028C70_ENDIAN_8IN16;
978
979 case V_028C70_COLOR_32_32:
980 return V_028C70_ENDIAN_8IN32;
981
982 /* 128-bit buffers. */
983 case V_028C70_COLOR_32_32_32_32:
984 return V_028C70_ENDIAN_8IN32;
985 default:
986 return V_028C70_ENDIAN_NONE; /* Unsupported. */
987 }
988 } else {
989 return V_028C70_ENDIAN_NONE;
990 }
991 }
992
993 /* Returns the size in bits of the widest component of a CB format */
994 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
995 {
996 switch(colorformat) {
997 case V_028C70_COLOR_4_4_4_4:
998 return 4;
999
1000 case V_028C70_COLOR_1_5_5_5:
1001 case V_028C70_COLOR_5_5_5_1:
1002 return 5;
1003
1004 case V_028C70_COLOR_5_6_5:
1005 return 6;
1006
1007 case V_028C70_COLOR_8:
1008 case V_028C70_COLOR_8_8:
1009 case V_028C70_COLOR_8_8_8_8:
1010 return 8;
1011
1012 case V_028C70_COLOR_10_10_10_2:
1013 case V_028C70_COLOR_2_10_10_10:
1014 return 10;
1015
1016 case V_028C70_COLOR_10_11_11:
1017 case V_028C70_COLOR_11_11_10:
1018 return 11;
1019
1020 case V_028C70_COLOR_16:
1021 case V_028C70_COLOR_16_16:
1022 case V_028C70_COLOR_16_16_16_16:
1023 return 16;
1024
1025 case V_028C70_COLOR_8_24:
1026 case V_028C70_COLOR_24_8:
1027 return 24;
1028
1029 case V_028C70_COLOR_32:
1030 case V_028C70_COLOR_32_32:
1031 case V_028C70_COLOR_32_32_32_32:
1032 case V_028C70_COLOR_X24_8_32_FLOAT:
1033 return 32;
1034 }
1035
1036 assert(!"Unknown maximum component size");
1037 return 0;
1038 }
1039
1040 static uint32_t si_translate_dbformat(enum pipe_format format)
1041 {
1042 switch (format) {
1043 case PIPE_FORMAT_Z16_UNORM:
1044 return V_028040_Z_16;
1045 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1046 case PIPE_FORMAT_X8Z24_UNORM:
1047 case PIPE_FORMAT_Z24X8_UNORM:
1048 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1049 return V_028040_Z_24; /* deprecated on SI */
1050 case PIPE_FORMAT_Z32_FLOAT:
1051 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1052 return V_028040_Z_32_FLOAT;
1053 default:
1054 return V_028040_Z_INVALID;
1055 }
1056 }
1057
1058 /*
1059 * Texture translation
1060 */
1061
1062 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1063 enum pipe_format format,
1064 const struct util_format_description *desc,
1065 int first_non_void)
1066 {
1067 struct r600_screen *rscreen = (struct r600_screen*)screen;
1068 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1069 boolean uniform = TRUE;
1070 int i;
1071
1072 /* Colorspace (return non-RGB formats directly). */
1073 switch (desc->colorspace) {
1074 /* Depth stencil formats */
1075 case UTIL_FORMAT_COLORSPACE_ZS:
1076 switch (format) {
1077 case PIPE_FORMAT_Z16_UNORM:
1078 return V_008F14_IMG_DATA_FORMAT_16;
1079 case PIPE_FORMAT_X24S8_UINT:
1080 case PIPE_FORMAT_Z24X8_UNORM:
1081 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1082 return V_008F14_IMG_DATA_FORMAT_8_24;
1083 case PIPE_FORMAT_X8Z24_UNORM:
1084 case PIPE_FORMAT_S8X24_UINT:
1085 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1086 return V_008F14_IMG_DATA_FORMAT_24_8;
1087 case PIPE_FORMAT_S8_UINT:
1088 return V_008F14_IMG_DATA_FORMAT_8;
1089 case PIPE_FORMAT_Z32_FLOAT:
1090 return V_008F14_IMG_DATA_FORMAT_32;
1091 case PIPE_FORMAT_X32_S8X24_UINT:
1092 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1093 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1094 default:
1095 goto out_unknown;
1096 }
1097
1098 case UTIL_FORMAT_COLORSPACE_YUV:
1099 goto out_unknown; /* TODO */
1100
1101 case UTIL_FORMAT_COLORSPACE_SRGB:
1102 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1103 goto out_unknown;
1104 break;
1105
1106 default:
1107 break;
1108 }
1109
1110 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1111 if (!enable_s3tc)
1112 goto out_unknown;
1113
1114 switch (format) {
1115 case PIPE_FORMAT_RGTC1_SNORM:
1116 case PIPE_FORMAT_LATC1_SNORM:
1117 case PIPE_FORMAT_RGTC1_UNORM:
1118 case PIPE_FORMAT_LATC1_UNORM:
1119 return V_008F14_IMG_DATA_FORMAT_BC4;
1120 case PIPE_FORMAT_RGTC2_SNORM:
1121 case PIPE_FORMAT_LATC2_SNORM:
1122 case PIPE_FORMAT_RGTC2_UNORM:
1123 case PIPE_FORMAT_LATC2_UNORM:
1124 return V_008F14_IMG_DATA_FORMAT_BC5;
1125 default:
1126 goto out_unknown;
1127 }
1128 }
1129
1130 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1131
1132 if (!enable_s3tc)
1133 goto out_unknown;
1134
1135 if (!util_format_s3tc_enabled) {
1136 goto out_unknown;
1137 }
1138
1139 switch (format) {
1140 case PIPE_FORMAT_DXT1_RGB:
1141 case PIPE_FORMAT_DXT1_RGBA:
1142 case PIPE_FORMAT_DXT1_SRGB:
1143 case PIPE_FORMAT_DXT1_SRGBA:
1144 return V_008F14_IMG_DATA_FORMAT_BC1;
1145 case PIPE_FORMAT_DXT3_RGBA:
1146 case PIPE_FORMAT_DXT3_SRGBA:
1147 return V_008F14_IMG_DATA_FORMAT_BC2;
1148 case PIPE_FORMAT_DXT5_RGBA:
1149 case PIPE_FORMAT_DXT5_SRGBA:
1150 return V_008F14_IMG_DATA_FORMAT_BC3;
1151 default:
1152 goto out_unknown;
1153 }
1154 }
1155
1156 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1157 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1158 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1159 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1160 }
1161
1162 /* R8G8Bx_SNORM - TODO CxV8U8 */
1163
1164 /* See whether the components are of the same size. */
1165 for (i = 1; i < desc->nr_channels; i++) {
1166 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1167 }
1168
1169 /* Non-uniform formats. */
1170 if (!uniform) {
1171 switch(desc->nr_channels) {
1172 case 3:
1173 if (desc->channel[0].size == 5 &&
1174 desc->channel[1].size == 6 &&
1175 desc->channel[2].size == 5) {
1176 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1177 }
1178 goto out_unknown;
1179 case 4:
1180 if (desc->channel[0].size == 5 &&
1181 desc->channel[1].size == 5 &&
1182 desc->channel[2].size == 5 &&
1183 desc->channel[3].size == 1) {
1184 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1185 }
1186 if (desc->channel[0].size == 10 &&
1187 desc->channel[1].size == 10 &&
1188 desc->channel[2].size == 10 &&
1189 desc->channel[3].size == 2) {
1190 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1191 }
1192 goto out_unknown;
1193 }
1194 goto out_unknown;
1195 }
1196
1197 if (first_non_void < 0 || first_non_void > 3)
1198 goto out_unknown;
1199
1200 /* uniform formats */
1201 switch (desc->channel[first_non_void].size) {
1202 case 4:
1203 switch (desc->nr_channels) {
1204 #if 0 /* Not supported for render targets */
1205 case 2:
1206 return V_008F14_IMG_DATA_FORMAT_4_4;
1207 #endif
1208 case 4:
1209 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1210 }
1211 break;
1212 case 8:
1213 switch (desc->nr_channels) {
1214 case 1:
1215 return V_008F14_IMG_DATA_FORMAT_8;
1216 case 2:
1217 return V_008F14_IMG_DATA_FORMAT_8_8;
1218 case 4:
1219 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1220 }
1221 break;
1222 case 16:
1223 switch (desc->nr_channels) {
1224 case 1:
1225 return V_008F14_IMG_DATA_FORMAT_16;
1226 case 2:
1227 return V_008F14_IMG_DATA_FORMAT_16_16;
1228 case 4:
1229 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1230 }
1231 break;
1232 case 32:
1233 switch (desc->nr_channels) {
1234 case 1:
1235 return V_008F14_IMG_DATA_FORMAT_32;
1236 case 2:
1237 return V_008F14_IMG_DATA_FORMAT_32_32;
1238 #if 0 /* Not supported for render targets */
1239 case 3:
1240 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1241 #endif
1242 case 4:
1243 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1244 }
1245 }
1246
1247 out_unknown:
1248 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1249 return ~0;
1250 }
1251
1252 static unsigned si_tex_wrap(unsigned wrap)
1253 {
1254 switch (wrap) {
1255 default:
1256 case PIPE_TEX_WRAP_REPEAT:
1257 return V_008F30_SQ_TEX_WRAP;
1258 case PIPE_TEX_WRAP_CLAMP:
1259 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1260 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1261 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1262 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1263 return V_008F30_SQ_TEX_CLAMP_BORDER;
1264 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1265 return V_008F30_SQ_TEX_MIRROR;
1266 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1267 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1268 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1269 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1270 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1271 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1272 }
1273 }
1274
1275 static unsigned si_tex_filter(unsigned filter)
1276 {
1277 switch (filter) {
1278 default:
1279 case PIPE_TEX_FILTER_NEAREST:
1280 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1281 case PIPE_TEX_FILTER_LINEAR:
1282 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1283 }
1284 }
1285
1286 static unsigned si_tex_mipfilter(unsigned filter)
1287 {
1288 switch (filter) {
1289 case PIPE_TEX_MIPFILTER_NEAREST:
1290 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1291 case PIPE_TEX_MIPFILTER_LINEAR:
1292 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1293 default:
1294 case PIPE_TEX_MIPFILTER_NONE:
1295 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1296 }
1297 }
1298
1299 static unsigned si_tex_compare(unsigned compare)
1300 {
1301 switch (compare) {
1302 default:
1303 case PIPE_FUNC_NEVER:
1304 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1305 case PIPE_FUNC_LESS:
1306 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1307 case PIPE_FUNC_EQUAL:
1308 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1309 case PIPE_FUNC_LEQUAL:
1310 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1311 case PIPE_FUNC_GREATER:
1312 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1313 case PIPE_FUNC_NOTEQUAL:
1314 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1315 case PIPE_FUNC_GEQUAL:
1316 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1317 case PIPE_FUNC_ALWAYS:
1318 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1319 }
1320 }
1321
1322 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1323 {
1324 switch (dim) {
1325 default:
1326 case PIPE_TEXTURE_1D:
1327 return V_008F1C_SQ_RSRC_IMG_1D;
1328 case PIPE_TEXTURE_1D_ARRAY:
1329 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1330 case PIPE_TEXTURE_2D:
1331 case PIPE_TEXTURE_RECT:
1332 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1333 V_008F1C_SQ_RSRC_IMG_2D;
1334 case PIPE_TEXTURE_2D_ARRAY:
1335 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1336 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1337 case PIPE_TEXTURE_3D:
1338 return V_008F1C_SQ_RSRC_IMG_3D;
1339 case PIPE_TEXTURE_CUBE:
1340 return V_008F1C_SQ_RSRC_IMG_CUBE;
1341 }
1342 }
1343
1344 /*
1345 * Format support testing
1346 */
1347
1348 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1349 {
1350 return si_translate_texformat(screen, format, util_format_description(format),
1351 util_format_get_first_non_void_channel(format)) != ~0U;
1352 }
1353
1354 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1355 enum pipe_format format,
1356 const struct util_format_description *desc,
1357 int first_non_void)
1358 {
1359 unsigned type = desc->channel[first_non_void].type;
1360 int i;
1361
1362 if (type == UTIL_FORMAT_TYPE_FIXED)
1363 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1364
1365 /* See whether the components are of the same size. */
1366 for (i = 0; i < desc->nr_channels; i++) {
1367 if (desc->channel[first_non_void].size != desc->channel[i].size)
1368 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1369 }
1370
1371 switch (desc->channel[first_non_void].size) {
1372 case 8:
1373 switch (desc->nr_channels) {
1374 case 1:
1375 return V_008F0C_BUF_DATA_FORMAT_8;
1376 case 2:
1377 return V_008F0C_BUF_DATA_FORMAT_8_8;
1378 case 3:
1379 case 4:
1380 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1381 }
1382 break;
1383 case 16:
1384 switch (desc->nr_channels) {
1385 case 1:
1386 return V_008F0C_BUF_DATA_FORMAT_16;
1387 case 2:
1388 return V_008F0C_BUF_DATA_FORMAT_16_16;
1389 case 3:
1390 case 4:
1391 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1392 }
1393 break;
1394 case 32:
1395 /* From the Southern Islands ISA documentation about MTBUF:
1396 * 'Memory reads of data in memory that is 32 or 64 bits do not
1397 * undergo any format conversion.'
1398 */
1399 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1400 !desc->channel[first_non_void].pure_integer)
1401 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1402
1403 switch (desc->nr_channels) {
1404 case 1:
1405 return V_008F0C_BUF_DATA_FORMAT_32;
1406 case 2:
1407 return V_008F0C_BUF_DATA_FORMAT_32_32;
1408 case 3:
1409 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1410 case 4:
1411 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1412 }
1413 break;
1414 }
1415
1416 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1417 }
1418
1419 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1420 {
1421 const struct util_format_description *desc;
1422 int first_non_void;
1423 unsigned data_format;
1424
1425 desc = util_format_description(format);
1426 first_non_void = util_format_get_first_non_void_channel(format);
1427 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1428 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1429 }
1430
1431 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1432 {
1433 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1434 si_translate_colorswap(format) != ~0U;
1435 }
1436
1437 static bool si_is_zs_format_supported(enum pipe_format format)
1438 {
1439 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1440 }
1441
1442 boolean si_is_format_supported(struct pipe_screen *screen,
1443 enum pipe_format format,
1444 enum pipe_texture_target target,
1445 unsigned sample_count,
1446 unsigned usage)
1447 {
1448 struct r600_screen *rscreen = (struct r600_screen *)screen;
1449 unsigned retval = 0;
1450
1451 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1452 R600_ERR("r600: unsupported texture type %d\n", target);
1453 return FALSE;
1454 }
1455
1456 if (!util_format_is_supported(format, usage))
1457 return FALSE;
1458
1459 if (sample_count > 1) {
1460 if (HAVE_LLVM < 0x0304 || rscreen->b.chip_class != SI)
1461 return FALSE;
1462
1463 switch (sample_count) {
1464 case 2:
1465 case 4:
1466 case 8:
1467 break;
1468 default:
1469 return FALSE;
1470 }
1471 }
1472
1473 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1474 si_is_sampler_format_supported(screen, format)) {
1475 retval |= PIPE_BIND_SAMPLER_VIEW;
1476 }
1477
1478 if ((usage & (PIPE_BIND_RENDER_TARGET |
1479 PIPE_BIND_DISPLAY_TARGET |
1480 PIPE_BIND_SCANOUT |
1481 PIPE_BIND_SHARED)) &&
1482 si_is_colorbuffer_format_supported(format)) {
1483 retval |= usage &
1484 (PIPE_BIND_RENDER_TARGET |
1485 PIPE_BIND_DISPLAY_TARGET |
1486 PIPE_BIND_SCANOUT |
1487 PIPE_BIND_SHARED);
1488 }
1489
1490 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1491 si_is_zs_format_supported(format)) {
1492 retval |= PIPE_BIND_DEPTH_STENCIL;
1493 }
1494
1495 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1496 si_is_vertex_format_supported(screen, format)) {
1497 retval |= PIPE_BIND_VERTEX_BUFFER;
1498 }
1499
1500 if (usage & PIPE_BIND_TRANSFER_READ)
1501 retval |= PIPE_BIND_TRANSFER_READ;
1502 if (usage & PIPE_BIND_TRANSFER_WRITE)
1503 retval |= PIPE_BIND_TRANSFER_WRITE;
1504
1505 return retval == usage;
1506 }
1507
1508 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1509 {
1510 unsigned tile_mode_index = 0;
1511
1512 if (stencil) {
1513 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1514 } else {
1515 tile_mode_index = rtex->surface.tiling_index[level];
1516 }
1517 return tile_mode_index;
1518 }
1519
1520 /*
1521 * framebuffer handling
1522 */
1523
1524 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1525 const struct pipe_framebuffer_state *state, int cb)
1526 {
1527 struct r600_texture *rtex;
1528 struct r600_surface *surf;
1529 unsigned level = state->cbufs[cb]->u.tex.level;
1530 unsigned pitch, slice;
1531 unsigned color_info, color_attrib;
1532 unsigned tile_mode_index;
1533 unsigned format, swap, ntype, endian;
1534 uint64_t offset;
1535 const struct util_format_description *desc;
1536 int i;
1537 unsigned blend_clamp = 0, blend_bypass = 0;
1538 unsigned max_comp_size;
1539
1540 surf = (struct r600_surface *)state->cbufs[cb];
1541 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1542
1543 offset = rtex->surface.level[level].offset;
1544 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1545 offset += rtex->surface.level[level].slice_size *
1546 state->cbufs[cb]->u.tex.first_layer;
1547 }
1548 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1549 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1550 if (slice) {
1551 slice = slice - 1;
1552 }
1553
1554 tile_mode_index = si_tile_mode_index(rtex, level, false);
1555
1556 desc = util_format_description(surf->base.format);
1557 for (i = 0; i < 4; i++) {
1558 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1559 break;
1560 }
1561 }
1562 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1563 ntype = V_028C70_NUMBER_FLOAT;
1564 } else {
1565 ntype = V_028C70_NUMBER_UNORM;
1566 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1567 ntype = V_028C70_NUMBER_SRGB;
1568 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1569 if (desc->channel[i].pure_integer) {
1570 ntype = V_028C70_NUMBER_SINT;
1571 } else {
1572 assert(desc->channel[i].normalized);
1573 ntype = V_028C70_NUMBER_SNORM;
1574 }
1575 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1576 if (desc->channel[i].pure_integer) {
1577 ntype = V_028C70_NUMBER_UINT;
1578 } else {
1579 assert(desc->channel[i].normalized);
1580 ntype = V_028C70_NUMBER_UNORM;
1581 }
1582 }
1583 }
1584
1585 format = si_translate_colorformat(surf->base.format);
1586 if (format == V_028C70_COLOR_INVALID) {
1587 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1588 }
1589 assert(format != V_028C70_COLOR_INVALID);
1590 swap = si_translate_colorswap(surf->base.format);
1591 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1592 endian = V_028C70_ENDIAN_NONE;
1593 } else {
1594 endian = si_colorformat_endian_swap(format);
1595 }
1596
1597 /* blend clamp should be set for all NORM/SRGB types */
1598 if (ntype == V_028C70_NUMBER_UNORM ||
1599 ntype == V_028C70_NUMBER_SNORM ||
1600 ntype == V_028C70_NUMBER_SRGB)
1601 blend_clamp = 1;
1602
1603 /* set blend bypass according to docs if SINT/UINT or
1604 8/24 COLOR variants */
1605 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1606 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1607 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1608 blend_clamp = 0;
1609 blend_bypass = 1;
1610 }
1611
1612 color_info = S_028C70_FORMAT(format) |
1613 S_028C70_COMP_SWAP(swap) |
1614 S_028C70_BLEND_CLAMP(blend_clamp) |
1615 S_028C70_BLEND_BYPASS(blend_bypass) |
1616 S_028C70_NUMBER_TYPE(ntype) |
1617 S_028C70_ENDIAN(endian);
1618
1619 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1620 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1621
1622 if (rtex->resource.b.b.nr_samples > 1) {
1623 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1624
1625 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1626 S_028C74_NUM_FRAGMENTS(log_samples);
1627
1628 if (rtex->fmask.size) {
1629 color_info |= S_028C70_COMPRESSION(1);
1630 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1631
1632 /* due to a bug in the hw, FMASK_BANK_HEIGHT must be set on SI too */
1633 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index) |
1634 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1635 }
1636 }
1637
1638 if (rtex->cmask.size) {
1639 color_info |= S_028C70_FAST_CLEAR(1);
1640 }
1641
1642 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1643 offset >>= 8;
1644
1645 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1646 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1647 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1648 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1649 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1650
1651 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1652 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1653 } else {
1654 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1655 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1656 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1657 }
1658 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1659 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1660
1661 if (rtex->cmask.size) {
1662 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1663 offset + (rtex->cmask.offset >> 8));
1664 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1665 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1666 }
1667 if (rtex->fmask.size) {
1668 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1669 offset + (rtex->fmask.offset >> 8));
1670 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1671 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1672 }
1673
1674 /* set CB_COLOR1_INFO for possible dual-src blending */
1675 if (state->nr_cbufs == 1) {
1676 assert(cb == 0);
1677 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1678 }
1679
1680 /* Determine pixel shader export format */
1681 max_comp_size = si_colorformat_max_comp_size(format);
1682 if (ntype == V_028C70_NUMBER_SRGB ||
1683 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1684 max_comp_size <= 10) ||
1685 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1686 rctx->export_16bpc |= 1 << cb;
1687 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1688 if (state->nr_cbufs == 1)
1689 rctx->export_16bpc |= 1 << 1;
1690 }
1691 }
1692
1693 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1694 const struct pipe_framebuffer_state *state)
1695 {
1696 struct r600_screen *rscreen = rctx->screen;
1697 struct r600_texture *rtex;
1698 struct r600_surface *surf;
1699 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1700 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1701 uint32_t z_info, s_info, db_depth_info;
1702 uint64_t z_offs, s_offs;
1703
1704 if (state->zsbuf == NULL) {
1705 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1706 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1707 return;
1708 }
1709
1710 surf = (struct r600_surface *)state->zsbuf;
1711 level = surf->base.u.tex.level;
1712 rtex = (struct r600_texture*)surf->base.texture;
1713
1714 format = si_translate_dbformat(rtex->resource.b.b.format);
1715
1716 if (format == V_028040_Z_INVALID) {
1717 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1718 }
1719 assert(format != V_028040_Z_INVALID);
1720
1721 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1722 z_offs += rtex->surface.level[level].offset;
1723 s_offs += rtex->surface.stencil_level[level].offset;
1724
1725 z_offs >>= 8;
1726 s_offs >>= 8;
1727
1728 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1729 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1730 if (slice) {
1731 slice = slice - 1;
1732 }
1733
1734 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1735
1736 z_info = S_028040_FORMAT(format);
1737 if (rtex->resource.b.b.nr_samples > 1) {
1738 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1739 }
1740
1741 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1742 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1743 else
1744 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1745
1746 if (rctx->b.chip_class >= CIK) {
1747 switch (rtex->surface.level[level].mode) {
1748 case RADEON_SURF_MODE_2D:
1749 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1750 break;
1751 case RADEON_SURF_MODE_1D:
1752 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1753 case RADEON_SURF_MODE_LINEAR:
1754 default:
1755 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1756 break;
1757 }
1758 tile_split = rtex->surface.tile_split;
1759 stile_split = rtex->surface.stencil_tile_split;
1760 macro_aspect = rtex->surface.mtilea;
1761 bankw = rtex->surface.bankw;
1762 bankh = rtex->surface.bankh;
1763 tile_split = cik_tile_split(tile_split);
1764 stile_split = cik_tile_split(stile_split);
1765 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1766 bankw = cik_bank_wh(bankw);
1767 bankh = cik_bank_wh(bankh);
1768 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1769 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1770 rscreen->b.info.r600_num_backends);
1771
1772 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1773 S_02803C_PIPE_CONFIG(pipe_config) |
1774 S_02803C_BANK_WIDTH(bankw) |
1775 S_02803C_BANK_HEIGHT(bankh) |
1776 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1777 S_02803C_NUM_BANKS(nbanks);
1778 z_info |= S_028040_TILE_SPLIT(tile_split);
1779 s_info |= S_028044_TILE_SPLIT(stile_split);
1780 } else {
1781 tile_mode_index = si_tile_mode_index(rtex, level, false);
1782 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1783 tile_mode_index = si_tile_mode_index(rtex, level, true);
1784 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1785 }
1786
1787 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1788 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1789 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1790
1791 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1792 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1793 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1794
1795 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1796 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1797 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1798 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1799 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1800
1801 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1802 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1803 }
1804
1805 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1806 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1807 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1808 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1809 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1810
1811 /* 2xMSAA
1812 * There are two locations (-4, 4), (4, -4). */
1813 static uint32_t sample_locs_2x[] = {
1814 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1815 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1816 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1817 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1818 };
1819 static unsigned max_dist_2x = 4;
1820 /* 4xMSAA
1821 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1822 static uint32_t sample_locs_4x[] = {
1823 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1824 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1825 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1826 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1827 };
1828 static unsigned max_dist_4x = 6;
1829 /* Cayman/SI 8xMSAA */
1830 static uint32_t cm_sample_locs_8x[] = {
1831 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1832 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1833 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1834 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1835 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1836 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1837 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1838 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1839 };
1840 static unsigned cm_max_dist_8x = 8;
1841 /* Cayman/SI 16xMSAA */
1842 static uint32_t cm_sample_locs_16x[] = {
1843 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1844 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1845 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1846 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1847 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1848 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1849 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1850 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1851 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1852 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1853 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1854 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1855 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1856 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1857 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1858 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1859 };
1860 static unsigned cm_max_dist_16x = 8;
1861
1862 static void si_get_sample_position(struct pipe_context *ctx,
1863 unsigned sample_count,
1864 unsigned sample_index,
1865 float *out_value)
1866 {
1867 int offset, index;
1868 struct {
1869 int idx:4;
1870 } val;
1871 switch (sample_count) {
1872 case 1:
1873 default:
1874 out_value[0] = out_value[1] = 0.5;
1875 break;
1876 case 2:
1877 offset = 4 * (sample_index * 2);
1878 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1879 out_value[0] = (float)(val.idx + 8) / 16.0f;
1880 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1881 out_value[1] = (float)(val.idx + 8) / 16.0f;
1882 break;
1883 case 4:
1884 offset = 4 * (sample_index * 2);
1885 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1886 out_value[0] = (float)(val.idx + 8) / 16.0f;
1887 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1888 out_value[1] = (float)(val.idx + 8) / 16.0f;
1889 break;
1890 case 8:
1891 offset = 4 * (sample_index % 4 * 2);
1892 index = (sample_index / 4) * 4;
1893 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1894 out_value[0] = (float)(val.idx + 8) / 16.0f;
1895 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1896 out_value[1] = (float)(val.idx + 8) / 16.0f;
1897 break;
1898 case 16:
1899 offset = 4 * (sample_index % 4 * 2);
1900 index = (sample_index / 4) * 4;
1901 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1902 out_value[0] = (float)(val.idx + 8) / 16.0f;
1903 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1904 out_value[1] = (float)(val.idx + 8) / 16.0f;
1905 break;
1906 }
1907 }
1908
1909 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
1910 {
1911 unsigned max_dist = 0;
1912
1913 switch (nr_samples) {
1914 default:
1915 nr_samples = 0;
1916 break;
1917 case 2:
1918 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1919 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1920 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1921 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1922 max_dist = max_dist_2x;
1923 break;
1924 case 4:
1925 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1926 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1927 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1928 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1929 max_dist = max_dist_4x;
1930 break;
1931 case 8:
1932 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
1933 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
1934 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
1935 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
1936 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
1937 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
1938 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
1939 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
1940 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
1941 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
1942 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
1943 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
1944 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
1945 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
1946 max_dist = cm_max_dist_8x;
1947 break;
1948 case 16:
1949 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
1950 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
1951 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
1952 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
1953 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
1954 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
1955 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
1956 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
1957 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
1958 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
1959 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
1960 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
1961 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
1962 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
1963 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
1964 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
1965 max_dist = cm_max_dist_16x;
1966 break;
1967 }
1968
1969 if (nr_samples > 1) {
1970 unsigned log_samples = util_logbase2(nr_samples);
1971
1972 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
1973 S_028BDC_LAST_PIXEL(1) |
1974 S_028BDC_EXPAND_LINE_WIDTH(1));
1975 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
1976 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1977 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1978 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
1979
1980 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
1981 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1982 S_028804_PS_ITER_SAMPLES(log_samples) |
1983 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1984 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1985 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1986 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1987 } else {
1988 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
1989 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
1990
1991 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
1992 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1993 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1994 }
1995 }
1996
1997 static void si_set_framebuffer_state(struct pipe_context *ctx,
1998 const struct pipe_framebuffer_state *state)
1999 {
2000 struct r600_context *rctx = (struct r600_context *)ctx;
2001 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2002 uint32_t tl, br;
2003 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2004
2005 if (pm4 == NULL)
2006 return;
2007
2008 if (rctx->framebuffer.nr_cbufs) {
2009 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2010 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2011 }
2012 if (rctx->framebuffer.zsbuf) {
2013 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
2014 }
2015
2016 util_copy_framebuffer_state(&rctx->framebuffer, state);
2017
2018 /* build states */
2019 rctx->export_16bpc = 0;
2020 rctx->fb_compressed_cb_mask = 0;
2021 for (i = 0; i < state->nr_cbufs; i++) {
2022 struct r600_texture *rtex =
2023 (struct r600_texture*)state->cbufs[i]->texture;
2024
2025 si_cb(rctx, pm4, state, i);
2026
2027 if (rtex->fmask.size || rtex->cmask.size) {
2028 rctx->fb_compressed_cb_mask |= 1 << i;
2029 }
2030 }
2031 for (; i < 8; i++) {
2032 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2033 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2034 }
2035
2036 assert(!(rctx->export_16bpc & ~0xff));
2037 si_db(rctx, pm4, state);
2038
2039 tl_x = 0;
2040 tl_y = 0;
2041 br_x = state->width;
2042 br_y = state->height;
2043
2044 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2045 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2046
2047 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2048 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2049 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2050 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2051 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2052 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2053 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2054 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2055 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2056 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2057
2058 if (state->nr_cbufs)
2059 nr_samples = state->cbufs[0]->texture->nr_samples;
2060 else if (state->zsbuf)
2061 nr_samples = state->zsbuf->texture->nr_samples;
2062 else
2063 nr_samples = 0;
2064
2065 si_set_msaa_state(rctx, pm4, nr_samples);
2066 rctx->fb_log_samples = util_logbase2(nr_samples);
2067 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2068 util_format_is_pure_integer(state->cbufs[0]->format);
2069
2070 si_pm4_set_state(rctx, framebuffer, pm4);
2071 si_update_fb_rs_state(rctx);
2072 si_update_fb_blend_state(rctx);
2073 }
2074
2075 /*
2076 * shaders
2077 */
2078
2079 /* Compute the key for the hw shader variant */
2080 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2081 struct si_pipe_shader_selector *sel,
2082 union si_shader_key *key)
2083 {
2084 struct r600_context *rctx = (struct r600_context *)ctx;
2085 memset(key, 0, sizeof(*key));
2086
2087 if (sel->type == PIPE_SHADER_VERTEX) {
2088 unsigned i;
2089 if (!rctx->vertex_elements)
2090 return;
2091
2092 for (i = 0; i < rctx->vertex_elements->count; ++i)
2093 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2094
2095 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2096 key->vs.ucps_enabled |= 0x2;
2097 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2098 key->vs.ucps_enabled |= 0x1;
2099 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2100 if (sel->fs_write_all)
2101 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2102 key->ps.export_16bpc = rctx->export_16bpc;
2103
2104 if (rctx->queued.named.rasterizer) {
2105 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2106 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2107
2108 if (rctx->queued.named.blend) {
2109 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2110 rctx->queued.named.rasterizer->multisample_enable &&
2111 !rctx->fb_cb0_is_integer;
2112 }
2113 }
2114 if (rctx->queued.named.dsa) {
2115 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2116
2117 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2118 if (rctx->framebuffer.nr_cbufs &&
2119 rctx->framebuffer.cbufs[0] &&
2120 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2121 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2122 } else {
2123 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2124 }
2125 }
2126 }
2127
2128 /* Select the hw shader variant depending on the current state.
2129 * (*dirty) is set to 1 if current variant was changed */
2130 int si_shader_select(struct pipe_context *ctx,
2131 struct si_pipe_shader_selector *sel,
2132 unsigned *dirty)
2133 {
2134 union si_shader_key key;
2135 struct si_pipe_shader * shader = NULL;
2136 int r;
2137
2138 si_shader_selector_key(ctx, sel, &key);
2139
2140 /* Check if we don't need to change anything.
2141 * This path is also used for most shaders that don't need multiple
2142 * variants, it will cost just a computation of the key and this
2143 * test. */
2144 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2145 return 0;
2146 }
2147
2148 /* lookup if we have other variants in the list */
2149 if (sel->num_shaders > 1) {
2150 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2151
2152 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2153 p = c;
2154 c = c->next_variant;
2155 }
2156
2157 if (c) {
2158 p->next_variant = c->next_variant;
2159 shader = c;
2160 }
2161 }
2162
2163 if (unlikely(!shader)) {
2164 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2165 shader->selector = sel;
2166 shader->key = key;
2167
2168 r = si_pipe_shader_create(ctx, shader);
2169 if (unlikely(r)) {
2170 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2171 sel->type, r);
2172 sel->current = NULL;
2173 FREE(shader);
2174 return r;
2175 }
2176
2177 /* We don't know the value of fs_write_all property until we built
2178 * at least one variant, so we may need to recompute the key (include
2179 * rctx->framebuffer.nr_cbufs) after building first variant. */
2180 if (sel->type == PIPE_SHADER_FRAGMENT &&
2181 sel->num_shaders == 0 &&
2182 shader->shader.fs_write_all) {
2183 sel->fs_write_all = 1;
2184 si_shader_selector_key(ctx, sel, &shader->key);
2185 }
2186
2187 sel->num_shaders++;
2188 }
2189
2190 if (dirty)
2191 *dirty = 1;
2192
2193 shader->next_variant = sel->current;
2194 sel->current = shader;
2195
2196 return 0;
2197 }
2198
2199 static void *si_create_shader_state(struct pipe_context *ctx,
2200 const struct pipe_shader_state *state,
2201 unsigned pipe_shader_type)
2202 {
2203 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2204 int r;
2205
2206 sel->type = pipe_shader_type;
2207 sel->tokens = tgsi_dup_tokens(state->tokens);
2208 sel->so = state->stream_output;
2209
2210 r = si_shader_select(ctx, sel, NULL);
2211 if (r) {
2212 free(sel);
2213 return NULL;
2214 }
2215
2216 return sel;
2217 }
2218
2219 static void *si_create_fs_state(struct pipe_context *ctx,
2220 const struct pipe_shader_state *state)
2221 {
2222 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2223 }
2224
2225 static void *si_create_vs_state(struct pipe_context *ctx,
2226 const struct pipe_shader_state *state)
2227 {
2228 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2229 }
2230
2231 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2232 {
2233 struct r600_context *rctx = (struct r600_context *)ctx;
2234 struct si_pipe_shader_selector *sel = state;
2235
2236 if (rctx->vs_shader == sel)
2237 return;
2238
2239 rctx->vs_shader = sel;
2240
2241 if (sel && sel->current) {
2242 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2243 rctx->b.streamout.stride_in_dw = sel->so.stride;
2244 } else {
2245 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2246 }
2247
2248 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2249 }
2250
2251 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2252 {
2253 struct r600_context *rctx = (struct r600_context *)ctx;
2254 struct si_pipe_shader_selector *sel = state;
2255
2256 if (rctx->ps_shader == sel)
2257 return;
2258
2259 rctx->ps_shader = sel;
2260
2261 if (sel && sel->current)
2262 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2263 else
2264 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2265
2266 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2267 }
2268
2269 static void si_delete_shader_selector(struct pipe_context *ctx,
2270 struct si_pipe_shader_selector *sel)
2271 {
2272 struct r600_context *rctx = (struct r600_context *)ctx;
2273 struct si_pipe_shader *p = sel->current, *c;
2274
2275 while (p) {
2276 c = p->next_variant;
2277 si_pm4_delete_state(rctx, vs, p->pm4);
2278 si_pipe_shader_destroy(ctx, p);
2279 free(p);
2280 p = c;
2281 }
2282
2283 free(sel->tokens);
2284 free(sel);
2285 }
2286
2287 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2288 {
2289 struct r600_context *rctx = (struct r600_context *)ctx;
2290 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2291
2292 if (rctx->vs_shader == sel) {
2293 rctx->vs_shader = NULL;
2294 }
2295
2296 si_delete_shader_selector(ctx, sel);
2297 }
2298
2299 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2300 {
2301 struct r600_context *rctx = (struct r600_context *)ctx;
2302 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2303
2304 if (rctx->ps_shader == sel) {
2305 rctx->ps_shader = NULL;
2306 }
2307
2308 si_delete_shader_selector(ctx, sel);
2309 }
2310
2311 /*
2312 * Samplers
2313 */
2314
2315 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2316 struct pipe_resource *texture,
2317 const struct pipe_sampler_view *state)
2318 {
2319 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2320 struct r600_texture *tmp = (struct r600_texture*)texture;
2321 const struct util_format_description *desc;
2322 unsigned format, num_format;
2323 uint32_t pitch = 0;
2324 unsigned char state_swizzle[4], swizzle[4];
2325 unsigned height, depth, width;
2326 enum pipe_format pipe_format = state->format;
2327 struct radeon_surface_level *surflevel;
2328 int first_non_void;
2329 uint64_t va;
2330
2331 if (view == NULL)
2332 return NULL;
2333
2334 /* initialize base object */
2335 view->base = *state;
2336 view->base.texture = NULL;
2337 pipe_reference(NULL, &texture->reference);
2338 view->base.texture = texture;
2339 view->base.reference.count = 1;
2340 view->base.context = ctx;
2341
2342 state_swizzle[0] = state->swizzle_r;
2343 state_swizzle[1] = state->swizzle_g;
2344 state_swizzle[2] = state->swizzle_b;
2345 state_swizzle[3] = state->swizzle_a;
2346
2347 surflevel = tmp->surface.level;
2348
2349 /* Texturing with separate depth and stencil. */
2350 if (tmp->is_depth && !tmp->is_flushing_texture) {
2351 switch (pipe_format) {
2352 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2353 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2354 break;
2355 case PIPE_FORMAT_X8Z24_UNORM:
2356 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2357 /* Z24 is always stored like this. */
2358 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2359 break;
2360 case PIPE_FORMAT_X24S8_UINT:
2361 case PIPE_FORMAT_S8X24_UINT:
2362 case PIPE_FORMAT_X32_S8X24_UINT:
2363 pipe_format = PIPE_FORMAT_S8_UINT;
2364 surflevel = tmp->surface.stencil_level;
2365 break;
2366 default:;
2367 }
2368 }
2369
2370 desc = util_format_description(pipe_format);
2371
2372 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2373 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2374 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2375
2376 switch (pipe_format) {
2377 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2378 case PIPE_FORMAT_X24S8_UINT:
2379 case PIPE_FORMAT_X32_S8X24_UINT:
2380 case PIPE_FORMAT_X8Z24_UNORM:
2381 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2382 break;
2383 default:
2384 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2385 }
2386 } else {
2387 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2388 }
2389
2390 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2391
2392 switch (pipe_format) {
2393 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2394 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2395 break;
2396 default:
2397 if (first_non_void < 0) {
2398 if (util_format_is_compressed(pipe_format)) {
2399 switch (pipe_format) {
2400 case PIPE_FORMAT_DXT1_SRGB:
2401 case PIPE_FORMAT_DXT1_SRGBA:
2402 case PIPE_FORMAT_DXT3_SRGBA:
2403 case PIPE_FORMAT_DXT5_SRGBA:
2404 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2405 break;
2406 case PIPE_FORMAT_RGTC1_SNORM:
2407 case PIPE_FORMAT_LATC1_SNORM:
2408 case PIPE_FORMAT_RGTC2_SNORM:
2409 case PIPE_FORMAT_LATC2_SNORM:
2410 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2411 break;
2412 default:
2413 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2414 break;
2415 }
2416 } else {
2417 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2418 }
2419 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2420 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2421 } else {
2422 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2423
2424 switch (desc->channel[first_non_void].type) {
2425 case UTIL_FORMAT_TYPE_FLOAT:
2426 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2427 break;
2428 case UTIL_FORMAT_TYPE_SIGNED:
2429 if (desc->channel[first_non_void].normalized)
2430 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2431 else if (desc->channel[first_non_void].pure_integer)
2432 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2433 else
2434 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2435 break;
2436 case UTIL_FORMAT_TYPE_UNSIGNED:
2437 if (desc->channel[first_non_void].normalized)
2438 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2439 else if (desc->channel[first_non_void].pure_integer)
2440 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2441 else
2442 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2443 }
2444 }
2445 }
2446
2447 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2448 if (format == ~0) {
2449 format = 0;
2450 }
2451
2452 view->resource = &tmp->resource;
2453
2454 /* not supported any more */
2455 //endian = si_colorformat_endian_swap(format);
2456
2457 width = surflevel[0].npix_x;
2458 height = surflevel[0].npix_y;
2459 depth = surflevel[0].npix_z;
2460 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2461
2462 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2463 height = 1;
2464 depth = texture->array_size;
2465 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2466 depth = texture->array_size;
2467 }
2468
2469 va = r600_resource_va(ctx->screen, texture);
2470 va += surflevel[0].offset;
2471 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2472 view->state[0] = va >> 8;
2473 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2474 S_008F14_DATA_FORMAT(format) |
2475 S_008F14_NUM_FORMAT(num_format));
2476 view->state[2] = (S_008F18_WIDTH(width - 1) |
2477 S_008F18_HEIGHT(height - 1));
2478 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2479 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2480 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2481 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2482 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2483 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2484 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2485 util_logbase2(texture->nr_samples) :
2486 state->u.tex.last_level - tmp->mipmap_shift) |
2487 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2488 S_008F1C_POW2_PAD(texture->last_level > 0) |
2489 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2490 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2491 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2492 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2493 view->state[6] = 0;
2494 view->state[7] = 0;
2495
2496 /* Initialize the sampler view for FMASK. */
2497 if (tmp->fmask.size) {
2498 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2499 uint32_t fmask_format;
2500
2501 switch (texture->nr_samples) {
2502 case 2:
2503 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2504 break;
2505 case 4:
2506 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2507 break;
2508 case 8:
2509 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2510 break;
2511 default:
2512 assert(0);
2513 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2514 }
2515
2516 view->fmask_state[0] = va >> 8;
2517 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2518 S_008F14_DATA_FORMAT(fmask_format) |
2519 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2520 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2521 S_008F18_HEIGHT(height - 1);
2522 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2523 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2524 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2525 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2526 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2527 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2528 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2529 S_008F20_PITCH(tmp->fmask.pitch - 1);
2530 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2531 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2532 view->fmask_state[6] = 0;
2533 view->fmask_state[7] = 0;
2534 }
2535
2536 return &view->base;
2537 }
2538
2539 static void si_sampler_view_destroy(struct pipe_context *ctx,
2540 struct pipe_sampler_view *state)
2541 {
2542 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2543
2544 pipe_resource_reference(&state->texture, NULL);
2545 FREE(resource);
2546 }
2547
2548 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2549 {
2550 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2551 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2552 (linear_filter &&
2553 (wrap == PIPE_TEX_WRAP_CLAMP ||
2554 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2555 }
2556
2557 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2558 {
2559 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2560 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2561
2562 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2563 state->border_color.ui[2] || state->border_color.ui[3]) &&
2564 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2565 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2566 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2567 }
2568
2569 static void *si_create_sampler_state(struct pipe_context *ctx,
2570 const struct pipe_sampler_state *state)
2571 {
2572 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2573 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2574 unsigned border_color_type;
2575
2576 if (rstate == NULL) {
2577 return NULL;
2578 }
2579
2580 if (sampler_state_needs_border_color(state))
2581 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2582 else
2583 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2584
2585 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2586 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2587 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2588 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2589 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2590 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2591 aniso_flag_offset << 16 | /* XXX */
2592 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2593 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2594 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2595 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2596 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2597 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2598 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2599 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2600
2601 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2602 memcpy(rstate->border_color, state->border_color.ui,
2603 sizeof(rstate->border_color));
2604 }
2605
2606 return rstate;
2607 }
2608
2609 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2610 * the si_set_sampler_view calls. LTO might help too. */
2611 static void si_set_sampler_views(struct pipe_context *ctx,
2612 unsigned shader, unsigned start,
2613 unsigned count,
2614 struct pipe_sampler_view **views)
2615 {
2616 struct r600_context *rctx = (struct r600_context *)ctx;
2617 struct r600_textures_info *samplers = &rctx->samplers[shader];
2618 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2619 int i;
2620
2621 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2622 return;
2623
2624 assert(start == 0);
2625
2626 for (i = 0; i < count; i++) {
2627 if (views[i]) {
2628 struct r600_texture *rtex =
2629 (struct r600_texture*)views[i]->texture;
2630
2631 if (rtex->is_depth && !rtex->is_flushing_texture) {
2632 samplers->depth_texture_mask |= 1 << i;
2633 } else {
2634 samplers->depth_texture_mask &= ~(1 << i);
2635 }
2636 if (rtex->cmask.size || rtex->fmask.size) {
2637 samplers->compressed_colortex_mask |= 1 << i;
2638 } else {
2639 samplers->compressed_colortex_mask &= ~(1 << i);
2640 }
2641
2642 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2643
2644 if (rtex->fmask.size) {
2645 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2646 views[i], rviews[i]->fmask_state);
2647 } else {
2648 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2649 NULL, NULL);
2650 }
2651 } else {
2652 samplers->depth_texture_mask &= ~(1 << i);
2653 samplers->compressed_colortex_mask &= ~(1 << i);
2654 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2655 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2656 NULL, NULL);
2657 }
2658 }
2659 for (; i < samplers->n_views; i++) {
2660 samplers->depth_texture_mask &= ~(1 << i);
2661 samplers->compressed_colortex_mask &= ~(1 << i);
2662 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2663 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2664 NULL, NULL);
2665 }
2666
2667 samplers->n_views = count;
2668 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2669 }
2670
2671 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2672 void **states,
2673 struct r600_textures_info *samplers,
2674 unsigned user_data_reg)
2675 {
2676 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2677 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2678 uint32_t *border_color_table = NULL;
2679 int i, j;
2680
2681 if (!count)
2682 goto out;
2683
2684 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2685
2686 si_pm4_sh_data_begin(pm4);
2687 for (i = 0; i < count; i++) {
2688 if (rstates[i] &&
2689 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2690 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2691 if (!rctx->border_color_table ||
2692 ((rctx->border_color_offset + count - i) &
2693 C_008F3C_BORDER_COLOR_PTR)) {
2694 r600_resource_reference(&rctx->border_color_table, NULL);
2695 rctx->border_color_offset = 0;
2696
2697 rctx->border_color_table =
2698 r600_resource_create_custom(&rctx->screen->b.b,
2699 PIPE_USAGE_STAGING,
2700 4096 * 4 * 4);
2701 }
2702
2703 if (!border_color_table) {
2704 border_color_table =
2705 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2706 rctx->b.rings.gfx.cs,
2707 PIPE_TRANSFER_WRITE |
2708 PIPE_TRANSFER_UNSYNCHRONIZED);
2709 }
2710
2711 for (j = 0; j < 4; j++) {
2712 border_color_table[4 * rctx->border_color_offset + j] =
2713 util_le32_to_cpu(rstates[i]->border_color[j]);
2714 }
2715
2716 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2717 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2718 }
2719
2720 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2721 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2722 }
2723 }
2724 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2725
2726 if (border_color_table) {
2727 uint64_t va_offset =
2728 r600_resource_va(&rctx->screen->b.b,
2729 (void*)rctx->border_color_table);
2730
2731 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2732 if (rctx->b.chip_class >= CIK)
2733 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2734 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2735 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2736 }
2737
2738 memcpy(samplers->samplers, states, sizeof(void*) * count);
2739
2740 out:
2741 samplers->n_samplers = count;
2742 return pm4;
2743 }
2744
2745 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2746 {
2747 struct r600_context *rctx = (struct r600_context *)ctx;
2748 struct si_pm4_state *pm4;
2749
2750 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2751 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2752 si_pm4_set_state(rctx, vs_sampler, pm4);
2753 }
2754
2755 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2756 {
2757 struct r600_context *rctx = (struct r600_context *)ctx;
2758 struct si_pm4_state *pm4;
2759
2760 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2761 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2762 si_pm4_set_state(rctx, ps_sampler, pm4);
2763 }
2764
2765
2766 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2767 unsigned start, unsigned count,
2768 void **states)
2769 {
2770 assert(start == 0);
2771
2772 switch (shader) {
2773 case PIPE_SHADER_VERTEX:
2774 si_bind_vs_sampler_states(ctx, count, states);
2775 break;
2776 case PIPE_SHADER_FRAGMENT:
2777 si_bind_ps_sampler_states(ctx, count, states);
2778 break;
2779 default:
2780 ;
2781 }
2782 }
2783
2784
2785
2786 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2787 {
2788 struct r600_context *rctx = (struct r600_context *)ctx;
2789 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2790 uint16_t mask = sample_mask;
2791
2792 if (pm4 == NULL)
2793 return;
2794
2795 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2796 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2797
2798 si_pm4_set_state(rctx, sample_mask, pm4);
2799 }
2800
2801 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2802 {
2803 free(state);
2804 }
2805
2806 /*
2807 * Vertex elements & buffers
2808 */
2809
2810 static void *si_create_vertex_elements(struct pipe_context *ctx,
2811 unsigned count,
2812 const struct pipe_vertex_element *elements)
2813 {
2814 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2815 int i;
2816
2817 assert(count < PIPE_MAX_ATTRIBS);
2818 if (!v)
2819 return NULL;
2820
2821 v->count = count;
2822 for (i = 0; i < count; ++i) {
2823 const struct util_format_description *desc;
2824 unsigned data_format, num_format;
2825 int first_non_void;
2826
2827 desc = util_format_description(elements[i].src_format);
2828 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2829 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2830 desc, first_non_void);
2831
2832 switch (desc->channel[first_non_void].type) {
2833 case UTIL_FORMAT_TYPE_FIXED:
2834 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2835 break;
2836 case UTIL_FORMAT_TYPE_SIGNED:
2837 if (desc->channel[first_non_void].normalized)
2838 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2839 else if (desc->channel[first_non_void].pure_integer)
2840 num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
2841 else
2842 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
2843 break;
2844 case UTIL_FORMAT_TYPE_UNSIGNED:
2845 if (desc->channel[first_non_void].normalized)
2846 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2847 else if (desc->channel[first_non_void].pure_integer)
2848 num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
2849 else
2850 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
2851 break;
2852 case UTIL_FORMAT_TYPE_FLOAT:
2853 default:
2854 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2855 }
2856
2857 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2858 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2859 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2860 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2861 S_008F0C_NUM_FORMAT(num_format) |
2862 S_008F0C_DATA_FORMAT(data_format);
2863 }
2864 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2865
2866 return v;
2867 }
2868
2869 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2870 {
2871 struct r600_context *rctx = (struct r600_context *)ctx;
2872 struct si_vertex_element *v = (struct si_vertex_element*)state;
2873
2874 rctx->vertex_elements = v;
2875 }
2876
2877 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2878 {
2879 struct r600_context *rctx = (struct r600_context *)ctx;
2880
2881 if (rctx->vertex_elements == state)
2882 rctx->vertex_elements = NULL;
2883 FREE(state);
2884 }
2885
2886 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2887 const struct pipe_vertex_buffer *buffers)
2888 {
2889 struct r600_context *rctx = (struct r600_context *)ctx;
2890
2891 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2892 }
2893
2894 static void si_set_index_buffer(struct pipe_context *ctx,
2895 const struct pipe_index_buffer *ib)
2896 {
2897 struct r600_context *rctx = (struct r600_context *)ctx;
2898
2899 if (ib) {
2900 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2901 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2902 } else {
2903 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2904 }
2905 }
2906
2907 /*
2908 * Misc
2909 */
2910 static void si_set_polygon_stipple(struct pipe_context *ctx,
2911 const struct pipe_poly_stipple *state)
2912 {
2913 }
2914
2915 static void si_texture_barrier(struct pipe_context *ctx)
2916 {
2917 struct r600_context *rctx = (struct r600_context *)ctx;
2918
2919 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2920 R600_CONTEXT_FLUSH_AND_INV_CB;
2921 }
2922
2923 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
2924 {
2925 struct pipe_blend_state blend;
2926
2927 memset(&blend, 0, sizeof(blend));
2928 blend.independent_blend_enable = true;
2929 blend.rt[0].colormask = 0xf;
2930 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
2931 }
2932
2933 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2934 struct pipe_resource *texture,
2935 const struct pipe_surface *surf_tmpl)
2936 {
2937 struct r600_texture *rtex = (struct r600_texture*)texture;
2938 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
2939 unsigned level = surf_tmpl->u.tex.level;
2940
2941 if (surface == NULL)
2942 return NULL;
2943
2944 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2945 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2946 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
2947
2948 pipe_reference_init(&surface->base.reference, 1);
2949 pipe_resource_reference(&surface->base.texture, texture);
2950 surface->base.context = pipe;
2951 surface->base.format = surf_tmpl->format;
2952 surface->base.width = rtex->surface.level[level].npix_x;
2953 surface->base.height = rtex->surface.level[level].npix_y;
2954 surface->base.texture = texture;
2955 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
2956 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
2957 surface->base.u.tex.level = level;
2958
2959 return &surface->base;
2960 }
2961
2962 static void r600_surface_destroy(struct pipe_context *pipe,
2963 struct pipe_surface *surface)
2964 {
2965 pipe_resource_reference(&surface->texture, NULL);
2966 FREE(surface);
2967 }
2968
2969 static boolean si_dma_copy(struct pipe_context *ctx,
2970 struct pipe_resource *dst,
2971 unsigned dst_level,
2972 unsigned dst_x, unsigned dst_y, unsigned dst_z,
2973 struct pipe_resource *src,
2974 unsigned src_level,
2975 const struct pipe_box *src_box)
2976 {
2977 /* XXX implement this or share evergreen_dma_blit with r600g */
2978 return FALSE;
2979 }
2980
2981 void si_init_state_functions(struct r600_context *rctx)
2982 {
2983 int i;
2984
2985 rctx->b.b.create_blend_state = si_create_blend_state;
2986 rctx->b.b.bind_blend_state = si_bind_blend_state;
2987 rctx->b.b.delete_blend_state = si_delete_blend_state;
2988 rctx->b.b.set_blend_color = si_set_blend_color;
2989
2990 rctx->b.b.create_rasterizer_state = si_create_rs_state;
2991 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2992 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2993
2994 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2995 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2996 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2997
2998 for (i = 0; i < 8; i++) {
2999 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3000 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3001 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3002 }
3003 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3004 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3005 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3006
3007 rctx->b.b.set_clip_state = si_set_clip_state;
3008 rctx->b.b.set_scissor_states = si_set_scissor_states;
3009 rctx->b.b.set_viewport_states = si_set_viewport_states;
3010 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3011
3012 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3013 rctx->b.b.get_sample_position = si_get_sample_position;
3014
3015 rctx->b.b.create_vs_state = si_create_vs_state;
3016 rctx->b.b.create_fs_state = si_create_fs_state;
3017 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3018 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3019 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3020 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3021
3022 rctx->b.b.create_sampler_state = si_create_sampler_state;
3023 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3024 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3025
3026 rctx->b.b.create_sampler_view = si_create_sampler_view;
3027 rctx->b.b.set_sampler_views = si_set_sampler_views;
3028 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3029
3030 rctx->b.b.set_sample_mask = si_set_sample_mask;
3031
3032 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3033 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3034 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3035 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3036 rctx->b.b.set_index_buffer = si_set_index_buffer;
3037
3038 rctx->b.b.texture_barrier = si_texture_barrier;
3039 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3040 rctx->b.b.create_surface = r600_create_surface;
3041 rctx->b.b.surface_destroy = r600_surface_destroy;
3042 rctx->b.dma_copy = si_dma_copy;
3043
3044 rctx->b.b.draw_vbo = si_draw_vbo;
3045 }
3046
3047 void si_init_config(struct r600_context *rctx)
3048 {
3049 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3050
3051 if (pm4 == NULL)
3052 return;
3053
3054 si_cmd_context_control(pm4);
3055
3056 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3057
3058 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3059 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3060 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3061 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3062 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3063 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3064 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3065 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3066 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3067 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3068 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3069 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3070 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3071 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3072 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3073 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3074 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3075 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3076 if (rctx->b.chip_class == SI) {
3077 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3078 S_028AA8_SWITCH_ON_EOP(1) |
3079 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3080 S_028AA8_PRIMGROUP_SIZE(63));
3081 }
3082 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3083 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3084 if (rctx->b.chip_class < CIK)
3085 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3086 S_008A14_CLIP_VTX_REORDER_ENA(1));
3087
3088 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3089 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3090 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3091
3092 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3093
3094 if (rctx->b.chip_class >= CIK) {
3095 switch (rctx->screen->b.family) {
3096 case CHIP_BONAIRE:
3097 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3098 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3099 break;
3100 case CHIP_KAVERI:
3101 /* XXX todo */
3102 case CHIP_KABINI:
3103 /* XXX todo */
3104 default:
3105 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3106 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3107 break;
3108 }
3109 } else {
3110 switch (rctx->screen->b.family) {
3111 case CHIP_TAHITI:
3112 case CHIP_PITCAIRN:
3113 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3114 break;
3115 case CHIP_VERDE:
3116 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3117 break;
3118 case CHIP_OLAND:
3119 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3120 break;
3121 case CHIP_HAINAN:
3122 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3123 break;
3124 default:
3125 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3126 break;
3127 }
3128 }
3129
3130 si_pm4_set_state(rctx, init, pm4);
3131 }