da78b7ea769f5043678eefaa73b3c210354415b9
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "si_query.h"
27 #include "sid.h"
28 #include "util/fast_idiv_by_const.h"
29 #include "util/format/u_format.h"
30 #include "util/format/u_format_s3tc.h"
31 #include "util/u_dual_blend.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_blend.h"
36
37 #include "gfx10_format_table.h"
38
39 static unsigned si_map_swizzle(unsigned swizzle)
40 {
41 switch (swizzle) {
42 case PIPE_SWIZZLE_Y:
43 return V_008F0C_SQ_SEL_Y;
44 case PIPE_SWIZZLE_Z:
45 return V_008F0C_SQ_SEL_Z;
46 case PIPE_SWIZZLE_W:
47 return V_008F0C_SQ_SEL_W;
48 case PIPE_SWIZZLE_0:
49 return V_008F0C_SQ_SEL_0;
50 case PIPE_SWIZZLE_1:
51 return V_008F0C_SQ_SEL_1;
52 default: /* PIPE_SWIZZLE_X */
53 return V_008F0C_SQ_SEL_X;
54 }
55 }
56
57 /* 12.4 fixed-point */
58 static unsigned si_pack_float_12p4(float x)
59 {
60 return x <= 0 ? 0 : x >= 4096 ? 0xffff : x * 16;
61 }
62
63 /*
64 * Inferred framebuffer and blender state.
65 *
66 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
67 * if there is not enough PS outputs.
68 */
69 static void si_emit_cb_render_state(struct si_context *sctx)
70 {
71 struct radeon_cmdbuf *cs = sctx->gfx_cs;
72 struct si_state_blend *blend = sctx->queued.named.blend;
73 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
74 * but you never know. */
75 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_mask;
76 unsigned i;
77
78 /* Avoid a hang that happens when dual source blending is enabled
79 * but there is not enough color outputs. This is undefined behavior,
80 * so disable color writes completely.
81 *
82 * Reproducible with Unigine Heaven 4.0 and drirc missing.
83 */
84 if (blend->dual_src_blend && sctx->ps_shader.cso &&
85 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
86 cb_target_mask = 0;
87
88 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
89 * I think we don't have to do anything between IBs.
90 */
91 if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask) {
92 sctx->last_cb_target_mask = cb_target_mask;
93
94 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
95 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
96 }
97
98 unsigned initial_cdw = cs->current.cdw;
99 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
100 cb_target_mask);
101
102 if (sctx->chip_class >= GFX8) {
103 /* DCC MSAA workaround.
104 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
105 * COMBINER_DISABLE, but that would be more complicated.
106 */
107 bool oc_disable =
108 blend->dcc_msaa_corruption_4bit & cb_target_mask && sctx->framebuffer.nr_samples >= 2;
109 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
110
111 radeon_opt_set_context_reg(
112 sctx, R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
113 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
114 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
115 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
116 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->info.has_dcc_constant_encode));
117 }
118
119 /* RB+ register settings. */
120 if (sctx->screen->info.rbplus_allowed) {
121 unsigned spi_shader_col_format =
122 sctx->ps_shader.cso ? sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format
123 : 0;
124 unsigned sx_ps_downconvert = 0;
125 unsigned sx_blend_opt_epsilon = 0;
126 unsigned sx_blend_opt_control = 0;
127
128 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
129 struct si_surface *surf = (struct si_surface *)sctx->framebuffer.state.cbufs[i];
130 unsigned format, swap, spi_format, colormask;
131 bool has_alpha, has_rgb;
132
133 if (!surf) {
134 /* If the color buffer is not set, the driver sets 32_R
135 * as the SPI color format, because the hw doesn't allow
136 * holes between color outputs, so also set this to
137 * enable RB+.
138 */
139 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
140 continue;
141 }
142
143 format = G_028C70_FORMAT(surf->cb_color_info);
144 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
145 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
146 colormask = (cb_target_mask >> (i * 4)) & 0xf;
147
148 /* Set if RGB and A are present. */
149 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
150
151 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 ||
152 format == V_028C70_COLOR_32)
153 has_rgb = !has_alpha;
154 else
155 has_rgb = true;
156
157 /* Check the colormask and export format. */
158 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
159 has_rgb = false;
160 if (!(colormask & PIPE_MASK_A))
161 has_alpha = false;
162
163 if (spi_format == V_028714_SPI_SHADER_ZERO) {
164 has_rgb = false;
165 has_alpha = false;
166 }
167
168 /* Disable value checking for disabled channels. */
169 if (!has_rgb)
170 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
171 if (!has_alpha)
172 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
173
174 /* Enable down-conversion for 32bpp and smaller formats. */
175 switch (format) {
176 case V_028C70_COLOR_8:
177 case V_028C70_COLOR_8_8:
178 case V_028C70_COLOR_8_8_8_8:
179 /* For 1 and 2-channel formats, use the superset thereof. */
180 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
181 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
182 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
183 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
184 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
185 }
186 break;
187
188 case V_028C70_COLOR_5_6_5:
189 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_1_5_5_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_4_4_4_4:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_32:
210 if (swap == V_028C70_SWAP_STD && spi_format == V_028714_SPI_SHADER_32_R)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
212 else if (swap == V_028C70_SWAP_ALT_REV && spi_format == V_028714_SPI_SHADER_32_AR)
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
214 break;
215
216 case V_028C70_COLOR_16:
217 case V_028C70_COLOR_16_16:
218 /* For 1-channel formats, use the superset thereof. */
219 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
220 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
221 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
222 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
223 if (swap == V_028C70_SWAP_STD || swap == V_028C70_SWAP_STD_REV)
224 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
225 else
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
227 }
228 break;
229
230 case V_028C70_COLOR_10_11_11:
231 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
233 break;
234
235 case V_028C70_COLOR_2_10_10_10:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_5_9_9_9:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4);
245 break;
246 }
247 }
248
249 /* If there are no color outputs, the first color export is
250 * always enabled as 32_R, so also set this to enable RB+.
251 */
252 if (!sx_ps_downconvert)
253 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
254
255 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
256 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
257 sx_ps_downconvert, sx_blend_opt_epsilon, sx_blend_opt_control);
258 }
259 if (initial_cdw != cs->current.cdw)
260 sctx->context_roll = true;
261 }
262
263 /*
264 * Blender functions
265 */
266
267 static uint32_t si_translate_blend_function(int blend_func)
268 {
269 switch (blend_func) {
270 case PIPE_BLEND_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case PIPE_BLEND_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case PIPE_BLEND_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case PIPE_BLEND_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case PIPE_BLEND_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 PRINT_ERR("Unknown blend function %d\n", blend_func);
282 assert(0);
283 break;
284 }
285 return 0;
286 }
287
288 static uint32_t si_translate_blend_factor(int blend_fact)
289 {
290 switch (blend_fact) {
291 case PIPE_BLENDFACTOR_ONE:
292 return V_028780_BLEND_ONE;
293 case PIPE_BLENDFACTOR_SRC_COLOR:
294 return V_028780_BLEND_SRC_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA:
296 return V_028780_BLEND_SRC_ALPHA;
297 case PIPE_BLENDFACTOR_DST_ALPHA:
298 return V_028780_BLEND_DST_ALPHA;
299 case PIPE_BLENDFACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE;
303 case PIPE_BLENDFACTOR_CONST_COLOR:
304 return V_028780_BLEND_CONSTANT_COLOR;
305 case PIPE_BLENDFACTOR_CONST_ALPHA:
306 return V_028780_BLEND_CONSTANT_ALPHA;
307 case PIPE_BLENDFACTOR_ZERO:
308 return V_028780_BLEND_ZERO;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA:
324 return V_028780_BLEND_SRC1_ALPHA;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
326 return V_028780_BLEND_INV_SRC1_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
331 assert(0);
332 break;
333 }
334 return 0;
335 }
336
337 static uint32_t si_translate_blend_opt_function(int blend_func)
338 {
339 switch (blend_func) {
340 case PIPE_BLEND_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case PIPE_BLEND_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case PIPE_BLEND_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case PIPE_BLEND_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case PIPE_BLEND_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
356 {
357 switch (blend_fact) {
358 case PIPE_BLENDFACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case PIPE_BLENDFACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case PIPE_BLENDFACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 static void si_blend_check_commutativity(struct si_screen *sscreen, struct si_state_blend *blend,
381 enum pipe_blend_func func, enum pipe_blendfactor src,
382 enum pipe_blendfactor dst, unsigned chanmask)
383 {
384 /* Src factor is allowed when it does not depend on Dst */
385 static const uint32_t src_allowed =
386 (1u << PIPE_BLENDFACTOR_ONE) | (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
387 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
388 (1u << PIPE_BLENDFACTOR_CONST_COLOR) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
389 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
390 (1u << PIPE_BLENDFACTOR_ZERO) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
393 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
394
395 if (dst == PIPE_BLENDFACTOR_ONE && (src_allowed & (1u << src))) {
396 /* Addition is commutative, but floating point addition isn't
397 * associative: subtle changes can be introduced via different
398 * rounding.
399 *
400 * Out-of-order is also non-deterministic, which means that
401 * this breaks OpenGL invariance requirements. So only enable
402 * out-of-order additive blending if explicitly allowed by a
403 * setting.
404 */
405 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
406 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
407 blend->commutative_4bit |= chanmask;
408 }
409 }
410
411 /**
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
414 */
415 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor, unsigned *dst_factor,
416 unsigned expected_dst, unsigned replacement_src)
417 {
418 if (*src_factor == expected_dst && *dst_factor == PIPE_BLENDFACTOR_ZERO) {
419 *src_factor = PIPE_BLENDFACTOR_ZERO;
420 *dst_factor = replacement_src;
421
422 /* Commuting the operands requires reversing subtractions. */
423 if (*func == PIPE_BLEND_SUBTRACT)
424 *func = PIPE_BLEND_REVERSE_SUBTRACT;
425 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
426 *func = PIPE_BLEND_SUBTRACT;
427 }
428 }
429
430 static void *si_create_blend_state_mode(struct pipe_context *ctx,
431 const struct pipe_blend_state *state, unsigned mode)
432 {
433 struct si_context *sctx = (struct si_context *)ctx;
434 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
435 struct si_pm4_state *pm4 = &blend->pm4;
436 uint32_t sx_mrt_blend_opt[8] = {0};
437 uint32_t color_control = 0;
438 bool logicop_enable = state->logicop_enable && state->logicop_func != PIPE_LOGICOP_COPY;
439
440 if (!blend)
441 return NULL;
442
443 blend->alpha_to_coverage = state->alpha_to_coverage;
444 blend->alpha_to_one = state->alpha_to_one;
445 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
446 blend->logicop_enable = logicop_enable;
447
448 unsigned num_shader_outputs = state->max_rt + 1; /* estimate */
449 if (blend->dual_src_blend)
450 num_shader_outputs = MAX2(num_shader_outputs, 2);
451
452 if (logicop_enable) {
453 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
454 } else {
455 color_control |= S_028808_ROP3(0xcc);
456 }
457
458 if (state->alpha_to_coverage && state->alpha_to_coverage_dither) {
459 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
460 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
461 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
462 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
463 S_028B70_OFFSET_ROUND(1));
464 } else {
465 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
466 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
467 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
468 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
469 S_028B70_OFFSET_ROUND(0));
470 }
471
472 if (state->alpha_to_coverage)
473 blend->need_src_alpha_4bit |= 0xf;
474
475 blend->cb_target_mask = 0;
476 blend->cb_target_enabled_4bit = 0;
477
478 for (int i = 0; i < num_shader_outputs; i++) {
479 /* state->rt entries > 0 only written if independent blending */
480 const int j = state->independent_blend_enable ? i : 0;
481
482 unsigned eqRGB = state->rt[j].rgb_func;
483 unsigned srcRGB = state->rt[j].rgb_src_factor;
484 unsigned dstRGB = state->rt[j].rgb_dst_factor;
485 unsigned eqA = state->rt[j].alpha_func;
486 unsigned srcA = state->rt[j].alpha_src_factor;
487 unsigned dstA = state->rt[j].alpha_dst_factor;
488
489 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
490 unsigned blend_cntl = 0;
491
492 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
493 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
494
495 /* Only set dual source blending for MRT0 to avoid a hang. */
496 if (i >= 1 && blend->dual_src_blend) {
497 /* Vulkan does this for dual source blending. */
498 if (i == 1)
499 blend_cntl |= S_028780_ENABLE(1);
500
501 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
502 continue;
503 }
504
505 /* Only addition and subtraction equations are supported with
506 * dual source blending.
507 */
508 if (blend->dual_src_blend && (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
509 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
510 assert(!"Unsupported equation for dual source blending");
511 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
512 continue;
513 }
514
515 /* cb_render_state will disable unused ones */
516 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
517 if (state->rt[j].colormask)
518 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
519
520 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
521 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
522 continue;
523 }
524
525 si_blend_check_commutativity(sctx->screen, blend, eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
526 si_blend_check_commutativity(sctx->screen, blend, eqA, srcA, dstA, 0x8 << (4 * i));
527
528 /* Blending optimizations for RB+.
529 * These transformations don't change the behavior.
530 *
531 * First, get rid of DST in the blend factors:
532 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
533 */
534 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, PIPE_BLENDFACTOR_DST_COLOR,
535 PIPE_BLENDFACTOR_SRC_COLOR);
536 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_COLOR,
537 PIPE_BLENDFACTOR_SRC_COLOR);
538 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_ALPHA,
539 PIPE_BLENDFACTOR_SRC_ALPHA);
540
541 /* Look up the ideal settings from tables. */
542 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
543 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
544 srcA_opt = si_translate_blend_opt_factor(srcA, true);
545 dstA_opt = si_translate_blend_opt_factor(dstA, true);
546
547 /* Handle interdependencies. */
548 if (util_blend_factor_uses_dest(srcRGB, false))
549 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
550 if (util_blend_factor_uses_dest(srcA, false))
551 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
552
553 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
554 (dstRGB == PIPE_BLENDFACTOR_ZERO || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
555 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
556 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
557
558 /* Set the final value. */
559 sx_mrt_blend_opt[i] = S_028760_COLOR_SRC_OPT(srcRGB_opt) |
560 S_028760_COLOR_DST_OPT(dstRGB_opt) |
561 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
562 S_028760_ALPHA_SRC_OPT(srcA_opt) | S_028760_ALPHA_DST_OPT(dstA_opt) |
563 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
564
565 /* Set blend state. */
566 blend_cntl |= S_028780_ENABLE(1);
567 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
568 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
569 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
570
571 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
572 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
573 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
574 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
575 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
576 }
577 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
578
579 blend->blend_enable_4bit |= 0xfu << (i * 4);
580
581 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10)
582 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
583
584 /* This is only important for formats without alpha. */
585 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
586 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
587 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
588 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
589 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
590 }
591
592 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10 && logicop_enable)
593 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
594
595 if (blend->cb_target_mask) {
596 color_control |= S_028808_MODE(mode);
597 } else {
598 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
599 }
600
601 if (sctx->screen->info.rbplus_allowed) {
602 /* Disable RB+ blend optimizations for dual source blending.
603 * Vulkan does this.
604 */
605 if (blend->dual_src_blend) {
606 for (int i = 0; i < num_shader_outputs; i++) {
607 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
608 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
609 }
610 }
611
612 for (int i = 0; i < num_shader_outputs; i++)
613 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
614
615 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
616 if (blend->dual_src_blend || logicop_enable || mode == V_028808_CB_RESOLVE)
617 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
618 }
619
620 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
621 return blend;
622 }
623
624 static void *si_create_blend_state(struct pipe_context *ctx, const struct pipe_blend_state *state)
625 {
626 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
627 }
628
629 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
630 {
631 struct si_context *sctx = (struct si_context *)ctx;
632 struct si_state_blend *old_blend = sctx->queued.named.blend;
633 struct si_state_blend *blend = (struct si_state_blend *)state;
634
635 if (!blend)
636 blend = (struct si_state_blend *)sctx->noop_blend;
637
638 si_pm4_bind_state(sctx, blend, blend);
639
640 if (old_blend->cb_target_mask != blend->cb_target_mask ||
641 old_blend->dual_src_blend != blend->dual_src_blend ||
642 (old_blend->dcc_msaa_corruption_4bit != blend->dcc_msaa_corruption_4bit &&
643 sctx->framebuffer.nr_samples >= 2 && sctx->screen->dcc_msaa_allowed))
644 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
645
646 if (old_blend->cb_target_mask != blend->cb_target_mask ||
647 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
648 old_blend->alpha_to_one != blend->alpha_to_one ||
649 old_blend->dual_src_blend != blend->dual_src_blend ||
650 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
651 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
652 sctx->do_update_shaders = true;
653
654 if (sctx->screen->dpbb_allowed &&
655 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
656 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
657 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
658 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
659
660 if (sctx->screen->has_out_of_order_rast &&
661 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
662 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
663 old_blend->commutative_4bit != blend->commutative_4bit ||
664 old_blend->logicop_enable != blend->logicop_enable)))
665 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
666 }
667
668 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
669 {
670 struct si_context *sctx = (struct si_context *)ctx;
671
672 if (sctx->queued.named.blend == state)
673 si_bind_blend_state(ctx, sctx->noop_blend);
674
675 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
676 }
677
678 static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state)
679 {
680 struct si_context *sctx = (struct si_context *)ctx;
681 static const struct pipe_blend_color zeros;
682
683 sctx->blend_color.state = *state;
684 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
685 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
686 }
687
688 static void si_emit_blend_color(struct si_context *sctx)
689 {
690 struct radeon_cmdbuf *cs = sctx->gfx_cs;
691
692 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
693 radeon_emit_array(cs, (uint32_t *)sctx->blend_color.state.color, 4);
694 }
695
696 /*
697 * Clipping
698 */
699
700 static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state)
701 {
702 struct si_context *sctx = (struct si_context *)ctx;
703 struct pipe_constant_buffer cb;
704 static const struct pipe_clip_state zeros;
705
706 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
707 return;
708
709 sctx->clip_state.state = *state;
710 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
711 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
712
713 cb.buffer = NULL;
714 cb.user_buffer = state->ucp;
715 cb.buffer_offset = 0;
716 cb.buffer_size = 4 * 4 * 8;
717 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
718 pipe_resource_reference(&cb.buffer, NULL);
719 }
720
721 static void si_emit_clip_state(struct si_context *sctx)
722 {
723 struct radeon_cmdbuf *cs = sctx->gfx_cs;
724
725 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6 * 4);
726 radeon_emit_array(cs, (uint32_t *)sctx->clip_state.state.ucp, 6 * 4);
727 }
728
729 static void si_emit_clip_regs(struct si_context *sctx)
730 {
731 struct si_shader *vs = si_get_vs_state(sctx);
732 struct si_shader_selector *vs_sel = vs->selector;
733 struct si_shader_info *info = &vs_sel->info;
734 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
735 bool window_space = info->stage == MESA_SHADER_VERTEX ?
736 info->base.vs.window_space_position : 0;
737 unsigned clipdist_mask = vs_sel->clipdist_mask;
738 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
739 unsigned culldist_mask = vs_sel->culldist_mask;
740 unsigned total_mask;
741
742 if (vs->key.opt.clip_disable) {
743 assert(!info->base.cull_distance_array_size);
744 clipdist_mask = 0;
745 culldist_mask = 0;
746 }
747 total_mask = clipdist_mask | culldist_mask;
748
749 /* Clip distances on points have no effect, so need to be implemented
750 * as cull distances. This applies for the clipvertex case as well.
751 *
752 * Setting this for primitives other than points should have no adverse
753 * effects.
754 */
755 clipdist_mask &= rs->clip_plane_enable;
756 culldist_mask |= clipdist_mask;
757
758 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
759 unsigned pa_cl_cntl = S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
760 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
761 S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->chip_class >= GFX10_3) |
762 S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->chip_class >= GFX10_3) |
763 clipdist_mask | (culldist_mask << 8);
764
765 if (sctx->chip_class >= GFX10) {
766 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
767 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL, pa_cl_cntl,
768 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
769 } else {
770 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL__CL,
771 vs_sel->pa_cl_vs_out_cntl | pa_cl_cntl);
772 }
773 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
774 rs->pa_cl_clip_cntl | ucp_mask | S_028810_CLIP_DISABLE(window_space));
775
776 if (initial_cdw != sctx->gfx_cs->current.cdw)
777 sctx->context_roll = true;
778 }
779
780 /*
781 * inferred state between framebuffer and rasterizer
782 */
783 static void si_update_poly_offset_state(struct si_context *sctx)
784 {
785 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
786
787 if (!rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
788 si_pm4_bind_state(sctx, poly_offset, NULL);
789 return;
790 }
791
792 /* Use the user format, not db_render_format, so that the polygon
793 * offset behaves as expected by applications.
794 */
795 switch (sctx->framebuffer.state.zsbuf->texture->format) {
796 case PIPE_FORMAT_Z16_UNORM:
797 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
798 break;
799 default: /* 24-bit */
800 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
801 break;
802 case PIPE_FORMAT_Z32_FLOAT:
803 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
804 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
805 break;
806 }
807 }
808
809 /*
810 * Rasterizer
811 */
812
813 static uint32_t si_translate_fill(uint32_t func)
814 {
815 switch (func) {
816 case PIPE_POLYGON_MODE_FILL:
817 return V_028814_X_DRAW_TRIANGLES;
818 case PIPE_POLYGON_MODE_LINE:
819 return V_028814_X_DRAW_LINES;
820 case PIPE_POLYGON_MODE_POINT:
821 return V_028814_X_DRAW_POINTS;
822 default:
823 assert(0);
824 return V_028814_X_DRAW_POINTS;
825 }
826 }
827
828 static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rasterizer_state *state)
829 {
830 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
831 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
832 struct si_pm4_state *pm4 = &rs->pm4;
833 unsigned tmp, i;
834 float psize_min, psize_max;
835
836 if (!rs) {
837 return NULL;
838 }
839
840 if (!state->front_ccw) {
841 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
842 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
843 } else {
844 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
845 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
846 }
847 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
848 rs->provoking_vertex_first = state->flatshade_first;
849 rs->scissor_enable = state->scissor;
850 rs->clip_halfz = state->clip_halfz;
851 rs->two_side = state->light_twoside;
852 rs->multisample_enable = state->multisample;
853 rs->force_persample_interp = state->force_persample_interp;
854 rs->clip_plane_enable = state->clip_plane_enable;
855 rs->half_pixel_center = state->half_pixel_center;
856 rs->line_stipple_enable = state->line_stipple_enable;
857 rs->poly_stipple_enable = state->poly_stipple_enable;
858 rs->line_smooth = state->line_smooth;
859 rs->line_width = state->line_width;
860 rs->poly_smooth = state->poly_smooth;
861 rs->uses_poly_offset = state->offset_point || state->offset_line || state->offset_tri;
862 rs->clamp_fragment_color = state->clamp_fragment_color;
863 rs->clamp_vertex_color = state->clamp_vertex_color;
864 rs->flatshade = state->flatshade;
865 rs->flatshade_first = state->flatshade_first;
866 rs->sprite_coord_enable = state->sprite_coord_enable;
867 rs->rasterizer_discard = state->rasterizer_discard;
868 rs->polygon_mode_enabled =
869 (state->fill_front != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_FRONT)) ||
870 (state->fill_back != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_BACK));
871 rs->polygon_mode_is_lines =
872 (state->fill_front == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_FRONT)) ||
873 (state->fill_back == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_BACK));
874 rs->pa_sc_line_stipple = state->line_stipple_enable
875 ? S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
876 S_028A0C_REPEAT_COUNT(state->line_stipple_factor)
877 : 0;
878 rs->pa_cl_clip_cntl = S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
879 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
880 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
881 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
882 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
883
884 si_pm4_set_reg(
885 pm4, R_0286D4_SPI_INTERP_CONTROL_0,
886 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
887 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
888 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
889 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
890 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
891 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
892
893 /* point size 12.4 fixed point */
894 tmp = (unsigned)(state->point_size * 8.0);
895 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
896
897 if (state->point_size_per_vertex) {
898 psize_min = util_get_min_point_size(state);
899 psize_max = SI_MAX_POINT_SIZE;
900 } else {
901 /* Force the point size to be as if the vertex output was disabled. */
902 psize_min = state->point_size;
903 psize_max = state->point_size;
904 }
905 rs->max_point_size = psize_max;
906
907 /* Divide by two, because 0.5 = 1 pixel. */
908 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
909 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min / 2)) |
910 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max / 2)));
911
912 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
913 S_028A08_WIDTH(si_pack_float_12p4(state->line_width / 2)));
914 si_pm4_set_reg(
915 pm4, R_028A48_PA_SC_MODE_CNTL_0,
916 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
917 S_028A48_MSAA_ENABLE(state->multisample || state->poly_smooth || state->line_smooth) |
918 S_028A48_VPORT_SCISSOR_ENABLE(1) |
919 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
920
921 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
922 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
923 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
924 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
925 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
926 S_028814_FACE(!state->front_ccw) |
927 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
928 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
929 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
930 S_028814_POLY_MODE(rs->polygon_mode_enabled) |
931 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
932 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
933
934 if (!rs->uses_poly_offset)
935 return rs;
936
937 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
938 if (!rs->pm4_poly_offset) {
939 FREE(rs);
940 return NULL;
941 }
942
943 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
944 for (i = 0; i < 3; i++) {
945 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
946 float offset_units = state->offset_units;
947 float offset_scale = state->offset_scale * 16.0f;
948 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
949
950 if (!state->offset_units_unscaled) {
951 switch (i) {
952 case 0: /* 16-bit zbuffer */
953 offset_units *= 4.0f;
954 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
955 break;
956 case 1: /* 24-bit zbuffer */
957 offset_units *= 2.0f;
958 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
959 break;
960 case 2: /* 32-bit zbuffer */
961 offset_units *= 1.0f;
962 pa_su_poly_offset_db_fmt_cntl =
963 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
964 break;
965 }
966 }
967
968 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale));
969 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
970 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale));
971 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
972 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, pa_su_poly_offset_db_fmt_cntl);
973 }
974
975 return rs;
976 }
977
978 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
979 {
980 struct si_context *sctx = (struct si_context *)ctx;
981 struct si_state_rasterizer *old_rs = (struct si_state_rasterizer *)sctx->queued.named.rasterizer;
982 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
983
984 if (!rs)
985 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
986
987 if (old_rs->multisample_enable != rs->multisample_enable) {
988 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
989
990 /* Update the small primitive filter workaround if necessary. */
991 if (sctx->screen->info.has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1)
992 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
993 }
994
995 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
996 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
997
998 si_pm4_bind_state(sctx, rasterizer, rs);
999 si_update_poly_offset_state(sctx);
1000
1001 if (old_rs->scissor_enable != rs->scissor_enable)
1002 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1003
1004 if (old_rs->line_width != rs->line_width || old_rs->max_point_size != rs->max_point_size ||
1005 old_rs->half_pixel_center != rs->half_pixel_center)
1006 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1007
1008 if (old_rs->clip_halfz != rs->clip_halfz)
1009 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1010
1011 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1012 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1013 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1014
1015 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1016 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1017 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1018 old_rs->flatshade != rs->flatshade || old_rs->two_side != rs->two_side ||
1019 old_rs->multisample_enable != rs->multisample_enable ||
1020 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1021 old_rs->poly_smooth != rs->poly_smooth || old_rs->line_smooth != rs->line_smooth ||
1022 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1023 old_rs->force_persample_interp != rs->force_persample_interp)
1024 sctx->do_update_shaders = true;
1025 }
1026
1027 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1028 {
1029 struct si_context *sctx = (struct si_context *)ctx;
1030 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1031
1032 if (sctx->queued.named.rasterizer == state)
1033 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1034
1035 FREE(rs->pm4_poly_offset);
1036 si_pm4_delete_state(sctx, rasterizer, rs);
1037 }
1038
1039 /*
1040 * infeered state between dsa and stencil ref
1041 */
1042 static void si_emit_stencil_ref(struct si_context *sctx)
1043 {
1044 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1045 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1046 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1047
1048 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1049 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1050 S_028430_STENCILMASK(dsa->valuemask[0]) |
1051 S_028430_STENCILWRITEMASK(dsa->writemask[0]) | S_028430_STENCILOPVAL(1));
1052 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1053 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1054 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1055 S_028434_STENCILOPVAL_BF(1));
1056 }
1057
1058 static void si_set_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref *state)
1059 {
1060 struct si_context *sctx = (struct si_context *)ctx;
1061
1062 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1063 return;
1064
1065 sctx->stencil_ref.state = *state;
1066 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1067 }
1068
1069 /*
1070 * DSA
1071 */
1072
1073 static uint32_t si_translate_stencil_op(int s_op)
1074 {
1075 switch (s_op) {
1076 case PIPE_STENCIL_OP_KEEP:
1077 return V_02842C_STENCIL_KEEP;
1078 case PIPE_STENCIL_OP_ZERO:
1079 return V_02842C_STENCIL_ZERO;
1080 case PIPE_STENCIL_OP_REPLACE:
1081 return V_02842C_STENCIL_REPLACE_TEST;
1082 case PIPE_STENCIL_OP_INCR:
1083 return V_02842C_STENCIL_ADD_CLAMP;
1084 case PIPE_STENCIL_OP_DECR:
1085 return V_02842C_STENCIL_SUB_CLAMP;
1086 case PIPE_STENCIL_OP_INCR_WRAP:
1087 return V_02842C_STENCIL_ADD_WRAP;
1088 case PIPE_STENCIL_OP_DECR_WRAP:
1089 return V_02842C_STENCIL_SUB_WRAP;
1090 case PIPE_STENCIL_OP_INVERT:
1091 return V_02842C_STENCIL_INVERT;
1092 default:
1093 PRINT_ERR("Unknown stencil op %d", s_op);
1094 assert(0);
1095 break;
1096 }
1097 return 0;
1098 }
1099
1100 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1101 {
1102 return s->enabled && s->writemask &&
1103 (s->fail_op != PIPE_STENCIL_OP_KEEP || s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1104 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1105 }
1106
1107 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1108 {
1109 /* REPLACE is normally order invariant, except when the stencil
1110 * reference value is written by the fragment shader. Tracking this
1111 * interaction does not seem worth the effort, so be conservative. */
1112 return op != PIPE_STENCIL_OP_INCR && op != PIPE_STENCIL_OP_DECR && op != PIPE_STENCIL_OP_REPLACE;
1113 }
1114
1115 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1116 * invariant in the sense that the set of passing fragments as well as the
1117 * final stencil buffer result does not depend on the order of fragments. */
1118 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1119 {
1120 return !state->enabled || !state->writemask ||
1121 /* The following assumes that Z writes are disabled. */
1122 (state->func == PIPE_FUNC_ALWAYS && si_order_invariant_stencil_op(state->zpass_op) &&
1123 si_order_invariant_stencil_op(state->zfail_op)) ||
1124 (state->func == PIPE_FUNC_NEVER && si_order_invariant_stencil_op(state->fail_op));
1125 }
1126
1127 static void *si_create_dsa_state(struct pipe_context *ctx,
1128 const struct pipe_depth_stencil_alpha_state *state)
1129 {
1130 struct si_context *sctx = (struct si_context *)ctx;
1131 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1132 struct si_pm4_state *pm4 = &dsa->pm4;
1133 unsigned db_depth_control;
1134 uint32_t db_stencil_control = 0;
1135
1136 if (!dsa) {
1137 return NULL;
1138 }
1139
1140 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1141 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1142 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1143 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1144
1145 db_depth_control =
1146 S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1147 S_028800_ZFUNC(state->depth.func) | S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1148
1149 /* stencil */
1150 if (state->stencil[0].enabled) {
1151 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1152 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1153 db_stencil_control |=
1154 S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1155 db_stencil_control |=
1156 S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1157 db_stencil_control |=
1158 S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1159
1160 if (state->stencil[1].enabled) {
1161 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1162 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1163 db_stencil_control |=
1164 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1165 db_stencil_control |=
1166 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1167 db_stencil_control |=
1168 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1169 }
1170 }
1171
1172 /* alpha */
1173 if (state->alpha.enabled) {
1174 dsa->alpha_func = state->alpha.func;
1175
1176 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1177 fui(state->alpha.ref_value));
1178 } else {
1179 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1180 }
1181
1182 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1183 if (state->stencil[0].enabled)
1184 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1185 if (state->depth.bounds_test) {
1186 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1187 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1188 }
1189
1190 dsa->depth_enabled = state->depth.enabled;
1191 dsa->depth_write_enabled = state->depth.enabled && state->depth.writemask;
1192 dsa->stencil_enabled = state->stencil[0].enabled;
1193 dsa->stencil_write_enabled =
1194 state->stencil[0].enabled &&
1195 (si_dsa_writes_stencil(&state->stencil[0]) || si_dsa_writes_stencil(&state->stencil[1]));
1196 dsa->db_can_write = dsa->depth_write_enabled || dsa->stencil_write_enabled;
1197
1198 bool zfunc_is_ordered =
1199 state->depth.func == PIPE_FUNC_NEVER || state->depth.func == PIPE_FUNC_LESS ||
1200 state->depth.func == PIPE_FUNC_LEQUAL || state->depth.func == PIPE_FUNC_GREATER ||
1201 state->depth.func == PIPE_FUNC_GEQUAL;
1202
1203 bool nozwrite_and_order_invariant_stencil =
1204 !dsa->db_can_write ||
1205 (!dsa->depth_write_enabled && si_order_invariant_stencil_state(&state->stencil[0]) &&
1206 si_order_invariant_stencil_state(&state->stencil[1]));
1207
1208 dsa->order_invariance[1].zs =
1209 nozwrite_and_order_invariant_stencil || (!dsa->stencil_write_enabled && zfunc_is_ordered);
1210 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1211
1212 dsa->order_invariance[1].pass_set =
1213 nozwrite_and_order_invariant_stencil ||
1214 (!dsa->stencil_write_enabled &&
1215 (state->depth.func == PIPE_FUNC_ALWAYS || state->depth.func == PIPE_FUNC_NEVER));
1216 dsa->order_invariance[0].pass_set =
1217 !dsa->depth_write_enabled ||
1218 (state->depth.func == PIPE_FUNC_ALWAYS || state->depth.func == PIPE_FUNC_NEVER);
1219
1220 dsa->order_invariance[1].pass_last = sctx->screen->assume_no_z_fights &&
1221 !dsa->stencil_write_enabled && dsa->depth_write_enabled &&
1222 zfunc_is_ordered;
1223 dsa->order_invariance[0].pass_last =
1224 sctx->screen->assume_no_z_fights && dsa->depth_write_enabled && zfunc_is_ordered;
1225
1226 return dsa;
1227 }
1228
1229 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1230 {
1231 struct si_context *sctx = (struct si_context *)ctx;
1232 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1233 struct si_state_dsa *dsa = state;
1234
1235 if (!dsa)
1236 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1237
1238 si_pm4_bind_state(sctx, dsa, dsa);
1239
1240 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1241 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1242 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1243 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1244 }
1245
1246 if (old_dsa->alpha_func != dsa->alpha_func)
1247 sctx->do_update_shaders = true;
1248
1249 if (sctx->screen->dpbb_allowed && ((old_dsa->depth_enabled != dsa->depth_enabled ||
1250 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1251 old_dsa->db_can_write != dsa->db_can_write)))
1252 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1253
1254 if (sctx->screen->has_out_of_order_rast &&
1255 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1256 sizeof(old_dsa->order_invariance))))
1257 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1258 }
1259
1260 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1261 {
1262 struct si_context *sctx = (struct si_context *)ctx;
1263
1264 if (sctx->queued.named.dsa == state)
1265 si_bind_dsa_state(ctx, sctx->noop_dsa);
1266
1267 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1268 }
1269
1270 static void *si_create_db_flush_dsa(struct si_context *sctx)
1271 {
1272 struct pipe_depth_stencil_alpha_state dsa = {};
1273
1274 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1275 }
1276
1277 /* DB RENDER STATE */
1278
1279 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1280 {
1281 struct si_context *sctx = (struct si_context *)ctx;
1282
1283 /* Pipeline stat & streamout queries. */
1284 if (enable) {
1285 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1286 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1287 } else {
1288 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1289 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1290 }
1291
1292 /* Occlusion queries. */
1293 if (sctx->occlusion_queries_disabled != !enable) {
1294 sctx->occlusion_queries_disabled = !enable;
1295 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1296 }
1297 }
1298
1299 void si_set_occlusion_query_state(struct si_context *sctx, bool old_perfect_enable)
1300 {
1301 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1302
1303 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1304
1305 if (perfect_enable != old_perfect_enable)
1306 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1307 }
1308
1309 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1310 {
1311 st->saved_compute = sctx->cs_shader_state.program;
1312
1313 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1314 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1315
1316 st->saved_ssbo_writable_mask = 0;
1317
1318 for (unsigned i = 0; i < 3; i++) {
1319 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1320 (1u << si_get_shaderbuf_slot(i)))
1321 st->saved_ssbo_writable_mask |= 1 << i;
1322 }
1323 }
1324
1325 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1326 {
1327 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1328
1329 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1330 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1331
1332 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1333 st->saved_ssbo_writable_mask);
1334 for (unsigned i = 0; i < 3; ++i)
1335 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1336 }
1337
1338 static void si_emit_db_render_state(struct si_context *sctx)
1339 {
1340 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1341 unsigned db_shader_control, db_render_control, db_count_control;
1342 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1343
1344 /* DB_RENDER_CONTROL */
1345 if (sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled) {
1346 db_render_control = S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1347 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1348 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1349 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1350 db_render_control = S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1351 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1352 } else {
1353 db_render_control = S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1354 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1355 }
1356
1357 /* DB_COUNT_CONTROL (occlusion queries) */
1358 if (sctx->num_occlusion_queries > 0 && !sctx->occlusion_queries_disabled) {
1359 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1360 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1361
1362 if (sctx->chip_class >= GFX7) {
1363 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1364
1365 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1366 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1367 S_028004_SAMPLE_RATE(log_sample_rate) | S_028004_ZPASS_ENABLE(1) |
1368 S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
1369 } else {
1370 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1371 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1372 }
1373 } else {
1374 /* Disable occlusion queries. */
1375 if (sctx->chip_class >= GFX7) {
1376 db_count_control = 0;
1377 } else {
1378 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1379 }
1380 }
1381
1382 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1383 db_render_control, db_count_control);
1384
1385 /* DB_RENDER_OVERRIDE2 */
1386 radeon_opt_set_context_reg(
1387 sctx, R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
1388 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1389 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1390 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
1391 S_028010_CENTROID_COMPUTATION_MODE(sctx->chip_class >= GFX10_3 ? 2 : 0));
1392
1393 db_shader_control = sctx->ps_db_shader_control;
1394
1395 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1396 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1397 db_shader_control &= C_02880C_Z_ORDER;
1398 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1399 }
1400
1401 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1402 if (!rs->multisample_enable)
1403 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1404
1405 if (sctx->screen->info.has_rbplus && !sctx->screen->info.rbplus_allowed)
1406 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1407
1408 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1409 db_shader_control);
1410
1411 if (initial_cdw != sctx->gfx_cs->current.cdw)
1412 sctx->context_roll = true;
1413 }
1414
1415 /*
1416 * format translation
1417 */
1418 static uint32_t si_translate_colorformat(enum chip_class chip_class,
1419 enum pipe_format format)
1420 {
1421 const struct util_format_description *desc = util_format_description(format);
1422 if (!desc)
1423 return V_028C70_COLOR_INVALID;
1424
1425 #define HAS_SIZE(x, y, z, w) \
1426 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1427 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1428
1429 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1430 return V_028C70_COLOR_10_11_11;
1431
1432 if (chip_class >= GFX10_3 &&
1433 format == PIPE_FORMAT_R9G9B9E5_FLOAT) /* isn't plain */
1434 return V_028C70_COLOR_5_9_9_9;
1435
1436 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1437 return V_028C70_COLOR_INVALID;
1438
1439 /* hw cannot support mixed formats (except depth/stencil, since
1440 * stencil is not written to). */
1441 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1442 return V_028C70_COLOR_INVALID;
1443
1444 switch (desc->nr_channels) {
1445 case 1:
1446 switch (desc->channel[0].size) {
1447 case 8:
1448 return V_028C70_COLOR_8;
1449 case 16:
1450 return V_028C70_COLOR_16;
1451 case 32:
1452 return V_028C70_COLOR_32;
1453 }
1454 break;
1455 case 2:
1456 if (desc->channel[0].size == desc->channel[1].size) {
1457 switch (desc->channel[0].size) {
1458 case 8:
1459 return V_028C70_COLOR_8_8;
1460 case 16:
1461 return V_028C70_COLOR_16_16;
1462 case 32:
1463 return V_028C70_COLOR_32_32;
1464 }
1465 } else if (HAS_SIZE(8, 24, 0, 0)) {
1466 return V_028C70_COLOR_24_8;
1467 } else if (HAS_SIZE(24, 8, 0, 0)) {
1468 return V_028C70_COLOR_8_24;
1469 }
1470 break;
1471 case 3:
1472 if (HAS_SIZE(5, 6, 5, 0)) {
1473 return V_028C70_COLOR_5_6_5;
1474 } else if (HAS_SIZE(32, 8, 24, 0)) {
1475 return V_028C70_COLOR_X24_8_32_FLOAT;
1476 }
1477 break;
1478 case 4:
1479 if (desc->channel[0].size == desc->channel[1].size &&
1480 desc->channel[0].size == desc->channel[2].size &&
1481 desc->channel[0].size == desc->channel[3].size) {
1482 switch (desc->channel[0].size) {
1483 case 4:
1484 return V_028C70_COLOR_4_4_4_4;
1485 case 8:
1486 return V_028C70_COLOR_8_8_8_8;
1487 case 16:
1488 return V_028C70_COLOR_16_16_16_16;
1489 case 32:
1490 return V_028C70_COLOR_32_32_32_32;
1491 }
1492 } else if (HAS_SIZE(5, 5, 5, 1)) {
1493 return V_028C70_COLOR_1_5_5_5;
1494 } else if (HAS_SIZE(1, 5, 5, 5)) {
1495 return V_028C70_COLOR_5_5_5_1;
1496 } else if (HAS_SIZE(10, 10, 10, 2)) {
1497 return V_028C70_COLOR_2_10_10_10;
1498 }
1499 break;
1500 }
1501 return V_028C70_COLOR_INVALID;
1502 }
1503
1504 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1505 {
1506 if (SI_BIG_ENDIAN) {
1507 switch (colorformat) {
1508 /* 8-bit buffers. */
1509 case V_028C70_COLOR_8:
1510 return V_028C70_ENDIAN_NONE;
1511
1512 /* 16-bit buffers. */
1513 case V_028C70_COLOR_5_6_5:
1514 case V_028C70_COLOR_1_5_5_5:
1515 case V_028C70_COLOR_4_4_4_4:
1516 case V_028C70_COLOR_16:
1517 case V_028C70_COLOR_8_8:
1518 return V_028C70_ENDIAN_8IN16;
1519
1520 /* 32-bit buffers. */
1521 case V_028C70_COLOR_8_8_8_8:
1522 case V_028C70_COLOR_2_10_10_10:
1523 case V_028C70_COLOR_8_24:
1524 case V_028C70_COLOR_24_8:
1525 case V_028C70_COLOR_16_16:
1526 return V_028C70_ENDIAN_8IN32;
1527
1528 /* 64-bit buffers. */
1529 case V_028C70_COLOR_16_16_16_16:
1530 return V_028C70_ENDIAN_8IN16;
1531
1532 case V_028C70_COLOR_32_32:
1533 return V_028C70_ENDIAN_8IN32;
1534
1535 /* 128-bit buffers. */
1536 case V_028C70_COLOR_32_32_32_32:
1537 return V_028C70_ENDIAN_8IN32;
1538 default:
1539 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1540 }
1541 } else {
1542 return V_028C70_ENDIAN_NONE;
1543 }
1544 }
1545
1546 static uint32_t si_translate_dbformat(enum pipe_format format)
1547 {
1548 switch (format) {
1549 case PIPE_FORMAT_Z16_UNORM:
1550 return V_028040_Z_16;
1551 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1552 case PIPE_FORMAT_X8Z24_UNORM:
1553 case PIPE_FORMAT_Z24X8_UNORM:
1554 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1555 return V_028040_Z_24; /* deprecated on AMD GCN */
1556 case PIPE_FORMAT_Z32_FLOAT:
1557 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1558 return V_028040_Z_32_FLOAT;
1559 default:
1560 return V_028040_Z_INVALID;
1561 }
1562 }
1563
1564 /*
1565 * Texture translation
1566 */
1567
1568 static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
1569 const struct util_format_description *desc,
1570 int first_non_void)
1571 {
1572 struct si_screen *sscreen = (struct si_screen *)screen;
1573 bool uniform = true;
1574 int i;
1575
1576 assert(sscreen->info.chip_class <= GFX9);
1577
1578 /* Colorspace (return non-RGB formats directly). */
1579 switch (desc->colorspace) {
1580 /* Depth stencil formats */
1581 case UTIL_FORMAT_COLORSPACE_ZS:
1582 switch (format) {
1583 case PIPE_FORMAT_Z16_UNORM:
1584 return V_008F14_IMG_DATA_FORMAT_16;
1585 case PIPE_FORMAT_X24S8_UINT:
1586 case PIPE_FORMAT_S8X24_UINT:
1587 /*
1588 * Implemented as an 8_8_8_8 data format to fix texture
1589 * gathers in stencil sampling. This affects at least
1590 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1591 */
1592 if (sscreen->info.chip_class <= GFX8)
1593 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1594
1595 if (format == PIPE_FORMAT_X24S8_UINT)
1596 return V_008F14_IMG_DATA_FORMAT_8_24;
1597 else
1598 return V_008F14_IMG_DATA_FORMAT_24_8;
1599 case PIPE_FORMAT_Z24X8_UNORM:
1600 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1601 return V_008F14_IMG_DATA_FORMAT_8_24;
1602 case PIPE_FORMAT_X8Z24_UNORM:
1603 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1604 return V_008F14_IMG_DATA_FORMAT_24_8;
1605 case PIPE_FORMAT_S8_UINT:
1606 return V_008F14_IMG_DATA_FORMAT_8;
1607 case PIPE_FORMAT_Z32_FLOAT:
1608 return V_008F14_IMG_DATA_FORMAT_32;
1609 case PIPE_FORMAT_X32_S8X24_UINT:
1610 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1611 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1612 default:
1613 goto out_unknown;
1614 }
1615
1616 case UTIL_FORMAT_COLORSPACE_YUV:
1617 goto out_unknown; /* TODO */
1618
1619 case UTIL_FORMAT_COLORSPACE_SRGB:
1620 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1621 goto out_unknown;
1622 break;
1623
1624 default:
1625 break;
1626 }
1627
1628 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1629 if (!sscreen->info.has_format_bc1_through_bc7)
1630 goto out_unknown;
1631
1632 switch (format) {
1633 case PIPE_FORMAT_RGTC1_SNORM:
1634 case PIPE_FORMAT_LATC1_SNORM:
1635 case PIPE_FORMAT_RGTC1_UNORM:
1636 case PIPE_FORMAT_LATC1_UNORM:
1637 return V_008F14_IMG_DATA_FORMAT_BC4;
1638 case PIPE_FORMAT_RGTC2_SNORM:
1639 case PIPE_FORMAT_LATC2_SNORM:
1640 case PIPE_FORMAT_RGTC2_UNORM:
1641 case PIPE_FORMAT_LATC2_UNORM:
1642 return V_008F14_IMG_DATA_FORMAT_BC5;
1643 default:
1644 goto out_unknown;
1645 }
1646 }
1647
1648 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1649 (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA10 ||
1650 sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2)) {
1651 switch (format) {
1652 case PIPE_FORMAT_ETC1_RGB8:
1653 case PIPE_FORMAT_ETC2_RGB8:
1654 case PIPE_FORMAT_ETC2_SRGB8:
1655 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1656 case PIPE_FORMAT_ETC2_RGB8A1:
1657 case PIPE_FORMAT_ETC2_SRGB8A1:
1658 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1659 case PIPE_FORMAT_ETC2_RGBA8:
1660 case PIPE_FORMAT_ETC2_SRGBA8:
1661 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1662 case PIPE_FORMAT_ETC2_R11_UNORM:
1663 case PIPE_FORMAT_ETC2_R11_SNORM:
1664 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1665 case PIPE_FORMAT_ETC2_RG11_UNORM:
1666 case PIPE_FORMAT_ETC2_RG11_SNORM:
1667 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1668 default:
1669 goto out_unknown;
1670 }
1671 }
1672
1673 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1674 if (!sscreen->info.has_format_bc1_through_bc7)
1675 goto out_unknown;
1676
1677 switch (format) {
1678 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1679 case PIPE_FORMAT_BPTC_SRGBA:
1680 return V_008F14_IMG_DATA_FORMAT_BC7;
1681 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1682 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1683 return V_008F14_IMG_DATA_FORMAT_BC6;
1684 default:
1685 goto out_unknown;
1686 }
1687 }
1688
1689 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1690 switch (format) {
1691 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1692 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1693 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1694 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1695 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1696 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1697 default:
1698 goto out_unknown;
1699 }
1700 }
1701
1702 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1703 if (!sscreen->info.has_format_bc1_through_bc7)
1704 goto out_unknown;
1705
1706 switch (format) {
1707 case PIPE_FORMAT_DXT1_RGB:
1708 case PIPE_FORMAT_DXT1_RGBA:
1709 case PIPE_FORMAT_DXT1_SRGB:
1710 case PIPE_FORMAT_DXT1_SRGBA:
1711 return V_008F14_IMG_DATA_FORMAT_BC1;
1712 case PIPE_FORMAT_DXT3_RGBA:
1713 case PIPE_FORMAT_DXT3_SRGBA:
1714 return V_008F14_IMG_DATA_FORMAT_BC2;
1715 case PIPE_FORMAT_DXT5_RGBA:
1716 case PIPE_FORMAT_DXT5_SRGBA:
1717 return V_008F14_IMG_DATA_FORMAT_BC3;
1718 default:
1719 goto out_unknown;
1720 }
1721 }
1722
1723 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1724 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1725 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1726 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1727 }
1728
1729 /* R8G8Bx_SNORM - TODO CxV8U8 */
1730
1731 /* hw cannot support mixed formats (except depth/stencil, since only
1732 * depth is read).*/
1733 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1734 goto out_unknown;
1735
1736 /* See whether the components are of the same size. */
1737 for (i = 1; i < desc->nr_channels; i++) {
1738 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1739 }
1740
1741 /* Non-uniform formats. */
1742 if (!uniform) {
1743 switch (desc->nr_channels) {
1744 case 3:
1745 if (desc->channel[0].size == 5 && desc->channel[1].size == 6 &&
1746 desc->channel[2].size == 5) {
1747 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1748 }
1749 goto out_unknown;
1750 case 4:
1751 if (desc->channel[0].size == 5 && desc->channel[1].size == 5 &&
1752 desc->channel[2].size == 5 && desc->channel[3].size == 1) {
1753 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1754 }
1755 if (desc->channel[0].size == 1 && desc->channel[1].size == 5 &&
1756 desc->channel[2].size == 5 && desc->channel[3].size == 5) {
1757 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1758 }
1759 if (desc->channel[0].size == 10 && desc->channel[1].size == 10 &&
1760 desc->channel[2].size == 10 && desc->channel[3].size == 2) {
1761 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1762 }
1763 goto out_unknown;
1764 }
1765 goto out_unknown;
1766 }
1767
1768 if (first_non_void < 0 || first_non_void > 3)
1769 goto out_unknown;
1770
1771 /* uniform formats */
1772 switch (desc->channel[first_non_void].size) {
1773 case 4:
1774 switch (desc->nr_channels) {
1775 #if 0 /* Not supported for render targets */
1776 case 2:
1777 return V_008F14_IMG_DATA_FORMAT_4_4;
1778 #endif
1779 case 4:
1780 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1781 }
1782 break;
1783 case 8:
1784 switch (desc->nr_channels) {
1785 case 1:
1786 return V_008F14_IMG_DATA_FORMAT_8;
1787 case 2:
1788 return V_008F14_IMG_DATA_FORMAT_8_8;
1789 case 4:
1790 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1791 }
1792 break;
1793 case 16:
1794 switch (desc->nr_channels) {
1795 case 1:
1796 return V_008F14_IMG_DATA_FORMAT_16;
1797 case 2:
1798 return V_008F14_IMG_DATA_FORMAT_16_16;
1799 case 4:
1800 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1801 }
1802 break;
1803 case 32:
1804 switch (desc->nr_channels) {
1805 case 1:
1806 return V_008F14_IMG_DATA_FORMAT_32;
1807 case 2:
1808 return V_008F14_IMG_DATA_FORMAT_32_32;
1809 #if 0 /* Not supported for render targets */
1810 case 3:
1811 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1812 #endif
1813 case 4:
1814 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1815 }
1816 }
1817
1818 out_unknown:
1819 return ~0;
1820 }
1821
1822 static unsigned si_tex_wrap(unsigned wrap)
1823 {
1824 switch (wrap) {
1825 default:
1826 case PIPE_TEX_WRAP_REPEAT:
1827 return V_008F30_SQ_TEX_WRAP;
1828 case PIPE_TEX_WRAP_CLAMP:
1829 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1830 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1831 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1832 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1833 return V_008F30_SQ_TEX_CLAMP_BORDER;
1834 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1835 return V_008F30_SQ_TEX_MIRROR;
1836 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1837 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1838 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1839 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1840 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1841 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1842 }
1843 }
1844
1845 static unsigned si_tex_mipfilter(unsigned filter)
1846 {
1847 switch (filter) {
1848 case PIPE_TEX_MIPFILTER_NEAREST:
1849 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1850 case PIPE_TEX_MIPFILTER_LINEAR:
1851 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1852 default:
1853 case PIPE_TEX_MIPFILTER_NONE:
1854 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1855 }
1856 }
1857
1858 static unsigned si_tex_compare(unsigned compare)
1859 {
1860 switch (compare) {
1861 default:
1862 case PIPE_FUNC_NEVER:
1863 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1864 case PIPE_FUNC_LESS:
1865 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1866 case PIPE_FUNC_EQUAL:
1867 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1868 case PIPE_FUNC_LEQUAL:
1869 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1870 case PIPE_FUNC_GREATER:
1871 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1872 case PIPE_FUNC_NOTEQUAL:
1873 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1874 case PIPE_FUNC_GEQUAL:
1875 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1876 case PIPE_FUNC_ALWAYS:
1877 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1878 }
1879 }
1880
1881 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, unsigned view_target,
1882 unsigned nr_samples)
1883 {
1884 unsigned res_target = tex->buffer.b.b.target;
1885
1886 if (view_target == PIPE_TEXTURE_CUBE || view_target == PIPE_TEXTURE_CUBE_ARRAY)
1887 res_target = view_target;
1888 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1889 else if (res_target == PIPE_TEXTURE_CUBE || res_target == PIPE_TEXTURE_CUBE_ARRAY)
1890 res_target = PIPE_TEXTURE_2D_ARRAY;
1891
1892 /* GFX9 allocates 1D textures as 2D. */
1893 if ((res_target == PIPE_TEXTURE_1D || res_target == PIPE_TEXTURE_1D_ARRAY) &&
1894 sscreen->info.chip_class == GFX9 &&
1895 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1896 if (res_target == PIPE_TEXTURE_1D)
1897 res_target = PIPE_TEXTURE_2D;
1898 else
1899 res_target = PIPE_TEXTURE_2D_ARRAY;
1900 }
1901
1902 switch (res_target) {
1903 default:
1904 case PIPE_TEXTURE_1D:
1905 return V_008F1C_SQ_RSRC_IMG_1D;
1906 case PIPE_TEXTURE_1D_ARRAY:
1907 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1908 case PIPE_TEXTURE_2D:
1909 case PIPE_TEXTURE_RECT:
1910 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : V_008F1C_SQ_RSRC_IMG_2D;
1911 case PIPE_TEXTURE_2D_ARRAY:
1912 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1913 case PIPE_TEXTURE_3D:
1914 return V_008F1C_SQ_RSRC_IMG_3D;
1915 case PIPE_TEXTURE_CUBE:
1916 case PIPE_TEXTURE_CUBE_ARRAY:
1917 return V_008F1C_SQ_RSRC_IMG_CUBE;
1918 }
1919 }
1920
1921 /*
1922 * Format support testing
1923 */
1924
1925 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1926 {
1927 struct si_screen *sscreen = (struct si_screen *)screen;
1928
1929 if (sscreen->info.chip_class >= GFX10) {
1930 const struct gfx10_format *fmt = &gfx10_format_table[format];
1931 if (!fmt->img_format || fmt->buffers_only)
1932 return false;
1933 return true;
1934 }
1935
1936 const struct util_format_description *desc = util_format_description(format);
1937 if (!desc)
1938 return false;
1939
1940 return si_translate_texformat(screen, format, desc,
1941 util_format_get_first_non_void_channel(format)) != ~0U;
1942 }
1943
1944 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1945 const struct util_format_description *desc,
1946 int first_non_void)
1947 {
1948 int i;
1949
1950 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
1951
1952 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1953 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1954
1955 assert(first_non_void >= 0);
1956
1957 if (desc->nr_channels == 4 && desc->channel[0].size == 10 && desc->channel[1].size == 10 &&
1958 desc->channel[2].size == 10 && desc->channel[3].size == 2)
1959 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1960
1961 /* See whether the components are of the same size. */
1962 for (i = 0; i < desc->nr_channels; i++) {
1963 if (desc->channel[first_non_void].size != desc->channel[i].size)
1964 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1965 }
1966
1967 switch (desc->channel[first_non_void].size) {
1968 case 8:
1969 switch (desc->nr_channels) {
1970 case 1:
1971 case 3: /* 3 loads */
1972 return V_008F0C_BUF_DATA_FORMAT_8;
1973 case 2:
1974 return V_008F0C_BUF_DATA_FORMAT_8_8;
1975 case 4:
1976 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1977 }
1978 break;
1979 case 16:
1980 switch (desc->nr_channels) {
1981 case 1:
1982 case 3: /* 3 loads */
1983 return V_008F0C_BUF_DATA_FORMAT_16;
1984 case 2:
1985 return V_008F0C_BUF_DATA_FORMAT_16_16;
1986 case 4:
1987 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1988 }
1989 break;
1990 case 32:
1991 switch (desc->nr_channels) {
1992 case 1:
1993 return V_008F0C_BUF_DATA_FORMAT_32;
1994 case 2:
1995 return V_008F0C_BUF_DATA_FORMAT_32_32;
1996 case 3:
1997 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1998 case 4:
1999 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2000 }
2001 break;
2002 case 64:
2003 /* Legacy double formats. */
2004 switch (desc->nr_channels) {
2005 case 1: /* 1 load */
2006 return V_008F0C_BUF_DATA_FORMAT_32_32;
2007 case 2: /* 1 load */
2008 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2009 case 3: /* 3 loads */
2010 return V_008F0C_BUF_DATA_FORMAT_32_32;
2011 case 4: /* 2 loads */
2012 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2013 }
2014 break;
2015 }
2016
2017 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2018 }
2019
2020 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2021 const struct util_format_description *desc,
2022 int first_non_void)
2023 {
2024 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2025
2026 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2027 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2028
2029 assert(first_non_void >= 0);
2030
2031 switch (desc->channel[first_non_void].type) {
2032 case UTIL_FORMAT_TYPE_SIGNED:
2033 case UTIL_FORMAT_TYPE_FIXED:
2034 if (desc->channel[first_non_void].size >= 32 || desc->channel[first_non_void].pure_integer)
2035 return V_008F0C_BUF_NUM_FORMAT_SINT;
2036 else if (desc->channel[first_non_void].normalized)
2037 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2038 else
2039 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2040 break;
2041 case UTIL_FORMAT_TYPE_UNSIGNED:
2042 if (desc->channel[first_non_void].size >= 32 || desc->channel[first_non_void].pure_integer)
2043 return V_008F0C_BUF_NUM_FORMAT_UINT;
2044 else if (desc->channel[first_non_void].normalized)
2045 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2046 else
2047 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2048 break;
2049 case UTIL_FORMAT_TYPE_FLOAT:
2050 default:
2051 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2052 }
2053 }
2054
2055 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format,
2056 unsigned usage)
2057 {
2058 struct si_screen *sscreen = (struct si_screen *)screen;
2059 const struct util_format_description *desc;
2060 int first_non_void;
2061 unsigned data_format;
2062
2063 assert((usage & ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_VERTEX_BUFFER)) ==
2064 0);
2065
2066 desc = util_format_description(format);
2067 if (!desc)
2068 return 0;
2069
2070 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2071 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2072 * for read-only access (with caveats surrounding bounds checks), but
2073 * obviously fails for write access which we have to implement for
2074 * shader images. Luckily, OpenGL doesn't expect this to be supported
2075 * anyway, and so the only impact is on PBO uploads / downloads, which
2076 * shouldn't be expected to be fast for GL_RGB anyway.
2077 */
2078 if (desc->block.bits == 3 * 8 || desc->block.bits == 3 * 16) {
2079 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2080 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2081 if (!usage)
2082 return 0;
2083 }
2084 }
2085
2086 if (sscreen->info.chip_class >= GFX10) {
2087 const struct gfx10_format *fmt = &gfx10_format_table[format];
2088 if (!fmt->img_format || fmt->img_format >= 128)
2089 return 0;
2090 return usage;
2091 }
2092
2093 first_non_void = util_format_get_first_non_void_channel(format);
2094 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2095 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2096 return 0;
2097
2098 return usage;
2099 }
2100
2101 static bool si_is_colorbuffer_format_supported(enum chip_class chip_class,
2102 enum pipe_format format)
2103 {
2104 return si_translate_colorformat(chip_class, format) != V_028C70_COLOR_INVALID &&
2105 si_translate_colorswap(format, false) != ~0U;
2106 }
2107
2108 static bool si_is_zs_format_supported(enum pipe_format format)
2109 {
2110 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2111 }
2112
2113 static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
2114 enum pipe_texture_target target, unsigned sample_count,
2115 unsigned storage_sample_count, unsigned usage)
2116 {
2117 struct si_screen *sscreen = (struct si_screen *)screen;
2118 unsigned retval = 0;
2119
2120 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2121 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2122 return false;
2123 }
2124
2125 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2126 return false;
2127
2128 if (sample_count > 1) {
2129 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2130 return false;
2131
2132 /* Only power-of-two sample counts are supported. */
2133 if (!util_is_power_of_two_or_zero(sample_count) ||
2134 !util_is_power_of_two_or_zero(storage_sample_count))
2135 return false;
2136
2137 /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
2138 * so don't expose 16 samples there.
2139 */
2140 const unsigned max_eqaa_samples = sscreen->info.num_render_backends == 1 ? 8 : 16;
2141 const unsigned max_samples = 8;
2142
2143 /* MSAA support without framebuffer attachments. */
2144 if (format == PIPE_FORMAT_NONE && sample_count <= max_eqaa_samples)
2145 return true;
2146
2147 if (!sscreen->info.has_eqaa_surface_allocator || util_format_is_depth_or_stencil(format)) {
2148 /* Color without EQAA or depth/stencil. */
2149 if (sample_count > max_samples || sample_count != storage_sample_count)
2150 return false;
2151 } else {
2152 /* Color with EQAA. */
2153 if (sample_count > max_eqaa_samples || storage_sample_count > max_samples)
2154 return false;
2155 }
2156 }
2157
2158 if (usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) {
2159 if (target == PIPE_BUFFER) {
2160 retval |= si_is_vertex_format_supported(
2161 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE));
2162 } else {
2163 if (si_is_sampler_format_supported(screen, format))
2164 retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
2165 }
2166 }
2167
2168 if ((usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2169 PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) &&
2170 si_is_colorbuffer_format_supported(sscreen->info.chip_class, format)) {
2171 retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2172 PIPE_BIND_SHARED);
2173 if (!util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format))
2174 retval |= usage & PIPE_BIND_BLENDABLE;
2175 }
2176
2177 if ((usage & PIPE_BIND_DEPTH_STENCIL) && si_is_zs_format_supported(format)) {
2178 retval |= PIPE_BIND_DEPTH_STENCIL;
2179 }
2180
2181 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2182 retval |= si_is_vertex_format_supported(screen, format, PIPE_BIND_VERTEX_BUFFER);
2183 }
2184
2185 if ((usage & PIPE_BIND_LINEAR) && !util_format_is_compressed(format) &&
2186 !(usage & PIPE_BIND_DEPTH_STENCIL))
2187 retval |= PIPE_BIND_LINEAR;
2188
2189 return retval == usage;
2190 }
2191
2192 /*
2193 * framebuffer handling
2194 */
2195
2196 static void si_choose_spi_color_formats(struct si_surface *surf, unsigned format, unsigned swap,
2197 unsigned ntype, bool is_depth)
2198 {
2199 struct ac_spi_color_formats formats = {};
2200
2201 ac_choose_spi_color_formats(format, swap, ntype, is_depth, &formats);
2202
2203 surf->spi_shader_col_format = formats.normal;
2204 surf->spi_shader_col_format_alpha = formats.alpha;
2205 surf->spi_shader_col_format_blend = formats.blend;
2206 surf->spi_shader_col_format_blend_alpha = formats.blend_alpha;
2207 }
2208
2209 static void si_initialize_color_surface(struct si_context *sctx, struct si_surface *surf)
2210 {
2211 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2212 unsigned color_info, color_attrib;
2213 unsigned format, swap, ntype, endian;
2214 const struct util_format_description *desc;
2215 int firstchan;
2216 unsigned blend_clamp = 0, blend_bypass = 0;
2217
2218 desc = util_format_description(surf->base.format);
2219 for (firstchan = 0; firstchan < 4; firstchan++) {
2220 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2221 break;
2222 }
2223 }
2224 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2225 ntype = V_028C70_NUMBER_FLOAT;
2226 } else {
2227 ntype = V_028C70_NUMBER_UNORM;
2228 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2229 ntype = V_028C70_NUMBER_SRGB;
2230 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2231 if (desc->channel[firstchan].pure_integer) {
2232 ntype = V_028C70_NUMBER_SINT;
2233 } else {
2234 assert(desc->channel[firstchan].normalized);
2235 ntype = V_028C70_NUMBER_SNORM;
2236 }
2237 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2238 if (desc->channel[firstchan].pure_integer) {
2239 ntype = V_028C70_NUMBER_UINT;
2240 } else {
2241 assert(desc->channel[firstchan].normalized);
2242 ntype = V_028C70_NUMBER_UNORM;
2243 }
2244 }
2245 }
2246
2247 format = si_translate_colorformat(sctx->chip_class, surf->base.format);
2248 if (format == V_028C70_COLOR_INVALID) {
2249 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2250 }
2251 assert(format != V_028C70_COLOR_INVALID);
2252 swap = si_translate_colorswap(surf->base.format, false);
2253 endian = si_colorformat_endian_swap(format);
2254
2255 /* blend clamp should be set for all NORM/SRGB types */
2256 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
2257 ntype == V_028C70_NUMBER_SRGB)
2258 blend_clamp = 1;
2259
2260 /* set blend bypass according to docs if SINT/UINT or
2261 8/24 COLOR variants */
2262 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2263 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2264 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2265 blend_clamp = 0;
2266 blend_bypass = 1;
2267 }
2268
2269 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2270 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_8_8 ||
2271 format == V_028C70_COLOR_8_8_8_8)
2272 surf->color_is_int8 = true;
2273 else if (format == V_028C70_COLOR_10_10_10_2 || format == V_028C70_COLOR_2_10_10_10)
2274 surf->color_is_int10 = true;
2275 }
2276
2277 color_info =
2278 S_028C70_FORMAT(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) |
2279 S_028C70_BLEND_BYPASS(blend_bypass) | S_028C70_SIMPLE_FLOAT(1) |
2280 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM && ntype != V_028C70_NUMBER_SNORM &&
2281 ntype != V_028C70_NUMBER_SRGB && format != V_028C70_COLOR_8_24 &&
2282 format != V_028C70_COLOR_24_8) |
2283 S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian);
2284
2285 /* Intensity is implemented as Red, so treat it that way. */
2286 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2287 util_format_is_intensity(surf->base.format));
2288
2289 if (tex->buffer.b.b.nr_samples > 1) {
2290 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2291 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2292
2293 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS(log_fragments);
2294
2295 if (tex->surface.fmask_offset) {
2296 color_info |= S_028C70_COMPRESSION(1);
2297 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2298
2299 if (sctx->chip_class == GFX6) {
2300 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2301 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2302 }
2303 }
2304 }
2305
2306 if (sctx->chip_class >= GFX10) {
2307 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2308
2309 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2310 64 for APU because all of our APUs to date use DIMMs which have
2311 a request granularity size of 64B while all other chips have a
2312 32B request size */
2313 if (!sctx->screen->info.has_dedicated_vram)
2314 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2315
2316 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2317 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.dcc.max_compressed_block_size) |
2318 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2319 S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.dcc.independent_64B_blocks) |
2320 S_028C78_INDEPENDENT_128B_BLOCKS(tex->surface.u.gfx9.dcc.independent_128B_blocks);
2321 } else if (sctx->chip_class >= GFX8) {
2322 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2323 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2324
2325 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2326 64 for APU because all of our APUs to date use DIMMs which have
2327 a request granularity size of 64B while all other chips have a
2328 32B request size */
2329 if (!sctx->screen->info.has_dedicated_vram)
2330 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2331
2332 if (tex->buffer.b.b.nr_storage_samples > 1) {
2333 if (tex->surface.bpe == 1)
2334 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2335 else if (tex->surface.bpe == 2)
2336 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2337 }
2338
2339 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2340 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2341 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2342 }
2343
2344 /* This must be set for fast clear to work without FMASK. */
2345 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2346 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2347 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2348 }
2349
2350 /* GFX10 field has the same base shift as the GFX6 field */
2351 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2352 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2353 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2354
2355 if (sctx->chip_class >= GFX10) {
2356 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2357
2358 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2359 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2360 S_028EE0_RESOURCE_LEVEL(1);
2361 } else if (sctx->chip_class == GFX9) {
2362 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2363 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2364 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2365 }
2366
2367 if (sctx->chip_class >= GFX9) {
2368 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2369 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2370 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2371 }
2372
2373 surf->cb_color_view = color_view;
2374 surf->cb_color_info = color_info;
2375 surf->cb_color_attrib = color_attrib;
2376
2377 /* Determine pixel shader export format */
2378 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2379
2380 surf->color_initialized = true;
2381 }
2382
2383 static void si_init_depth_surface(struct si_context *sctx, struct si_surface *surf)
2384 {
2385 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2386 unsigned level = surf->base.u.tex.level;
2387 unsigned format, stencil_format;
2388 uint32_t z_info, s_info;
2389
2390 format = si_translate_dbformat(tex->db_render_format);
2391 stencil_format = tex->surface.has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2392
2393 assert(format != V_028040_Z_INVALID);
2394 if (format == V_028040_Z_INVALID)
2395 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2396
2397 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2398 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2399 surf->db_htile_data_base = 0;
2400 surf->db_htile_surface = 0;
2401
2402 if (sctx->chip_class >= GFX10) {
2403 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2404 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2405 }
2406
2407 if (sctx->chip_class >= GFX9) {
2408 assert(tex->surface.u.gfx9.surf_offset == 0);
2409 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2410 surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.stencil_offset) >> 8;
2411 z_info = S_028038_FORMAT(format) |
2412 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2413 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2414 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2415 s_info = S_02803C_FORMAT(stencil_format) |
2416 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2417
2418 if (sctx->chip_class == GFX9) {
2419 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2420 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2421 }
2422 surf->db_depth_view |= S_028008_MIPID(level);
2423 surf->db_depth_size =
2424 S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) | S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2425
2426 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2427 z_info |= S_028038_TILE_SURFACE_ENABLE(1) | S_028038_ALLOW_EXPCLEAR(1);
2428
2429 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2430 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2431 * See that for explanation.
2432 */
2433 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2434 } else {
2435 /* Use all HTILE for depth if there's no stencil. */
2436 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2437 }
2438
2439 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8;
2440 surf->db_htile_surface =
2441 S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
2442 if (sctx->chip_class == GFX9) {
2443 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
2444 }
2445 }
2446 } else {
2447 /* GFX6-GFX8 */
2448 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2449
2450 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2451
2452 surf->db_depth_base =
2453 (tex->buffer.gpu_address + tex->surface.u.legacy.level[level].offset) >> 8;
2454 surf->db_stencil_base =
2455 (tex->buffer.gpu_address + tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2456
2457 z_info =
2458 S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2459 s_info = S_028044_FORMAT(stencil_format);
2460 surf->db_depth_info = 0;
2461
2462 if (sctx->chip_class >= GFX7) {
2463 struct radeon_info *info = &sctx->screen->info;
2464 unsigned index = tex->surface.u.legacy.tiling_index[level];
2465 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2466 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2467 unsigned tile_mode = info->si_tile_mode_array[index];
2468 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2469 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2470
2471 surf->db_depth_info |= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2472 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2473 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2474 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2475 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2476 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2477 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2478 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2479 } else {
2480 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2481 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2482 tile_mode_index = si_tile_mode_index(tex, level, true);
2483 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2484 }
2485
2486 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2487 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2488 surf->db_depth_slice =
2489 S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * levelinfo->nblk_y) / 64 - 1);
2490
2491 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2492 z_info |= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1);
2493
2494 if (tex->surface.has_stencil) {
2495 /* Workaround: For a not yet understood reason, the
2496 * combination of MSAA, fast stencil clear and stencil
2497 * decompress messes with subsequent stencil buffer
2498 * uses. Problem was reproduced on Verde, Bonaire,
2499 * Tonga, and Carrizo.
2500 *
2501 * Disabling EXPCLEAR works around the problem.
2502 *
2503 * Check piglit's arb_texture_multisample-stencil-clear
2504 * test if you want to try changing this.
2505 */
2506 if (tex->buffer.b.b.nr_samples <= 1)
2507 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2508 }
2509
2510 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8;
2511 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2512 }
2513 }
2514
2515 surf->db_z_info = z_info;
2516 surf->db_stencil_info = s_info;
2517
2518 surf->depth_initialized = true;
2519 }
2520
2521 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2522 {
2523 if (sctx->decompression_enabled)
2524 return;
2525
2526 if (sctx->framebuffer.state.zsbuf) {
2527 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2528 struct si_texture *tex = (struct si_texture *)surf->texture;
2529
2530 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2531
2532 if (tex->surface.has_stencil)
2533 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2534 }
2535
2536 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2537 while (compressed_cb_mask) {
2538 unsigned i = u_bit_scan(&compressed_cb_mask);
2539 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2540 struct si_texture *tex = (struct si_texture *)surf->texture;
2541
2542 if (tex->surface.fmask_offset) {
2543 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2544 tex->fmask_is_identity = false;
2545 }
2546 if (tex->dcc_gather_statistics)
2547 tex->separate_dcc_dirty = true;
2548 }
2549 }
2550
2551 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2552 {
2553 for (int i = 0; i < state->nr_cbufs; ++i) {
2554 struct si_surface *surf = NULL;
2555 struct si_texture *tex;
2556
2557 if (!state->cbufs[i])
2558 continue;
2559 surf = (struct si_surface *)state->cbufs[i];
2560 tex = (struct si_texture *)surf->base.texture;
2561
2562 p_atomic_dec(&tex->framebuffers_bound);
2563 }
2564 }
2565
2566 static void si_set_framebuffer_state(struct pipe_context *ctx,
2567 const struct pipe_framebuffer_state *state)
2568 {
2569 struct si_context *sctx = (struct si_context *)ctx;
2570 struct si_surface *surf = NULL;
2571 struct si_texture *tex;
2572 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2573 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2574 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2575 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2576 bool old_has_stencil =
2577 old_has_zsbuf &&
2578 ((struct si_texture *)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2579 bool unbound = false;
2580 int i;
2581
2582 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2583 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2584 * We could implement the full workaround here, but it's a useless case.
2585 */
2586 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2587 unreachable("the framebuffer shouldn't have zero area");
2588 return;
2589 }
2590
2591 si_update_fb_dirtiness_after_rendering(sctx);
2592
2593 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2594 if (!sctx->framebuffer.state.cbufs[i])
2595 continue;
2596
2597 tex = (struct si_texture *)sctx->framebuffer.state.cbufs[i]->texture;
2598 if (tex->dcc_gather_statistics)
2599 vi_separate_dcc_stop_query(sctx, tex);
2600 }
2601
2602 /* Disable DCC if the formats are incompatible. */
2603 for (i = 0; i < state->nr_cbufs; i++) {
2604 if (!state->cbufs[i])
2605 continue;
2606
2607 surf = (struct si_surface *)state->cbufs[i];
2608 tex = (struct si_texture *)surf->base.texture;
2609
2610 if (!surf->dcc_incompatible)
2611 continue;
2612
2613 /* Since the DCC decompression calls back into set_framebuffer-
2614 * _state, we need to unbind the framebuffer, so that
2615 * vi_separate_dcc_stop_query isn't called twice with the same
2616 * color buffer.
2617 */
2618 if (!unbound) {
2619 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2620 unbound = true;
2621 }
2622
2623 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2624 if (!si_texture_disable_dcc(sctx, tex))
2625 si_decompress_dcc(sctx, tex);
2626
2627 surf->dcc_incompatible = false;
2628 }
2629
2630 /* Only flush TC when changing the framebuffer state, because
2631 * the only client not using TC that can change textures is
2632 * the framebuffer.
2633 *
2634 * Wait for compute shaders because of possible transitions:
2635 * - FB write -> shader read
2636 * - shader write -> FB read
2637 *
2638 * DB caches are flushed on demand (using si_decompress_textures).
2639 *
2640 * When MSAA is enabled, CB and TC caches are flushed on demand
2641 * (after FMASK decompression). Shader write -> FB read transitions
2642 * cannot happen for MSAA textures, because MSAA shader images are
2643 * not supported.
2644 *
2645 * Only flush and wait for CB if there is actually a bound color buffer.
2646 */
2647 if (sctx->framebuffer.uncompressed_cb_mask) {
2648 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2649 sctx->framebuffer.CB_has_shader_readable_metadata,
2650 sctx->framebuffer.all_DCC_pipe_aligned);
2651 }
2652
2653 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2654
2655 /* u_blitter doesn't invoke depth decompression when it does multiple
2656 * blits in a row, but the only case when it matters for DB is when
2657 * doing generate_mipmap. So here we flush DB manually between
2658 * individual generate_mipmap blits.
2659 * Note that lower mipmap levels aren't compressed.
2660 */
2661 if (sctx->generate_mipmap_for_depth) {
2662 si_make_DB_shader_coherent(sctx, 1, false, sctx->framebuffer.DB_has_shader_readable_metadata);
2663 } else if (sctx->chip_class == GFX9) {
2664 /* It appears that DB metadata "leaks" in a sequence of:
2665 * - depth clear
2666 * - DCC decompress for shader image writes (with DB disabled)
2667 * - render with DEPTH_BEFORE_SHADER=1
2668 * Flushing DB metadata works around the problem.
2669 */
2670 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2671 }
2672
2673 /* Take the maximum of the old and new count. If the new count is lower,
2674 * dirtying is needed to disable the unbound colorbuffers.
2675 */
2676 sctx->framebuffer.dirty_cbufs |=
2677 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2678 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2679
2680 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2681 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2682
2683 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2684 sctx->framebuffer.spi_shader_col_format = 0;
2685 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2686 sctx->framebuffer.spi_shader_col_format_blend = 0;
2687 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2688 sctx->framebuffer.color_is_int8 = 0;
2689 sctx->framebuffer.color_is_int10 = 0;
2690
2691 sctx->framebuffer.compressed_cb_mask = 0;
2692 sctx->framebuffer.uncompressed_cb_mask = 0;
2693 sctx->framebuffer.displayable_dcc_cb_mask = 0;
2694 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2695 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2696 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2697 sctx->framebuffer.any_dst_linear = false;
2698 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2699 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2700 sctx->framebuffer.all_DCC_pipe_aligned = true;
2701 sctx->framebuffer.min_bytes_per_pixel = 0;
2702 sctx->framebuffer.color_big_page = true;
2703 sctx->framebuffer.zs_big_page = true;
2704
2705 for (i = 0; i < state->nr_cbufs; i++) {
2706 if (!state->cbufs[i])
2707 continue;
2708
2709 surf = (struct si_surface *)state->cbufs[i];
2710 tex = (struct si_texture *)surf->base.texture;
2711
2712 if (!surf->color_initialized) {
2713 si_initialize_color_surface(sctx, surf);
2714 }
2715
2716 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2717 sctx->framebuffer.spi_shader_col_format |= surf->spi_shader_col_format << (i * 4);
2718 sctx->framebuffer.spi_shader_col_format_alpha |= surf->spi_shader_col_format_alpha << (i * 4);
2719 sctx->framebuffer.spi_shader_col_format_blend |= surf->spi_shader_col_format_blend << (i * 4);
2720 sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
2721 << (i * 4);
2722
2723 sctx->framebuffer.color_big_page &=
2724 tex->buffer.bo_alignment % (64 * 1024) == 0;
2725
2726 if (surf->color_is_int8)
2727 sctx->framebuffer.color_is_int8 |= 1 << i;
2728 if (surf->color_is_int10)
2729 sctx->framebuffer.color_is_int10 |= 1 << i;
2730
2731 if (tex->surface.fmask_offset)
2732 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2733 else
2734 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2735
2736 if (tex->surface.display_dcc_offset)
2737 sctx->framebuffer.displayable_dcc_cb_mask |= 1 << i;
2738
2739 /* Don't update nr_color_samples for non-AA buffers.
2740 * (e.g. destination of MSAA resolve)
2741 */
2742 if (tex->buffer.b.b.nr_samples >= 2 &&
2743 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2744 sctx->framebuffer.nr_color_samples =
2745 MIN2(sctx->framebuffer.nr_color_samples, tex->buffer.b.b.nr_storage_samples);
2746 sctx->framebuffer.nr_color_samples = MAX2(1, sctx->framebuffer.nr_color_samples);
2747 }
2748
2749 if (tex->surface.is_linear)
2750 sctx->framebuffer.any_dst_linear = true;
2751
2752 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2753 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2754
2755 if (sctx->chip_class >= GFX9 && !tex->surface.u.gfx9.dcc.pipe_aligned)
2756 sctx->framebuffer.all_DCC_pipe_aligned = false;
2757 }
2758
2759 si_context_add_resource_size(sctx, surf->base.texture);
2760
2761 p_atomic_inc(&tex->framebuffers_bound);
2762
2763 if (tex->dcc_gather_statistics) {
2764 /* Dirty tracking must be enabled for DCC usage analysis. */
2765 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2766 vi_separate_dcc_start_query(sctx, tex);
2767 }
2768
2769 /* Update the minimum but don't keep 0. */
2770 if (!sctx->framebuffer.min_bytes_per_pixel ||
2771 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2772 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
2773 }
2774
2775 /* For optimal DCC performance. */
2776 if (sctx->chip_class >= GFX10)
2777 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2778 else
2779 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2780
2781 struct si_texture *zstex = NULL;
2782
2783 if (state->zsbuf) {
2784 surf = (struct si_surface *)state->zsbuf;
2785 zstex = (struct si_texture *)surf->base.texture;
2786
2787 if (!surf->depth_initialized) {
2788 si_init_depth_surface(sctx, surf);
2789 }
2790
2791 sctx->framebuffer.zs_big_page = zstex->buffer.bo_alignment % (64 * 1024) == 0;
2792
2793 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
2794 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2795
2796 si_context_add_resource_size(sctx, surf->base.texture);
2797
2798 /* Update the minimum but don't keep 0. */
2799 if (!sctx->framebuffer.min_bytes_per_pixel ||
2800 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2801 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
2802 }
2803
2804 si_update_ps_colorbuf0_slot(sctx);
2805 si_update_poly_offset_state(sctx);
2806 si_update_ngg_small_prim_precision(sctx);
2807 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2808 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2809
2810 if (sctx->screen->dpbb_allowed)
2811 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2812
2813 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2814 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2815
2816 if (sctx->screen->has_out_of_order_rast &&
2817 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2818 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2819 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2820 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2821
2822 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2823 struct pipe_constant_buffer constbuf = {0};
2824
2825 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2826 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2827
2828 constbuf.buffer = sctx->sample_pos_buffer;
2829
2830 /* Set sample locations as fragment shader constants. */
2831 switch (sctx->framebuffer.nr_samples) {
2832 case 1:
2833 constbuf.buffer_offset = 0;
2834 break;
2835 case 2:
2836 constbuf.buffer_offset =
2837 (ubyte *)sctx->sample_positions.x2 - (ubyte *)sctx->sample_positions.x1;
2838 break;
2839 case 4:
2840 constbuf.buffer_offset =
2841 (ubyte *)sctx->sample_positions.x4 - (ubyte *)sctx->sample_positions.x1;
2842 break;
2843 case 8:
2844 constbuf.buffer_offset =
2845 (ubyte *)sctx->sample_positions.x8 - (ubyte *)sctx->sample_positions.x1;
2846 break;
2847 case 16:
2848 constbuf.buffer_offset =
2849 (ubyte *)sctx->sample_positions.x16 - (ubyte *)sctx->sample_positions.x1;
2850 break;
2851 default:
2852 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx->framebuffer.nr_samples);
2853 assert(0);
2854 }
2855 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2856 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2857
2858 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2859 }
2860
2861 sctx->do_update_shaders = true;
2862
2863 if (!sctx->decompression_enabled) {
2864 /* Prevent textures decompression when the framebuffer state
2865 * changes come from the decompression passes themselves.
2866 */
2867 sctx->need_check_render_feedback = true;
2868 }
2869 }
2870
2871 static void si_emit_framebuffer_state(struct si_context *sctx)
2872 {
2873 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2874 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2875 unsigned i, nr_cbufs = state->nr_cbufs;
2876 struct si_texture *tex = NULL;
2877 struct si_surface *cb = NULL;
2878 unsigned cb_color_info = 0;
2879
2880 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
2881 unsigned meta_write_policy, meta_read_policy;
2882 /* TODO: investigate whether LRU improves performance on other chips too */
2883 if (sctx->screen->info.num_render_backends <= 4) {
2884 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
2885 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
2886 } else {
2887 meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
2888 meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
2889 }
2890
2891 /* Colorbuffers. */
2892 for (i = 0; i < nr_cbufs; i++) {
2893 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2894 unsigned cb_color_attrib;
2895
2896 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2897 continue;
2898
2899 cb = (struct si_surface *)state->cbufs[i];
2900 if (!cb) {
2901 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2902 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2903 continue;
2904 }
2905
2906 tex = (struct si_texture *)cb->base.texture;
2907 radeon_add_to_buffer_list(
2908 sctx, sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE,
2909 tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER);
2910
2911 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
2912 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, tex->cmask_buffer, RADEON_USAGE_READWRITE,
2913 RADEON_PRIO_SEPARATE_META);
2914 }
2915
2916 if (tex->dcc_separate_buffer)
2917 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, tex->dcc_separate_buffer,
2918 RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
2919
2920 /* Compute mutable surface parameters. */
2921 cb_color_base = tex->buffer.gpu_address >> 8;
2922 cb_color_fmask = 0;
2923 cb_color_cmask = tex->cmask_base_address_reg;
2924 cb_dcc_base = 0;
2925 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2926 cb_color_attrib = cb->cb_color_attrib;
2927
2928 if (cb->base.u.tex.level > 0)
2929 cb_color_info &= C_028C70_FAST_CLEAR;
2930
2931 if (tex->surface.fmask_offset) {
2932 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
2933 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
2934 }
2935
2936 /* Set up DCC. */
2937 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2938 bool is_msaa_resolve_dst = state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
2939 state->cbufs[1] == &cb->base &&
2940 state->cbufs[1]->texture->nr_samples <= 1;
2941
2942 if (!is_msaa_resolve_dst)
2943 cb_color_info |= S_028C70_DCC_ENABLE(1);
2944
2945 cb_dcc_base =
2946 ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset) >>
2947 8;
2948
2949 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
2950 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
2951 cb_dcc_base |= dcc_tile_swizzle;
2952 }
2953
2954 if (sctx->chip_class >= GFX10) {
2955 unsigned cb_color_attrib3;
2956
2957 /* Set mutable surface parameters. */
2958 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2959 cb_color_base |= tex->surface.tile_swizzle;
2960 if (!tex->surface.fmask_offset)
2961 cb_color_fmask = cb_color_base;
2962 if (cb->base.u.tex.level > 0)
2963 cb_color_cmask = cb_color_base;
2964
2965 cb_color_attrib3 = cb->cb_color_attrib3 |
2966 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2967 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2968 S_028EE0_CMASK_PIPE_ALIGNED(1) |
2969 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
2970
2971 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
2972 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2973 radeon_emit(cs, 0); /* hole */
2974 radeon_emit(cs, 0); /* hole */
2975 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2976 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2977 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2978 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2979 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
2980 radeon_emit(cs, 0); /* hole */
2981 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2982 radeon_emit(cs, 0); /* hole */
2983 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2984 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2985 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2986
2987 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
2988 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
2989 cb_color_cmask >> 32);
2990 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
2991 cb_color_fmask >> 32);
2992 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
2993 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2);
2994 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
2995 } else if (sctx->chip_class == GFX9) {
2996 struct gfx9_surf_meta_flags meta = {
2997 .rb_aligned = 1,
2998 .pipe_aligned = 1,
2999 };
3000
3001 if (tex->surface.dcc_offset)
3002 meta = tex->surface.u.gfx9.dcc;
3003
3004 /* Set mutable surface parameters. */
3005 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3006 cb_color_base |= tex->surface.tile_swizzle;
3007 if (!tex->surface.fmask_offset)
3008 cb_color_fmask = cb_color_base;
3009 if (cb->base.u.tex.level > 0)
3010 cb_color_cmask = cb_color_base;
3011 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3012 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3013 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3014 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3015
3016 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3017 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3018 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3019 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3020 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3021 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3022 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3023 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3024 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3025 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3026 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3027 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3028 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3029 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3030 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3031 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3032
3033 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3034 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3035 } else {
3036 /* Compute mutable surface parameters (GFX6-GFX8). */
3037 const struct legacy_surf_level *level_info =
3038 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3039 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3040 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3041
3042 cb_color_base += level_info->offset >> 8;
3043 /* Only macrotiled modes can set tile swizzle. */
3044 if (level_info->mode == RADEON_SURF_MODE_2D)
3045 cb_color_base |= tex->surface.tile_swizzle;
3046
3047 if (!tex->surface.fmask_offset)
3048 cb_color_fmask = cb_color_base;
3049 if (cb->base.u.tex.level > 0)
3050 cb_color_cmask = cb_color_base;
3051 if (cb_dcc_base)
3052 cb_dcc_base += level_info->dcc_offset >> 8;
3053
3054 pitch_tile_max = level_info->nblk_x / 8 - 1;
3055 slice_tile_max = level_info->nblk_x * level_info->nblk_y / 64 - 1;
3056 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3057
3058 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3059 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3060 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3061
3062 if (tex->surface.fmask_offset) {
3063 if (sctx->chip_class >= GFX7)
3064 cb_color_pitch |=
3065 S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3066 cb_color_attrib |=
3067 S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3068 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3069 } else {
3070 /* This must be set for fast clear to work without FMASK. */
3071 if (sctx->chip_class >= GFX7)
3072 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3073 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3074 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3075 }
3076
3077 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3078 sctx->chip_class >= GFX8 ? 14 : 13);
3079 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3080 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3081 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3082 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3083 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3084 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3085 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3086 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3087 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3088 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3089 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3090 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3091 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3092
3093 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3094 radeon_emit(cs, cb_dcc_base);
3095 }
3096 }
3097 for (; i < 8; i++)
3098 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3099 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3100
3101 /* ZS buffer. */
3102 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3103 struct si_surface *zb = (struct si_surface *)state->zsbuf;
3104 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3105 unsigned db_z_info = zb->db_z_info;
3106 unsigned db_stencil_info = zb->db_stencil_info;
3107 unsigned db_htile_surface = zb->db_htile_surface;
3108
3109 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE,
3110 zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3111 : RADEON_PRIO_DEPTH_BUFFER);
3112
3113 /* Set fields dependent on tc_compatile_htile. */
3114 if (sctx->chip_class >= GFX9 &&
3115 vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS)) {
3116 unsigned max_zplanes = 4;
3117
3118 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM && tex->buffer.b.b.nr_samples > 1)
3119 max_zplanes = 2;
3120
3121 db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
3122
3123 if (sctx->chip_class >= GFX10) {
3124 db_z_info |= S_028040_ITERATE_FLUSH(1);
3125 db_stencil_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled);
3126 } else {
3127 db_z_info |= S_028038_ITERATE_FLUSH(1);
3128 db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3129 }
3130 }
3131
3132 if (sctx->chip_class >= GFX10) {
3133 bool zs_big_page = sctx->chip_class >= GFX10_3 &&
3134 sctx->framebuffer.zs_big_page;
3135
3136 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3137 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3138
3139 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3140 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3141 radeon_emit(cs, db_z_info | /* DB_Z_INFO */
3142 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3143 radeon_emit(cs, db_stencil_info); /* DB_STENCIL_INFO */
3144 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3145 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3146 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3147 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3148
3149 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 6);
3150 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3151 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3152 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3153 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3154 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3155 radeon_emit(cs, /* DB_RMI_L2_CACHE_CONTROL */
3156 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM) |
3157 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) |
3158 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
3159 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
3160 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) |
3161 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) |
3162 S_02807C_HTILE_RD_POLICY(meta_read_policy) |
3163 S_02807C_Z_BIG_PAGE(zs_big_page) |
3164 S_02807C_S_BIG_PAGE(zs_big_page));
3165 } else if (sctx->chip_class == GFX9) {
3166 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3167 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3168 radeon_emit(cs,
3169 S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3170 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3171
3172 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3173 radeon_emit(cs, db_z_info | /* DB_Z_INFO */
3174 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3175 radeon_emit(cs, db_stencil_info); /* DB_STENCIL_INFO */
3176 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3177 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3178 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3179 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3180 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3181 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3182 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3183 radeon_emit(cs,
3184 S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3185
3186 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3187 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3188 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3189 } else {
3190 /* GFX6-GFX8 */
3191 /* Set fields dependent on tc_compatile_htile. */
3192 if (si_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS)) {
3193 if (!tex->surface.has_stencil && !tex->tc_compatible_htile) {
3194 /* Use all of the htile_buffer for depth if there's no stencil.
3195 * This must not be set when TC-compatible HTILE is enabled
3196 * due to a hw bug.
3197 */
3198 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3199 }
3200
3201 if (tex->tc_compatible_htile) {
3202 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3203
3204 /* 0 = full compression. N = only compress up to N-1 Z planes. */
3205 if (tex->buffer.b.b.nr_samples <= 1)
3206 db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3207 else if (tex->buffer.b.b.nr_samples <= 4)
3208 db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3209 else
3210 db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3211 }
3212 }
3213
3214 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3215
3216 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3217 radeon_emit(cs, zb->db_depth_info | /* DB_DEPTH_INFO */
3218 S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile));
3219 radeon_emit(cs, db_z_info | /* DB_Z_INFO */
3220 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3221 radeon_emit(cs, db_stencil_info); /* DB_STENCIL_INFO */
3222 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3223 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3224 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3225 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3226 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3227 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3228 }
3229
3230 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3231 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3232 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3233
3234 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3235 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
3236 } else if (sctx->framebuffer.dirty_zsbuf) {
3237 if (sctx->chip_class == GFX9)
3238 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3239 else
3240 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3241
3242 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3243 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3244 }
3245
3246 /* Framebuffer dimensions. */
3247 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_cs_preamble_state */
3248 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3249 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3250
3251 if (nr_cbufs) {
3252 bool color_big_page = sctx->chip_class >= GFX10_3 &&
3253 sctx->framebuffer.color_big_page;
3254 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
3255 S_028410_CMASK_WR_POLICY(meta_write_policy) |
3256 S_028410_FMASK_WR_POLICY(meta_write_policy) |
3257 S_028410_DCC_WR_POLICY(meta_write_policy) |
3258 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM) |
3259 S_028410_CMASK_RD_POLICY(meta_read_policy) |
3260 S_028410_FMASK_RD_POLICY(meta_read_policy) |
3261 S_028410_DCC_RD_POLICY(meta_read_policy) |
3262 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA) |
3263 S_028410_FMASK_BIG_PAGE(color_big_page) |
3264 S_028410_COLOR_BIG_PAGE(color_big_page));
3265 }
3266
3267 if (sctx->screen->dfsm_allowed) {
3268 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3269 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3270 }
3271
3272 sctx->framebuffer.dirty_cbufs = 0;
3273 sctx->framebuffer.dirty_zsbuf = false;
3274 }
3275
3276 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3277 {
3278 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3279 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3280 unsigned nr_samples = sctx->framebuffer.nr_samples;
3281 bool has_msaa_sample_loc_bug = sctx->screen->info.has_msaa_sample_loc_bug;
3282
3283 /* Smoothing (only possible with nr_samples == 1) uses the same
3284 * sample locations as the MSAA it simulates.
3285 */
3286 if (nr_samples <= 1 && sctx->smoothing_enabled)
3287 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3288
3289 /* On Polaris, the small primitive filter uses the sample locations
3290 * even when MSAA is off, so we need to make sure they're set to 0.
3291 *
3292 * GFX10 uses sample locations unconditionally, so they always need
3293 * to be set up.
3294 */
3295 if ((nr_samples >= 2 || has_msaa_sample_loc_bug || sctx->chip_class >= GFX10) &&
3296 nr_samples != sctx->sample_locs_num_samples) {
3297 sctx->sample_locs_num_samples = nr_samples;
3298 si_emit_sample_locations(cs, nr_samples);
3299 }
3300
3301 if (sctx->family >= CHIP_POLARIS10) {
3302 unsigned small_prim_filter_cntl =
3303 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3304 /* line bug */
3305 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3306
3307 /* The alternative of setting sample locations to 0 would
3308 * require a DB flush to avoid Z errors, see
3309 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3310 */
3311 if (has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1 && !rs->multisample_enable)
3312 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3313
3314 radeon_opt_set_context_reg(sctx, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3315 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL, small_prim_filter_cntl);
3316 }
3317
3318 /* The exclusion bits can be set to improve rasterization efficiency
3319 * if no sample lies on the pixel boundary (-8 sample offset).
3320 */
3321 bool exclusion = sctx->chip_class >= GFX7 && (!rs->multisample_enabl