2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "util/fast_idiv_by_const.h"
29 #include "util/format/u_format.h"
30 #include "util/format/u_format_s3tc.h"
31 #include "util/u_dual_blend.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
36 #include "gfx10_format_table.h"
38 static unsigned si_map_swizzle(unsigned swizzle
)
42 return V_008F0C_SQ_SEL_Y
;
44 return V_008F0C_SQ_SEL_Z
;
46 return V_008F0C_SQ_SEL_W
;
48 return V_008F0C_SQ_SEL_0
;
50 return V_008F0C_SQ_SEL_1
;
51 default: /* PIPE_SWIZZLE_X */
52 return V_008F0C_SQ_SEL_X
;
56 /* 12.4 fixed-point */
57 static unsigned si_pack_float_12p4(float x
)
59 return x
<= 0 ? 0 : x
>= 4096 ? 0xffff : x
* 16;
63 * Inferred framebuffer and blender state.
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
68 static void si_emit_cb_render_state(struct si_context
*sctx
)
70 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
71 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
& blend
->cb_target_mask
;
77 /* Avoid a hang that happens when dual source blending is enabled
78 * but there is not enough color outputs. This is undefined behavior,
79 * so disable color writes completely.
81 * Reproducible with Unigine Heaven 4.0 and drirc missing.
83 if (blend
->dual_src_blend
&& sctx
->ps_shader
.cso
&&
84 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
87 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
88 * I think we don't have to do anything between IBs.
90 if (sctx
->screen
->dpbb_allowed
&& sctx
->last_cb_target_mask
!= cb_target_mask
) {
91 sctx
->last_cb_target_mask
= cb_target_mask
;
93 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
94 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
97 unsigned initial_cdw
= cs
->current
.cdw
;
98 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
, SI_TRACKED_CB_TARGET_MASK
,
101 if (sctx
->chip_class
>= GFX8
) {
102 /* DCC MSAA workaround.
103 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
104 * COMBINER_DISABLE, but that would be more complicated.
107 blend
->dcc_msaa_corruption_4bit
& cb_target_mask
&& sctx
->framebuffer
.nr_samples
>= 2;
108 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
110 radeon_opt_set_context_reg(
111 sctx
, R_028424_CB_DCC_CONTROL
, SI_TRACKED_CB_DCC_CONTROL
,
112 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
113 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
114 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
115 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->info
.has_dcc_constant_encode
));
118 /* RB+ register settings. */
119 if (sctx
->screen
->info
.rbplus_allowed
) {
120 unsigned spi_shader_col_format
=
121 sctx
->ps_shader
.cso
? sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
123 unsigned sx_ps_downconvert
= 0;
124 unsigned sx_blend_opt_epsilon
= 0;
125 unsigned sx_blend_opt_control
= 0;
127 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
128 struct si_surface
*surf
= (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
129 unsigned format
, swap
, spi_format
, colormask
;
130 bool has_alpha
, has_rgb
;
133 /* If the color buffer is not set, the driver sets 32_R
134 * as the SPI color format, because the hw doesn't allow
135 * holes between color outputs, so also set this to
138 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
142 format
= G_028C70_FORMAT(surf
->cb_color_info
);
143 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
144 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
145 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
147 /* Set if RGB and A are present. */
148 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
150 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_16
||
151 format
== V_028C70_COLOR_32
)
152 has_rgb
= !has_alpha
;
156 /* Check the colormask and export format. */
157 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
159 if (!(colormask
& PIPE_MASK_A
))
162 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
167 /* Disable value checking for disabled channels. */
169 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
171 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
173 /* Enable down-conversion for 32bpp and smaller formats. */
175 case V_028C70_COLOR_8
:
176 case V_028C70_COLOR_8_8
:
177 case V_028C70_COLOR_8_8_8_8
:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
180 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
181 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
182 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
183 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
187 case V_028C70_COLOR_5_6_5
:
188 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
189 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
190 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
194 case V_028C70_COLOR_1_5_5_5
:
195 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
196 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
197 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
201 case V_028C70_COLOR_4_4_4_4
:
202 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
203 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
204 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
208 case V_028C70_COLOR_32
:
209 if (swap
== V_028C70_SWAP_STD
&& spi_format
== V_028714_SPI_SHADER_32_R
)
210 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
211 else if (swap
== V_028C70_SWAP_ALT_REV
&& spi_format
== V_028714_SPI_SHADER_32_AR
)
212 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
215 case V_028C70_COLOR_16
:
216 case V_028C70_COLOR_16_16
:
217 /* For 1-channel formats, use the superset thereof. */
218 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
219 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
220 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
221 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
222 if (swap
== V_028C70_SWAP_STD
|| swap
== V_028C70_SWAP_STD_REV
)
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
225 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
229 case V_028C70_COLOR_10_11_11
:
230 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
234 case V_028C70_COLOR_2_10_10_10
:
235 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
236 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
237 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
243 /* If there are no color outputs, the first color export is
244 * always enabled as 32_R, so also set this to enable RB+.
246 if (!sx_ps_downconvert
)
247 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
249 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
250 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
, SI_TRACKED_SX_PS_DOWNCONVERT
,
251 sx_ps_downconvert
, sx_blend_opt_epsilon
, sx_blend_opt_control
);
253 if (initial_cdw
!= cs
->current
.cdw
)
254 sctx
->context_roll
= true;
261 static uint32_t si_translate_blend_function(int blend_func
)
263 switch (blend_func
) {
265 return V_028780_COMB_DST_PLUS_SRC
;
266 case PIPE_BLEND_SUBTRACT
:
267 return V_028780_COMB_SRC_MINUS_DST
;
268 case PIPE_BLEND_REVERSE_SUBTRACT
:
269 return V_028780_COMB_DST_MINUS_SRC
;
271 return V_028780_COMB_MIN_DST_SRC
;
273 return V_028780_COMB_MAX_DST_SRC
;
275 PRINT_ERR("Unknown blend function %d\n", blend_func
);
282 static uint32_t si_translate_blend_factor(int blend_fact
)
284 switch (blend_fact
) {
285 case PIPE_BLENDFACTOR_ONE
:
286 return V_028780_BLEND_ONE
;
287 case PIPE_BLENDFACTOR_SRC_COLOR
:
288 return V_028780_BLEND_SRC_COLOR
;
289 case PIPE_BLENDFACTOR_SRC_ALPHA
:
290 return V_028780_BLEND_SRC_ALPHA
;
291 case PIPE_BLENDFACTOR_DST_ALPHA
:
292 return V_028780_BLEND_DST_ALPHA
;
293 case PIPE_BLENDFACTOR_DST_COLOR
:
294 return V_028780_BLEND_DST_COLOR
;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
297 case PIPE_BLENDFACTOR_CONST_COLOR
:
298 return V_028780_BLEND_CONSTANT_COLOR
;
299 case PIPE_BLENDFACTOR_CONST_ALPHA
:
300 return V_028780_BLEND_CONSTANT_ALPHA
;
301 case PIPE_BLENDFACTOR_ZERO
:
302 return V_028780_BLEND_ZERO
;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
315 case PIPE_BLENDFACTOR_SRC1_COLOR
:
316 return V_028780_BLEND_SRC1_COLOR
;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
318 return V_028780_BLEND_SRC1_ALPHA
;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
320 return V_028780_BLEND_INV_SRC1_COLOR
;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
322 return V_028780_BLEND_INV_SRC1_ALPHA
;
324 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
331 static uint32_t si_translate_blend_opt_function(int blend_func
)
333 switch (blend_func
) {
335 return V_028760_OPT_COMB_ADD
;
336 case PIPE_BLEND_SUBTRACT
:
337 return V_028760_OPT_COMB_SUBTRACT
;
338 case PIPE_BLEND_REVERSE_SUBTRACT
:
339 return V_028760_OPT_COMB_REVSUBTRACT
;
341 return V_028760_OPT_COMB_MIN
;
343 return V_028760_OPT_COMB_MAX
;
345 return V_028760_OPT_COMB_BLEND_DISABLED
;
349 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
351 switch (blend_fact
) {
352 case PIPE_BLENDFACTOR_ZERO
:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
354 case PIPE_BLENDFACTOR_ONE
:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
356 case PIPE_BLENDFACTOR_SRC_COLOR
:
357 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
360 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
362 case PIPE_BLENDFACTOR_SRC_ALPHA
:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
367 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
374 static void si_blend_check_commutativity(struct si_screen
*sscreen
, struct si_state_blend
*blend
,
375 enum pipe_blend_func func
, enum pipe_blendfactor src
,
376 enum pipe_blendfactor dst
, unsigned chanmask
)
378 /* Src factor is allowed when it does not depend on Dst */
379 static const uint32_t src_allowed
=
380 (1u << PIPE_BLENDFACTOR_ONE
) | (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
381 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
382 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
383 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
384 (1u << PIPE_BLENDFACTOR_ZERO
) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
385 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
386 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
387 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
389 if (dst
== PIPE_BLENDFACTOR_ONE
&& (src_allowed
& (1u << src
))) {
390 /* Addition is commutative, but floating point addition isn't
391 * associative: subtle changes can be introduced via different
394 * Out-of-order is also non-deterministic, which means that
395 * this breaks OpenGL invariance requirements. So only enable
396 * out-of-order additive blending if explicitly allowed by a
399 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
400 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
401 blend
->commutative_4bit
|= chanmask
;
406 * Get rid of DST in the blend factors by commuting the operands:
407 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
409 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
, unsigned *dst_factor
,
410 unsigned expected_dst
, unsigned replacement_src
)
412 if (*src_factor
== expected_dst
&& *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
413 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
414 *dst_factor
= replacement_src
;
416 /* Commuting the operands requires reversing subtractions. */
417 if (*func
== PIPE_BLEND_SUBTRACT
)
418 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
419 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
420 *func
= PIPE_BLEND_SUBTRACT
;
424 static bool si_blend_factor_uses_dst(unsigned factor
)
426 return factor
== PIPE_BLENDFACTOR_DST_COLOR
|| factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
427 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
428 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
|| factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
431 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
432 const struct pipe_blend_state
*state
, unsigned mode
)
434 struct si_context
*sctx
= (struct si_context
*)ctx
;
435 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
436 struct si_pm4_state
*pm4
= &blend
->pm4
;
437 uint32_t sx_mrt_blend_opt
[8] = {0};
438 uint32_t color_control
= 0;
439 bool logicop_enable
= state
->logicop_enable
&& state
->logicop_func
!= PIPE_LOGICOP_COPY
;
444 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
445 blend
->alpha_to_one
= state
->alpha_to_one
;
446 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
447 blend
->logicop_enable
= logicop_enable
;
449 unsigned num_shader_outputs
= state
->max_rt
+ 1; /* estimate */
450 if (blend
->dual_src_blend
)
451 num_shader_outputs
= MAX2(num_shader_outputs
, 2);
453 if (logicop_enable
) {
454 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
456 color_control
|= S_028808_ROP3(0xcc);
459 if (state
->alpha_to_coverage
&& state
->alpha_to_coverage_dither
) {
460 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
461 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
462 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
463 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
464 S_028B70_OFFSET_ROUND(1));
466 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
467 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
468 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
469 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
470 S_028B70_OFFSET_ROUND(0));
473 if (state
->alpha_to_coverage
)
474 blend
->need_src_alpha_4bit
|= 0xf;
476 blend
->cb_target_mask
= 0;
477 blend
->cb_target_enabled_4bit
= 0;
479 for (int i
= 0; i
< num_shader_outputs
; i
++) {
480 /* state->rt entries > 0 only written if independent blending */
481 const int j
= state
->independent_blend_enable
? i
: 0;
483 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
484 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
485 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
486 unsigned eqA
= state
->rt
[j
].alpha_func
;
487 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
488 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
490 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
491 unsigned blend_cntl
= 0;
493 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
494 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
496 /* Only set dual source blending for MRT0 to avoid a hang. */
497 if (i
>= 1 && blend
->dual_src_blend
) {
498 /* Vulkan does this for dual source blending. */
500 blend_cntl
|= S_028780_ENABLE(1);
502 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
506 /* Only addition and subtraction equations are supported with
507 * dual source blending.
509 if (blend
->dual_src_blend
&& (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
510 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
511 assert(!"Unsupported equation for dual source blending");
512 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
516 /* cb_render_state will disable unused ones */
517 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
518 if (state
->rt
[j
].colormask
)
519 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
521 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
522 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
526 si_blend_check_commutativity(sctx
->screen
, blend
, eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
527 si_blend_check_commutativity(sctx
->screen
, blend
, eqA
, srcA
, dstA
, 0x8 << (4 * i
));
529 /* Blending optimizations for RB+.
530 * These transformations don't change the behavior.
532 * First, get rid of DST in the blend factors:
533 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
535 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
, PIPE_BLENDFACTOR_DST_COLOR
,
536 PIPE_BLENDFACTOR_SRC_COLOR
);
537 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_COLOR
,
538 PIPE_BLENDFACTOR_SRC_COLOR
);
539 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_ALPHA
,
540 PIPE_BLENDFACTOR_SRC_ALPHA
);
542 /* Look up the ideal settings from tables. */
543 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
544 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
545 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
546 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
548 /* Handle interdependencies. */
549 if (si_blend_factor_uses_dst(srcRGB
))
550 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
551 if (si_blend_factor_uses_dst(srcA
))
552 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
554 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
555 (dstRGB
== PIPE_BLENDFACTOR_ZERO
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
556 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
557 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
559 /* Set the final value. */
560 sx_mrt_blend_opt
[i
] = S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
561 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
562 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
563 S_028760_ALPHA_SRC_OPT(srcA_opt
) | S_028760_ALPHA_DST_OPT(dstA_opt
) |
564 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
566 /* Set blend state. */
567 blend_cntl
|= S_028780_ENABLE(1);
568 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
569 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
570 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
572 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
573 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
574 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
575 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
576 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
578 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
580 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
582 if (sctx
->chip_class
>= GFX8
&& sctx
->chip_class
<= GFX10
)
583 blend
->dcc_msaa_corruption_4bit
|= 0xfu
<< (i
* 4);
585 /* This is only important for formats without alpha. */
586 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
587 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
588 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
589 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
590 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
593 if (sctx
->chip_class
>= GFX8
&& sctx
->chip_class
<= GFX10
&& logicop_enable
)
594 blend
->dcc_msaa_corruption_4bit
|= blend
->cb_target_enabled_4bit
;
596 if (blend
->cb_target_mask
) {
597 color_control
|= S_028808_MODE(mode
);
599 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
602 if (sctx
->screen
->info
.rbplus_allowed
) {
603 /* Disable RB+ blend optimizations for dual source blending.
606 if (blend
->dual_src_blend
) {
607 for (int i
= 0; i
< num_shader_outputs
; i
++) {
608 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
609 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
613 for (int i
= 0; i
< num_shader_outputs
; i
++)
614 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4, sx_mrt_blend_opt
[i
]);
616 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
617 if (blend
->dual_src_blend
|| logicop_enable
|| mode
== V_028808_CB_RESOLVE
)
618 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
621 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
625 static void *si_create_blend_state(struct pipe_context
*ctx
, const struct pipe_blend_state
*state
)
627 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
630 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
632 struct si_context
*sctx
= (struct si_context
*)ctx
;
633 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
634 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
637 blend
= (struct si_state_blend
*)sctx
->noop_blend
;
639 si_pm4_bind_state(sctx
, blend
, blend
);
641 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
642 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
643 (old_blend
->dcc_msaa_corruption_4bit
!= blend
->dcc_msaa_corruption_4bit
&&
644 sctx
->framebuffer
.nr_samples
>= 2 && sctx
->screen
->dcc_msaa_allowed
))
645 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
647 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
648 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
649 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
650 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
651 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
652 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
653 sctx
->do_update_shaders
= true;
655 if (sctx
->screen
->dpbb_allowed
&&
656 (old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
657 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
658 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
659 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
661 if (sctx
->screen
->has_out_of_order_rast
&&
662 ((old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
663 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
664 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
665 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
666 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
669 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
671 struct si_context
*sctx
= (struct si_context
*)ctx
;
673 if (sctx
->queued
.named
.blend
== state
)
674 si_bind_blend_state(ctx
, sctx
->noop_blend
);
676 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
679 static void si_set_blend_color(struct pipe_context
*ctx
, const struct pipe_blend_color
*state
)
681 struct si_context
*sctx
= (struct si_context
*)ctx
;
682 static const struct pipe_blend_color zeros
;
684 sctx
->blend_color
.state
= *state
;
685 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
686 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
689 static void si_emit_blend_color(struct si_context
*sctx
)
691 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
693 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
694 radeon_emit_array(cs
, (uint32_t *)sctx
->blend_color
.state
.color
, 4);
701 static void si_set_clip_state(struct pipe_context
*ctx
, const struct pipe_clip_state
*state
)
703 struct si_context
*sctx
= (struct si_context
*)ctx
;
704 struct pipe_constant_buffer cb
;
705 static const struct pipe_clip_state zeros
;
707 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
710 sctx
->clip_state
.state
= *state
;
711 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
712 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
715 cb
.user_buffer
= state
->ucp
;
716 cb
.buffer_offset
= 0;
717 cb
.buffer_size
= 4 * 4 * 8;
718 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
719 pipe_resource_reference(&cb
.buffer
, NULL
);
722 static void si_emit_clip_state(struct si_context
*sctx
)
724 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
726 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6 * 4);
727 radeon_emit_array(cs
, (uint32_t *)sctx
->clip_state
.state
.ucp
, 6 * 4);
730 static void si_emit_clip_regs(struct si_context
*sctx
)
732 struct si_shader
*vs
= si_get_vs_state(sctx
);
733 struct si_shader_selector
*vs_sel
= vs
->selector
;
734 struct si_shader_info
*info
= &vs_sel
->info
;
735 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
736 unsigned window_space
= info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
737 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
738 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
739 unsigned culldist_mask
= vs_sel
->culldist_mask
;
742 if (vs
->key
.opt
.clip_disable
) {
743 assert(!info
->culldist_writemask
);
747 total_mask
= clipdist_mask
| culldist_mask
;
749 /* Clip distances on points have no effect, so need to be implemented
750 * as cull distances. This applies for the clipvertex case as well.
752 * Setting this for primitives other than points should have no adverse
755 clipdist_mask
&= rs
->clip_plane_enable
;
756 culldist_mask
|= clipdist_mask
;
758 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
759 unsigned pa_cl_cntl
= S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
760 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) | clipdist_mask
|
761 (culldist_mask
<< 8);
763 if (sctx
->chip_class
>= GFX10
) {
764 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
765 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
, pa_cl_cntl
,
766 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
768 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
, SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
,
769 vs_sel
->pa_cl_vs_out_cntl
| pa_cl_cntl
);
771 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
, SI_TRACKED_PA_CL_CLIP_CNTL
,
772 rs
->pa_cl_clip_cntl
| ucp_mask
| S_028810_CLIP_DISABLE(window_space
));
774 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
775 sctx
->context_roll
= true;
779 * inferred state between framebuffer and rasterizer
781 static void si_update_poly_offset_state(struct si_context
*sctx
)
783 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
785 if (!rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
786 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
790 /* Use the user format, not db_render_format, so that the polygon
791 * offset behaves as expected by applications.
793 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
794 case PIPE_FORMAT_Z16_UNORM
:
795 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
797 default: /* 24-bit */
798 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
800 case PIPE_FORMAT_Z32_FLOAT
:
801 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
802 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
811 static uint32_t si_translate_fill(uint32_t func
)
814 case PIPE_POLYGON_MODE_FILL
:
815 return V_028814_X_DRAW_TRIANGLES
;
816 case PIPE_POLYGON_MODE_LINE
:
817 return V_028814_X_DRAW_LINES
;
818 case PIPE_POLYGON_MODE_POINT
:
819 return V_028814_X_DRAW_POINTS
;
822 return V_028814_X_DRAW_POINTS
;
826 static void *si_create_rs_state(struct pipe_context
*ctx
, const struct pipe_rasterizer_state
*state
)
828 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
829 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
830 struct si_pm4_state
*pm4
= &rs
->pm4
;
832 float psize_min
, psize_max
;
838 if (!state
->front_ccw
) {
839 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
840 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
842 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
843 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
845 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
846 rs
->provoking_vertex_first
= state
->flatshade_first
;
847 rs
->scissor_enable
= state
->scissor
;
848 rs
->clip_halfz
= state
->clip_halfz
;
849 rs
->two_side
= state
->light_twoside
;
850 rs
->multisample_enable
= state
->multisample
;
851 rs
->force_persample_interp
= state
->force_persample_interp
;
852 rs
->clip_plane_enable
= state
->clip_plane_enable
;
853 rs
->half_pixel_center
= state
->half_pixel_center
;
854 rs
->line_stipple_enable
= state
->line_stipple_enable
;
855 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
856 rs
->line_smooth
= state
->line_smooth
;
857 rs
->line_width
= state
->line_width
;
858 rs
->poly_smooth
= state
->poly_smooth
;
859 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
860 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
861 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
862 rs
->flatshade
= state
->flatshade
;
863 rs
->flatshade_first
= state
->flatshade_first
;
864 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
865 rs
->rasterizer_discard
= state
->rasterizer_discard
;
866 rs
->polygon_mode_enabled
=
867 (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
868 (state
->fill_back
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_BACK
));
869 rs
->polygon_mode_is_lines
=
870 (state
->fill_front
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
871 (state
->fill_back
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_BACK
));
872 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
873 ? S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
874 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
)
876 rs
->pa_cl_clip_cntl
= S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
877 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
878 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
879 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
880 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
883 pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
884 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
885 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
886 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
887 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
888 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
889 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
891 /* point size 12.4 fixed point */
892 tmp
= (unsigned)(state
->point_size
* 8.0);
893 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
895 if (state
->point_size_per_vertex
) {
896 psize_min
= util_get_min_point_size(state
);
897 psize_max
= SI_MAX_POINT_SIZE
;
899 /* Force the point size to be as if the vertex output was disabled. */
900 psize_min
= state
->point_size
;
901 psize_max
= state
->point_size
;
903 rs
->max_point_size
= psize_max
;
905 /* Divide by two, because 0.5 = 1 pixel. */
906 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
907 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/ 2)) |
908 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/ 2)));
910 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
911 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/ 2)));
913 pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
914 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
915 S_028A48_MSAA_ENABLE(state
->multisample
|| state
->poly_smooth
|| state
->line_smooth
) |
916 S_028A48_VPORT_SCISSOR_ENABLE(1) |
917 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
919 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
920 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
921 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
922 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
923 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
924 S_028814_FACE(!state
->front_ccw
) |
925 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
926 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
927 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
928 S_028814_POLY_MODE(rs
->polygon_mode_enabled
) |
929 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
930 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
932 if (!rs
->uses_poly_offset
)
935 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
936 if (!rs
->pm4_poly_offset
) {
941 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
942 for (i
= 0; i
< 3; i
++) {
943 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
944 float offset_units
= state
->offset_units
;
945 float offset_scale
= state
->offset_scale
* 16.0f
;
946 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
948 if (!state
->offset_units_unscaled
) {
950 case 0: /* 16-bit zbuffer */
951 offset_units
*= 4.0f
;
952 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
954 case 1: /* 24-bit zbuffer */
955 offset_units
*= 2.0f
;
956 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
958 case 2: /* 32-bit zbuffer */
959 offset_units
*= 1.0f
;
960 pa_su_poly_offset_db_fmt_cntl
=
961 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
966 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, fui(offset_scale
));
967 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
968 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
, fui(offset_scale
));
969 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
970 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, pa_su_poly_offset_db_fmt_cntl
);
976 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
978 struct si_context
*sctx
= (struct si_context
*)ctx
;
979 struct si_state_rasterizer
*old_rs
= (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
980 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
983 rs
= (struct si_state_rasterizer
*)sctx
->discard_rasterizer_state
;
985 if (old_rs
->multisample_enable
!= rs
->multisample_enable
) {
986 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
988 /* Update the small primitive filter workaround if necessary. */
989 if (sctx
->screen
->info
.has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1)
990 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
993 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
994 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
996 si_pm4_bind_state(sctx
, rasterizer
, rs
);
997 si_update_poly_offset_state(sctx
);
999 if (old_rs
->scissor_enable
!= rs
->scissor_enable
)
1000 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1002 if (old_rs
->line_width
!= rs
->line_width
|| old_rs
->max_point_size
!= rs
->max_point_size
||
1003 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1004 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1006 if (old_rs
->clip_halfz
!= rs
->clip_halfz
)
1007 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1009 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1010 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1011 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1013 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1014 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1015 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1016 old_rs
->flatshade
!= rs
->flatshade
|| old_rs
->two_side
!= rs
->two_side
||
1017 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1018 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1019 old_rs
->poly_smooth
!= rs
->poly_smooth
|| old_rs
->line_smooth
!= rs
->line_smooth
||
1020 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1021 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1022 sctx
->do_update_shaders
= true;
1025 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1027 struct si_context
*sctx
= (struct si_context
*)ctx
;
1028 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1030 if (sctx
->queued
.named
.rasterizer
== state
)
1031 si_bind_rs_state(ctx
, sctx
->discard_rasterizer_state
);
1033 FREE(rs
->pm4_poly_offset
);
1034 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1038 * infeered state between dsa and stencil ref
1040 static void si_emit_stencil_ref(struct si_context
*sctx
)
1042 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1043 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1044 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1046 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1047 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1048 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1049 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) | S_028430_STENCILOPVAL(1));
1050 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1051 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1052 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1053 S_028434_STENCILOPVAL_BF(1));
1056 static void si_set_stencil_ref(struct pipe_context
*ctx
, const struct pipe_stencil_ref
*state
)
1058 struct si_context
*sctx
= (struct si_context
*)ctx
;
1060 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1063 sctx
->stencil_ref
.state
= *state
;
1064 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1071 static uint32_t si_translate_stencil_op(int s_op
)
1074 case PIPE_STENCIL_OP_KEEP
:
1075 return V_02842C_STENCIL_KEEP
;
1076 case PIPE_STENCIL_OP_ZERO
:
1077 return V_02842C_STENCIL_ZERO
;
1078 case PIPE_STENCIL_OP_REPLACE
:
1079 return V_02842C_STENCIL_REPLACE_TEST
;
1080 case PIPE_STENCIL_OP_INCR
:
1081 return V_02842C_STENCIL_ADD_CLAMP
;
1082 case PIPE_STENCIL_OP_DECR
:
1083 return V_02842C_STENCIL_SUB_CLAMP
;
1084 case PIPE_STENCIL_OP_INCR_WRAP
:
1085 return V_02842C_STENCIL_ADD_WRAP
;
1086 case PIPE_STENCIL_OP_DECR_WRAP
:
1087 return V_02842C_STENCIL_SUB_WRAP
;
1088 case PIPE_STENCIL_OP_INVERT
:
1089 return V_02842C_STENCIL_INVERT
;
1091 PRINT_ERR("Unknown stencil op %d", s_op
);
1098 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1100 return s
->enabled
&& s
->writemask
&&
1101 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
|| s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1102 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1105 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1107 /* REPLACE is normally order invariant, except when the stencil
1108 * reference value is written by the fragment shader. Tracking this
1109 * interaction does not seem worth the effort, so be conservative. */
1110 return op
!= PIPE_STENCIL_OP_INCR
&& op
!= PIPE_STENCIL_OP_DECR
&& op
!= PIPE_STENCIL_OP_REPLACE
;
1113 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1114 * invariant in the sense that the set of passing fragments as well as the
1115 * final stencil buffer result does not depend on the order of fragments. */
1116 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1118 return !state
->enabled
|| !state
->writemask
||
1119 /* The following assumes that Z writes are disabled. */
1120 (state
->func
== PIPE_FUNC_ALWAYS
&& si_order_invariant_stencil_op(state
->zpass_op
) &&
1121 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1122 (state
->func
== PIPE_FUNC_NEVER
&& si_order_invariant_stencil_op(state
->fail_op
));
1125 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1126 const struct pipe_depth_stencil_alpha_state
*state
)
1128 struct si_context
*sctx
= (struct si_context
*)ctx
;
1129 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1130 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1131 unsigned db_depth_control
;
1132 uint32_t db_stencil_control
= 0;
1138 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1139 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1140 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1141 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1144 S_028800_Z_ENABLE(state
->depth
.enabled
) | S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1145 S_028800_ZFUNC(state
->depth
.func
) | S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1148 if (state
->stencil
[0].enabled
) {
1149 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1150 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1151 db_stencil_control
|=
1152 S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1153 db_stencil_control
|=
1154 S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1155 db_stencil_control
|=
1156 S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1158 if (state
->stencil
[1].enabled
) {
1159 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1160 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1161 db_stencil_control
|=
1162 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1163 db_stencil_control
|=
1164 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1165 db_stencil_control
|=
1166 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1171 if (state
->alpha
.enabled
) {
1172 dsa
->alpha_func
= state
->alpha
.func
;
1174 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+ SI_SGPR_ALPHA_REF
* 4,
1175 fui(state
->alpha
.ref_value
));
1177 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1180 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1181 if (state
->stencil
[0].enabled
)
1182 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1183 if (state
->depth
.bounds_test
) {
1184 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1185 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1188 dsa
->depth_enabled
= state
->depth
.enabled
;
1189 dsa
->depth_write_enabled
= state
->depth
.enabled
&& state
->depth
.writemask
;
1190 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1191 dsa
->stencil_write_enabled
=
1192 state
->stencil
[0].enabled
&&
1193 (si_dsa_writes_stencil(&state
->stencil
[0]) || si_dsa_writes_stencil(&state
->stencil
[1]));
1194 dsa
->db_can_write
= dsa
->depth_write_enabled
|| dsa
->stencil_write_enabled
;
1196 bool zfunc_is_ordered
=
1197 state
->depth
.func
== PIPE_FUNC_NEVER
|| state
->depth
.func
== PIPE_FUNC_LESS
||
1198 state
->depth
.func
== PIPE_FUNC_LEQUAL
|| state
->depth
.func
== PIPE_FUNC_GREATER
||
1199 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1201 bool nozwrite_and_order_invariant_stencil
=
1202 !dsa
->db_can_write
||
1203 (!dsa
->depth_write_enabled
&& si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1204 si_order_invariant_stencil_state(&state
->stencil
[1]));
1206 dsa
->order_invariance
[1].zs
=
1207 nozwrite_and_order_invariant_stencil
|| (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1208 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1210 dsa
->order_invariance
[1].pass_set
=
1211 nozwrite_and_order_invariant_stencil
||
1212 (!dsa
->stencil_write_enabled
&&
1213 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
));
1214 dsa
->order_invariance
[0].pass_set
=
1215 !dsa
->depth_write_enabled
||
1216 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
);
1218 dsa
->order_invariance
[1].pass_last
= sctx
->screen
->assume_no_z_fights
&&
1219 !dsa
->stencil_write_enabled
&& dsa
->depth_write_enabled
&&
1221 dsa
->order_invariance
[0].pass_last
=
1222 sctx
->screen
->assume_no_z_fights
&& dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1227 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1229 struct si_context
*sctx
= (struct si_context
*)ctx
;
1230 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1231 struct si_state_dsa
*dsa
= state
;
1234 dsa
= (struct si_state_dsa
*)sctx
->noop_dsa
;
1236 si_pm4_bind_state(sctx
, dsa
, dsa
);
1238 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1239 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1240 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1241 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1244 if (old_dsa
->alpha_func
!= dsa
->alpha_func
)
1245 sctx
->do_update_shaders
= true;
1247 if (sctx
->screen
->dpbb_allowed
&& ((old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1248 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1249 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1250 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1252 if (sctx
->screen
->has_out_of_order_rast
&&
1253 (memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1254 sizeof(old_dsa
->order_invariance
))))
1255 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1258 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1260 struct si_context
*sctx
= (struct si_context
*)ctx
;
1262 if (sctx
->queued
.named
.dsa
== state
)
1263 si_bind_dsa_state(ctx
, sctx
->noop_dsa
);
1265 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1268 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1270 struct pipe_depth_stencil_alpha_state dsa
= {};
1272 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1275 /* DB RENDER STATE */
1277 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1279 struct si_context
*sctx
= (struct si_context
*)ctx
;
1281 /* Pipeline stat & streamout queries. */
1283 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1284 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1286 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1287 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1290 /* Occlusion queries. */
1291 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1292 sctx
->occlusion_queries_disabled
= !enable
;
1293 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1297 void si_set_occlusion_query_state(struct si_context
*sctx
, bool old_perfect_enable
)
1299 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1301 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1303 if (perfect_enable
!= old_perfect_enable
)
1304 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1307 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1309 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1311 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1312 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1314 st
->saved_ssbo_writable_mask
= 0;
1316 for (unsigned i
= 0; i
< 3; i
++) {
1317 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1318 (1u << si_get_shaderbuf_slot(i
)))
1319 st
->saved_ssbo_writable_mask
|= 1 << i
;
1323 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1325 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1327 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1328 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1330 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1331 st
->saved_ssbo_writable_mask
);
1332 for (unsigned i
= 0; i
< 3; ++i
)
1333 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1336 static void si_emit_db_render_state(struct si_context
*sctx
)
1338 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1339 unsigned db_shader_control
, db_render_control
, db_count_control
;
1340 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1342 /* DB_RENDER_CONTROL */
1343 if (sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
) {
1344 db_render_control
= S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1345 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1346 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1347 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1348 db_render_control
= S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1349 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1351 db_render_control
= S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1352 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1355 /* DB_COUNT_CONTROL (occlusion queries) */
1356 if (sctx
->num_occlusion_queries
> 0 && !sctx
->occlusion_queries_disabled
) {
1357 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1358 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1360 if (sctx
->chip_class
>= GFX7
) {
1361 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1363 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1364 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1365 S_028004_SAMPLE_RATE(log_sample_rate
) | S_028004_ZPASS_ENABLE(1) |
1366 S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
1368 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1369 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1372 /* Disable occlusion queries. */
1373 if (sctx
->chip_class
>= GFX7
) {
1374 db_count_control
= 0;
1376 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1380 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
, SI_TRACKED_DB_RENDER_CONTROL
,
1381 db_render_control
, db_count_control
);
1383 /* DB_RENDER_OVERRIDE2 */
1384 radeon_opt_set_context_reg(
1385 sctx
, R_028010_DB_RENDER_OVERRIDE2
, SI_TRACKED_DB_RENDER_OVERRIDE2
,
1386 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1387 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1388 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1390 db_shader_control
= sctx
->ps_db_shader_control
;
1392 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1393 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1394 db_shader_control
&= C_02880C_Z_ORDER
;
1395 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1398 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1399 if (!rs
->multisample_enable
)
1400 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1402 if (sctx
->screen
->info
.has_rbplus
&& !sctx
->screen
->info
.rbplus_allowed
)
1403 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1405 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
, SI_TRACKED_DB_SHADER_CONTROL
,
1408 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1409 sctx
->context_roll
= true;
1413 * format translation
1415 static uint32_t si_translate_colorformat(enum pipe_format format
)
1417 const struct util_format_description
*desc
= util_format_description(format
);
1419 return V_028C70_COLOR_INVALID
;
1421 #define HAS_SIZE(x, y, z, w) \
1422 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1423 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1425 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1426 return V_028C70_COLOR_10_11_11
;
1428 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1429 return V_028C70_COLOR_INVALID
;
1431 /* hw cannot support mixed formats (except depth/stencil, since
1432 * stencil is not written to). */
1433 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1434 return V_028C70_COLOR_INVALID
;
1436 switch (desc
->nr_channels
) {
1438 switch (desc
->channel
[0].size
) {
1440 return V_028C70_COLOR_8
;
1442 return V_028C70_COLOR_16
;
1444 return V_028C70_COLOR_32
;
1448 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1449 switch (desc
->channel
[0].size
) {
1451 return V_028C70_COLOR_8_8
;
1453 return V_028C70_COLOR_16_16
;
1455 return V_028C70_COLOR_32_32
;
1457 } else if (HAS_SIZE(8, 24, 0, 0)) {
1458 return V_028C70_COLOR_24_8
;
1459 } else if (HAS_SIZE(24, 8, 0, 0)) {
1460 return V_028C70_COLOR_8_24
;
1464 if (HAS_SIZE(5, 6, 5, 0)) {
1465 return V_028C70_COLOR_5_6_5
;
1466 } else if (HAS_SIZE(32, 8, 24, 0)) {
1467 return V_028C70_COLOR_X24_8_32_FLOAT
;
1471 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1472 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1473 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1474 switch (desc
->channel
[0].size
) {
1476 return V_028C70_COLOR_4_4_4_4
;
1478 return V_028C70_COLOR_8_8_8_8
;
1480 return V_028C70_COLOR_16_16_16_16
;
1482 return V_028C70_COLOR_32_32_32_32
;
1484 } else if (HAS_SIZE(5, 5, 5, 1)) {
1485 return V_028C70_COLOR_1_5_5_5
;
1486 } else if (HAS_SIZE(1, 5, 5, 5)) {
1487 return V_028C70_COLOR_5_5_5_1
;
1488 } else if (HAS_SIZE(10, 10, 10, 2)) {
1489 return V_028C70_COLOR_2_10_10_10
;
1493 return V_028C70_COLOR_INVALID
;
1496 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1498 if (SI_BIG_ENDIAN
) {
1499 switch (colorformat
) {
1500 /* 8-bit buffers. */
1501 case V_028C70_COLOR_8
:
1502 return V_028C70_ENDIAN_NONE
;
1504 /* 16-bit buffers. */
1505 case V_028C70_COLOR_5_6_5
:
1506 case V_028C70_COLOR_1_5_5_5
:
1507 case V_028C70_COLOR_4_4_4_4
:
1508 case V_028C70_COLOR_16
:
1509 case V_028C70_COLOR_8_8
:
1510 return V_028C70_ENDIAN_8IN16
;
1512 /* 32-bit buffers. */
1513 case V_028C70_COLOR_8_8_8_8
:
1514 case V_028C70_COLOR_2_10_10_10
:
1515 case V_028C70_COLOR_8_24
:
1516 case V_028C70_COLOR_24_8
:
1517 case V_028C70_COLOR_16_16
:
1518 return V_028C70_ENDIAN_8IN32
;
1520 /* 64-bit buffers. */
1521 case V_028C70_COLOR_16_16_16_16
:
1522 return V_028C70_ENDIAN_8IN16
;
1524 case V_028C70_COLOR_32_32
:
1525 return V_028C70_ENDIAN_8IN32
;
1527 /* 128-bit buffers. */
1528 case V_028C70_COLOR_32_32_32_32
:
1529 return V_028C70_ENDIAN_8IN32
;
1531 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1534 return V_028C70_ENDIAN_NONE
;
1538 static uint32_t si_translate_dbformat(enum pipe_format format
)
1541 case PIPE_FORMAT_Z16_UNORM
:
1542 return V_028040_Z_16
;
1543 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1544 case PIPE_FORMAT_X8Z24_UNORM
:
1545 case PIPE_FORMAT_Z24X8_UNORM
:
1546 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1547 return V_028040_Z_24
; /* deprecated on AMD GCN */
1548 case PIPE_FORMAT_Z32_FLOAT
:
1549 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1550 return V_028040_Z_32_FLOAT
;
1552 return V_028040_Z_INVALID
;
1557 * Texture translation
1560 static uint32_t si_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
1561 const struct util_format_description
*desc
,
1564 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1565 bool uniform
= true;
1568 assert(sscreen
->info
.chip_class
<= GFX9
);
1570 /* Colorspace (return non-RGB formats directly). */
1571 switch (desc
->colorspace
) {
1572 /* Depth stencil formats */
1573 case UTIL_FORMAT_COLORSPACE_ZS
:
1575 case PIPE_FORMAT_Z16_UNORM
:
1576 return V_008F14_IMG_DATA_FORMAT_16
;
1577 case PIPE_FORMAT_X24S8_UINT
:
1578 case PIPE_FORMAT_S8X24_UINT
:
1580 * Implemented as an 8_8_8_8 data format to fix texture
1581 * gathers in stencil sampling. This affects at least
1582 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1584 if (sscreen
->info
.chip_class
<= GFX8
)
1585 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1587 if (format
== PIPE_FORMAT_X24S8_UINT
)
1588 return V_008F14_IMG_DATA_FORMAT_8_24
;
1590 return V_008F14_IMG_DATA_FORMAT_24_8
;
1591 case PIPE_FORMAT_Z24X8_UNORM
:
1592 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1593 return V_008F14_IMG_DATA_FORMAT_8_24
;
1594 case PIPE_FORMAT_X8Z24_UNORM
:
1595 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1596 return V_008F14_IMG_DATA_FORMAT_24_8
;
1597 case PIPE_FORMAT_S8_UINT
:
1598 return V_008F14_IMG_DATA_FORMAT_8
;
1599 case PIPE_FORMAT_Z32_FLOAT
:
1600 return V_008F14_IMG_DATA_FORMAT_32
;
1601 case PIPE_FORMAT_X32_S8X24_UINT
:
1602 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1603 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1608 case UTIL_FORMAT_COLORSPACE_YUV
:
1609 goto out_unknown
; /* TODO */
1611 case UTIL_FORMAT_COLORSPACE_SRGB
:
1612 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1620 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1621 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1625 case PIPE_FORMAT_RGTC1_SNORM
:
1626 case PIPE_FORMAT_LATC1_SNORM
:
1627 case PIPE_FORMAT_RGTC1_UNORM
:
1628 case PIPE_FORMAT_LATC1_UNORM
:
1629 return V_008F14_IMG_DATA_FORMAT_BC4
;
1630 case PIPE_FORMAT_RGTC2_SNORM
:
1631 case PIPE_FORMAT_LATC2_SNORM
:
1632 case PIPE_FORMAT_RGTC2_UNORM
:
1633 case PIPE_FORMAT_LATC2_UNORM
:
1634 return V_008F14_IMG_DATA_FORMAT_BC5
;
1640 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1641 (sscreen
->info
.family
== CHIP_STONEY
|| sscreen
->info
.family
== CHIP_VEGA10
||
1642 sscreen
->info
.family
== CHIP_RAVEN
)) {
1644 case PIPE_FORMAT_ETC1_RGB8
:
1645 case PIPE_FORMAT_ETC2_RGB8
:
1646 case PIPE_FORMAT_ETC2_SRGB8
:
1647 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1648 case PIPE_FORMAT_ETC2_RGB8A1
:
1649 case PIPE_FORMAT_ETC2_SRGB8A1
:
1650 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1651 case PIPE_FORMAT_ETC2_RGBA8
:
1652 case PIPE_FORMAT_ETC2_SRGBA8
:
1653 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1654 case PIPE_FORMAT_ETC2_R11_UNORM
:
1655 case PIPE_FORMAT_ETC2_R11_SNORM
:
1656 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1657 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1658 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1659 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1665 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1666 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1670 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1671 case PIPE_FORMAT_BPTC_SRGBA
:
1672 return V_008F14_IMG_DATA_FORMAT_BC7
;
1673 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1674 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1675 return V_008F14_IMG_DATA_FORMAT_BC6
;
1681 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1683 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1684 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1685 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1686 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1687 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1688 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1694 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1695 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1699 case PIPE_FORMAT_DXT1_RGB
:
1700 case PIPE_FORMAT_DXT1_RGBA
:
1701 case PIPE_FORMAT_DXT1_SRGB
:
1702 case PIPE_FORMAT_DXT1_SRGBA
:
1703 return V_008F14_IMG_DATA_FORMAT_BC1
;
1704 case PIPE_FORMAT_DXT3_RGBA
:
1705 case PIPE_FORMAT_DXT3_SRGBA
:
1706 return V_008F14_IMG_DATA_FORMAT_BC2
;
1707 case PIPE_FORMAT_DXT5_RGBA
:
1708 case PIPE_FORMAT_DXT5_SRGBA
:
1709 return V_008F14_IMG_DATA_FORMAT_BC3
;
1715 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1716 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1717 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1718 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1721 /* R8G8Bx_SNORM - TODO CxV8U8 */
1723 /* hw cannot support mixed formats (except depth/stencil, since only
1725 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1728 /* See whether the components are of the same size. */
1729 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1730 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1733 /* Non-uniform formats. */
1735 switch (desc
->nr_channels
) {
1737 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 6 &&
1738 desc
->channel
[2].size
== 5) {
1739 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1743 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 5 &&
1744 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 1) {
1745 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1747 if (desc
->channel
[0].size
== 1 && desc
->channel
[1].size
== 5 &&
1748 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 5) {
1749 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1751 if (desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1752 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2) {
1753 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1760 if (first_non_void
< 0 || first_non_void
> 3)
1763 /* uniform formats */
1764 switch (desc
->channel
[first_non_void
].size
) {
1766 switch (desc
->nr_channels
) {
1767 #if 0 /* Not supported for render targets */
1769 return V_008F14_IMG_DATA_FORMAT_4_4
;
1772 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1776 switch (desc
->nr_channels
) {
1778 return V_008F14_IMG_DATA_FORMAT_8
;
1780 return V_008F14_IMG_DATA_FORMAT_8_8
;
1782 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1786 switch (desc
->nr_channels
) {
1788 return V_008F14_IMG_DATA_FORMAT_16
;
1790 return V_008F14_IMG_DATA_FORMAT_16_16
;
1792 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1796 switch (desc
->nr_channels
) {
1798 return V_008F14_IMG_DATA_FORMAT_32
;
1800 return V_008F14_IMG_DATA_FORMAT_32_32
;
1801 #if 0 /* Not supported for render targets */
1803 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1806 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1814 static unsigned si_tex_wrap(unsigned wrap
)
1818 case PIPE_TEX_WRAP_REPEAT
:
1819 return V_008F30_SQ_TEX_WRAP
;
1820 case PIPE_TEX_WRAP_CLAMP
:
1821 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1822 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1823 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1824 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1825 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1826 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1827 return V_008F30_SQ_TEX_MIRROR
;
1828 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1829 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1830 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1831 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1832 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1833 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1837 static unsigned si_tex_mipfilter(unsigned filter
)
1840 case PIPE_TEX_MIPFILTER_NEAREST
:
1841 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1842 case PIPE_TEX_MIPFILTER_LINEAR
:
1843 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1845 case PIPE_TEX_MIPFILTER_NONE
:
1846 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1850 static unsigned si_tex_compare(unsigned compare
)
1854 case PIPE_FUNC_NEVER
:
1855 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1856 case PIPE_FUNC_LESS
:
1857 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1858 case PIPE_FUNC_EQUAL
:
1859 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1860 case PIPE_FUNC_LEQUAL
:
1861 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1862 case PIPE_FUNC_GREATER
:
1863 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1864 case PIPE_FUNC_NOTEQUAL
:
1865 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1866 case PIPE_FUNC_GEQUAL
:
1867 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1868 case PIPE_FUNC_ALWAYS
:
1869 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1873 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
, unsigned view_target
,
1874 unsigned nr_samples
)
1876 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1878 if (view_target
== PIPE_TEXTURE_CUBE
|| view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1879 res_target
= view_target
;
1880 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1881 else if (res_target
== PIPE_TEXTURE_CUBE
|| res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1882 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1884 /* GFX9 allocates 1D textures as 2D. */
1885 if ((res_target
== PIPE_TEXTURE_1D
|| res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1886 sscreen
->info
.chip_class
== GFX9
&&
1887 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1888 if (res_target
== PIPE_TEXTURE_1D
)
1889 res_target
= PIPE_TEXTURE_2D
;
1891 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1894 switch (res_target
) {
1896 case PIPE_TEXTURE_1D
:
1897 return V_008F1C_SQ_RSRC_IMG_1D
;
1898 case PIPE_TEXTURE_1D_ARRAY
:
1899 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1900 case PIPE_TEXTURE_2D
:
1901 case PIPE_TEXTURE_RECT
:
1902 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
: V_008F1C_SQ_RSRC_IMG_2D
;
1903 case PIPE_TEXTURE_2D_ARRAY
:
1904 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1905 case PIPE_TEXTURE_3D
:
1906 return V_008F1C_SQ_RSRC_IMG_3D
;
1907 case PIPE_TEXTURE_CUBE
:
1908 case PIPE_TEXTURE_CUBE_ARRAY
:
1909 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1914 * Format support testing
1917 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1919 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1921 if (sscreen
->info
.chip_class
>= GFX10
) {
1922 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
1923 if (!fmt
->img_format
|| fmt
->buffers_only
)
1928 const struct util_format_description
*desc
= util_format_description(format
);
1932 return si_translate_texformat(screen
, format
, desc
,
1933 util_format_get_first_non_void_channel(format
)) != ~0U;
1936 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1937 const struct util_format_description
*desc
,
1942 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
1944 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1945 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1947 assert(first_non_void
>= 0);
1949 if (desc
->nr_channels
== 4 && desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1950 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2)
1951 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1953 /* See whether the components are of the same size. */
1954 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1955 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1956 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1959 switch (desc
->channel
[first_non_void
].size
) {
1961 switch (desc
->nr_channels
) {
1963 case 3: /* 3 loads */
1964 return V_008F0C_BUF_DATA_FORMAT_8
;
1966 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1968 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1972 switch (desc
->nr_channels
) {
1974 case 3: /* 3 loads */
1975 return V_008F0C_BUF_DATA_FORMAT_16
;
1977 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1979 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1983 switch (desc
->nr_channels
) {
1985 return V_008F0C_BUF_DATA_FORMAT_32
;
1987 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1989 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1991 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1995 /* Legacy double formats. */
1996 switch (desc
->nr_channels
) {
1997 case 1: /* 1 load */
1998 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1999 case 2: /* 1 load */
2000 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2001 case 3: /* 3 loads */
2002 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2003 case 4: /* 2 loads */
2004 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2009 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2012 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2013 const struct util_format_description
*desc
,
2016 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2018 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2019 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2021 assert(first_non_void
>= 0);
2023 switch (desc
->channel
[first_non_void
].type
) {
2024 case UTIL_FORMAT_TYPE_SIGNED
:
2025 case UTIL_FORMAT_TYPE_FIXED
:
2026 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2027 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2028 else if (desc
->channel
[first_non_void
].normalized
)
2029 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2031 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2033 case UTIL_FORMAT_TYPE_UNSIGNED
:
2034 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2035 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2036 else if (desc
->channel
[first_non_void
].normalized
)
2037 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2039 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2041 case UTIL_FORMAT_TYPE_FLOAT
:
2043 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2047 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2050 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2051 const struct util_format_description
*desc
;
2053 unsigned data_format
;
2055 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_VERTEX_BUFFER
)) ==
2058 desc
= util_format_description(format
);
2062 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2063 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2064 * for read-only access (with caveats surrounding bounds checks), but
2065 * obviously fails for write access which we have to implement for
2066 * shader images. Luckily, OpenGL doesn't expect this to be supported
2067 * anyway, and so the only impact is on PBO uploads / downloads, which
2068 * shouldn't be expected to be fast for GL_RGB anyway.
2070 if (desc
->block
.bits
== 3 * 8 || desc
->block
.bits
== 3 * 16) {
2071 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2072 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2078 if (sscreen
->info
.chip_class
>= GFX10
) {
2079 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2080 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2085 first_non_void
= util_format_get_first_non_void_channel(format
);
2086 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2087 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2093 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2095 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2096 si_translate_colorswap(format
, false) != ~0U;
2099 static bool si_is_zs_format_supported(enum pipe_format format
)
2101 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2104 static bool si_is_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2105 enum pipe_texture_target target
, unsigned sample_count
,
2106 unsigned storage_sample_count
, unsigned usage
)
2108 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2109 unsigned retval
= 0;
2111 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2112 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2116 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2119 if (sample_count
> 1) {
2120 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2123 /* Only power-of-two sample counts are supported. */
2124 if (!util_is_power_of_two_or_zero(sample_count
) ||
2125 !util_is_power_of_two_or_zero(storage_sample_count
))
2128 /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
2129 * so don't expose 16 samples there.
2131 const unsigned max_eqaa_samples
= sscreen
->info
.num_render_backends
== 1 ? 8 : 16;
2132 const unsigned max_samples
= 8;
2134 /* MSAA support without framebuffer attachments. */
2135 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= max_eqaa_samples
)
2138 if (!sscreen
->info
.has_eqaa_surface_allocator
|| util_format_is_depth_or_stencil(format
)) {
2139 /* Color without EQAA or depth/stencil. */
2140 if (sample_count
> max_samples
|| sample_count
!= storage_sample_count
)
2143 /* Color with EQAA. */
2144 if (sample_count
> max_eqaa_samples
|| storage_sample_count
> max_samples
)
2149 if (usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
)) {
2150 if (target
== PIPE_BUFFER
) {
2151 retval
|= si_is_vertex_format_supported(
2152 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
));
2154 if (si_is_sampler_format_supported(screen
, format
))
2155 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
);
2159 if ((usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2160 PIPE_BIND_SHARED
| PIPE_BIND_BLENDABLE
)) &&
2161 si_is_colorbuffer_format_supported(format
)) {
2162 retval
|= usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2164 if (!util_format_is_pure_integer(format
) && !util_format_is_depth_or_stencil(format
))
2165 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2168 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) && si_is_zs_format_supported(format
)) {
2169 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2172 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2173 retval
|= si_is_vertex_format_supported(screen
, format
, PIPE_BIND_VERTEX_BUFFER
);
2176 if ((usage
& PIPE_BIND_LINEAR
) && !util_format_is_compressed(format
) &&
2177 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2178 retval
|= PIPE_BIND_LINEAR
;
2180 return retval
== usage
;
2184 * framebuffer handling
2187 static void si_choose_spi_color_formats(struct si_surface
*surf
, unsigned format
, unsigned swap
,
2188 unsigned ntype
, bool is_depth
)
2190 /* Alpha is needed for alpha-to-coverage.
2191 * Blending may be with or without alpha.
2193 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2194 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2195 unsigned blend
= 0; /* supports blending, but may not export alpha */
2196 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2198 /* Choose the SPI color formats. These are required values for RB+.
2199 * Other chips have multiple choices, though they are not necessarily better.
2202 case V_028C70_COLOR_5_6_5
:
2203 case V_028C70_COLOR_1_5_5_5
:
2204 case V_028C70_COLOR_5_5_5_1
:
2205 case V_028C70_COLOR_4_4_4_4
:
2206 case V_028C70_COLOR_10_11_11
:
2207 case V_028C70_COLOR_11_11_10
:
2208 case V_028C70_COLOR_8
:
2209 case V_028C70_COLOR_8_8
:
2210 case V_028C70_COLOR_8_8_8_8
:
2211 case V_028C70_COLOR_10_10_10_2
:
2212 case V_028C70_COLOR_2_10_10_10
:
2213 if (ntype
== V_028C70_NUMBER_UINT
)
2214 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2215 else if (ntype
== V_028C70_NUMBER_SINT
)
2216 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2218 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2221 case V_028C70_COLOR_16
:
2222 case V_028C70_COLOR_16_16
:
2223 case V_028C70_COLOR_16_16_16_16
:
2224 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) {
2225 /* UNORM16 and SNORM16 don't support blending */
2226 if (ntype
== V_028C70_NUMBER_UNORM
)
2227 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2229 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2231 /* Use 32 bits per channel for blending. */
2232 if (format
== V_028C70_COLOR_16
) {
2233 if (swap
== V_028C70_SWAP_STD
) { /* R */
2234 blend
= V_028714_SPI_SHADER_32_R
;
2235 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2236 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2237 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2240 } else if (format
== V_028C70_COLOR_16_16
) {
2241 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2242 blend
= V_028714_SPI_SHADER_32_GR
;
2243 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2244 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2245 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2248 } else /* 16_16_16_16 */
2249 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2250 } else if (ntype
== V_028C70_NUMBER_UINT
)
2251 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2252 else if (ntype
== V_028C70_NUMBER_SINT
)
2253 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2254 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2255 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2260 case V_028C70_COLOR_32
:
2261 if (swap
== V_028C70_SWAP_STD
) { /* R */
2262 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2263 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2264 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2265 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2270 case V_028C70_COLOR_32_32
:
2271 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2272 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2273 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2274 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2275 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2280 case V_028C70_COLOR_32_32_32_32
:
2281 case V_028C70_COLOR_8_24
:
2282 case V_028C70_COLOR_24_8
:
2283 case V_028C70_COLOR_X24_8_32_FLOAT
:
2284 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2292 /* The DB->CB copy needs 32_ABGR. */
2294 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2296 surf
->spi_shader_col_format
= normal
;
2297 surf
->spi_shader_col_format_alpha
= alpha
;
2298 surf
->spi_shader_col_format_blend
= blend
;
2299 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2302 static void si_initialize_color_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2304 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2305 unsigned color_info
, color_attrib
;
2306 unsigned format
, swap
, ntype
, endian
;
2307 const struct util_format_description
*desc
;
2309 unsigned blend_clamp
= 0, blend_bypass
= 0;
2311 desc
= util_format_description(surf
->base
.format
);
2312 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2313 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2317 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2318 ntype
= V_028C70_NUMBER_FLOAT
;
2320 ntype
= V_028C70_NUMBER_UNORM
;
2321 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2322 ntype
= V_028C70_NUMBER_SRGB
;
2323 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2324 if (desc
->channel
[firstchan
].pure_integer
) {
2325 ntype
= V_028C70_NUMBER_SINT
;
2327 assert(desc
->channel
[firstchan
].normalized
);
2328 ntype
= V_028C70_NUMBER_SNORM
;
2330 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2331 if (desc
->channel
[firstchan
].pure_integer
) {
2332 ntype
= V_028C70_NUMBER_UINT
;
2334 assert(desc
->channel
[firstchan
].normalized
);
2335 ntype
= V_028C70_NUMBER_UNORM
;
2340 format
= si_translate_colorformat(surf
->base
.format
);
2341 if (format
== V_028C70_COLOR_INVALID
) {
2342 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2344 assert(format
!= V_028C70_COLOR_INVALID
);
2345 swap
= si_translate_colorswap(surf
->base
.format
, false);
2346 endian
= si_colorformat_endian_swap(format
);
2348 /* blend clamp should be set for all NORM/SRGB types */
2349 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
2350 ntype
== V_028C70_NUMBER_SRGB
)
2353 /* set blend bypass according to docs if SINT/UINT or
2354 8/24 COLOR variants */
2355 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2356 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2357 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2362 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2363 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_8_8
||
2364 format
== V_028C70_COLOR_8_8_8_8
)
2365 surf
->color_is_int8
= true;
2366 else if (format
== V_028C70_COLOR_10_10_10_2
|| format
== V_028C70_COLOR_2_10_10_10
)
2367 surf
->color_is_int10
= true;
2371 S_028C70_FORMAT(format
) | S_028C70_COMP_SWAP(swap
) | S_028C70_BLEND_CLAMP(blend_clamp
) |
2372 S_028C70_BLEND_BYPASS(blend_bypass
) | S_028C70_SIMPLE_FLOAT(1) |
2373 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&& ntype
!= V_028C70_NUMBER_SNORM
&&
2374 ntype
!= V_028C70_NUMBER_SRGB
&& format
!= V_028C70_COLOR_8_24
&&
2375 format
!= V_028C70_COLOR_24_8
) |
2376 S_028C70_NUMBER_TYPE(ntype
) | S_028C70_ENDIAN(endian
);
2378 /* Intensity is implemented as Red, so treat it that way. */
2379 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2380 util_format_is_intensity(surf
->base
.format
));
2382 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2383 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2384 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2386 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) | S_028C74_NUM_FRAGMENTS(log_fragments
);
2388 if (tex
->surface
.fmask_offset
) {
2389 color_info
|= S_028C70_COMPRESSION(1);
2390 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2392 if (sctx
->chip_class
== GFX6
) {
2393 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2394 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2399 if (sctx
->chip_class
>= GFX10
) {
2400 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2402 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2403 64 for APU because all of our APUs to date use DIMMs which have
2404 a request granularity size of 64B while all other chips have a
2406 if (!sctx
->screen
->info
.has_dedicated_vram
)
2407 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2409 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2410 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
) |
2411 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2412 S_028C78_INDEPENDENT_64B_BLOCKS(tex
->surface
.u
.gfx9
.dcc
.independent_64B_blocks
) |
2413 S_028C78_INDEPENDENT_128B_BLOCKS(tex
->surface
.u
.gfx9
.dcc
.independent_128B_blocks
);
2414 } else if (sctx
->chip_class
>= GFX8
) {
2415 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2416 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2418 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2419 64 for APU because all of our APUs to date use DIMMs which have
2420 a request granularity size of 64B while all other chips have a
2422 if (!sctx
->screen
->info
.has_dedicated_vram
)
2423 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2425 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2426 if (tex
->surface
.bpe
== 1)
2427 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2428 else if (tex
->surface
.bpe
== 2)
2429 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2432 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2433 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2434 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2437 /* This must be set for fast clear to work without FMASK. */
2438 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2439 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2440 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2443 /* GFX10 field has the same base shift as the GFX6 field */
2444 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2445 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2446 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2448 if (sctx
->chip_class
>= GFX10
) {
2449 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2451 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2452 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2453 S_028EE0_RESOURCE_LEVEL(1);
2454 } else if (sctx
->chip_class
== GFX9
) {
2455 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2456 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2457 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2460 if (sctx
->chip_class
>= GFX9
) {
2461 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2462 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2463 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2466 surf
->cb_color_view
= color_view
;
2467 surf
->cb_color_info
= color_info
;
2468 surf
->cb_color_attrib
= color_attrib
;
2470 /* Determine pixel shader export format */
2471 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2473 surf
->color_initialized
= true;
2476 static void si_init_depth_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2478 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2479 unsigned level
= surf
->base
.u
.tex
.level
;
2480 unsigned format
, stencil_format
;
2481 uint32_t z_info
, s_info
;
2483 format
= si_translate_dbformat(tex
->db_render_format
);
2484 stencil_format
= tex
->surface
.has_stencil
? V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2486 assert(format
!= V_028040_Z_INVALID
);
2487 if (format
== V_028040_Z_INVALID
)
2488 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2490 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2491 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2492 surf
->db_htile_data_base
= 0;
2493 surf
->db_htile_surface
= 0;
2495 if (sctx
->chip_class
>= GFX10
) {
2496 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2497 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2500 if (sctx
->chip_class
>= GFX9
) {
2501 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2502 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2503 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2504 z_info
= S_028038_FORMAT(format
) |
2505 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2506 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2507 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2508 s_info
= S_02803C_FORMAT(stencil_format
) |
2509 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2511 if (sctx
->chip_class
== GFX9
) {
2512 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2513 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2515 surf
->db_depth_view
|= S_028008_MIPID(level
);
2516 surf
->db_depth_size
=
2517 S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) | S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2519 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2520 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) | S_028038_ALLOW_EXPCLEAR(1);
2522 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2523 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2524 * See that for explanation.
2526 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2528 /* Use all HTILE for depth if there's no stencil. */
2529 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2532 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2533 surf
->db_htile_surface
=
2534 S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
2535 if (sctx
->chip_class
== GFX9
) {
2536 surf
->db_htile_surface
|= S_028ABC_RB_ALIGNED(1);
2541 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2543 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2545 surf
->db_depth_base
=
2546 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2547 surf
->db_stencil_base
=
2548 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2551 S_028040_FORMAT(format
) | S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2552 s_info
= S_028044_FORMAT(stencil_format
);
2553 surf
->db_depth_info
= 0;
2555 if (sctx
->chip_class
>= GFX7
) {
2556 struct radeon_info
*info
= &sctx
->screen
->info
;
2557 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2558 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2559 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2560 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2561 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2562 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2564 surf
->db_depth_info
|= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2565 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2566 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2567 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2568 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2569 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2570 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2571 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2573 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2574 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2575 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2576 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2579 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2580 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2581 surf
->db_depth_slice
=
2582 S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
* levelinfo
->nblk_y
) / 64 - 1);
2584 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2585 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1);
2587 if (tex
->surface
.has_stencil
) {
2588 /* Workaround: For a not yet understood reason, the
2589 * combination of MSAA, fast stencil clear and stencil
2590 * decompress messes with subsequent stencil buffer
2591 * uses. Problem was reproduced on Verde, Bonaire,
2592 * Tonga, and Carrizo.
2594 * Disabling EXPCLEAR works around the problem.
2596 * Check piglit's arb_texture_multisample-stencil-clear
2597 * test if you want to try changing this.
2599 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2600 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2603 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2604 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2608 surf
->db_z_info
= z_info
;
2609 surf
->db_stencil_info
= s_info
;
2611 surf
->depth_initialized
= true;
2614 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2616 if (sctx
->decompression_enabled
)
2619 if (sctx
->framebuffer
.state
.zsbuf
) {
2620 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2621 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2623 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2625 if (tex
->surface
.has_stencil
)
2626 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2629 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2630 while (compressed_cb_mask
) {
2631 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2632 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2633 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2635 if (tex
->surface
.fmask_offset
) {
2636 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2637 tex
->fmask_is_identity
= false;
2639 if (tex
->dcc_gather_statistics
)
2640 tex
->separate_dcc_dirty
= true;
2644 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2646 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2647 struct si_surface
*surf
= NULL
;
2648 struct si_texture
*tex
;
2650 if (!state
->cbufs
[i
])
2652 surf
= (struct si_surface
*)state
->cbufs
[i
];
2653 tex
= (struct si_texture
*)surf
->base
.texture
;
2655 p_atomic_dec(&tex
->framebuffers_bound
);
2659 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2660 const struct pipe_framebuffer_state
*state
)
2662 struct si_context
*sctx
= (struct si_context
*)ctx
;
2663 struct si_surface
*surf
= NULL
;
2664 struct si_texture
*tex
;
2665 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2666 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2667 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2668 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2669 bool old_has_stencil
=
2671 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2672 bool unbound
= false;
2675 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2676 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2677 * We could implement the full workaround here, but it's a useless case.
2679 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2680 unreachable("the framebuffer shouldn't have zero area");
2684 si_update_fb_dirtiness_after_rendering(sctx
);
2686 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2687 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2690 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2691 if (tex
->dcc_gather_statistics
)
2692 vi_separate_dcc_stop_query(sctx
, tex
);
2695 /* Disable DCC if the formats are incompatible. */
2696 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2697 if (!state
->cbufs
[i
])
2700 surf
= (struct si_surface
*)state
->cbufs
[i
];
2701 tex
= (struct si_texture
*)surf
->base
.texture
;
2703 if (!surf
->dcc_incompatible
)
2706 /* Since the DCC decompression calls back into set_framebuffer-
2707 * _state, we need to unbind the framebuffer, so that
2708 * vi_separate_dcc_stop_query isn't called twice with the same
2712 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2716 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2717 if (!si_texture_disable_dcc(sctx
, tex
))
2718 si_decompress_dcc(sctx
, tex
);
2720 surf
->dcc_incompatible
= false;
2723 /* Only flush TC when changing the framebuffer state, because
2724 * the only client not using TC that can change textures is
2727 * Wait for compute shaders because of possible transitions:
2728 * - FB write -> shader read
2729 * - shader write -> FB read
2731 * DB caches are flushed on demand (using si_decompress_textures).
2733 * When MSAA is enabled, CB and TC caches are flushed on demand
2734 * (after FMASK decompression). Shader write -> FB read transitions
2735 * cannot happen for MSAA textures, because MSAA shader images are
2738 * Only flush and wait for CB if there is actually a bound color buffer.
2740 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2741 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2742 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2743 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2746 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2748 /* u_blitter doesn't invoke depth decompression when it does multiple
2749 * blits in a row, but the only case when it matters for DB is when
2750 * doing generate_mipmap. So here we flush DB manually between
2751 * individual generate_mipmap blits.
2752 * Note that lower mipmap levels aren't compressed.
2754 if (sctx
->generate_mipmap_for_depth
) {
2755 si_make_DB_shader_coherent(sctx
, 1, false, sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2756 } else if (sctx
->chip_class
== GFX9
) {
2757 /* It appears that DB metadata "leaks" in a sequence of:
2759 * - DCC decompress for shader image writes (with DB disabled)
2760 * - render with DEPTH_BEFORE_SHADER=1
2761 * Flushing DB metadata works around the problem.
2763 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2766 /* Take the maximum of the old and new count. If the new count is lower,
2767 * dirtying is needed to disable the unbound colorbuffers.
2769 sctx
->framebuffer
.dirty_cbufs
|=
2770 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2771 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2773 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2774 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2776 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2777 sctx
->framebuffer
.spi_shader_col_format
= 0;
2778 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2779 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2780 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2781 sctx
->framebuffer
.color_is_int8
= 0;
2782 sctx
->framebuffer
.color_is_int10
= 0;
2784 sctx
->framebuffer
.compressed_cb_mask
= 0;
2785 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2786 sctx
->framebuffer
.displayable_dcc_cb_mask
= 0;
2787 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2788 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2789 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2790 sctx
->framebuffer
.any_dst_linear
= false;
2791 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2792 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2793 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2794 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2796 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2797 if (!state
->cbufs
[i
])
2800 surf
= (struct si_surface
*)state
->cbufs
[i
];
2801 tex
= (struct si_texture
*)surf
->base
.texture
;
2803 if (!surf
->color_initialized
) {
2804 si_initialize_color_surface(sctx
, surf
);
2807 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2808 sctx
->framebuffer
.spi_shader_col_format
|= surf
->spi_shader_col_format
<< (i
* 4);
2809 sctx
->framebuffer
.spi_shader_col_format_alpha
|= surf
->spi_shader_col_format_alpha
<< (i
* 4);
2810 sctx
->framebuffer
.spi_shader_col_format_blend
|= surf
->spi_shader_col_format_blend
<< (i
* 4);
2811 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|= surf
->spi_shader_col_format_blend_alpha
2814 if (surf
->color_is_int8
)
2815 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2816 if (surf
->color_is_int10
)
2817 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2819 if (tex
->surface
.fmask_offset
)
2820 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2822 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2824 if (tex
->surface
.display_dcc_offset
)
2825 sctx
->framebuffer
.displayable_dcc_cb_mask
|= 1 << i
;
2827 /* Don't update nr_color_samples for non-AA buffers.
2828 * (e.g. destination of MSAA resolve)
2830 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2831 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2832 sctx
->framebuffer
.nr_color_samples
=
2833 MIN2(sctx
->framebuffer
.nr_color_samples
, tex
->buffer
.b
.b
.nr_storage_samples
);
2834 sctx
->framebuffer
.nr_color_samples
= MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2837 if (tex
->surface
.is_linear
)
2838 sctx
->framebuffer
.any_dst_linear
= true;
2840 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
2841 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2843 if (sctx
->chip_class
>= GFX9
&& !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
2844 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
2847 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2849 p_atomic_inc(&tex
->framebuffers_bound
);
2851 if (tex
->dcc_gather_statistics
) {
2852 /* Dirty tracking must be enabled for DCC usage analysis. */
2853 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2854 vi_separate_dcc_start_query(sctx
, tex
);
2857 /* Update the minimum but don't keep 0. */
2858 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2859 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2860 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
2863 /* For optimal DCC performance. */
2864 if (sctx
->chip_class
>= GFX10
)
2865 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
2867 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
2869 struct si_texture
*zstex
= NULL
;
2872 surf
= (struct si_surface
*)state
->zsbuf
;
2873 zstex
= (struct si_texture
*)surf
->base
.texture
;
2875 if (!surf
->depth_initialized
) {
2876 si_init_depth_surface(sctx
, surf
);
2879 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
, PIPE_MASK_ZS
))
2880 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2882 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2884 /* Update the minimum but don't keep 0. */
2885 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2886 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2887 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
2890 si_update_ps_colorbuf0_slot(sctx
);
2891 si_update_poly_offset_state(sctx
);
2892 si_update_ngg_small_prim_precision(sctx
);
2893 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2894 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2896 if (sctx
->screen
->dpbb_allowed
)
2897 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2899 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2900 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2902 if (sctx
->screen
->has_out_of_order_rast
&&
2903 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2904 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2905 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2906 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2908 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2909 struct pipe_constant_buffer constbuf
= {0};
2911 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2912 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2914 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2916 /* Set sample locations as fragment shader constants. */
2917 switch (sctx
->framebuffer
.nr_samples
) {
2919 constbuf
.buffer_offset
= 0;
2922 constbuf
.buffer_offset
=
2923 (ubyte
*)sctx
->sample_positions
.x2
- (ubyte
*)sctx
->sample_positions
.x1
;
2926 constbuf
.buffer_offset
=
2927 (ubyte
*)sctx
->sample_positions
.x4
- (ubyte
*)sctx
->sample_positions
.x1
;
2930 constbuf
.buffer_offset
=
2931 (ubyte
*)sctx
->sample_positions
.x8
- (ubyte
*)sctx
->sample_positions
.x1
;
2934 constbuf
.buffer_offset
=
2935 (ubyte
*)sctx
->sample_positions
.x16
- (ubyte
*)sctx
->sample_positions
.x1
;
2938 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx
->framebuffer
.nr_samples
);
2941 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2942 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2944 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
2947 sctx
->do_update_shaders
= true;
2949 if (!sctx
->decompression_enabled
) {
2950 /* Prevent textures decompression when the framebuffer state
2951 * changes come from the decompression passes themselves.
2953 sctx
->need_check_render_feedback
= true;
2957 static void si_emit_framebuffer_state(struct si_context
*sctx
)
2959 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2960 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2961 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2962 struct si_texture
*tex
= NULL
;
2963 struct si_surface
*cb
= NULL
;
2964 unsigned cb_color_info
= 0;
2967 for (i
= 0; i
< nr_cbufs
; i
++) {
2968 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
2969 unsigned cb_color_attrib
;
2971 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2974 cb
= (struct si_surface
*)state
->cbufs
[i
];
2976 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2977 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2981 tex
= (struct si_texture
*)cb
->base
.texture
;
2982 radeon_add_to_buffer_list(
2983 sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
2984 tex
->buffer
.b
.b
.nr_samples
> 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA
: RADEON_PRIO_COLOR_BUFFER
);
2986 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
2987 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2988 RADEON_PRIO_SEPARATE_META
);
2991 if (tex
->dcc_separate_buffer
)
2992 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->dcc_separate_buffer
,
2993 RADEON_USAGE_READWRITE
, RADEON_PRIO_SEPARATE_META
);
2995 /* Compute mutable surface parameters. */
2996 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
2998 cb_color_cmask
= tex
->cmask_base_address_reg
;
3000 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3001 cb_color_attrib
= cb
->cb_color_attrib
;
3003 if (cb
->base
.u
.tex
.level
> 0)
3004 cb_color_info
&= C_028C70_FAST_CLEAR
;
3006 if (tex
->surface
.fmask_offset
) {
3007 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
) >> 8;
3008 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3012 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3013 bool is_msaa_resolve_dst
= state
->cbufs
[0] && state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3014 state
->cbufs
[1] == &cb
->base
&&
3015 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3017 if (!is_msaa_resolve_dst
)
3018 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3021 ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) + tex
->surface
.dcc_offset
) >>
3024 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3025 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3026 cb_dcc_base
|= dcc_tile_swizzle
;
3029 if (sctx
->chip_class
>= GFX10
) {
3030 unsigned cb_color_attrib3
;
3032 /* Set mutable surface parameters. */
3033 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3034 cb_color_base
|= tex
->surface
.tile_swizzle
;
3035 if (!tex
->surface
.fmask_offset
)
3036 cb_color_fmask
= cb_color_base
;
3037 if (cb
->base
.u
.tex
.level
> 0)
3038 cb_color_cmask
= cb_color_base
;
3040 cb_color_attrib3
= cb
->cb_color_attrib3
|
3041 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3042 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3043 S_028EE0_CMASK_PIPE_ALIGNED(1) |
3044 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3046 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3047 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3048 radeon_emit(cs
, 0); /* hole */
3049 radeon_emit(cs
, 0); /* hole */
3050 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3051 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3052 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3053 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3054 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3055 radeon_emit(cs
, 0); /* hole */
3056 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3057 radeon_emit(cs
, 0); /* hole */
3058 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3059 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3060 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3062 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4, cb_color_base
>> 32);
3063 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3064 cb_color_cmask
>> 32);
3065 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3066 cb_color_fmask
>> 32);
3067 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4, cb_dcc_base
>> 32);
3068 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4, cb
->cb_color_attrib2
);
3069 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4, cb_color_attrib3
);
3070 } else if (sctx
->chip_class
== GFX9
) {
3071 struct gfx9_surf_meta_flags meta
= {
3076 if (tex
->surface
.dcc_offset
)
3077 meta
= tex
->surface
.u
.gfx9
.dcc
;
3079 /* Set mutable surface parameters. */
3080 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3081 cb_color_base
|= tex
->surface
.tile_swizzle
;
3082 if (!tex
->surface
.fmask_offset
)
3083 cb_color_fmask
= cb_color_base
;
3084 if (cb
->base
.u
.tex
.level
> 0)
3085 cb_color_cmask
= cb_color_base
;
3086 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3087 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3088 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3089 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3091 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3092 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3093 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3094 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3095 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3096 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3097 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3098 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3099 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3100 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3101 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3102 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3103 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3104 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3105 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3106 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3108 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3109 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3111 /* Compute mutable surface parameters (GFX6-GFX8). */
3112 const struct legacy_surf_level
*level_info
=
3113 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3114 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3115 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3117 cb_color_base
+= level_info
->offset
>> 8;
3118 /* Only macrotiled modes can set tile swizzle. */
3119 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3120 cb_color_base
|= tex
->surface
.tile_swizzle
;
3122 if (!tex
->surface
.fmask_offset
)
3123 cb_color_fmask
= cb_color_base
;
3124 if (cb
->base
.u
.tex
.level
> 0)
3125 cb_color_cmask
= cb_color_base
;
3127 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3129 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3130 slice_tile_max
= level_info
->nblk_x
* level_info
->nblk_y
/ 64 - 1;
3131 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3133 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3134 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3135 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3137 if (tex
->surface
.fmask_offset
) {
3138 if (sctx
->chip_class
>= GFX7
)
3140 S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3142 S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3143 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3145 /* This must be set for fast clear to work without FMASK. */
3146 if (sctx
->chip_class
>= GFX7
)
3147 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3148 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3149 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3152 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3153 sctx
->chip_class
>= GFX8
? 14 : 13);
3154 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3155 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3156 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3157 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3158 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3159 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3160 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3161 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3162 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3163 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3164 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3165 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3166 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3168 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3169 radeon_emit(cs
, cb_dcc_base
);
3173 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3174 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3177 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3178 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3179 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3180 unsigned db_z_info
= zb
->db_z_info
;
3181 unsigned db_stencil_info
= zb
->db_stencil_info
;
3182 unsigned db_htile_surface
= zb
->db_htile_surface
;
3184 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
3185 zb
->base
.texture
->nr_samples
> 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3186 : RADEON_PRIO_DEPTH_BUFFER
);
3188 /* Set fields dependent on tc_compatile_htile. */
3189 if (sctx
->chip_class
>= GFX9
&&
3190 vi_tc_compat_htile_enabled(tex
, zb
->base
.u
.tex
.level
, PIPE_MASK_ZS
)) {
3191 unsigned max_zplanes
= 4;
3193 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&& tex
->buffer
.b
.b
.nr_samples
> 1)
3196 db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
3198 if (sctx
->chip_class
>= GFX10
) {
3199 db_z_info
|= S_028040_ITERATE_FLUSH(1);
3200 db_stencil_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
3202 db_z_info
|= S_028038_ITERATE_FLUSH(1);
3203 db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
3207 if (sctx
->chip_class
>= GFX10
) {
3208 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3209 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3211 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3212 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3213 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3214 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3215 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3216 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3217 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3218 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3219 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3221 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3222 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3223 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3224 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3225 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3226 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3227 } else if (sctx
->chip_class
== GFX9
) {
3228 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3229 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3231 S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3232 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3234 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3235 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3236 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3237 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3238 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3239 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3240 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3241 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3242 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3243 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3244 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3246 S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3248 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3249 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3250 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3253 /* Set fields dependent on tc_compatile_htile. */
3254 if (si_htile_enabled(tex
, zb
->base
.u
.tex
.level
, PIPE_MASK_ZS
)) {
3255 if (!tex
->surface
.has_stencil
&& !tex
->tc_compatible_htile
) {
3256 /* Use all of the htile_buffer for depth if there's no stencil.
3257 * This must not be set when TC-compatible HTILE is enabled
3260 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3263 if (tex
->tc_compatible_htile
) {
3264 db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
3266 /* 0 = full compression. N = only compress up to N-1 Z planes. */
3267 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
3268 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3269 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
3270 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3272 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3276 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3278 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3279 radeon_emit(cs
, zb
->db_depth_info
| /* DB_DEPTH_INFO */
3280 S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
));
3281 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3282 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3283 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3284 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3285 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3286 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3287 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3288 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3289 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3292 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3293 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3294 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3296 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3297 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, db_htile_surface
);
3298 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3299 if (sctx
->chip_class
== GFX9
)
3300 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3302 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3304 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3305 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3308 /* Framebuffer dimensions. */
3309 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3310 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3311 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3313 if (sctx
->screen
->dfsm_allowed
) {
3314 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3315 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3318 sctx
->framebuffer
.dirty_cbufs
= 0;
3319 sctx
->framebuffer
.dirty_zsbuf
= false;
3322 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3324 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3325 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3326 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3327 bool has_msaa_sample_loc_bug
= sctx
->screen
->info
.has_msaa_sample_loc_bug
;
3329 /* Smoothing (only possible with nr_samples == 1) uses the same
3330 * sample locations as the MSAA it simulates.
3332 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3333 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3335 /* On Polaris, the small primitive filter uses the sample locations
3336 * even when MSAA is off, so we need to make sure they're set to 0.
3338 * GFX10 uses sample locations unconditionally, so they always need
3341 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
|| sctx
->chip_class
>= GFX10
) &&
3342 nr_samples
!= sctx
->sample_locs_num_samples
) {
3343 sctx
->sample_locs_num_samples
= nr_samples
;
3344 si_emit_sample_locations(cs
, nr_samples
);
3347 if (sctx
->family
>= CHIP_POLARIS10
) {
3348 unsigned small_prim_filter_cntl
=
3349 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3351 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3353 /* The alternative of setting sample locations to 0 would
3354 * require a DB flush to avoid Z errors, see
3355 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3357 if (has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1 && !rs
->multisample_enable
)
3358 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3360 radeon_opt_set_context_reg(sctx
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3361 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
, small_prim_filter_cntl
);
3364 /* The exclusion bits can be set to improve rasterization efficiency
3365 * if no sample lies on the pixel boundary (-8 sample offset).
3367 bool exclusion
= sctx
->chip_class
>= GFX7
&& (!rs
->multisample_enable
|| nr_samples
!= 16);
3368 radeon_opt_set_context_reg(
3369 sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3370 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3373 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3375 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3376 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3378 if (!sctx
->screen
->has_out_of_order_rast
)
3381 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3383 colormask
&= blend
->cb_target_enabled_4bit
;
3385 /* Conservative: No logic op. */
3386 if (colormask
&& blend
->logicop_enable
)
3389 struct si_dsa_order_invariance dsa_order_invariant
= {.zs
= true,
3391 .pass_last
= false};
3393 if (sctx
->framebuffer
.state
.zsbuf
) {
3394 struct si_texture
*zstex
= (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3395 bool has_stencil
= zstex
->surface
.has_stencil
;
3396 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3397 if (!dsa_order_invariant
.zs
)
3400 /* The set of PS invocations is always order invariant,
3401 * except when early Z/S tests are requested. */
3402 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.writes_memory
&&
3403 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3404 !dsa_order_invariant
.pass_set
)
3407 if (sctx
->num_perfect_occlusion_queries
!= 0 && !dsa_order_invariant
.pass_set
)
3414 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3417 /* Only commutative blending. */
3418 if (blendmask
& ~blend
->commutative_4bit
)
3421 if (!dsa_order_invariant
.pass_set
)
3425 if (colormask
& ~blendmask
) {
3426 if (!dsa_order_invariant
.pass_last
)
3433 static void si_emit_msaa_config(struct si_context
*sctx
)
3435 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3436 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3437 /* 33% faster rendering to linear color buffers */
3438 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3439 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3440 unsigned sc_mode_cntl_1
=
3441 S_028A4C_WALK_SIZE(dst_is_linear
) | S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3442 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3443 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3444 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3446 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3447 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3448 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3449 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) |
3450 S_028804_INTERPOLATE_COMP_Z(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3451 unsigned coverage_samples
, color_samples
, z_samples
;
3452 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3454 /* S: Coverage samples (up to 16x):
3455 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3456 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3458 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3459 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3460 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3461 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3462 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3465 * F: Color samples (up to 8x, must be <= coverage samples):
3466 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3467 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3469 * Can be anything between coverage and color samples:
3470 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3471 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3472 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3473 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3474 * # All are currently set the same as coverage samples.
3476 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3477 * flag for undefined color samples. A shader-based resolve must handle unknowns
3478 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3479 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3480 * useful. The CB resolve always drops unknowns.
3482 * Sensible AA configurations:
3483 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3484 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3485 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3486 * EQAA 8s 8z 8f = 8x MSAA
3487 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3488 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3489 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3490 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3491 * EQAA 4s 4z 4f = 4x MSAA
3492 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3493 * EQAA 2s 2z 2f = 2x MSAA
3495 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3496 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3497 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3499 if (sctx
->framebuffer
.state
.zsbuf
) {
3500 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3501 z_samples
= MAX2(1, z_samples
);
3503 z_samples
= coverage_samples
;
3505 } else if (sctx
->smoothing_enabled
) {
3506 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3508 coverage_samples
= color_samples
= z_samples
= 1;
3511 /* Required by OpenGL line rasterization.
3513 * TODO: We should also enable perpendicular endcaps for AA lines,
3514 * but that requires implementing line stippling in the pixel
3515 * shader. SC can only do line stippling with axis-aligned
3518 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3519 unsigned sc_aa_config
= 0;
3521 if (coverage_samples
> 1) {
3522 /* distance from the pixel center, indexed by log2(nr_samples) */
3523 static unsigned max_dist
[] = {
3530 unsigned log_samples
= util_logbase2(coverage_samples
);
3531 unsigned log_z_samples
= util_logbase2(z_samples
);
3532 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3533 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3535 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3536 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3537 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3538 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3540 if (sctx
->framebuffer
.nr_samples
> 1) {
3541 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3542 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3543 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3544 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3545 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3546 } else if (sctx
->smoothing_enabled
) {
3547 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3551 unsigned initial_cdw
= cs
->current
.cdw
;
3553 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3554 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
, SI_TRACKED_PA_SC_LINE_CNTL
,
3555 sc_line_cntl
, sc_aa_config
);
3556 /* R_028804_DB_EQAA */
3557 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
, db_eqaa
);
3558 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3559 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
, SI_TRACKED_PA_SC_MODE_CNTL_1
,
3562 if (initial_cdw
!= cs
->current
.cdw
) {
3563 sctx
->context_roll
= true;
3565 /* GFX9: Flush DFSM when the AA mode changes. */
3566 if (sctx
->screen
->dfsm_allowed
) {
3567 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3568 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3573 void si_update_ps_iter_samples(struct si_context
*sctx
)
3575 if (sctx
->framebuffer
.nr_samples
> 1)
3576 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3577 if (sctx
->screen
->dpbb_allowed
)
3578 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3581 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3583 struct si_context
*sctx
= (struct si_context
*)ctx
;
3585 /* The hardware can only do sample shading with 2^n samples. */
3586 min_samples
= util_next_power_of_two(min_samples
);
3588 if (sctx
->ps_iter_samples
== min_samples
)
3591 sctx
->ps_iter_samples
= min_samples
;
3592 sctx
->do_update_shaders
= true;
3594 si_update_ps_iter_samples(sctx
);
3602 * Build the sampler view descriptor for a buffer texture.
3603 * @param state 256-bit descriptor; only the high 128 bits are filled in
3605 void si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3606 enum pipe_format format
, unsigned offset
, unsigned size
,
3609 const struct util_format_description
*desc
;
3611 unsigned num_records
;
3613 desc
= util_format_description(format
);
3614 stride
= desc
->block
.bits
/ 8;
3616 num_records
= size
/ stride
;
3617 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3619 /* The NUM_RECORDS field has a different meaning depending on the chip,
3620 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3623 * - If STRIDE == 0, it's in byte units.
3624 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3627 * - For SMEM and STRIDE == 0, it's in byte units.
3628 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3629 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3630 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3631 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3632 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3633 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3634 * That way the same descriptor can be used by both SMEM and VMEM.
3637 * - For SMEM and STRIDE == 0, it's in byte units.
3638 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3639 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3640 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3642 if (screen
->info
.chip_class
== GFX8
)
3643 num_records
*= stride
;
3646 state
[5] = S_008F04_STRIDE(stride
);
3647 state
[6] = num_records
;
3648 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3649 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3650 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3651 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3653 if (screen
->info
.chip_class
>= GFX10
) {
3654 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3656 /* OOB_SELECT chooses the out-of-bounds check:
3657 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3658 * - 1: index >= NUM_RECORDS
3659 * - 2: NUM_RECORDS == 0
3660 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3661 * else: swizzle_address >= NUM_RECORDS
3663 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3664 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET
) |
3665 S_008F0C_RESOURCE_LEVEL(1);
3668 unsigned num_format
, data_format
;
3670 first_non_void
= util_format_get_first_non_void_channel(format
);
3671 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3672 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3674 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
3678 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3680 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3682 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3683 /* For the pre-defined border color values (white, opaque
3684 * black, transparent black), the only thing that matters is
3685 * that the alpha channel winds up in the correct place
3686 * (because the RGB channels are all the same) so either of
3687 * these enumerations will work.
3689 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3690 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3692 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3693 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3694 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3695 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3697 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3698 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3699 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3700 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3701 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3708 * Build the sampler view descriptor for a texture.
3710 static void gfx10_make_texture_descriptor(
3711 struct si_screen
*screen
, struct si_texture
*tex
, bool sampler
, enum pipe_texture_target target
,
3712 enum pipe_format pipe_format
, const unsigned char state_swizzle
[4], unsigned first_level
,
3713 unsigned last_level
, unsigned first_layer
, unsigned last_layer
, unsigned width
, unsigned height
,
3714 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3716 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3717 const struct util_format_description
*desc
;
3718 unsigned img_format
;
3719 unsigned char swizzle
[4];
3723 desc
= util_format_description(pipe_format
);
3724 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3726 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3727 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3728 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3729 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3730 bool is_stencil
= false;
3732 switch (pipe_format
) {
3733 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3734 case PIPE_FORMAT_X32_S8X24_UINT
:
3735 case PIPE_FORMAT_X8Z24_UNORM
:
3736 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3739 case PIPE_FORMAT_X24S8_UINT
:
3741 * X24S8 is implemented as an 8_8_8_8 data format, to
3742 * fix texture gathers. This affects at least
3743 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3745 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3749 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3750 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3753 if (tex
->upgraded_depth
&& !is_stencil
) {
3754 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3755 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3758 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3761 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3762 /* For the purpose of shader images, treat cube maps as 2D
3765 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3767 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3770 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3772 depth
= res
->array_size
;
3773 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3774 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3775 depth
= res
->array_size
;
3776 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3777 depth
= res
->array_size
/ 6;
3780 state
[1] = S_00A004_FORMAT(img_format
) | S_00A004_WIDTH_LO(width
- 1);
3781 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3782 S_00A008_RESOURCE_LEVEL(1);
3784 S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3785 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3786 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3787 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3788 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ? 0 : first_level
) |
3789 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
) : last_level
) |
3790 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) | S_00A00C_TYPE(type
);
3791 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3792 * to know the total number of layers.
3795 S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
) ? depth
- 1 : last_layer
) |
3796 S_00A010_BASE_ARRAY(first_layer
);
3797 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3798 S_00A014_MAX_MIP(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
)
3799 : tex
->buffer
.b
.b
.last_level
) |
3800 S_00A014_PERF_MOD(4);
3804 if (vi_dcc_enabled(tex
, first_level
)) {
3805 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
3806 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
) |
3807 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
3810 /* Initialize the sampler view for FMASK. */
3811 if (tex
->surface
.fmask_offset
) {
3814 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
3816 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3817 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3819 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
3822 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
3825 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
3828 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
3831 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
3834 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
3837 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
3840 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
3843 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
3846 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
3849 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
3852 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
3855 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
3858 unreachable("invalid nr_samples");
3861 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3862 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) | S_00A004_FORMAT(format
) |
3863 S_00A004_WIDTH_LO(width
- 1);
3864 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3865 S_00A008_RESOURCE_LEVEL(1);
3867 S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3868 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3869 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3870 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3871 fmask_state
[4] = S_00A010_DEPTH(last_layer
) | S_00A010_BASE_ARRAY(first_layer
);
3873 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(1);
3879 * Build the sampler view descriptor for a texture (SI-GFX9).
3881 static void si_make_texture_descriptor(struct si_screen
*screen
, struct si_texture
*tex
,
3882 bool sampler
, enum pipe_texture_target target
,
3883 enum pipe_format pipe_format
,
3884 const unsigned char state_swizzle
[4], unsigned first_level
,
3885 unsigned last_level
, unsigned first_layer
,
3886 unsigned last_layer
, unsigned width
, unsigned height
,
3887 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3889 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3890 const struct util_format_description
*desc
;
3891 unsigned char swizzle
[4];
3893 unsigned num_format
, data_format
, type
, num_samples
;
3896 desc
= util_format_description(pipe_format
);
3898 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
? MAX2(1, res
->nr_samples
)
3899 : MAX2(1, res
->nr_storage_samples
);
3901 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3902 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3903 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3904 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3906 switch (pipe_format
) {
3907 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3908 case PIPE_FORMAT_X32_S8X24_UINT
:
3909 case PIPE_FORMAT_X8Z24_UNORM
:
3910 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3912 case PIPE_FORMAT_X24S8_UINT
:
3914 * X24S8 is implemented as an 8_8_8_8 data format, to
3915 * fix texture gathers. This affects at least
3916 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3918 if (screen
->info
.chip_class
<= GFX8
)
3919 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3921 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3924 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3927 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3930 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3932 switch (pipe_format
) {
3933 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3934 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3937 if (first_non_void
< 0) {
3938 if (util_format_is_compressed(pipe_format
)) {
3939 switch (pipe_format
) {
3940 case PIPE_FORMAT_DXT1_SRGB
:
3941 case PIPE_FORMAT_DXT1_SRGBA
:
3942 case PIPE_FORMAT_DXT3_SRGBA
:
3943 case PIPE_FORMAT_DXT5_SRGBA
:
3944 case PIPE_FORMAT_BPTC_SRGBA
:
3945 case PIPE_FORMAT_ETC2_SRGB8
:
3946 case PIPE_FORMAT_ETC2_SRGB8A1
:
3947 case PIPE_FORMAT_ETC2_SRGBA8
:
3948 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3950 case PIPE_FORMAT_RGTC1_SNORM
:
3951 case PIPE_FORMAT_LATC1_SNORM
:
3952 case PIPE_FORMAT_RGTC2_SNORM
:
3953 case PIPE_FORMAT_LATC2_SNORM
:
3954 case PIPE_FORMAT_ETC2_R11_SNORM
:
3955 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3956 /* implies float, so use SNORM/UNORM to determine
3957 whether data is signed or not */
3958 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3959 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3962 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3965 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3966 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3968 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3970 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3971 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3973 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3975 switch (desc
->channel
[first_non_void
].type
) {
3976 case UTIL_FORMAT_TYPE_FLOAT
:
3977 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3979 case UTIL_FORMAT_TYPE_SIGNED
:
3980 if (desc
->channel
[first_non_void
].normalized
)
3981 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3982 else if (desc
->channel
[first_non_void
].pure_integer
)
3983 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3985 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3987 case UTIL_FORMAT_TYPE_UNSIGNED
:
3988 if (desc
->channel
[first_non_void
].normalized
)
3989 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3990 else if (desc
->channel
[first_non_void
].pure_integer
)
3991 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3993 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3998 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3999 if (data_format
== ~0) {
4003 /* S8 with Z32 HTILE needs a special format. */
4004 if (screen
->info
.chip_class
== GFX9
&& pipe_format
== PIPE_FORMAT_S8_UINT
)
4005 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4007 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4008 (screen
->info
.chip_class
<= GFX8
&& res
->target
== PIPE_TEXTURE_3D
))) {
4009 /* For the purpose of shader images, treat cube maps and 3D
4010 * textures as 2D arrays. For 3D textures, the address
4011 * calculations for mipmaps are different, so we rely on the
4012 * caller to effectively disable mipmaps.
4014 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4016 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4018 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4021 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4023 depth
= res
->array_size
;
4024 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4025 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4026 depth
= res
->array_size
;
4027 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4028 depth
= res
->array_size
/ 6;
4031 state
[1] = (S_008F14_DATA_FORMAT(data_format
) | S_008F14_NUM_FORMAT(num_format
));
4032 state
[2] = (S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1) | S_008F18_PERF_MOD(4));
4033 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4034 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4035 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4036 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4037 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4038 S_008F1C_LAST_LEVEL(num_samples
> 1 ? util_logbase2(num_samples
) : last_level
) |
4039 S_008F1C_TYPE(type
));
4041 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4045 if (screen
->info
.chip_class
== GFX9
) {
4046 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4048 /* Depth is the the last accessible layer on Gfx9.
4049 * The hw doesn't need to know the total number of layers.
4051 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4052 state
[4] |= S_008F20_DEPTH(depth
- 1);
4054 state
[4] |= S_008F20_DEPTH(last_layer
);
4056 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4057 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ? util_logbase2(num_samples
)
4058 : tex
->buffer
.b
.b
.last_level
);
4060 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4061 state
[4] |= S_008F20_DEPTH(depth
- 1);
4062 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4065 if (vi_dcc_enabled(tex
, first_level
)) {
4066 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4068 /* The last dword is unused by hw. The shader uses it to clear
4069 * bits in the first dword of sampler state.
4071 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4072 if (first_level
== last_level
)
4073 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4075 state
[7] = 0xffffffff;
4079 /* Initialize the sampler view for FMASK. */
4080 if (tex
->surface
.fmask_offset
) {
4081 uint32_t data_format
, num_format
;
4083 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
4085 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4086 if (screen
->info
.chip_class
== GFX9
) {
4087 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4088 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4090 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4093 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4096 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4099 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4102 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4105 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4108 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4111 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4114 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4117 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4120 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4123 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4126 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4129 unreachable("invalid nr_samples");
4132 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4134 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4137 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4140 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4143 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4146 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4149 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4152 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4155 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4158 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4161 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4164 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4167 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4170 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4173 unreachable("invalid nr_samples");
4175 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4179 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4180 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) | S_008F14_DATA_FORMAT(data_format
) |
4181 S_008F14_NUM_FORMAT(num_format
);
4182 fmask_state
[2] = S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1);
4184 S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4185 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4186 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4188 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4192 if (screen
->info
.chip_class
== GFX9
) {
4193 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4195 S_008F20_DEPTH(last_layer
) | S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4196 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(1) |
4197 S_008F24_META_RB_ALIGNED(1);
4199 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4200 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4201 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4202 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4208 * Create a sampler view.
4210 * @param ctx context
4211 * @param texture texture
4212 * @param state sampler view template
4213 * @param width0 width0 override (for compressed textures as int)
4214 * @param height0 height0 override (for compressed textures as int)
4215 * @param force_level set the base address to the level (for compressed textures)
4217 struct pipe_sampler_view
*si_create_sampler_view_custom(struct pipe_context
*ctx
,
4218 struct pipe_resource
*texture
,
4219 const struct pipe_sampler_view
*state
,
4220 unsigned width0
, unsigned height0
,
4221 unsigned force_level
)
4223 struct si_context
*sctx
= (struct si_context
*)ctx
;
4224 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4225 struct si_texture
*tex
= (struct si_texture
*)texture
;
4226 unsigned base_level
, first_level
, last_level
;
4227 unsigned char state_swizzle
[4];
4228 unsigned height
, depth
, width
;
4229 unsigned last_layer
= state
->u
.tex
.last_layer
;
4230 enum pipe_format pipe_format
;
4231 const struct legacy_surf_level
*surflevel
;
4236 /* initialize base object */
4237 view
->base
= *state
;
4238 view
->base
.texture
= NULL
;
4239 view
->base
.reference
.count
= 1;
4240 view
->base
.context
= ctx
;
4243 pipe_resource_reference(&view
->base
.texture
, texture
);
4245 if (state
->format
== PIPE_FORMAT_X24S8_UINT
|| state
->format
== PIPE_FORMAT_S8X24_UINT
||
4246 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
|| state
->format
== PIPE_FORMAT_S8_UINT
)
4247 view
->is_stencil_sampler
= true;
4249 /* Buffer resource. */
4250 if (texture
->target
== PIPE_BUFFER
) {
4251 si_make_buffer_descriptor(sctx
->screen
, si_resource(texture
), state
->format
,
4252 state
->u
.buf
.offset
, state
->u
.buf
.size
, view
->state
);
4256 state_swizzle
[0] = state
->swizzle_r
;
4257 state_swizzle
[1] = state
->swizzle_g
;
4258 state_swizzle
[2] = state
->swizzle_b
;
4259 state_swizzle
[3] = state
->swizzle_a
;
4262 first_level
= state
->u
.tex
.first_level
;
4263 last_level
= state
->u
.tex
.last_level
;
4266 depth
= texture
->depth0
;
4268 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4269 assert(force_level
== first_level
&& force_level
== last_level
);
4270 base_level
= force_level
;
4273 width
= u_minify(width
, force_level
);
4274 height
= u_minify(height
, force_level
);
4275 depth
= u_minify(depth
, force_level
);
4278 /* This is not needed if gallium frontends set last_layer correctly. */
4279 if (state
->target
== PIPE_TEXTURE_1D
|| state
->target
== PIPE_TEXTURE_2D
||
4280 state
->target
== PIPE_TEXTURE_RECT
|| state
->target
== PIPE_TEXTURE_CUBE
)
4281 last_layer
= state
->u
.tex
.first_layer
;
4283 /* Texturing with separate depth and stencil. */
4284 pipe_format
= state
->format
;
4286 /* Depth/stencil texturing sometimes needs separate texture. */
4287 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4288 if (!tex
->flushed_depth_texture
&& !si_init_flushed_depth_texture(ctx
, texture
)) {
4289 pipe_resource_reference(&view
->base
.texture
, NULL
);
4294 assert(tex
->flushed_depth_texture
);
4296 /* Override format for the case where the flushed texture
4297 * contains only Z or only S.
4299 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4300 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4302 tex
= tex
->flushed_depth_texture
;
4305 surflevel
= tex
->surface
.u
.legacy
.level
;
4307 if (tex
->db_compatible
) {
4308 if (!view
->is_stencil_sampler
)
4309 pipe_format
= tex
->db_render_format
;
4311 switch (pipe_format
) {
4312 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4313 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4315 case PIPE_FORMAT_X8Z24_UNORM
:
4316 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4317 /* Z24 is always stored like this for DB
4320 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4322 case PIPE_FORMAT_X24S8_UINT
:
4323 case PIPE_FORMAT_S8X24_UINT
:
4324 case PIPE_FORMAT_X32_S8X24_UINT
:
4325 pipe_format
= PIPE_FORMAT_S8_UINT
;
4326 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4332 view
->dcc_incompatible
=
4333 vi_dcc_formats_are_incompatible(texture
, state
->u
.tex
.first_level
, state
->format
);
4335 sctx
->screen
->make_texture_descriptor(
4336 sctx
->screen
, tex
, true, state
->target
, pipe_format
, state_swizzle
, first_level
, last_level
,
4337 state
->u
.tex
.first_layer
, last_layer
, width
, height
, depth
, view
->state
, view
->fmask_state
);
4339 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4340 view
->is_integer
= false;
4342 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4343 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4346 /* Whether the number format is {U,S}{SCALED,INT} */
4347 view
->is_integer
= (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4348 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4349 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4353 view
->base_level_info
= &surflevel
[base_level
];
4354 view
->base_level
= base_level
;
4355 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4359 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
4360 struct pipe_resource
*texture
,
4361 const struct pipe_sampler_view
*state
)
4363 return si_create_sampler_view_custom(ctx
, texture
, state
, texture
? texture
->width0
: 0,
4364 texture
? texture
->height0
: 0, 0);
4367 static void si_sampler_view_destroy(struct pipe_context
*ctx
, struct pipe_sampler_view
*state
)
4369 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4371 pipe_resource_reference(&state
->texture
, NULL
);
4375 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4377 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4378 (linear_filter
&& (wrap
== PIPE_TEX_WRAP_CLAMP
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4381 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4382 const struct pipe_sampler_state
*state
,
4383 const union pipe_color_union
*color
, bool is_integer
)
4385 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4386 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4388 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4389 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4390 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4391 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4393 #define simple_border_types(elt) \
4395 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 0) \
4396 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4397 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 1) \
4398 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4399 if (color->elt[0] == 1 && color->elt[1] == 1 && color->elt[2] == 1 && color->elt[3] == 1) \
4400 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4404 simple_border_types(ui
);
4406 simple_border_types(f
);
4408 #undef simple_border_types
4412 /* Check if the border has been uploaded already. */
4413 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4414 if (memcmp(&sctx
->border_color_table
[i
], color
, sizeof(*color
)) == 0)
4417 if (i
>= SI_MAX_BORDER_COLORS
) {
4418 /* Getting 4096 unique border colors is very unlikely. */
4419 fprintf(stderr
, "radeonsi: The border color table is full. "
4420 "Any new border colors will be just black. "
4421 "Please file a bug.\n");
4422 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4425 if (i
== sctx
->border_color_count
) {
4426 /* Upload a new border color. */
4427 memcpy(&sctx
->border_color_table
[i
], color
, sizeof(*color
));
4428 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
], color
, sizeof(*color
));
4429 sctx
->border_color_count
++;
4432 return S_008F3C_BORDER_COLOR_PTR(i
) |
4433 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4436 static inline int S_FIXED(float value
, unsigned frac_bits
)
4438 return value
* (1 << frac_bits
);
4441 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4443 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4444 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4445 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4447 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4448 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4451 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4464 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4465 const struct pipe_sampler_state
*state
)
4467 struct si_context
*sctx
= (struct si_context
*)ctx
;
4468 struct si_screen
*sscreen
= sctx
->screen
;
4469 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4470 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
: state
->max_anisotropy
;
4471 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4472 bool trunc_coord
= state
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
&&
4473 state
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
&&
4474 state
->compare_mode
== PIPE_TEX_COMPARE_NONE
;
4475 union pipe_color_union clamped_border_color
;
4482 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4485 (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) | S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4486 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) | S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4487 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4488 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4489 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4490 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4491 S_008F30_TRUNC_COORD(trunc_coord
) |
4492 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4493 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4494 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4495 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4496 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4497 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4498 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4499 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4500 S_008F38_MIP_POINT_PRECLAMP(0));
4501 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4503 if (sscreen
->info
.chip_class
>= GFX10
) {
4504 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4506 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4507 S_008F38_FILTER_PREC_FIX(1) |
4508 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4511 /* Create sampler resource for integer textures. */
4512 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4513 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4515 /* Create sampler resource for upgraded depth textures. */
4516 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4518 for (unsigned i
= 0; i
< 4; ++i
) {
4519 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4520 * when the border color is 1.0. */
4521 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4524 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4525 if (sscreen
->info
.chip_class
<= GFX9
)
4526 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4528 rstate
->upgraded_depth_val
[3] =
4529 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4535 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4537 struct si_context
*sctx
= (struct si_context
*)ctx
;
4539 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4542 sctx
->sample_mask
= sample_mask
;
4543 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4546 static void si_emit_sample_mask(struct si_context
*sctx
)
4548 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4549 unsigned mask
= sctx
->sample_mask
;
4551 /* Needed for line and polygon smoothing as well as for the Polaris
4552 * small primitive filter. We expect the gallium frontend to take care of
4555 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4556 (mask
& 1 && sctx
->blitter
->running
));
4558 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4559 radeon_emit(cs
, mask
| (mask
<< 16));
4560 radeon_emit(cs
, mask
| (mask
<< 16));
4563 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4566 struct si_sampler_state
*s
= state
;
4568 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4575 * Vertex elements & buffers
4578 struct si_fast_udiv_info32
si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4580 struct util_fast_udiv_info info
= util_compute_fast_udiv_info(D
, num_bits
, 32);
4582 struct si_fast_udiv_info32 result
= {
4591 static void *si_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
4592 const struct pipe_vertex_element
*elements
)
4594 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4595 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4596 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4597 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4598 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4599 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4600 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4601 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4602 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4605 assert(count
<= SI_MAX_ATTRIBS
);
4611 unsigned alloc_count
=
4612 count
> sscreen
->num_vbos_in_user_sgprs
? count
- sscreen
->num_vbos_in_user_sgprs
: 0;
4613 v
->vb_desc_list_alloc_size
= align(alloc_count
* 16, SI_CPDMA_ALIGNMENT
);
4615 for (i
= 0; i
< count
; ++i
) {
4616 const struct util_format_description
*desc
;
4617 const struct util_format_channel_description
*channel
;
4619 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4621 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4626 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4627 if (instance_divisor
) {
4628 v
->uses_instance_divisors
= true;
4630 if (instance_divisor
== 1) {
4631 v
->instance_divisor_is_one
|= 1u << i
;
4633 v
->instance_divisor_is_fetched
|= 1u << i
;
4634 divisor_factors
[i
] = si_compute_fast_udiv_info32(instance_divisor
, 32);
4638 if (!used
[vbo_index
]) {
4639 v
->first_vb_use_mask
|= 1 << i
;
4640 used
[vbo_index
] = true;
4643 desc
= util_format_description(elements
[i
].src_format
);
4644 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4645 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4647 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4648 v
->src_offset
[i
] = elements
[i
].src_offset
;
4649 v
->vertex_buffer_index
[i
] = vbo_index
;
4651 bool always_fix
= false;
4652 union si_vs_fix_fetch fix_fetch
;
4653 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4656 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4659 switch (channel
->type
) {
4660 case UTIL_FORMAT_TYPE_FLOAT
:
4661 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4663 case UTIL_FORMAT_TYPE_FIXED
:
4664 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4666 case UTIL_FORMAT_TYPE_SIGNED
: {
4667 if (channel
->pure_integer
)
4668 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4669 else if (channel
->normalized
)
4670 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4672 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4675 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4676 if (channel
->pure_integer
)
4677 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4678 else if (channel
->normalized
)
4679 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4681 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4685 unreachable("bad format type");
4688 switch (elements
[i
].src_format
) {
4689 case PIPE_FORMAT_R11G11B10_FLOAT
:
4690 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4693 unreachable("bad other format");
4697 if (desc
->channel
[0].size
== 10) {
4698 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4699 log_hw_load_size
= 2;
4701 /* The hardware always treats the 2-bit alpha channel as
4702 * unsigned, so a shader workaround is needed. The affected
4703 * chips are GFX8 and older except Stoney (GFX8.1).
4705 always_fix
= sscreen
->info
.chip_class
<= GFX8
&& sscreen
->info
.family
!= CHIP_STONEY
&&
4706 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4707 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4708 fix_fetch
.u
.log_size
= 3; /* special encoding */
4709 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4710 log_hw_load_size
= 2;
4712 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4713 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4716 * - doubles (multiple loads + truncate to float)
4717 * - 32-bit requiring a conversion
4719 always_fix
= (fix_fetch
.u
.log_size
== 3) ||
4720 (fix_fetch
.u
.log_size
== 2 && fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4721 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4722 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4724 /* Also fixup 8_8_8 and 16_16_16. */
4725 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4727 log_hw_load_size
= fix_fetch
.u
.log_size
;
4731 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4732 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4733 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4734 fix_fetch
.u
.reverse
= 1;
4737 /* Force the workaround for unaligned access here already if the
4738 * offset relative to the vertex buffer base is unaligned.
4740 * There is a theoretical case in which this is too conservative:
4741 * if the vertex buffer's offset is also unaligned in just the
4742 * right way, we end up with an aligned address after all.
4743 * However, this case should be extremely rare in practice (it
4744 * won't happen in well-behaved applications), and taking it
4745 * into account would complicate the fast path (where everything
4746 * is nicely aligned).
4748 bool check_alignment
=
4749 log_hw_load_size
>= 1 &&
4750 (sscreen
->info
.chip_class
== GFX6
|| sscreen
->info
.chip_class
>= GFX10
);
4751 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4753 if (check_alignment
&& (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
4756 if (always_fix
|| check_alignment
|| opencode
)
4757 v
->fix_fetch
[i
] = fix_fetch
.bits
;
4760 v
->fix_fetch_opencode
|= 1 << i
;
4761 if (opencode
|| always_fix
)
4762 v
->fix_fetch_always
|= 1 << i
;
4764 if (check_alignment
&& !opencode
) {
4765 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
4767 v
->fix_fetch_unaligned
|= 1 << i
;
4768 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
4769 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
4772 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
4773 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
4774 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
4775 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
4777 if (sscreen
->info
.chip_class
>= GFX10
) {
4778 const struct gfx10_format
*fmt
= &gfx10_format_table
[elements
[i
].src_format
];
4779 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
4780 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) | S_008F0C_RESOURCE_LEVEL(1);
4782 unsigned data_format
, num_format
;
4783 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4784 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4785 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
4789 if (v
->instance_divisor_is_fetched
) {
4790 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
4792 v
->instance_divisor_factor_buffer
= (struct si_resource
*)pipe_buffer_create(
4793 &sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, num_divisors
* sizeof(divisor_factors
[0]));
4794 if (!v
->instance_divisor_factor_buffer
) {
4799 sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
4800 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
4805 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4807 struct si_context
*sctx
= (struct si_context
*)ctx
;
4808 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4809 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4811 sctx
->vertex_elements
= v
;
4812 sctx
->num_vertex_elements
= v
? v
->count
: 0;
4814 if (sctx
->num_vertex_elements
) {
4815 sctx
->vertex_buffers_dirty
= true;
4817 sctx
->vertex_buffer_pointer_dirty
= false;
4818 sctx
->vertex_buffer_user_sgprs_dirty
= false;
4821 if (v
&& (!old
|| old
->count
!= v
->count
||
4822 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4823 /* we don't check which divisors changed */
4824 v
->uses_instance_divisors
||
4825 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) &
4826 sctx
->vertex_buffer_unaligned
||
4827 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
4828 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
4829 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
4830 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4831 * functions of fix_fetch and the src_offset alignment.
4832 * If they change and fix_fetch doesn't, it must be due to different
4833 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4834 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
4835 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4836 sctx
->do_update_shaders
= true;
4838 if (v
&& v
->instance_divisor_is_fetched
) {
4839 struct pipe_constant_buffer cb
;
4841 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
4842 cb
.user_buffer
= NULL
;
4843 cb
.buffer_offset
= 0;
4844 cb
.buffer_size
= 0xffffffff;
4845 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4849 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4851 struct si_context
*sctx
= (struct si_context
*)ctx
;
4852 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4854 if (sctx
->vertex_elements
== state
) {
4855 sctx
->vertex_elements
= NULL
;
4856 sctx
->num_vertex_elements
= 0;
4858 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
4862 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
4863 const struct pipe_vertex_buffer
*buffers
)
4865 struct si_context
*sctx
= (struct si_context
*)ctx
;
4866 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4867 unsigned updated_mask
= u_bit_consecutive(start_slot
, count
);
4868 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
4869 uint32_t unaligned
= 0;
4872 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4875 for (i
= 0; i
< count
; i
++) {
4876 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4877 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4878 struct pipe_resource
*buf
= src
->buffer
.resource
;
4879 unsigned slot_bit
= 1 << (start_slot
+ i
);
4881 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4882 dsti
->buffer_offset
= src
->buffer_offset
;
4883 dsti
->stride
= src
->stride
;
4885 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
4886 unaligned
|= slot_bit
;
4888 si_context_add_resource_size(sctx
, buf
);
4890 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4893 for (i
= 0; i
< count
; i
++) {
4894 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4896 unaligned
&= ~updated_mask
;
4898 sctx
->vertex_buffers_dirty
= true;
4899 sctx
->vertex_buffer_unaligned
= (orig_unaligned
& ~updated_mask
) | unaligned
;
4901 /* Check whether alignment may have changed in a way that requires
4902 * shader changes. This check is conservative: a vertex buffer can only
4903 * trigger a shader change if the misalignment amount changes (e.g.
4904 * from byte-aligned to short-aligned), but we only keep track of
4905 * whether buffers are at least dword-aligned, since that should always
4906 * be the case in well-behaved applications anyway.
4908 if (sctx
->vertex_elements
&& (sctx
->vertex_elements
->vb_alignment_check_mask
&
4909 (unaligned
| orig_unaligned
) & updated_mask
))
4910 sctx
->do_update_shaders
= true;
4917 static void si_set_tess_state(struct pipe_context
*ctx
, const float default_outer_level
[4],
4918 const float default_inner_level
[2])
4920 struct si_context
*sctx
= (struct si_context
*)ctx
;
4921 struct pipe_constant_buffer cb
;
4924 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4925 memcpy(array
+ 4, default_inner_level
, sizeof(float) * 2);
4928 cb
.user_buffer
= NULL
;
4929 cb
.buffer_size
= sizeof(array
);
4931 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
, (void *)array
, sizeof(array
),
4934 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4935 pipe_resource_reference(&cb
.buffer
, NULL
);
4938 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4940 struct si_context
*sctx
= (struct si_context
*)ctx
;
4942 si_update_fb_dirtiness_after_rendering(sctx
);
4944 /* Multisample surfaces are flushed in si_decompress_textures. */
4945 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
4946 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4947 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
4948 sctx
->framebuffer
.all_DCC_pipe_aligned
);
4952 /* This only ensures coherency for shader image/buffer stores. */
4953 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4955 struct si_context
*sctx
= (struct si_context
*)ctx
;
4957 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
4960 /* Subsequent commands must wait for all shader invocations to
4962 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
4964 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4965 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
| SI_CONTEXT_INV_VCACHE
;
4967 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
| PIPE_BARRIER_SHADER_BUFFER
| PIPE_BARRIER_TEXTURE
|
4968 PIPE_BARRIER_IMAGE
| PIPE_BARRIER_STREAMOUT_BUFFER
| PIPE_BARRIER_GLOBAL_BUFFER
)) {
4969 /* As far as I can tell, L1 contents are written back to L2
4970 * automatically at end of shader, but the contents of other
4971 * L1 caches might still be stale. */
4972 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
4975 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4976 /* Indices are read through TC L2 since GFX8.
4979 if (sctx
->screen
->info
.chip_class
<= GFX7
)
4980 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4983 /* MSAA color, any depth and any stencil are flushed in
4984 * si_decompress_textures when needed.
4986 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&& sctx
->framebuffer
.uncompressed_cb_mask
) {
4987 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4989 if (sctx
->chip_class
<= GFX8
)
4990 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4993 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4994 if (sctx
->screen
->info
.chip_class
<= GFX8
&& flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4995 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4998 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
5000 struct pipe_blend_state blend
;
5002 memset(&blend
, 0, sizeof(blend
));
5003 blend
.independent_blend_enable
= true;
5004 blend
.rt
[0].colormask
= 0xf;
5005 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5008 static void si_init_config(struct si_context
*sctx
);
5010 void si_init_state_compute_functions(struct si_context
*sctx
)
5012 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5013 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5014 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5015 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5016 sctx
->b
.memory_barrier
= si_memory_barrier
;
5019 void si_init_state_functions(struct si_context
*sctx
)
5021 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5022 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5023 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5024 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5025 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5026 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5027 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5028 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5029 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5030 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5031 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5033 sctx
->b
.create_blend_state
= si_create_blend_state
;
5034 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5035 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5036 sctx
->b
.set_blend_color
= si_set_blend_color
;
5038 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5039 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5040 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5042 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5043 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5044 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5046 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5047 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5048 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5049 sctx
->custom_blend_eliminate_fastclear
=
5050 si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5051 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5053 sctx
->b
.set_clip_state
= si_set_clip_state
;
5054 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5056 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5058 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5060 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5061 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5062 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5063 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5065 sctx
->b
.texture_barrier
= si_texture_barrier
;
5066 sctx
->b
.set_min_samples
= si_set_min_samples
;
5067 sctx
->b
.set_tess_state
= si_set_tess_state
;
5069 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5071 si_init_config(sctx
);
5074 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5076 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5078 if (sscreen
->info
.chip_class
>= GFX10
) {
5079 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5081 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5085 static void si_set_grbm_gfx_index(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned value
)
5087 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
: R_00802C_GRBM_GFX_INDEX
;
5088 si_pm4_set_reg(pm4
, reg
, value
);
5091 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned se
)
5093 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5094 si_set_grbm_gfx_index(sctx
, pm4
,
5095 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) : S_030800_SE_INDEX(se
)) |
5096 S_030800_SH_BROADCAST_WRITES(1) |
5097 S_030800_INSTANCE_BROADCAST_WRITES(1));
5100 static void si_write_harvested_raster_configs(struct si_context
*sctx
, struct si_pm4_state
*pm4
,
5101 unsigned raster_config
, unsigned raster_config_1
)
5103 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5104 unsigned raster_config_se
[4];
5107 ac_get_harvested_configs(&sctx
->screen
->info
, raster_config
, &raster_config_1
, raster_config_se
);
5109 for (se
= 0; se
< num_se
; se
++) {
5110 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5111 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5113 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5115 if (sctx
->chip_class
>= GFX7
) {
5116 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5120 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5122 struct si_screen
*sscreen
= sctx
->screen
;
5123 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5124 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5125 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5126 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5128 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5129 /* Always use the default config when all backends are enabled
5130 * (or when we failed to determine the enabled backends).
5132 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config
);
5133 if (sctx
->chip_class
>= GFX7
)
5134 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5136 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5140 static void si_init_config(struct si_context
*sctx
)
5142 struct si_screen
*sscreen
= sctx
->screen
;
5143 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5144 bool has_clear_state
= sscreen
->info
.has_clear_state
;
5145 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5150 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5151 si_pm4_cmd_add(pm4
, CC0_UPDATE_LOAD_ENABLES(1));
5152 si_pm4_cmd_add(pm4
, CC1_UPDATE_SHADOW_ENABLES(1));
5153 si_pm4_cmd_end(pm4
, false);
5155 if (has_clear_state
) {
5156 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5157 si_pm4_cmd_add(pm4
, 0);
5158 si_pm4_cmd_end(pm4
, false);
5161 if (sctx
->chip_class
<= GFX8
)
5162 si_set_raster_config(sctx
, pm4
);
5164 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5165 if (!has_clear_state
)
5166 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5168 /* FIXME calculate these values somehow ??? */
5169 if (sctx
->chip_class
<= GFX8
) {
5170 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5171 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5174 if (!has_clear_state
) {
5175 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5176 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5177 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5180 if (sscreen
->info
.chip_class
<= GFX9
)
5181 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5182 if (!has_clear_state
)
5183 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5184 if (sctx
->chip_class
< GFX7
)
5185 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
,
5186 S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1));
5188 /* CLEAR_STATE doesn't restore these correctly. */
5189 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5190 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5191 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5193 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5194 * I don't know why. Deduced by trial and error.
5196 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5197 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5198 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5199 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5200 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5201 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5204 if (!has_clear_state
) {
5205 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5206 S_028230_ER_TRI(0xA) | S_028230_ER_POINT(0xA) | S_028230_ER_RECT(0xA) |
5207 /* Required by DX10_DIAMOND_TEST_ENA: */
5208 S_028230_ER_LINE_LR(0x1A) | S_028230_ER_LINE_RL(0x26) |
5209 S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA));
5210 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5211 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5212 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5213 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5214 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5217 if (sctx
->chip_class
>= GFX10
) {
5218 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5219 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5220 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5221 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5222 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5223 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5224 } else if (sctx
->chip_class
== GFX9
) {
5225 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5226 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5227 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5229 /* These registers, when written, also overwrite the CLEAR_STATE
5230 * context, so we can't rely on CLEAR_STATE setting them.
5231 * It would be an issue if there was another UMD changing them.
5233 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5234 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5235 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5238 if (sctx
->chip_class
>= GFX7
) {
5239 if (sctx
->chip_class
>= GFX10
) {
5240 /* Logical CUs 16 - 31 */
5241 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
, S_00B404_CU_EN(0xffff));
5242 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
, S_00B104_CU_EN(0xffff));
5243 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
, S_00B004_CU_EN(0xffff));
5246 if (sctx
->chip_class
>= GFX9
) {
5247 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5248 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5250 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5251 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5252 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_WAVE_LIMIT(0x3F));
5253 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5254 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5256 /* If this is 0, Bonaire can hang even if GS isn't being used.
5257 * Other chips are unaffected. These are suboptimal values,
5258 * but we don't use on-chip GS.
5260 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5261 S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4));
5264 /* Compute LATE_ALLOC_VS.LIMIT. */
5265 unsigned num_cu_per_sh
= sscreen
->info
.min_good_cu_per_sa
;
5266 unsigned late_alloc_wave64
= 0; /* The limit is per SA. */
5267 unsigned cu_mask_vs
= 0xffff;
5268 unsigned cu_mask_gs
= 0xffff;
5270 if (sctx
->chip_class
>= GFX10
) {
5271 /* For Wave32, the hw will launch twice the number of late
5272 * alloc waves, so 1 == 2x wave32.
5274 if (!sscreen
->info
.use_late_alloc
) {
5275 late_alloc_wave64
= 0;
5276 } else if (num_cu_per_sh
<= 6) {
5277 late_alloc_wave64
= num_cu_per_sh
- 2;
5279 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5281 /* CU2 & CU3 disabled because of the dual CU design */
5282 /* Late alloc is not used for NGG on Navi14 due to a hw bug. */
5283 cu_mask_vs
= 0xfff3;
5284 cu_mask_gs
= sscreen
->use_ngg
&& sctx
->family
!= CHIP_NAVI14
? 0xfff3 : 0xffff;
5287 if (!sscreen
->info
.use_late_alloc
) {
5288 late_alloc_wave64
= 0;
5289 } else if (num_cu_per_sh
<= 4) {
5290 /* Too few available compute units per SA. Disallowing
5291 * VS to run on one CU could hurt us more than late VS
5292 * allocation would help.
5294 * 2 is the highest safe number that allows us to keep
5297 late_alloc_wave64
= 2;
5299 /* This is a good initial value, allowing 1 late_alloc
5300 * wave per SIMD on num_cu - 2.
5302 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5305 if (late_alloc_wave64
> 2)
5306 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5309 /* VS can't execute on one CU if the limit is > 2. */
5310 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5311 S_00B118_CU_EN(cu_mask_vs
) | S_00B118_WAVE_LIMIT(0x3F));
5312 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(late_alloc_wave64
));
5314 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5315 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5317 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5318 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5321 if (sctx
->chip_class
>= GFX10
) {
5322 /* Break up a pixel wave if it contains deallocs for more than
5323 * half the parameter cache.
5325 * To avoid a deadlock where pixel waves aren't launched
5326 * because they're waiting for more pixels while the frontend
5327 * is stuck waiting for PC space, the maximum allowed value is
5328 * the size of the PC minus the largest possible allocation for
5329 * a single primitive shader subgroup.
5331 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
, S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5332 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5334 if (!has_clear_state
) {
5335 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5336 sscreen
->info
.pa_sc_tile_steering_override
);
5339 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
5340 unsigned meta_write_policy
, meta_read_policy
;
5341 /* TODO: investigate whether LRU improves performance on other chips too */
5342 if (sscreen
->info
.num_render_backends
<= 4) {
5343 meta_write_policy
= V_02807C_CACHE_LRU_WR
; /* cache writes */
5344 meta_read_policy
= V_02807C_CACHE_LRU_RD
; /* cache reads */
5346 meta_write_policy
= V_02807C_CACHE_STREAM_WR
; /* write combine */
5347 meta_read_policy
= V_02807C_CACHE_NOA_RD
; /* don't cache reads */
5350 si_pm4_set_reg(pm4
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
5351 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5352 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5353 S_02807C_HTILE_WR_POLICY(meta_write_policy
) |
5354 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5355 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5356 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5357 S_02807C_HTILE_RD_POLICY(meta_read_policy
));
5360 pm4
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
5361 S_028410_CMASK_WR_POLICY(meta_write_policy
) | S_028410_FMASK_WR_POLICY(meta_write_policy
) |
5362 S_028410_DCC_WR_POLICY(meta_write_policy
) |
5363 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5364 S_028410_CMASK_RD_POLICY(meta_read_policy
) |
5365 S_028410_FMASK_RD_POLICY(meta_read_policy
) | S_028410_DCC_RD_POLICY(meta_read_policy
) |
5366 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
5367 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5369 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5370 S_00B0C0_SOFT_GROUPING_EN(1) | S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5371 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5374 if (sctx
->chip_class
>= GFX9
) {
5375 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
,
5376 S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) |
5377 S_028B50_DONUT_SPLIT(24) | S_028B50_TRAP_SPLIT(6));
5378 } else if (sctx
->chip_class
>= GFX8
) {
5379 unsigned vgt_tess_distribution
;
5381 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) |
5382 S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT(16);
5384 /* Testing with Unigine Heaven extreme tesselation yielded best results
5385 * with TRAP_SPLIT = 3.
5387 if (sctx
->family
== CHIP_FIJI
|| sctx
->family
>= CHIP_POLARIS10
)
5388 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5390 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5391 } else if (!has_clear_state
) {
5392 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5393 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5396 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5397 if (sctx
->chip_class
>= GFX7
) {
5398 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, S_028084_ADDRESS(border_color_va
>> 40));
5400 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
, RADEON_PRIO_BORDER_COLORS
);
5402 if (sctx
->chip_class
>= GFX9
) {
5403 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5404 S_028C48_MAX_ALLOC_COUNT(sscreen
->info
.pbb_max_alloc_count
- 1) |
5405 S_028C48_MAX_PRIM_PER_BATCH(1023));
5406 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5407 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5408 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5411 sctx
->init_config
= pm4
;