projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: move geometry shader properties from si_shader to si_shader_selector
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_framebuffer.h"
36 #include "util/u_helpers.h"
37 #include "util/u_memory.h"
38 #include "util/u_simple_shaders.h"
39
40 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
41 void (*emit)(struct si_context *ctx, struct r600_atom *state),
42 unsigned num_dw)
43 {
44 atom->emit = (void*)emit;
45 atom->num_dw = num_dw;
46 atom->dirty = false;
47 *list_elem = atom;
48 }
49
50 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
51 {
52 if (sscreen->b.chip_class == CIK &&
53 sscreen->b.info.cik_macrotile_mode_array_valid) {
54 unsigned index, tileb;
55
56 tileb = 8 * 8 * tex->surface.bpe;
57 tileb = MIN2(tex->surface.tile_split, tileb);
58
59 for (index = 0; tileb > 64; index++) {
60 tileb >>= 1;
61 }
62 assert(index < 16);
63
64 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
65 }
66
67 if (sscreen->b.chip_class == SI &&
68 sscreen->b.info.si_tile_mode_array_valid) {
69 /* Don't use stencil_tiling_index, because num_banks is always
70 * read from the depth mode. */
71 unsigned tile_mode_index = tex->surface.tiling_index[0];
72 assert(tile_mode_index < 32);
73
74 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
75 }
76
77 /* The old way. */
78 switch (sscreen->b.tiling_info.num_banks) {
79 case 2:
80 return V_02803C_ADDR_SURF_2_BANK;
81 case 4:
82 return V_02803C_ADDR_SURF_4_BANK;
83 case 8:
84 default:
85 return V_02803C_ADDR_SURF_8_BANK;
86 case 16:
87 return V_02803C_ADDR_SURF_16_BANK;
88 }
89 }
90
91 unsigned cik_tile_split(unsigned tile_split)
92 {
93 switch (tile_split) {
94 case 64:
95 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
96 break;
97 case 128:
98 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
99 break;
100 case 256:
101 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
102 break;
103 case 512:
104 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
105 break;
106 default:
107 case 1024:
108 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
109 break;
110 case 2048:
111 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
112 break;
113 case 4096:
114 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
115 break;
116 }
117 return tile_split;
118 }
119
120 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
121 {
122 switch (macro_tile_aspect) {
123 default:
124 case 1:
125 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
126 break;
127 case 2:
128 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
129 break;
130 case 4:
131 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
132 break;
133 case 8:
134 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
135 break;
136 }
137 return macro_tile_aspect;
138 }
139
140 unsigned cik_bank_wh(unsigned bankwh)
141 {
142 switch (bankwh) {
143 default:
144 case 1:
145 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
146 break;
147 case 2:
148 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
149 break;
150 case 4:
151 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
152 break;
153 case 8:
154 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
155 break;
156 }
157 return bankwh;
158 }
159
160 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
161 {
162 if (sscreen->b.info.si_tile_mode_array_valid) {
163 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
164
165 return G_009910_PIPE_CONFIG(gb_tile_mode);
166 }
167
168 /* This is probably broken for a lot of chips, but it's only used
169 * if the kernel cannot return the tile mode array for CIK. */
170 switch (sscreen->b.info.r600_num_tile_pipes) {
171 case 16:
172 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
173 case 8:
174 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
175 case 4:
176 default:
177 if (sscreen->b.info.r600_num_backends == 4)
178 return V_02803C_X_ADDR_SURF_P4_16X16;
179 else
180 return V_02803C_X_ADDR_SURF_P4_8X16;
181 case 2:
182 return V_02803C_ADDR_SURF_P2;
183 }
184 }
185
186 static unsigned si_map_swizzle(unsigned swizzle)
187 {
188 switch (swizzle) {
189 case UTIL_FORMAT_SWIZZLE_Y:
190 return V_008F0C_SQ_SEL_Y;
191 case UTIL_FORMAT_SWIZZLE_Z:
192 return V_008F0C_SQ_SEL_Z;
193 case UTIL_FORMAT_SWIZZLE_W:
194 return V_008F0C_SQ_SEL_W;
195 case UTIL_FORMAT_SWIZZLE_0:
196 return V_008F0C_SQ_SEL_0;
197 case UTIL_FORMAT_SWIZZLE_1:
198 return V_008F0C_SQ_SEL_1;
199 default: /* UTIL_FORMAT_SWIZZLE_X */
200 return V_008F0C_SQ_SEL_X;
201 }
202 }
203
204 static uint32_t S_FIXED(float value, uint32_t frac_bits)
205 {
206 return value * (1 << frac_bits);
207 }
208
209 /* 12.4 fixed-point */
210 static unsigned si_pack_float_12p4(float x)
211 {
212 return x <= 0 ? 0 :
213 x >= 4096 ? 0xffff : x * 16;
214 }
215
216 /*
217 * inferred framebuffer and blender state
218 */
219 static void si_update_fb_blend_state(struct si_context *sctx)
220 {
221 struct si_pm4_state *pm4;
222 struct si_state_blend *blend = sctx->queued.named.blend;
223 uint32_t mask;
224
225 if (blend == NULL)
226 return;
227
228 pm4 = si_pm4_alloc_state(sctx);
229 if (pm4 == NULL)
230 return;
231
232 mask = (1ULL << ((unsigned)sctx->framebuffer.state.nr_cbufs * 4)) - 1;
233 mask &= blend->cb_target_mask;
234 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
235
236 si_pm4_set_state(sctx, fb_blend, pm4);
237 }
238
239 /*
240 * Blender functions
241 */
242
243 static uint32_t si_translate_blend_function(int blend_func)
244 {
245 switch (blend_func) {
246 case PIPE_BLEND_ADD:
247 return V_028780_COMB_DST_PLUS_SRC;
248 case PIPE_BLEND_SUBTRACT:
249 return V_028780_COMB_SRC_MINUS_DST;
250 case PIPE_BLEND_REVERSE_SUBTRACT:
251 return V_028780_COMB_DST_MINUS_SRC;
252 case PIPE_BLEND_MIN:
253 return V_028780_COMB_MIN_DST_SRC;
254 case PIPE_BLEND_MAX:
255 return V_028780_COMB_MAX_DST_SRC;
256 default:
257 R600_ERR("Unknown blend function %d\n", blend_func);
258 assert(0);
259 break;
260 }
261 return 0;
262 }
263
264 static uint32_t si_translate_blend_factor(int blend_fact)
265 {
266 switch (blend_fact) {
267 case PIPE_BLENDFACTOR_ONE:
268 return V_028780_BLEND_ONE;
269 case PIPE_BLENDFACTOR_SRC_COLOR:
270 return V_028780_BLEND_SRC_COLOR;
271 case PIPE_BLENDFACTOR_SRC_ALPHA:
272 return V_028780_BLEND_SRC_ALPHA;
273 case PIPE_BLENDFACTOR_DST_ALPHA:
274 return V_028780_BLEND_DST_ALPHA;
275 case PIPE_BLENDFACTOR_DST_COLOR:
276 return V_028780_BLEND_DST_COLOR;
277 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
278 return V_028780_BLEND_SRC_ALPHA_SATURATE;
279 case PIPE_BLENDFACTOR_CONST_COLOR:
280 return V_028780_BLEND_CONSTANT_COLOR;
281 case PIPE_BLENDFACTOR_CONST_ALPHA:
282 return V_028780_BLEND_CONSTANT_ALPHA;
283 case PIPE_BLENDFACTOR_ZERO:
284 return V_028780_BLEND_ZERO;
285 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
286 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
287 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
288 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
289 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
290 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
291 case PIPE_BLENDFACTOR_INV_DST_COLOR:
292 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
293 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
294 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
295 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
296 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
297 case PIPE_BLENDFACTOR_SRC1_COLOR:
298 return V_028780_BLEND_SRC1_COLOR;
299 case PIPE_BLENDFACTOR_SRC1_ALPHA:
300 return V_028780_BLEND_SRC1_ALPHA;
301 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
302 return V_028780_BLEND_INV_SRC1_COLOR;
303 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
304 return V_028780_BLEND_INV_SRC1_ALPHA;
305 default:
306 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
307 assert(0);
308 break;
309 }
310 return 0;
311 }
312
313 static void *si_create_blend_state_mode(struct pipe_context *ctx,
314 const struct pipe_blend_state *state,
315 unsigned mode)
316 {
317 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
318 struct si_pm4_state *pm4 = &blend->pm4;
319
320 uint32_t color_control = 0;
321
322 if (blend == NULL)
323 return NULL;
324
325 blend->alpha_to_one = state->alpha_to_one;
326
327 if (state->logicop_enable) {
328 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
329 } else {
330 color_control |= S_028808_ROP3(0xcc);
331 }
332
333 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
334 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
335 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
336 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
337 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
338 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
339
340 blend->cb_target_mask = 0;
341 for (int i = 0; i < 8; i++) {
342 /* state->rt entries > 0 only written if independent blending */
343 const int j = state->independent_blend_enable ? i : 0;
344
345 unsigned eqRGB = state->rt[j].rgb_func;
346 unsigned srcRGB = state->rt[j].rgb_src_factor;
347 unsigned dstRGB = state->rt[j].rgb_dst_factor;
348 unsigned eqA = state->rt[j].alpha_func;
349 unsigned srcA = state->rt[j].alpha_src_factor;
350 unsigned dstA = state->rt[j].alpha_dst_factor;
351
352 unsigned blend_cntl = 0;
353
354 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
355 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
356
357 if (!state->rt[j].blend_enable) {
358 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
359 continue;
360 }
361
362 blend_cntl |= S_028780_ENABLE(1);
363 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
364 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
365 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
366
367 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
368 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
369 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
370 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
371 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
372 }
373 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
374 }
375
376 if (blend->cb_target_mask) {
377 color_control |= S_028808_MODE(mode);
378 } else {
379 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
380 }
381 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
382
383 return blend;
384 }
385
386 static void *si_create_blend_state(struct pipe_context *ctx,
387 const struct pipe_blend_state *state)
388 {
389 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
390 }
391
392 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
393 {
394 struct si_context *sctx = (struct si_context *)ctx;
395 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
396 si_update_fb_blend_state(sctx);
397 }
398
399 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
400 {
401 struct si_context *sctx = (struct si_context *)ctx;
402 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
403 }
404
405 static void si_set_blend_color(struct pipe_context *ctx,
406 const struct pipe_blend_color *state)
407 {
408 struct si_context *sctx = (struct si_context *)ctx;
409 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
410
411 if (pm4 == NULL)
412 return;
413
414 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
415 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
416 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
417 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
418
419 si_pm4_set_state(sctx, blend_color, pm4);
420 }
421
422 /*
423 * Clipping, scissors and viewport
424 */
425
426 static void si_set_clip_state(struct pipe_context *ctx,
427 const struct pipe_clip_state *state)
428 {
429 struct si_context *sctx = (struct si_context *)ctx;
430 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
431 struct pipe_constant_buffer cb;
432
433 if (pm4 == NULL)
434 return;
435
436 for (int i = 0; i < 6; i++) {
437 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
438 fui(state->ucp[i][0]));
439 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
440 fui(state->ucp[i][1]));
441 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
442 fui(state->ucp[i][2]));
443 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
444 fui(state->ucp[i][3]));
445 }
446
447 cb.buffer = NULL;
448 cb.user_buffer = state->ucp;
449 cb.buffer_offset = 0;
450 cb.buffer_size = 4*4*8;
451 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
452 pipe_resource_reference(&cb.buffer, NULL);
453
454 si_pm4_set_state(sctx, clip, pm4);
455 }
456
457 static void si_set_scissor_states(struct pipe_context *ctx,
458 unsigned start_slot,
459 unsigned num_scissors,
460 const struct pipe_scissor_state *state)
461 {
462 struct si_context *sctx = (struct si_context *)ctx;
463 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
464 struct si_pm4_state *pm4 = &scissor->pm4;
465
466 if (scissor == NULL)
467 return;
468
469 scissor->scissor = *state;
470 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
471 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
472 S_028250_WINDOW_OFFSET_DISABLE(1));
473 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
474 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
475
476 si_pm4_set_state(sctx, scissor, scissor);
477 }
478
479 static void si_set_viewport_states(struct pipe_context *ctx,
480 unsigned start_slot,
481 unsigned num_viewports,
482 const struct pipe_viewport_state *state)
483 {
484 struct si_context *sctx = (struct si_context *)ctx;
485 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
486 struct si_pm4_state *pm4 = &viewport->pm4;
487
488 if (viewport == NULL)
489 return;
490
491 viewport->viewport = *state;
492 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
493 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
494 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
495 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
496 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
497 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
498
499 si_pm4_set_state(sctx, viewport, viewport);
500 }
501
502 /*
503 * inferred state between framebuffer and rasterizer
504 */
505 static void si_update_fb_rs_state(struct si_context *sctx)
506 {
507 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
508 struct si_pm4_state *pm4;
509 float offset_units;
510
511 if (!rs || !sctx->framebuffer.state.zsbuf)
512 return;
513
514 offset_units = sctx->queued.named.rasterizer->offset_units;
515 switch (sctx->framebuffer.state.zsbuf->texture->format) {
516 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
517 case PIPE_FORMAT_X8Z24_UNORM:
518 case PIPE_FORMAT_Z24X8_UNORM:
519 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
520 offset_units *= 2.0f;
521 break;
522 case PIPE_FORMAT_Z32_FLOAT:
523 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
524 offset_units *= 1.0f;
525 break;
526 case PIPE_FORMAT_Z16_UNORM:
527 offset_units *= 4.0f;
528 break;
529 default:
530 return;
531 }
532
533 pm4 = si_pm4_alloc_state(sctx);
534
535 if (pm4 == NULL)
536 return;
537
538 /* FIXME some of those reg can be computed with cso */
539 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
540 fui(sctx->queued.named.rasterizer->offset_scale));
541 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
542 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
543 fui(sctx->queued.named.rasterizer->offset_scale));
544 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
545
546 si_pm4_set_state(sctx, fb_rs, pm4);
547 }
548
549 /*
550 * Rasterizer
551 */
552
553 static uint32_t si_translate_fill(uint32_t func)
554 {
555 switch(func) {
556 case PIPE_POLYGON_MODE_FILL:
557 return V_028814_X_DRAW_TRIANGLES;
558 case PIPE_POLYGON_MODE_LINE:
559 return V_028814_X_DRAW_LINES;
560 case PIPE_POLYGON_MODE_POINT:
561 return V_028814_X_DRAW_POINTS;
562 default:
563 assert(0);
564 return V_028814_X_DRAW_POINTS;
565 }
566 }
567
568 static void *si_create_rs_state(struct pipe_context *ctx,
569 const struct pipe_rasterizer_state *state)
570 {
571 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
572 struct si_pm4_state *pm4 = &rs->pm4;
573 unsigned tmp;
574 unsigned prov_vtx = 1, polygon_dual_mode;
575 float psize_min, psize_max;
576
577 if (rs == NULL) {
578 return NULL;
579 }
580
581 rs->two_side = state->light_twoside;
582 rs->multisample_enable = state->multisample;
583 rs->clip_plane_enable = state->clip_plane_enable;
584 rs->line_stipple_enable = state->line_stipple_enable;
585
586 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
587 state->fill_back != PIPE_POLYGON_MODE_FILL);
588
589 if (state->flatshade_first)
590 prov_vtx = 0;
591
592 rs->flatshade = state->flatshade;
593 rs->sprite_coord_enable = state->sprite_coord_enable;
594 rs->pa_sc_line_stipple = state->line_stipple_enable ?
595 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
596 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
597 rs->pa_su_sc_mode_cntl =
598 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
599 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
600 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
601 S_028814_FACE(!state->front_ccw) |
602 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
603 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
604 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
605 S_028814_POLY_MODE(polygon_dual_mode) |
606 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
607 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
608 rs->pa_cl_clip_cntl =
609 S_028810_PS_UCP_MODE(3) |
610 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
611 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
612 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
613 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
614
615 /* offset */
616 rs->offset_units = state->offset_units;
617 rs->offset_scale = state->offset_scale * 12.0f;
618
619 tmp = S_0286D4_FLAT_SHADE_ENA(1);
620 if (state->sprite_coord_enable) {
621 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
622 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
623 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
624 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
625 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
626 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
627 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
628 }
629 }
630 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
631
632 /* point size 12.4 fixed point */
633 tmp = (unsigned)(state->point_size * 8.0);
634 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
635
636 if (state->point_size_per_vertex) {
637 psize_min = util_get_min_point_size(state);
638 psize_max = 8192;
639 } else {
640 /* Force the point size to be as if the vertex output was disabled. */
641 psize_min = state->point_size;
642 psize_max = state->point_size;
643 }
644 /* Divide by two, because 0.5 = 1 pixel. */
645 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
646 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
647 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
648
649 tmp = (unsigned)state->line_width * 8;
650 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
651 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
652 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
653 S_028A48_MSAA_ENABLE(state->multisample) |
654 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
655
656 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
657 S_028BE4_PIX_CENTER(state->half_pixel_center) |
658 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
659
660 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
661
662 return rs;
663 }
664
665 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
666 {
667 struct si_context *sctx = (struct si_context *)ctx;
668 struct si_state_rasterizer *old_rs =
669 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
670 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
671
672 if (state == NULL)
673 return;
674
675 // TODO
676 sctx->sprite_coord_enable = rs->sprite_coord_enable;
677 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
678 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
679
680 if (sctx->framebuffer.nr_samples > 1 &&
681 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
682 sctx->db_render_state.dirty = true;
683
684 si_pm4_bind_state(sctx, rasterizer, rs);
685 si_update_fb_rs_state(sctx);
686 }
687
688 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
689 {
690 struct si_context *sctx = (struct si_context *)ctx;
691 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
692 }
693
694 /*
695 * infeered state between dsa and stencil ref
696 */
697 static void si_update_dsa_stencil_ref(struct si_context *sctx)
698 {
699 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
700 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
701 struct si_state_dsa *dsa = sctx->queued.named.dsa;
702
703 if (pm4 == NULL)
704 return;
705
706 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
707 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
708 S_028430_STENCILMASK(dsa->valuemask[0]) |
709 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
710 S_028430_STENCILOPVAL(1));
711 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
712 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
713 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
714 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
715 S_028434_STENCILOPVAL_BF(1));
716
717 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
718 }
719
720 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
721 const struct pipe_stencil_ref *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 sctx->stencil_ref = *state;
725 si_update_dsa_stencil_ref(sctx);
726 }
727
728
729 /*
730 * DSA
731 */
732
733 static uint32_t si_translate_stencil_op(int s_op)
734 {
735 switch (s_op) {
736 case PIPE_STENCIL_OP_KEEP:
737 return V_02842C_STENCIL_KEEP;
738 case PIPE_STENCIL_OP_ZERO:
739 return V_02842C_STENCIL_ZERO;
740 case PIPE_STENCIL_OP_REPLACE:
741 return V_02842C_STENCIL_REPLACE_TEST;
742 case PIPE_STENCIL_OP_INCR:
743 return V_02842C_STENCIL_ADD_CLAMP;
744 case PIPE_STENCIL_OP_DECR:
745 return V_02842C_STENCIL_SUB_CLAMP;
746 case PIPE_STENCIL_OP_INCR_WRAP:
747 return V_02842C_STENCIL_ADD_WRAP;
748 case PIPE_STENCIL_OP_DECR_WRAP:
749 return V_02842C_STENCIL_SUB_WRAP;
750 case PIPE_STENCIL_OP_INVERT:
751 return V_02842C_STENCIL_INVERT;
752 default:
753 R600_ERR("Unknown stencil op %d", s_op);
754 assert(0);
755 break;
756 }
757 return 0;
758 }
759
760 static void *si_create_dsa_state(struct pipe_context *ctx,
761 const struct pipe_depth_stencil_alpha_state *state)
762 {
763 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
764 struct si_pm4_state *pm4 = &dsa->pm4;
765 unsigned db_depth_control;
766 uint32_t db_stencil_control = 0;
767
768 if (dsa == NULL) {
769 return NULL;
770 }
771
772 dsa->valuemask[0] = state->stencil[0].valuemask;
773 dsa->valuemask[1] = state->stencil[1].valuemask;
774 dsa->writemask[0] = state->stencil[0].writemask;
775 dsa->writemask[1] = state->stencil[1].writemask;
776
777 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
778 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
779 S_028800_ZFUNC(state->depth.func);
780
781 /* stencil */
782 if (state->stencil[0].enabled) {
783 db_depth_control |= S_028800_STENCIL_ENABLE(1);
784 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
785 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
786 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
787 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
788
789 if (state->stencil[1].enabled) {
790 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
791 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
792 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
793 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
794 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
795 }
796 }
797
798 /* alpha */
799 if (state->alpha.enabled) {
800 dsa->alpha_func = state->alpha.func;
801 dsa->alpha_ref = state->alpha.ref_value;
802
803 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
804 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
805 } else {
806 dsa->alpha_func = PIPE_FUNC_ALWAYS;
807 }
808
809 /* misc */
810 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
811 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
812
813 return dsa;
814 }
815
816 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
817 {
818 struct si_context *sctx = (struct si_context *)ctx;
819 struct si_state_dsa *dsa = state;
820
821 if (state == NULL)
822 return;
823
824 si_pm4_bind_state(sctx, dsa, dsa);
825 si_update_dsa_stencil_ref(sctx);
826 }
827
828 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
829 {
830 struct si_context *sctx = (struct si_context *)ctx;
831 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
832 }
833
834 static void *si_create_db_flush_dsa(struct si_context *sctx)
835 {
836 struct pipe_depth_stencil_alpha_state dsa = {};
837
838 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
839 }
840
841 /* DB RENDER STATE */
842
843 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
844 {
845 struct si_context *sctx = (struct si_context*)ctx;
846
847 sctx->db_render_state.dirty = true;
848 }
849
850 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
851 {
852 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
853 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
854 unsigned db_shader_control;
855
856 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
857
858 /* DB_RENDER_CONTROL */
859 if (sctx->dbcb_depth_copy_enabled ||
860 sctx->dbcb_stencil_copy_enabled) {
861 radeon_emit(cs,
862 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
863 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
864 S_028000_COPY_CENTROID(1) |
865 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
866 } else if (sctx->db_inplace_flush_enabled) {
867 radeon_emit(cs,
868 S_028000_DEPTH_COMPRESS_DISABLE(1) |
869 S_028000_STENCIL_COMPRESS_DISABLE(1));
870 } else if (sctx->db_depth_clear) {
871 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
872 } else {
873 radeon_emit(cs, 0);
874 }
875
876 /* DB_COUNT_CONTROL (occlusion queries) */
877 if (sctx->b.num_occlusion_queries > 0) {
878 if (sctx->b.chip_class >= CIK) {
879 radeon_emit(cs,
880 S_028004_PERFECT_ZPASS_COUNTS(1) |
881 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
882 S_028004_ZPASS_ENABLE(1) |
883 S_028004_SLICE_EVEN_ENABLE(1) |
884 S_028004_SLICE_ODD_ENABLE(1));
885 } else {
886 radeon_emit(cs,
887 S_028004_PERFECT_ZPASS_COUNTS(1) |
888 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
889 }
890 } else {
891 /* Disable occlusion queries. */
892 if (sctx->b.chip_class >= CIK) {
893 radeon_emit(cs, 0);
894 } else {
895 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
896 }
897 }
898
899 /* DB_RENDER_OVERRIDE2 */
900 if (sctx->db_depth_disable_expclear) {
901 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
902 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
903 } else {
904 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
905 }
906
907 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
908 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
909 sctx->ps_db_shader_control;
910
911 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
912 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
913 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
914
915 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
916 db_shader_control);
917 }
918
919 /*
920 * format translation
921 */
922 static uint32_t si_translate_colorformat(enum pipe_format format)
923 {
924 const struct util_format_description *desc = util_format_description(format);
925
926 #define HAS_SIZE(x,y,z,w) \
927 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
928 desc->channel[2].size == (z) && desc->channel[3].size == (w))
929
930 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
931 return V_028C70_COLOR_10_11_11;
932
933 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
934 return V_028C70_COLOR_INVALID;
935
936 switch (desc->nr_channels) {
937 case 1:
938 switch (desc->channel[0].size) {
939 case 8:
940 return V_028C70_COLOR_8;
941 case 16:
942 return V_028C70_COLOR_16;
943 case 32:
944 return V_028C70_COLOR_32;
945 }
946 break;
947 case 2:
948 if (desc->channel[0].size == desc->channel[1].size) {
949 switch (desc->channel[0].size) {
950 case 8:
951 return V_028C70_COLOR_8_8;
952 case 16:
953 return V_028C70_COLOR_16_16;
954 case 32:
955 return V_028C70_COLOR_32_32;
956 }
957 } else if (HAS_SIZE(8,24,0,0)) {
958 return V_028C70_COLOR_24_8;
959 } else if (HAS_SIZE(24,8,0,0)) {
960 return V_028C70_COLOR_8_24;
961 }
962 break;
963 case 3:
964 if (HAS_SIZE(5,6,5,0)) {
965 return V_028C70_COLOR_5_6_5;
966 } else if (HAS_SIZE(32,8,24,0)) {
967 return V_028C70_COLOR_X24_8_32_FLOAT;
968 }
969 break;
970 case 4:
971 if (desc->channel[0].size == desc->channel[1].size &&
972 desc->channel[0].size == desc->channel[2].size &&
973 desc->channel[0].size == desc->channel[3].size) {
974 switch (desc->channel[0].size) {
975 case 4:
976 return V_028C70_COLOR_4_4_4_4;
977 case 8:
978 return V_028C70_COLOR_8_8_8_8;
979 case 16:
980 return V_028C70_COLOR_16_16_16_16;
981 case 32:
982 return V_028C70_COLOR_32_32_32_32;
983 }
984 } else if (HAS_SIZE(5,5,5,1)) {
985 return V_028C70_COLOR_1_5_5_5;
986 } else if (HAS_SIZE(10,10,10,2)) {
987 return V_028C70_COLOR_2_10_10_10;
988 }
989 break;
990 }
991 return V_028C70_COLOR_INVALID;
992 }
993
994 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
995 {
996 if (SI_BIG_ENDIAN) {
997 switch(colorformat) {
998 /* 8-bit buffers. */
999 case V_028C70_COLOR_8:
1000 return V_028C70_ENDIAN_NONE;
1001
1002 /* 16-bit buffers. */
1003 case V_028C70_COLOR_5_6_5:
1004 case V_028C70_COLOR_1_5_5_5:
1005 case V_028C70_COLOR_4_4_4_4:
1006 case V_028C70_COLOR_16:
1007 case V_028C70_COLOR_8_8:
1008 return V_028C70_ENDIAN_8IN16;
1009
1010 /* 32-bit buffers. */
1011 case V_028C70_COLOR_8_8_8_8:
1012 case V_028C70_COLOR_2_10_10_10:
1013 case V_028C70_COLOR_8_24:
1014 case V_028C70_COLOR_24_8:
1015 case V_028C70_COLOR_16_16:
1016 return V_028C70_ENDIAN_8IN32;
1017
1018 /* 64-bit buffers. */
1019 case V_028C70_COLOR_16_16_16_16:
1020 return V_028C70_ENDIAN_8IN16;
1021
1022 case V_028C70_COLOR_32_32:
1023 return V_028C70_ENDIAN_8IN32;
1024
1025 /* 128-bit buffers. */
1026 case V_028C70_COLOR_32_32_32_32:
1027 return V_028C70_ENDIAN_8IN32;
1028 default:
1029 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1030 }
1031 } else {
1032 return V_028C70_ENDIAN_NONE;
1033 }
1034 }
1035
1036 /* Returns the size in bits of the widest component of a CB format */
1037 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1038 {
1039 switch(colorformat) {
1040 case V_028C70_COLOR_4_4_4_4:
1041 return 4;
1042
1043 case V_028C70_COLOR_1_5_5_5:
1044 case V_028C70_COLOR_5_5_5_1:
1045 return 5;
1046
1047 case V_028C70_COLOR_5_6_5:
1048 return 6;
1049
1050 case V_028C70_COLOR_8:
1051 case V_028C70_COLOR_8_8:
1052 case V_028C70_COLOR_8_8_8_8:
1053 return 8;
1054
1055 case V_028C70_COLOR_10_10_10_2:
1056 case V_028C70_COLOR_2_10_10_10:
1057 return 10;
1058
1059 case V_028C70_COLOR_10_11_11:
1060 case V_028C70_COLOR_11_11_10:
1061 return 11;
1062
1063 case V_028C70_COLOR_16:
1064 case V_028C70_COLOR_16_16:
1065 case V_028C70_COLOR_16_16_16_16:
1066 return 16;
1067
1068 case V_028C70_COLOR_8_24:
1069 case V_028C70_COLOR_24_8:
1070 return 24;
1071
1072 case V_028C70_COLOR_32:
1073 case V_028C70_COLOR_32_32:
1074 case V_028C70_COLOR_32_32_32_32:
1075 case V_028C70_COLOR_X24_8_32_FLOAT:
1076 return 32;
1077 }
1078
1079 assert(!"Unknown maximum component size");
1080 return 0;
1081 }
1082
1083 static uint32_t si_translate_dbformat(enum pipe_format format)
1084 {
1085 switch (format) {
1086 case PIPE_FORMAT_Z16_UNORM:
1087 return V_028040_Z_16;
1088 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1089 case PIPE_FORMAT_X8Z24_UNORM:
1090 case PIPE_FORMAT_Z24X8_UNORM:
1091 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1092 return V_028040_Z_24; /* deprecated on SI */
1093 case PIPE_FORMAT_Z32_FLOAT:
1094 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1095 return V_028040_Z_32_FLOAT;
1096 default:
1097 return V_028040_Z_INVALID;
1098 }
1099 }
1100
1101 /*
1102 * Texture translation
1103 */
1104
1105 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1106 enum pipe_format format,
1107 const struct util_format_description *desc,
1108 int first_non_void)
1109 {
1110 struct si_screen *sscreen = (struct si_screen*)screen;
1111 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1112 boolean uniform = TRUE;
1113 int i;
1114
1115 /* Colorspace (return non-RGB formats directly). */
1116 switch (desc->colorspace) {
1117 /* Depth stencil formats */
1118 case UTIL_FORMAT_COLORSPACE_ZS:
1119 switch (format) {
1120 case PIPE_FORMAT_Z16_UNORM:
1121 return V_008F14_IMG_DATA_FORMAT_16;
1122 case PIPE_FORMAT_X24S8_UINT:
1123 case PIPE_FORMAT_Z24X8_UNORM:
1124 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1125 return V_008F14_IMG_DATA_FORMAT_8_24;
1126 case PIPE_FORMAT_X8Z24_UNORM:
1127 case PIPE_FORMAT_S8X24_UINT:
1128 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1129 return V_008F14_IMG_DATA_FORMAT_24_8;
1130 case PIPE_FORMAT_S8_UINT:
1131 return V_008F14_IMG_DATA_FORMAT_8;
1132 case PIPE_FORMAT_Z32_FLOAT:
1133 return V_008F14_IMG_DATA_FORMAT_32;
1134 case PIPE_FORMAT_X32_S8X24_UINT:
1135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1136 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1137 default:
1138 goto out_unknown;
1139 }
1140
1141 case UTIL_FORMAT_COLORSPACE_YUV:
1142 goto out_unknown; /* TODO */
1143
1144 case UTIL_FORMAT_COLORSPACE_SRGB:
1145 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1146 goto out_unknown;
1147 break;
1148
1149 default:
1150 break;
1151 }
1152
1153 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1154 if (!enable_s3tc)
1155 goto out_unknown;
1156
1157 switch (format) {
1158 case PIPE_FORMAT_RGTC1_SNORM:
1159 case PIPE_FORMAT_LATC1_SNORM:
1160 case PIPE_FORMAT_RGTC1_UNORM:
1161 case PIPE_FORMAT_LATC1_UNORM:
1162 return V_008F14_IMG_DATA_FORMAT_BC4;
1163 case PIPE_FORMAT_RGTC2_SNORM:
1164 case PIPE_FORMAT_LATC2_SNORM:
1165 case PIPE_FORMAT_RGTC2_UNORM:
1166 case PIPE_FORMAT_LATC2_UNORM:
1167 return V_008F14_IMG_DATA_FORMAT_BC5;
1168 default:
1169 goto out_unknown;
1170 }
1171 }
1172
1173 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1174 if (!enable_s3tc)
1175 goto out_unknown;
1176
1177 switch (format) {
1178 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1179 case PIPE_FORMAT_BPTC_SRGBA:
1180 return V_008F14_IMG_DATA_FORMAT_BC7;
1181 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1182 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1183 return V_008F14_IMG_DATA_FORMAT_BC6;
1184 default:
1185 goto out_unknown;
1186 }
1187 }
1188
1189 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1190 switch (format) {
1191 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1192 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1193 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1194 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1195 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1196 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1197 default:
1198 goto out_unknown;
1199 }
1200 }
1201
1202 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1203
1204 if (!enable_s3tc)
1205 goto out_unknown;
1206
1207 if (!util_format_s3tc_enabled) {
1208 goto out_unknown;
1209 }
1210
1211 switch (format) {
1212 case PIPE_FORMAT_DXT1_RGB:
1213 case PIPE_FORMAT_DXT1_RGBA:
1214 case PIPE_FORMAT_DXT1_SRGB:
1215 case PIPE_FORMAT_DXT1_SRGBA:
1216 return V_008F14_IMG_DATA_FORMAT_BC1;
1217 case PIPE_FORMAT_DXT3_RGBA:
1218 case PIPE_FORMAT_DXT3_SRGBA:
1219 return V_008F14_IMG_DATA_FORMAT_BC2;
1220 case PIPE_FORMAT_DXT5_RGBA:
1221 case PIPE_FORMAT_DXT5_SRGBA:
1222 return V_008F14_IMG_DATA_FORMAT_BC3;
1223 default:
1224 goto out_unknown;
1225 }
1226 }
1227
1228 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1229 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1230 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1231 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1232 }
1233
1234 /* R8G8Bx_SNORM - TODO CxV8U8 */
1235
1236 /* See whether the components are of the same size. */
1237 for (i = 1; i < desc->nr_channels; i++) {
1238 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1239 }
1240
1241 /* Non-uniform formats. */
1242 if (!uniform) {
1243 switch(desc->nr_channels) {
1244 case 3:
1245 if (desc->channel[0].size == 5 &&
1246 desc->channel[1].size == 6 &&
1247 desc->channel[2].size == 5) {
1248 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1249 }
1250 goto out_unknown;
1251 case 4:
1252 if (desc->channel[0].size == 5 &&
1253 desc->channel[1].size == 5 &&
1254 desc->channel[2].size == 5 &&
1255 desc->channel[3].size == 1) {
1256 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1257 }
1258 if (desc->channel[0].size == 10 &&
1259 desc->channel[1].size == 10 &&
1260 desc->channel[2].size == 10 &&
1261 desc->channel[3].size == 2) {
1262 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1263 }
1264 goto out_unknown;
1265 }
1266 goto out_unknown;
1267 }
1268
1269 if (first_non_void < 0 || first_non_void > 3)
1270 goto out_unknown;
1271
1272 /* uniform formats */
1273 switch (desc->channel[first_non_void].size) {
1274 case 4:
1275 switch (desc->nr_channels) {
1276 #if 0 /* Not supported for render targets */
1277 case 2:
1278 return V_008F14_IMG_DATA_FORMAT_4_4;
1279 #endif
1280 case 4:
1281 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1282 }
1283 break;
1284 case 8:
1285 switch (desc->nr_channels) {
1286 case 1:
1287 return V_008F14_IMG_DATA_FORMAT_8;
1288 case 2:
1289 return V_008F14_IMG_DATA_FORMAT_8_8;
1290 case 4:
1291 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1292 }
1293 break;
1294 case 16:
1295 switch (desc->nr_channels) {
1296 case 1:
1297 return V_008F14_IMG_DATA_FORMAT_16;
1298 case 2:
1299 return V_008F14_IMG_DATA_FORMAT_16_16;
1300 case 4:
1301 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1302 }
1303 break;
1304 case 32:
1305 switch (desc->nr_channels) {
1306 case 1:
1307 return V_008F14_IMG_DATA_FORMAT_32;
1308 case 2:
1309 return V_008F14_IMG_DATA_FORMAT_32_32;
1310 #if 0 /* Not supported for render targets */
1311 case 3:
1312 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1313 #endif
1314 case 4:
1315 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1316 }
1317 }
1318
1319 out_unknown:
1320 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1321 return ~0;
1322 }
1323
1324 static unsigned si_tex_wrap(unsigned wrap)
1325 {
1326 switch (wrap) {
1327 default:
1328 case PIPE_TEX_WRAP_REPEAT:
1329 return V_008F30_SQ_TEX_WRAP;
1330 case PIPE_TEX_WRAP_CLAMP:
1331 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1332 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1333 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1334 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1335 return V_008F30_SQ_TEX_CLAMP_BORDER;
1336 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1337 return V_008F30_SQ_TEX_MIRROR;
1338 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1339 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1340 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1341 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1342 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1343 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1344 }
1345 }
1346
1347 static unsigned si_tex_filter(unsigned filter)
1348 {
1349 switch (filter) {
1350 default:
1351 case PIPE_TEX_FILTER_NEAREST:
1352 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1353 case PIPE_TEX_FILTER_LINEAR:
1354 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1355 }
1356 }
1357
1358 static unsigned si_tex_mipfilter(unsigned filter)
1359 {
1360 switch (filter) {
1361 case PIPE_TEX_MIPFILTER_NEAREST:
1362 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1363 case PIPE_TEX_MIPFILTER_LINEAR:
1364 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1365 default:
1366 case PIPE_TEX_MIPFILTER_NONE:
1367 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1368 }
1369 }
1370
1371 static unsigned si_tex_compare(unsigned compare)
1372 {
1373 switch (compare) {
1374 default:
1375 case PIPE_FUNC_NEVER:
1376 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1377 case PIPE_FUNC_LESS:
1378 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1379 case PIPE_FUNC_EQUAL:
1380 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1381 case PIPE_FUNC_LEQUAL:
1382 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1383 case PIPE_FUNC_GREATER:
1384 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1385 case PIPE_FUNC_NOTEQUAL:
1386 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1387 case PIPE_FUNC_GEQUAL:
1388 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1389 case PIPE_FUNC_ALWAYS:
1390 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1391 }
1392 }
1393
1394 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1395 {
1396 switch (dim) {
1397 default:
1398 case PIPE_TEXTURE_1D:
1399 return V_008F1C_SQ_RSRC_IMG_1D;
1400 case PIPE_TEXTURE_1D_ARRAY:
1401 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1402 case PIPE_TEXTURE_2D:
1403 case PIPE_TEXTURE_RECT:
1404 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1405 V_008F1C_SQ_RSRC_IMG_2D;
1406 case PIPE_TEXTURE_2D_ARRAY:
1407 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1408 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1409 case PIPE_TEXTURE_3D:
1410 return V_008F1C_SQ_RSRC_IMG_3D;
1411 case PIPE_TEXTURE_CUBE:
1412 case PIPE_TEXTURE_CUBE_ARRAY:
1413 return V_008F1C_SQ_RSRC_IMG_CUBE;
1414 }
1415 }
1416
1417 /*
1418 * Format support testing
1419 */
1420
1421 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1422 {
1423 return si_translate_texformat(screen, format, util_format_description(format),
1424 util_format_get_first_non_void_channel(format)) != ~0U;
1425 }
1426
1427 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1428 const struct util_format_description *desc,
1429 int first_non_void)
1430 {
1431 unsigned type = desc->channel[first_non_void].type;
1432 int i;
1433
1434 if (type == UTIL_FORMAT_TYPE_FIXED)
1435 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1436
1437 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1438 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1439
1440 if (desc->nr_channels == 4 &&
1441 desc->channel[0].size == 10 &&
1442 desc->channel[1].size == 10 &&
1443 desc->channel[2].size == 10 &&
1444 desc->channel[3].size == 2)
1445 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1446
1447 /* See whether the components are of the same size. */
1448 for (i = 0; i < desc->nr_channels; i++) {
1449 if (desc->channel[first_non_void].size != desc->channel[i].size)
1450 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1451 }
1452
1453 switch (desc->channel[first_non_void].size) {
1454 case 8:
1455 switch (desc->nr_channels) {
1456 case 1:
1457 return V_008F0C_BUF_DATA_FORMAT_8;
1458 case 2:
1459 return V_008F0C_BUF_DATA_FORMAT_8_8;
1460 case 3:
1461 case 4:
1462 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1463 }
1464 break;
1465 case 16:
1466 switch (desc->nr_channels) {
1467 case 1:
1468 return V_008F0C_BUF_DATA_FORMAT_16;
1469 case 2:
1470 return V_008F0C_BUF_DATA_FORMAT_16_16;
1471 case 3:
1472 case 4:
1473 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1474 }
1475 break;
1476 case 32:
1477 /* From the Southern Islands ISA documentation about MTBUF:
1478 * 'Memory reads of data in memory that is 32 or 64 bits do not
1479 * undergo any format conversion.'
1480 */
1481 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1482 !desc->channel[first_non_void].pure_integer)
1483 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1484
1485 switch (desc->nr_channels) {
1486 case 1:
1487 return V_008F0C_BUF_DATA_FORMAT_32;
1488 case 2:
1489 return V_008F0C_BUF_DATA_FORMAT_32_32;
1490 case 3:
1491 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1492 case 4:
1493 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1494 }
1495 break;
1496 }
1497
1498 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1499 }
1500
1501 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1502 const struct util_format_description *desc,
1503 int first_non_void)
1504 {
1505 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1506 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1507
1508 switch (desc->channel[first_non_void].type) {
1509 case UTIL_FORMAT_TYPE_SIGNED:
1510 if (desc->channel[first_non_void].normalized)
1511 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1512 else if (desc->channel[first_non_void].pure_integer)
1513 return V_008F0C_BUF_NUM_FORMAT_SINT;
1514 else
1515 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1516 break;
1517 case UTIL_FORMAT_TYPE_UNSIGNED:
1518 if (desc->channel[first_non_void].normalized)
1519 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1520 else if (desc->channel[first_non_void].pure_integer)
1521 return V_008F0C_BUF_NUM_FORMAT_UINT;
1522 else
1523 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1524 break;
1525 case UTIL_FORMAT_TYPE_FLOAT:
1526 default:
1527 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1528 }
1529 }
1530
1531 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1532 {
1533 const struct util_format_description *desc;
1534 int first_non_void;
1535 unsigned data_format;
1536
1537 desc = util_format_description(format);
1538 first_non_void = util_format_get_first_non_void_channel(format);
1539 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1540 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1541 }
1542
1543 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1544 {
1545 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1546 r600_translate_colorswap(format) != ~0U;
1547 }
1548
1549 static bool si_is_zs_format_supported(enum pipe_format format)
1550 {
1551 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1552 }
1553
1554 boolean si_is_format_supported(struct pipe_screen *screen,
1555 enum pipe_format format,
1556 enum pipe_texture_target target,
1557 unsigned sample_count,
1558 unsigned usage)
1559 {
1560 struct si_screen *sscreen = (struct si_screen *)screen;
1561 unsigned retval = 0;
1562
1563 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1564 R600_ERR("r600: unsupported texture type %d\n", target);
1565 return FALSE;
1566 }
1567
1568 if (!util_format_is_supported(format, usage))
1569 return FALSE;
1570
1571 if (sample_count > 1) {
1572 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1573 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1574 return FALSE;
1575
1576 switch (sample_count) {
1577 case 2:
1578 case 4:
1579 case 8:
1580 break;
1581 default:
1582 return FALSE;
1583 }
1584 }
1585
1586 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1587 if (target == PIPE_BUFFER) {
1588 if (si_is_vertex_format_supported(screen, format))
1589 retval |= PIPE_BIND_SAMPLER_VIEW;
1590 } else {
1591 if (si_is_sampler_format_supported(screen, format))
1592 retval |= PIPE_BIND_SAMPLER_VIEW;
1593 }
1594 }
1595
1596 if ((usage & (PIPE_BIND_RENDER_TARGET |
1597 PIPE_BIND_DISPLAY_TARGET |
1598 PIPE_BIND_SCANOUT |
1599 PIPE_BIND_SHARED |
1600 PIPE_BIND_BLENDABLE)) &&
1601 si_is_colorbuffer_format_supported(format)) {
1602 retval |= usage &
1603 (PIPE_BIND_RENDER_TARGET |
1604 PIPE_BIND_DISPLAY_TARGET |
1605 PIPE_BIND_SCANOUT |
1606 PIPE_BIND_SHARED);
1607 if (!util_format_is_pure_integer(format) &&
1608 !util_format_is_depth_or_stencil(format))
1609 retval |= usage & PIPE_BIND_BLENDABLE;
1610 }
1611
1612 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1613 si_is_zs_format_supported(format)) {
1614 retval |= PIPE_BIND_DEPTH_STENCIL;
1615 }
1616
1617 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1618 si_is_vertex_format_supported(screen, format)) {
1619 retval |= PIPE_BIND_VERTEX_BUFFER;
1620 }
1621
1622 if (usage & PIPE_BIND_TRANSFER_READ)
1623 retval |= PIPE_BIND_TRANSFER_READ;
1624 if (usage & PIPE_BIND_TRANSFER_WRITE)
1625 retval |= PIPE_BIND_TRANSFER_WRITE;
1626
1627 return retval == usage;
1628 }
1629
1630 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1631 {
1632 unsigned tile_mode_index = 0;
1633
1634 if (stencil) {
1635 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1636 } else {
1637 tile_mode_index = rtex->surface.tiling_index[level];
1638 }
1639 return tile_mode_index;
1640 }
1641
1642 /*
1643 * framebuffer handling
1644 */
1645
1646 static void si_initialize_color_surface(struct si_context *sctx,
1647 struct r600_surface *surf)
1648 {
1649 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1650 unsigned level = surf->base.u.tex.level;
1651 uint64_t offset = rtex->surface.level[level].offset;
1652 unsigned pitch, slice;
1653 unsigned color_info, color_attrib, color_pitch, color_view;
1654 unsigned tile_mode_index;
1655 unsigned format, swap, ntype, endian;
1656 const struct util_format_description *desc;
1657 int i;
1658 unsigned blend_clamp = 0, blend_bypass = 0;
1659 unsigned max_comp_size;
1660
1661 /* Layered rendering doesn't work with LINEAR_GENERAL.
1662 * (LINEAR_ALIGNED and others work) */
1663 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1664 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1665 offset += rtex->surface.level[level].slice_size *
1666 surf->base.u.tex.first_layer;
1667 color_view = 0;
1668 } else {
1669 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1670 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1671 }
1672
1673 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1674 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1675 if (slice) {
1676 slice = slice - 1;
1677 }
1678
1679 tile_mode_index = si_tile_mode_index(rtex, level, false);
1680
1681 desc = util_format_description(surf->base.format);
1682 for (i = 0; i < 4; i++) {
1683 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1684 break;
1685 }
1686 }
1687 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1688 ntype = V_028C70_NUMBER_FLOAT;
1689 } else {
1690 ntype = V_028C70_NUMBER_UNORM;
1691 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1692 ntype = V_028C70_NUMBER_SRGB;
1693 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1694 if (desc->channel[i].pure_integer) {
1695 ntype = V_028C70_NUMBER_SINT;
1696 } else {
1697 assert(desc->channel[i].normalized);
1698 ntype = V_028C70_NUMBER_SNORM;
1699 }
1700 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1701 if (desc->channel[i].pure_integer) {
1702 ntype = V_028C70_NUMBER_UINT;
1703 } else {
1704 assert(desc->channel[i].normalized);
1705 ntype = V_028C70_NUMBER_UNORM;
1706 }
1707 }
1708 }
1709
1710 format = si_translate_colorformat(surf->base.format);
1711 if (format == V_028C70_COLOR_INVALID) {
1712 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1713 }
1714 assert(format != V_028C70_COLOR_INVALID);
1715 swap = r600_translate_colorswap(surf->base.format);
1716 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1717 endian = V_028C70_ENDIAN_NONE;
1718 } else {
1719 endian = si_colorformat_endian_swap(format);
1720 }
1721
1722 /* blend clamp should be set for all NORM/SRGB types */
1723 if (ntype == V_028C70_NUMBER_UNORM ||
1724 ntype == V_028C70_NUMBER_SNORM ||
1725 ntype == V_028C70_NUMBER_SRGB)
1726 blend_clamp = 1;
1727
1728 /* set blend bypass according to docs if SINT/UINT or
1729 8/24 COLOR variants */
1730 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1731 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1732 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1733 blend_clamp = 0;
1734 blend_bypass = 1;
1735 }
1736
1737 color_info = S_028C70_FORMAT(format) |
1738 S_028C70_COMP_SWAP(swap) |
1739 S_028C70_BLEND_CLAMP(blend_clamp) |
1740 S_028C70_BLEND_BYPASS(blend_bypass) |
1741 S_028C70_NUMBER_TYPE(ntype) |
1742 S_028C70_ENDIAN(endian);
1743
1744 color_pitch = S_028C64_TILE_MAX(pitch);
1745
1746 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1747 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1748
1749 if (rtex->resource.b.b.nr_samples > 1) {
1750 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1751
1752 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1753 S_028C74_NUM_FRAGMENTS(log_samples);
1754
1755 if (rtex->fmask.size) {
1756 color_info |= S_028C70_COMPRESSION(1);
1757 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1758
1759 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1760
1761 if (sctx->b.chip_class == SI) {
1762 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1763 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1764 }
1765 if (sctx->b.chip_class >= CIK) {
1766 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1767 }
1768 }
1769 }
1770
1771 offset += rtex->resource.gpu_address;
1772
1773 surf->cb_color_base = offset >> 8;
1774 surf->cb_color_pitch = color_pitch;
1775 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1776 surf->cb_color_view = color_view;
1777 surf->cb_color_info = color_info;
1778 surf->cb_color_attrib = color_attrib;
1779
1780 if (rtex->fmask.size) {
1781 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1782 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1783 } else {
1784 /* This must be set for fast clear to work without FMASK. */
1785 surf->cb_color_fmask = surf->cb_color_base;
1786 surf->cb_color_fmask_slice = surf->cb_color_slice;
1787 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1788
1789 if (sctx->b.chip_class == SI) {
1790 unsigned bankh = util_logbase2(rtex->surface.bankh);
1791 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1792 }
1793
1794 if (sctx->b.chip_class >= CIK) {
1795 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1796 }
1797 }
1798
1799 /* Determine pixel shader export format */
1800 max_comp_size = si_colorformat_max_comp_size(format);
1801 if (ntype == V_028C70_NUMBER_SRGB ||
1802 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1803 max_comp_size <= 10) ||
1804 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1805 surf->export_16bpc = true;
1806 }
1807
1808 surf->color_initialized = true;
1809 }
1810
1811 static void si_init_depth_surface(struct si_context *sctx,
1812 struct r600_surface *surf)
1813 {
1814 struct si_screen *sscreen = sctx->screen;
1815 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1816 unsigned level = surf->base.u.tex.level;
1817 struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
1818 unsigned format, tile_mode_index, array_mode;
1819 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1820 uint32_t z_info, s_info, db_depth_info;
1821 uint64_t z_offs, s_offs;
1822 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1823
1824 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1825 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1826 case PIPE_FORMAT_X8Z24_UNORM:
1827 case PIPE_FORMAT_Z24X8_UNORM:
1828 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1829 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1830 break;
1831 case PIPE_FORMAT_Z32_FLOAT:
1832 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1833 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1834 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1835 break;
1836 case PIPE_FORMAT_Z16_UNORM:
1837 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1838 break;
1839 default:
1840 assert(0);
1841 }
1842
1843 format = si_translate_dbformat(rtex->resource.b.b.format);
1844
1845 if (format == V_028040_Z_INVALID) {
1846 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1847 }
1848 assert(format != V_028040_Z_INVALID);
1849
1850 s_offs = z_offs = rtex->resource.gpu_address;
1851 z_offs += rtex->surface.level[level].offset;
1852 s_offs += rtex->surface.stencil_level[level].offset;
1853
1854 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1855
1856 z_info = S_028040_FORMAT(format);
1857 if (rtex->resource.b.b.nr_samples > 1) {
1858 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1859 }
1860
1861 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1862 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1863 else
1864 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1865
1866 if (sctx->b.chip_class >= CIK) {
1867 switch (rtex->surface.level[level].mode) {
1868 case RADEON_SURF_MODE_2D:
1869 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1870 break;
1871 case RADEON_SURF_MODE_1D:
1872 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1873 case RADEON_SURF_MODE_LINEAR:
1874 default:
1875 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1876 break;
1877 }
1878 tile_split = rtex->surface.tile_split;
1879 stile_split = rtex->surface.stencil_tile_split;
1880 macro_aspect = rtex->surface.mtilea;
1881 bankw = rtex->surface.bankw;
1882 bankh = rtex->surface.bankh;
1883 tile_split = cik_tile_split(tile_split);
1884 stile_split = cik_tile_split(stile_split);
1885 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1886 bankw = cik_bank_wh(bankw);
1887 bankh = cik_bank_wh(bankh);
1888 nbanks = si_num_banks(sscreen, rtex);
1889 tile_mode_index = si_tile_mode_index(rtex, level, false);
1890 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1891
1892 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1893 S_02803C_PIPE_CONFIG(pipe_config) |
1894 S_02803C_BANK_WIDTH(bankw) |
1895 S_02803C_BANK_HEIGHT(bankh) |
1896 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1897 S_02803C_NUM_BANKS(nbanks);
1898 z_info |= S_028040_TILE_SPLIT(tile_split);
1899 s_info |= S_028044_TILE_SPLIT(stile_split);
1900 } else {
1901 tile_mode_index = si_tile_mode_index(rtex, level, false);
1902 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1903 tile_mode_index = si_tile_mode_index(rtex, level, true);
1904 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1905 }
1906
1907 /* HiZ aka depth buffer htile */
1908 /* use htile only for first level */
1909 if (rtex->htile_buffer && !level) {
1910 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1911 S_028040_ALLOW_EXPCLEAR(1);
1912
1913 /* This is optimal for the clear value of 1.0 and using
1914 * the LESS and LEQUAL test functions. Set this to 0
1915 * for the opposite case. This can only be changed when
1916 * clearing. */
1917 z_info |= S_028040_ZRANGE_PRECISION(1);
1918
1919 /* Use all of the htile_buffer for depth, because we don't
1920 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1921 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1922
1923 uint64_t va = rtex->htile_buffer->gpu_address;
1924 db_htile_data_base = va >> 8;
1925 db_htile_surface = S_028ABC_FULL_CACHE(1);
1926 } else {
1927 db_htile_data_base = 0;
1928 db_htile_surface = 0;
1929 }
1930
1931 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1932
1933 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1934 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1935 surf->db_htile_data_base = db_htile_data_base;
1936 surf->db_depth_info = db_depth_info;
1937 surf->db_z_info = z_info;
1938 surf->db_stencil_info = s_info;
1939 surf->db_depth_base = z_offs >> 8;
1940 surf->db_stencil_base = s_offs >> 8;
1941 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1942 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1943 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1944 levelinfo->nblk_y) / 64 - 1);
1945 surf->db_htile_surface = db_htile_surface;
1946 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1947
1948 surf->depth_initialized = true;
1949 }
1950
1951 static void si_set_framebuffer_state(struct pipe_context *ctx,
1952 const struct pipe_framebuffer_state *state)
1953 {
1954 struct si_context *sctx = (struct si_context *)ctx;
1955 struct pipe_constant_buffer constbuf = {0};
1956 struct r600_surface *surf = NULL;
1957 struct r600_texture *rtex;
1958 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
1959 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
1960 int i;
1961
1962 if (sctx->framebuffer.state.nr_cbufs) {
1963 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1964 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1965 }
1966 if (sctx->framebuffer.state.zsbuf) {
1967 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
1968 R600_CONTEXT_FLUSH_AND_INV_DB_META;
1969 }
1970
1971 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
1972
1973 sctx->framebuffer.export_16bpc = 0;
1974 sctx->framebuffer.compressed_cb_mask = 0;
1975 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1976 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
1977 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1978 util_format_is_pure_integer(state->cbufs[0]->format);
1979
1980 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
1981 sctx->db_render_state.dirty = true;
1982
1983 for (i = 0; i < state->nr_cbufs; i++) {
1984 if (!state->cbufs[i])
1985 continue;
1986
1987 surf = (struct r600_surface*)state->cbufs[i];
1988 rtex = (struct r600_texture*)surf->base.texture;
1989
1990 if (!surf->color_initialized) {
1991 si_initialize_color_surface(sctx, surf);
1992 }
1993
1994 if (surf->export_16bpc) {
1995 sctx->framebuffer.export_16bpc |= 1 << i;
1996 }
1997
1998 if (rtex->fmask.size && rtex->cmask.size) {
1999 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2000 }
2001 }
2002 /* Set the 16BPC export for possible dual-src blending. */
2003 if (i == 1 && surf && surf->export_16bpc) {
2004 sctx->framebuffer.export_16bpc |= 1 << 1;
2005 }
2006
2007 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2008
2009 if (state->zsbuf) {
2010 surf = (struct r600_surface*)state->zsbuf;
2011
2012 if (!surf->depth_initialized) {
2013 si_init_depth_surface(sctx, surf);
2014 }
2015 }
2016
2017 si_update_fb_rs_state(sctx);
2018 si_update_fb_blend_state(sctx);
2019
2020 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
2021 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2022 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2023 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2024 sctx->framebuffer.atom.dirty = true;
2025
2026 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2027 sctx->msaa_config.dirty = true;
2028 sctx->db_render_state.dirty = true;
2029
2030 /* Set sample locations as fragment shader constants. */
2031 switch (sctx->framebuffer.nr_samples) {
2032 case 1:
2033 constbuf.user_buffer = sctx->b.sample_locations_1x;
2034 break;
2035 case 2:
2036 constbuf.user_buffer = sctx->b.sample_locations_2x;
2037 break;
2038 case 4:
2039 constbuf.user_buffer = sctx->b.sample_locations_4x;
2040 break;
2041 case 8:
2042 constbuf.user_buffer = sctx->b.sample_locations_8x;
2043 break;
2044 case 16:
2045 constbuf.user_buffer = sctx->b.sample_locations_16x;
2046 break;
2047 default:
2048 assert(0);
2049 }
2050 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2051 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2052 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2053 }
2054 }
2055
2056 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2057 {
2058 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2059 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2060 unsigned i, nr_cbufs = state->nr_cbufs;
2061 struct r600_texture *tex = NULL;
2062 struct r600_surface *cb = NULL;
2063
2064 /* Colorbuffers. */
2065 for (i = 0; i < nr_cbufs; i++) {
2066 cb = (struct r600_surface*)state->cbufs[i];
2067 if (!cb) {
2068 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2069 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2070 continue;
2071 }
2072
2073 tex = (struct r600_texture *)cb->base.texture;
2074 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2075 &tex->resource, RADEON_USAGE_READWRITE,
2076 tex->surface.nsamples > 1 ?
2077 RADEON_PRIO_COLOR_BUFFER_MSAA :
2078 RADEON_PRIO_COLOR_BUFFER);
2079
2080 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2081 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2082 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2083 RADEON_PRIO_COLOR_META);
2084 }
2085
2086 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2087 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2088 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2089 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2090 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2091 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2092 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2093 radeon_emit(cs, 0); /* R_028C78 unused */
2094 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2095 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2096 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2097 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2098 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2099 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2100 }
2101 /* set CB_COLOR1_INFO for possible dual-src blending */
2102 if (i == 1 && state->cbufs[0]) {
2103 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2104 cb->cb_color_info | tex->cb_color_info);
2105 i++;
2106 }
2107 for (; i < 8 ; i++) {
2108 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2109 }
2110
2111 /* ZS buffer. */
2112 if (state->zsbuf) {
2113 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2114 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2115
2116 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2117 &rtex->resource, RADEON_USAGE_READWRITE,
2118 zb->base.texture->nr_samples > 1 ?
2119 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2120 RADEON_PRIO_DEPTH_BUFFER);
2121
2122 if (zb->db_htile_data_base) {
2123 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2124 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2125 RADEON_PRIO_DEPTH_META);
2126 }
2127
2128 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2129 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2130
2131 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2132 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2133 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
2134 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2135 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2136 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2137 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2138 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2139 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2140 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2141
2142 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2143 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2144 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2145 zb->pa_su_poly_offset_db_fmt_cntl);
2146 } else {
2147 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2148 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2149 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2150 }
2151
2152 /* Framebuffer dimensions. */
2153 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2154 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2155 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2156
2157 cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples);
2158 }
2159
2160 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2161 {
2162 struct si_context *sctx = (struct si_context *)rctx;
2163 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2164
2165 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2166 sctx->ps_iter_samples);
2167 }
2168
2169 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2170
2171 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2172 {
2173 struct si_context *sctx = (struct si_context *)ctx;
2174
2175 if (sctx->ps_iter_samples == min_samples)
2176 return;
2177
2178 sctx->ps_iter_samples = min_samples;
2179
2180 if (sctx->framebuffer.nr_samples > 1)
2181 sctx->msaa_config.dirty = true;
2182 }
2183
2184 /*
2185 * shaders
2186 */
2187
2188 /* Compute the key for the hw shader variant */
2189 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2190 struct si_shader_selector *sel,
2191 union si_shader_key *key)
2192 {
2193 struct si_context *sctx = (struct si_context *)ctx;
2194 memset(key, 0, sizeof(*key));
2195
2196 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
2197 sctx->queued.named.rasterizer) {
2198 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2199 key->vs.ucps_enabled |= 0x2;
2200 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2201 key->vs.ucps_enabled |= 0x1;
2202 }
2203
2204 if (sel->type == PIPE_SHADER_VERTEX) {
2205 unsigned i;
2206 if (!sctx->vertex_elements)
2207 return;
2208
2209 for (i = 0; i < sctx->vertex_elements->count; ++i)
2210 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2211
2212 if (sctx->gs_shader) {
2213 key->vs.as_es = 1;
2214 key->vs.gs_used_inputs = sctx->gs_shader->gs_used_inputs;
2215 }
2216 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2217 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS][0])
2218 key->ps.nr_cbufs = sctx->framebuffer.state.nr_cbufs;
2219 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
2220
2221 if (sctx->queued.named.rasterizer) {
2222 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2223 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2224 key->ps.interp_at_sample = sctx->framebuffer.nr_samples > 1 &&
2225 sctx->ps_iter_samples == sctx->framebuffer.nr_samples;
2226
2227 if (sctx->queued.named.blend) {
2228 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2229 sctx->queued.named.rasterizer->multisample_enable &&
2230 !sctx->framebuffer.cb0_is_integer;
2231 }
2232 }
2233 if (sctx->queued.named.dsa) {
2234 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2235
2236 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2237 if (sctx->framebuffer.cb0_is_integer)
2238 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2239 } else {
2240 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2241 }
2242 }
2243 }
2244
2245 /* Select the hw shader variant depending on the current state. */
2246 int si_shader_select(struct pipe_context *ctx,
2247 struct si_shader_selector *sel)
2248 {
2249 union si_shader_key key;
2250 struct si_shader * shader = NULL;
2251 int r;
2252
2253 si_shader_selector_key(ctx, sel, &key);
2254
2255 /* Check if we don't need to change anything.
2256 * This path is also used for most shaders that don't need multiple
2257 * variants, it will cost just a computation of the key and this
2258 * test. */
2259 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2260 return 0;
2261 }
2262
2263 /* lookup if we have other variants in the list */
2264 if (sel->num_shaders > 1) {
2265 struct si_shader *p = sel->current, *c = p->next_variant;
2266
2267 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2268 p = c;
2269 c = c->next_variant;
2270 }
2271
2272 if (c) {
2273 p->next_variant = c->next_variant;
2274 shader = c;
2275 }
2276 }
2277
2278 if (shader) {
2279 shader->next_variant = sel->current;
2280 sel->current = shader;
2281 } else {
2282 shader = CALLOC(1, sizeof(struct si_shader));
2283 shader->selector = sel;
2284 shader->key = key;
2285
2286 shader->next_variant = sel->current;
2287 sel->current = shader;
2288 r = si_shader_create((struct si_screen*)ctx->screen, shader);
2289 if (unlikely(r)) {
2290 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2291 sel->type, r);
2292 sel->current = NULL;
2293 FREE(shader);
2294 return r;
2295 }
2296 sel->num_shaders++;
2297 }
2298
2299 return 0;
2300 }
2301
2302 static void *si_create_shader_state(struct pipe_context *ctx,
2303 const struct pipe_shader_state *state,
2304 unsigned pipe_shader_type)
2305 {
2306 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2307 int i;
2308
2309 sel->type = pipe_shader_type;
2310 sel->tokens = tgsi_dup_tokens(state->tokens);
2311 sel->so = state->stream_output;
2312 tgsi_scan_shader(state->tokens, &sel->info);
2313
2314 switch (pipe_shader_type) {
2315 case PIPE_SHADER_GEOMETRY:
2316 sel->gs_output_prim =
2317 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM][0];
2318 sel->gs_max_out_vertices =
2319 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES][0];
2320
2321 for (i = 0; i < sel->info.num_inputs; i++) {
2322 unsigned name = sel->info.input_semantic_name[i];
2323 unsigned index = sel->info.input_semantic_index[i];
2324
2325 switch (name) {
2326 case TGSI_SEMANTIC_PRIMID:
2327 break;
2328 default:
2329 sel->gs_used_inputs |=
2330 1llu << si_shader_io_get_unique_index(name, index);
2331 }
2332 }
2333 }
2334
2335 return sel;
2336 }
2337
2338 static void *si_create_fs_state(struct pipe_context *ctx,
2339 const struct pipe_shader_state *state)
2340 {
2341 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2342 }
2343
2344 static void *si_create_gs_state(struct pipe_context *ctx,
2345 const struct pipe_shader_state *state)
2346 {
2347 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
2348 }
2349
2350 static void *si_create_vs_state(struct pipe_context *ctx,
2351 const struct pipe_shader_state *state)
2352 {
2353 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2354 }
2355
2356 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2357 {
2358 struct si_context *sctx = (struct si_context *)ctx;
2359 struct si_shader_selector *sel = state;
2360
2361 if (sctx->vs_shader == sel || !sel)
2362 return;
2363
2364 sctx->vs_shader = sel;
2365 }
2366
2367 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2368 {
2369 struct si_context *sctx = (struct si_context *)ctx;
2370 struct si_shader_selector *sel = state;
2371
2372 if (sctx->gs_shader == sel)
2373 return;
2374
2375 sctx->gs_shader = sel;
2376 }
2377
2378 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2379 {
2380 struct si_context *sctx = (struct si_context *)ctx;
2381 struct si_shader_selector *sel = state;
2382
2383 /* skip if supplied shader is one already in use */
2384 if (sctx->ps_shader == sel)
2385 return;
2386
2387 /* use a dummy shader if binding a NULL shader */
2388 if (!sel) {
2389 if (!sctx->dummy_pixel_shader) {
2390 sctx->dummy_pixel_shader =
2391 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
2392 TGSI_SEMANTIC_GENERIC,
2393 TGSI_INTERPOLATE_CONSTANT);
2394 }
2395
2396 sel = sctx->dummy_pixel_shader;
2397 }
2398
2399 sctx->ps_shader = sel;
2400 }
2401
2402 static void si_delete_shader_selector(struct pipe_context *ctx,
2403 struct si_shader_selector *sel)
2404 {
2405 struct si_context *sctx = (struct si_context *)ctx;
2406 struct si_shader *p = sel->current, *c;
2407
2408 while (p) {
2409 c = p->next_variant;
2410 if (sel->type == PIPE_SHADER_GEOMETRY) {
2411 si_pm4_delete_state(sctx, gs, p->pm4);
2412 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
2413 } else if (sel->type == PIPE_SHADER_FRAGMENT)
2414 si_pm4_delete_state(sctx, ps, p->pm4);
2415 else if (p->key.vs.as_es)
2416 si_pm4_delete_state(sctx, es, p->pm4);
2417 else
2418 si_pm4_delete_state(sctx, vs, p->pm4);
2419 si_shader_destroy(ctx, p);
2420 free(p);
2421 p = c;
2422 }
2423
2424 free(sel->tokens);
2425 free(sel);
2426 }
2427
2428 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2429 {
2430 struct si_context *sctx = (struct si_context *)ctx;
2431 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2432
2433 if (sctx->vs_shader == sel) {
2434 sctx->vs_shader = NULL;
2435 }
2436
2437 si_delete_shader_selector(ctx, sel);
2438 }
2439
2440 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
2441 {
2442 struct si_context *sctx = (struct si_context *)ctx;
2443 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2444
2445 if (sctx->gs_shader == sel) {
2446 sctx->gs_shader = NULL;
2447 }
2448
2449 si_delete_shader_selector(ctx, sel);
2450 }
2451
2452 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2453 {
2454 struct si_context *sctx = (struct si_context *)ctx;
2455 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2456
2457 if (sctx->ps_shader == sel) {
2458 sctx->ps_shader = NULL;
2459 }
2460
2461 si_delete_shader_selector(ctx, sel);
2462 }
2463
2464 /*
2465 * Samplers
2466 */
2467
2468 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2469 struct pipe_resource *texture,
2470 const struct pipe_sampler_view *state)
2471 {
2472 struct si_context *sctx = (struct si_context*)ctx;
2473 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2474 struct r600_texture *tmp = (struct r600_texture*)texture;
2475 const struct util_format_description *desc;
2476 unsigned format, num_format;
2477 uint32_t pitch = 0;
2478 unsigned char state_swizzle[4], swizzle[4];
2479 unsigned height, depth, width;
2480 enum pipe_format pipe_format = state->format;
2481 struct radeon_surface_level *surflevel;
2482 int first_non_void;
2483 uint64_t va;
2484
2485 if (view == NULL)
2486 return NULL;
2487
2488 /* initialize base object */
2489 view->base = *state;
2490 view->base.texture = NULL;
2491 pipe_resource_reference(&view->base.texture, texture);
2492 view->base.reference.count = 1;
2493 view->base.context = ctx;
2494 view->resource = &tmp->resource;
2495
2496 /* Buffer resource. */
2497 if (texture->target == PIPE_BUFFER) {
2498 unsigned stride;
2499
2500 desc = util_format_description(state->format);
2501 first_non_void = util_format_get_first_non_void_channel(state->format);
2502 stride = desc->block.bits / 8;
2503 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2504 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2505 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2506
2507 view->state[0] = va;
2508 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2509 S_008F04_STRIDE(stride);
2510 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2511 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2512 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2513 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2514 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2515 S_008F0C_NUM_FORMAT(num_format) |
2516 S_008F0C_DATA_FORMAT(format);
2517
2518 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2519 return &view->base;
2520 }
2521
2522 state_swizzle[0] = state->swizzle_r;
2523 state_swizzle[1] = state->swizzle_g;
2524 state_swizzle[2] = state->swizzle_b;
2525 state_swizzle[3] = state->swizzle_a;
2526
2527 surflevel = tmp->surface.level;
2528
2529 /* Texturing with separate depth and stencil. */
2530 if (tmp->is_depth && !tmp->is_flushing_texture) {
2531 switch (pipe_format) {
2532 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2533 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2534 break;
2535 case PIPE_FORMAT_X8Z24_UNORM:
2536 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2537 /* Z24 is always stored like this. */
2538 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2539 break;
2540 case PIPE_FORMAT_X24S8_UINT:
2541 case PIPE_FORMAT_S8X24_UINT:
2542 case PIPE_FORMAT_X32_S8X24_UINT:
2543 pipe_format = PIPE_FORMAT_S8_UINT;
2544 surflevel = tmp->surface.stencil_level;
2545 break;
2546 default:;
2547 }
2548 }
2549
2550 desc = util_format_description(pipe_format);
2551
2552 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2553 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2554 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2555
2556 switch (pipe_format) {
2557 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2558 case PIPE_FORMAT_X24S8_UINT:
2559 case PIPE_FORMAT_X32_S8X24_UINT:
2560 case PIPE_FORMAT_X8Z24_UNORM:
2561 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2562 break;
2563 default:
2564 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2565 }
2566 } else {
2567 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2568 }
2569
2570 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2571
2572 switch (pipe_format) {
2573 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2574 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2575 break;
2576 default:
2577 if (first_non_void < 0) {
2578 if (util_format_is_compressed(pipe_format)) {
2579 switch (pipe_format) {
2580 case PIPE_FORMAT_DXT1_SRGB:
2581 case PIPE_FORMAT_DXT1_SRGBA:
2582 case PIPE_FORMAT_DXT3_SRGBA:
2583 case PIPE_FORMAT_DXT5_SRGBA:
2584 case PIPE_FORMAT_BPTC_SRGBA:
2585 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2586 break;
2587 case PIPE_FORMAT_RGTC1_SNORM:
2588 case PIPE_FORMAT_LATC1_SNORM:
2589 case PIPE_FORMAT_RGTC2_SNORM:
2590 case PIPE_FORMAT_LATC2_SNORM:
2591 /* implies float, so use SNORM/UNORM to determine
2592 whether data is signed or not */
2593 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2594 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2595 break;
2596 default:
2597 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2598 break;
2599 }
2600 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2601 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2602 } else {
2603 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2604 }
2605 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2606 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2607 } else {
2608 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2609
2610 switch (desc->channel[first_non_void].type) {
2611 case UTIL_FORMAT_TYPE_FLOAT:
2612 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2613 break;
2614 case UTIL_FORMAT_TYPE_SIGNED:
2615 if (desc->channel[first_non_void].normalized)
2616 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2617 else if (desc->channel[first_non_void].pure_integer)
2618 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2619 else
2620 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2621 break;
2622 case UTIL_FORMAT_TYPE_UNSIGNED:
2623 if (desc->channel[first_non_void].normalized)
2624 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2625 else if (desc->channel[first_non_void].pure_integer)
2626 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2627 else
2628 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2629 }
2630 }
2631 }
2632
2633 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2634 if (format == ~0) {
2635 format = 0;
2636 }
2637
2638 /* not supported any more */
2639 //endian = si_colorformat_endian_swap(format);
2640
2641 width = surflevel[0].npix_x;
2642 height = surflevel[0].npix_y;
2643 depth = surflevel[0].npix_z;
2644 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2645
2646 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2647 height = 1;
2648 depth = texture->array_size;
2649 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2650 depth = texture->array_size;
2651 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2652 depth = texture->array_size / 6;
2653
2654 va = tmp->resource.gpu_address + surflevel[0].offset;
2655 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2656
2657 view->state[0] = va >> 8;
2658 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2659 S_008F14_DATA_FORMAT(format) |
2660 S_008F14_NUM_FORMAT(num_format));
2661 view->state[2] = (S_008F18_WIDTH(width - 1) |
2662 S_008F18_HEIGHT(height - 1));
2663 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2664 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2665 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2666 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2667 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2668 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2669 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2670 util_logbase2(texture->nr_samples) :
2671 state->u.tex.last_level - tmp->mipmap_shift) |
2672 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2673 S_008F1C_POW2_PAD(texture->last_level > 0) |
2674 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2675 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2676 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2677 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2678 view->state[6] = 0;
2679 view->state[7] = 0;
2680
2681 /* Initialize the sampler view for FMASK. */
2682 if (tmp->fmask.size) {
2683 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2684 uint32_t fmask_format;
2685
2686 switch (texture->nr_samples) {
2687 case 2:
2688 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2689 break;
2690 case 4:
2691 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2692 break;
2693 case 8:
2694 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2695 break;
2696 default:
2697 assert(0);
2698 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2699 }
2700
2701 view->fmask_state[0] = va >> 8;
2702 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2703 S_008F14_DATA_FORMAT(fmask_format) |
2704 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2705 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2706 S_008F18_HEIGHT(height - 1);
2707 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2708 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2709 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2710 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2711 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2712 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2713 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2714 S_008F20_PITCH(tmp->fmask.pitch - 1);
2715 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2716 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2717 view->fmask_state[6] = 0;
2718 view->fmask_state[7] = 0;
2719 }
2720
2721 return &view->base;
2722 }
2723
2724 static void si_sampler_view_destroy(struct pipe_context *ctx,
2725 struct pipe_sampler_view *state)
2726 {
2727 struct si_sampler_view *view = (struct si_sampler_view *)state;
2728
2729 if (view->resource->b.b.target == PIPE_BUFFER)
2730 LIST_DELINIT(&view->list);
2731
2732 pipe_resource_reference(&state->texture, NULL);
2733 FREE(view);
2734 }
2735
2736 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2737 {
2738 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2739 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2740 (linear_filter &&
2741 (wrap == PIPE_TEX_WRAP_CLAMP ||
2742 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2743 }
2744
2745 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2746 {
2747 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2748 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2749
2750 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2751 state->border_color.ui[2] || state->border_color.ui[3]) &&
2752 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2753 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2754 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2755 }
2756
2757 static void *si_create_sampler_state(struct pipe_context *ctx,
2758 const struct pipe_sampler_state *state)
2759 {
2760 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2761 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2762 unsigned border_color_type;
2763
2764 if (rstate == NULL) {
2765 return NULL;
2766 }
2767
2768 if (sampler_state_needs_border_color(state))
2769 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2770 else
2771 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2772
2773 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2774 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2775 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2776 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2777 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2778 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2779 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2780 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2781 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2782 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2783 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2784 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2785 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2786 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2787
2788 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2789 memcpy(rstate->border_color, state->border_color.ui,
2790 sizeof(rstate->border_color));
2791 }
2792
2793 return rstate;
2794 }
2795
2796 /* Upload border colors and update the pointers in resource descriptors.
2797 * There can only be 4096 border colors per context.
2798 *
2799 * XXX: This is broken if the buffer gets reallocated.
2800 */
2801 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2802 void **states)
2803 {
2804 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2805 uint32_t *border_color_table = NULL;
2806 int i, j;
2807
2808 for (i = 0; i < count; i++) {
2809 if (rstates[i] &&
2810 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2811 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2812 if (!sctx->border_color_table ||
2813 ((sctx->border_color_offset + count - i) &
2814 C_008F3C_BORDER_COLOR_PTR)) {
2815 r600_resource_reference(&sctx->border_color_table, NULL);
2816 sctx->border_color_offset = 0;
2817
2818 sctx->border_color_table =
2819 si_resource_create_custom(&sctx->screen->b.b,
2820 PIPE_USAGE_DYNAMIC,
2821 4096 * 4 * 4);
2822 }
2823
2824 if (!border_color_table) {
2825 border_color_table =
2826 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2827 sctx->b.rings.gfx.cs,
2828 PIPE_TRANSFER_WRITE |
2829 PIPE_TRANSFER_UNSYNCHRONIZED);
2830 }
2831
2832 for (j = 0; j < 4; j++) {
2833 border_color_table[4 * sctx->border_color_offset + j] =
2834 util_le32_to_cpu(rstates[i]->border_color[j]);
2835 }
2836
2837 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2838 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2839 }
2840 }
2841
2842 if (border_color_table) {
2843 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2844
2845 uint64_t va_offset = sctx->border_color_table->gpu_address;
2846
2847 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2848 if (sctx->b.chip_class >= CIK)
2849 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2850 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2851 RADEON_PRIO_SHADER_DATA);
2852 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2853 }
2854 }
2855
2856 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2857 unsigned start, unsigned count,
2858 void **states)
2859 {
2860 struct si_context *sctx = (struct si_context *)ctx;
2861
2862 if (!count || shader >= SI_NUM_SHADERS)
2863 return;
2864
2865 si_set_border_colors(sctx, count, states);
2866 si_set_sampler_descriptors(sctx, shader, start, count, states);
2867 }
2868
2869 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2870 {
2871 struct si_context *sctx = (struct si_context *)ctx;
2872 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2873 struct si_pm4_state *pm4 = &state->pm4;
2874 uint16_t mask = sample_mask;
2875
2876 if (state == NULL)
2877 return;
2878
2879 state->sample_mask = mask;
2880 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2881 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2882
2883 si_pm4_set_state(sctx, sample_mask, state);
2884 }
2885
2886 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2887 {
2888 free(state);
2889 }
2890
2891 /*
2892 * Vertex elements & buffers
2893 */
2894
2895 static void *si_create_vertex_elements(struct pipe_context *ctx,
2896 unsigned count,
2897 const struct pipe_vertex_element *elements)
2898 {
2899 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2900 int i;
2901
2902 assert(count < PIPE_MAX_ATTRIBS);
2903 if (!v)
2904 return NULL;
2905
2906 v->count = count;
2907 for (i = 0; i < count; ++i) {
2908 const struct util_format_description *desc;
2909 unsigned data_format, num_format;
2910 int first_non_void;
2911
2912 desc = util_format_description(elements[i].src_format);
2913 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2914 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2915 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2916
2917 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2918 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2919 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2920 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2921 S_008F0C_NUM_FORMAT(num_format) |
2922 S_008F0C_DATA_FORMAT(data_format);
2923 v->format_size[i] = desc->block.bits / 8;
2924 }
2925 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2926
2927 return v;
2928 }
2929
2930 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2931 {
2932 struct si_context *sctx = (struct si_context *)ctx;
2933 struct si_vertex_element *v = (struct si_vertex_element*)state;
2934
2935 sctx->vertex_elements = v;
2936 sctx->vertex_buffers_dirty = true;
2937 }
2938
2939 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2940 {
2941 struct si_context *sctx = (struct si_context *)ctx;
2942
2943 if (sctx->vertex_elements == state)
2944 sctx->vertex_elements = NULL;
2945 FREE(state);
2946 }
2947
2948 static void si_set_vertex_buffers(struct pipe_context *ctx,
2949 unsigned start_slot, unsigned count,
2950 const struct pipe_vertex_buffer *buffers)
2951 {
2952 struct si_context *sctx = (struct si_context *)ctx;
2953 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2954 int i;
2955
2956 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2957
2958 if (buffers) {
2959 for (i = 0; i < count; i++) {
2960 const struct pipe_vertex_buffer *src = buffers + i;
2961 struct pipe_vertex_buffer *dsti = dst + i;
2962
2963 pipe_resource_reference(&dsti->buffer, src->buffer);
2964 dsti->buffer_offset = src->buffer_offset;
2965 dsti->stride = src->stride;
2966 }
2967 } else {
2968 for (i = 0; i < count; i++) {
2969 pipe_resource_reference(&dst[i].buffer, NULL);
2970 }
2971 }
2972 sctx->vertex_buffers_dirty = true;
2973 }
2974
2975 static void si_set_index_buffer(struct pipe_context *ctx,
2976 const struct pipe_index_buffer *ib)
2977 {
2978 struct si_context *sctx = (struct si_context *)ctx;
2979
2980 if (ib) {
2981 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2982 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2983 } else {
2984 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2985 }
2986 }
2987
2988 /*
2989 * Misc
2990 */
2991 static void si_set_polygon_stipple(struct pipe_context *ctx,
2992 const struct pipe_poly_stipple *state)
2993 {
2994 }
2995
2996 static void si_texture_barrier(struct pipe_context *ctx)
2997 {
2998 struct si_context *sctx = (struct si_context *)ctx;
2999
3000 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
3001 R600_CONTEXT_FLUSH_AND_INV_CB;
3002 }
3003
3004 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3005 {
3006 struct pipe_blend_state blend;
3007
3008 memset(&blend, 0, sizeof(blend));
3009 blend.independent_blend_enable = true;
3010 blend.rt[0].colormask = 0xf;
3011 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3012 }
3013
3014 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3015 bool include_draw_vbo)
3016 {
3017 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
3018 }
3019
3020 void si_init_state_functions(struct si_context *sctx)
3021 {
3022 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
3023 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
3024
3025 sctx->b.b.create_blend_state = si_create_blend_state;
3026 sctx->b.b.bind_blend_state = si_bind_blend_state;
3027 sctx->b.b.delete_blend_state = si_delete_blend_state;
3028 sctx->b.b.set_blend_color = si_set_blend_color;
3029
3030 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3031 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3032 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3033
3034 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3035 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3036 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3037
3038 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3039 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3040 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3041 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3042
3043 sctx->b.b.set_clip_state = si_set_clip_state;
3044 sctx->b.b.set_scissor_states = si_set_scissor_states;
3045 sctx->b.b.set_viewport_states = si_set_viewport_states;
3046 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3047
3048 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3049 sctx->b.b.get_sample_position = cayman_get_sample_position;
3050
3051 sctx->b.b.create_vs_state = si_create_vs_state;
3052 sctx->b.b.create_fs_state = si_create_fs_state;
3053 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3054 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3055 sctx->b.b.delete_vs_state = si_delete_vs_shader;
3056 sctx->b.b.delete_fs_state = si_delete_ps_shader;
3057
3058 sctx->b.b.create_gs_state = si_create_gs_state;
3059 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3060 sctx->b.b.delete_gs_state = si_delete_gs_shader;
3061
3062 sctx->b.b.create_sampler_state = si_create_sampler_state;
3063 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3064 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3065
3066 sctx->b.b.create_sampler_view = si_create_sampler_view;
3067 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3068
3069 sctx->b.b.set_sample_mask = si_set_sample_mask;
3070
3071 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3072 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3073 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3074 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3075 sctx->b.b.set_index_buffer = si_set_index_buffer;
3076
3077 sctx->b.b.texture_barrier = si_texture_barrier;
3078 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3079 sctx->b.b.set_min_samples = si_set_min_samples;
3080
3081 sctx->b.dma_copy = si_dma_copy;
3082 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3083 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3084
3085 sctx->b.b.draw_vbo = si_draw_vbo;
3086 }
3087
3088 void si_init_config(struct si_context *sctx)
3089 {
3090 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
3091
3092 if (pm4 == NULL)
3093 return;
3094
3095 si_cmd_context_control(pm4);
3096
3097 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3098 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3099 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3100 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3101 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3102 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3103 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3104 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3105 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3106 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3107 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3108 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3109
3110 /* FIXME calculate these values somehow ??? */
3111 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3112 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3113 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3114
3115 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3116 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3117 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3118 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3119
3120 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3121 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3122 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3123 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3124
3125 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3126 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3127 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3128 if (sctx->b.chip_class < CIK)
3129 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3130 S_008A14_CLIP_VTX_REORDER_ENA(1));
3131
3132 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3133 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3134
3135 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3136
3137 if (sctx->b.chip_class >= CIK) {
3138 switch (sctx->screen->b.family) {
3139 case CHIP_BONAIRE:
3140 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3141 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3142 break;
3143 case CHIP_HAWAII:
3144 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3145 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3146 break;
3147 case CHIP_KAVERI:
3148 /* XXX todo */
3149 case CHIP_KABINI:
3150 /* XXX todo */
3151 case CHIP_MULLINS:
3152 /* XXX todo */
3153 default:
3154 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3155 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3156 break;
3157 }
3158 } else {
3159 switch (sctx->screen->b.family) {
3160 case CHIP_TAHITI:
3161 case CHIP_PITCAIRN:
3162 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3163 break;
3164 case CHIP_VERDE:
3165 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3166 break;
3167 case CHIP_OLAND:
3168 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3169 break;
3170 case CHIP_HAINAN:
3171 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3172 break;
3173 default:
3174 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3175 break;
3176 }
3177 }
3178
3179 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3180 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3181 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3182 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3183 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3184 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3185 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3186
3187 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3188 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3189 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3190 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3191 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3192 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3193 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3194 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3195 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3196 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3197 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3198 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3199 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3200 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3201 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3202 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3203
3204 /* There is a hang if stencil is used and fast stencil is enabled
3205 * regardless of whether HTILE is depth-only or not.
3206 */
3207 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3208 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3209 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3210 S_02800C_FAST_STENCIL_DISABLE(1));
3211
3212 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3213 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3214 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3215
3216 if (sctx->b.chip_class >= CIK) {
3217 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3218 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3219 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3220 }
3221
3222 si_pm4_set_state(sctx, init, pm4);
3223 }