2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "util/fast_idiv_by_const.h"
29 #include "util/format/u_format.h"
30 #include "util/format/u_format_s3tc.h"
31 #include "util/u_dual_blend.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
37 unsigned img_format
: 9;
39 /* Various formats are only supported with workarounds for vertex fetch,
40 * and some 32_32_32 formats are supported natively, but only for buffers
41 * (possibly with some image support, actually, but no filtering). */
42 bool buffers_only
: 1;
45 #include "gfx10_format_table.h"
47 static unsigned si_map_swizzle(unsigned swizzle
)
51 return V_008F0C_SQ_SEL_Y
;
53 return V_008F0C_SQ_SEL_Z
;
55 return V_008F0C_SQ_SEL_W
;
57 return V_008F0C_SQ_SEL_0
;
59 return V_008F0C_SQ_SEL_1
;
60 default: /* PIPE_SWIZZLE_X */
61 return V_008F0C_SQ_SEL_X
;
65 /* 12.4 fixed-point */
66 static unsigned si_pack_float_12p4(float x
)
68 return x
<= 0 ? 0 : x
>= 4096 ? 0xffff : x
* 16;
72 * Inferred framebuffer and blender state.
74 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
75 * if there is not enough PS outputs.
77 static void si_emit_cb_render_state(struct si_context
*sctx
)
79 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
80 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
81 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
82 * but you never know. */
83 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
& blend
->cb_target_mask
;
86 /* Avoid a hang that happens when dual source blending is enabled
87 * but there is not enough color outputs. This is undefined behavior,
88 * so disable color writes completely.
90 * Reproducible with Unigine Heaven 4.0 and drirc missing.
92 if (blend
->dual_src_blend
&& sctx
->ps_shader
.cso
&&
93 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
96 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
97 * I think we don't have to do anything between IBs.
99 if (sctx
->screen
->dpbb_allowed
&& sctx
->last_cb_target_mask
!= cb_target_mask
) {
100 sctx
->last_cb_target_mask
= cb_target_mask
;
102 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
103 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
106 unsigned initial_cdw
= cs
->current
.cdw
;
107 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
, SI_TRACKED_CB_TARGET_MASK
,
110 if (sctx
->chip_class
>= GFX8
) {
111 /* DCC MSAA workaround.
112 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
113 * COMBINER_DISABLE, but that would be more complicated.
116 blend
->dcc_msaa_corruption_4bit
& cb_target_mask
&& sctx
->framebuffer
.nr_samples
>= 2;
117 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
119 radeon_opt_set_context_reg(
120 sctx
, R_028424_CB_DCC_CONTROL
, SI_TRACKED_CB_DCC_CONTROL
,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->info
.has_dcc_constant_encode
));
127 /* RB+ register settings. */
128 if (sctx
->screen
->info
.rbplus_allowed
) {
129 unsigned spi_shader_col_format
=
130 sctx
->ps_shader
.cso
? sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
132 unsigned sx_ps_downconvert
= 0;
133 unsigned sx_blend_opt_epsilon
= 0;
134 unsigned sx_blend_opt_control
= 0;
136 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
137 struct si_surface
*surf
= (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
138 unsigned format
, swap
, spi_format
, colormask
;
139 bool has_alpha
, has_rgb
;
142 /* If the color buffer is not set, the driver sets 32_R
143 * as the SPI color format, because the hw doesn't allow
144 * holes between color outputs, so also set this to
147 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
151 format
= G_028C70_FORMAT(surf
->cb_color_info
);
152 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
153 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
154 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
156 /* Set if RGB and A are present. */
157 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
159 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_16
||
160 format
== V_028C70_COLOR_32
)
161 has_rgb
= !has_alpha
;
165 /* Check the colormask and export format. */
166 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
168 if (!(colormask
& PIPE_MASK_A
))
171 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
176 /* Disable value checking for disabled channels. */
178 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
180 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
182 /* Enable down-conversion for 32bpp and smaller formats. */
184 case V_028C70_COLOR_8
:
185 case V_028C70_COLOR_8_8
:
186 case V_028C70_COLOR_8_8_8_8
:
187 /* For 1 and 2-channel formats, use the superset thereof. */
188 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
189 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
190 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
191 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
192 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
196 case V_028C70_COLOR_5_6_5
:
197 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
198 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
199 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
203 case V_028C70_COLOR_1_5_5_5
:
204 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
205 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
206 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
210 case V_028C70_COLOR_4_4_4_4
:
211 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
212 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
213 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
217 case V_028C70_COLOR_32
:
218 if (swap
== V_028C70_SWAP_STD
&& spi_format
== V_028714_SPI_SHADER_32_R
)
219 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
220 else if (swap
== V_028C70_SWAP_ALT_REV
&& spi_format
== V_028714_SPI_SHADER_32_AR
)
221 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
224 case V_028C70_COLOR_16
:
225 case V_028C70_COLOR_16_16
:
226 /* For 1-channel formats, use the superset thereof. */
227 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
228 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
229 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
230 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
231 if (swap
== V_028C70_SWAP_STD
|| swap
== V_028C70_SWAP_STD_REV
)
232 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
234 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
238 case V_028C70_COLOR_10_11_11
:
239 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
240 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
243 case V_028C70_COLOR_2_10_10_10
:
244 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
245 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
246 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
252 /* If there are no color outputs, the first color export is
253 * always enabled as 32_R, so also set this to enable RB+.
255 if (!sx_ps_downconvert
)
256 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
258 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
259 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
, SI_TRACKED_SX_PS_DOWNCONVERT
,
260 sx_ps_downconvert
, sx_blend_opt_epsilon
, sx_blend_opt_control
);
262 if (initial_cdw
!= cs
->current
.cdw
)
263 sctx
->context_roll
= true;
270 static uint32_t si_translate_blend_function(int blend_func
)
272 switch (blend_func
) {
274 return V_028780_COMB_DST_PLUS_SRC
;
275 case PIPE_BLEND_SUBTRACT
:
276 return V_028780_COMB_SRC_MINUS_DST
;
277 case PIPE_BLEND_REVERSE_SUBTRACT
:
278 return V_028780_COMB_DST_MINUS_SRC
;
280 return V_028780_COMB_MIN_DST_SRC
;
282 return V_028780_COMB_MAX_DST_SRC
;
284 PRINT_ERR("Unknown blend function %d\n", blend_func
);
291 static uint32_t si_translate_blend_factor(int blend_fact
)
293 switch (blend_fact
) {
294 case PIPE_BLENDFACTOR_ONE
:
295 return V_028780_BLEND_ONE
;
296 case PIPE_BLENDFACTOR_SRC_COLOR
:
297 return V_028780_BLEND_SRC_COLOR
;
298 case PIPE_BLENDFACTOR_SRC_ALPHA
:
299 return V_028780_BLEND_SRC_ALPHA
;
300 case PIPE_BLENDFACTOR_DST_ALPHA
:
301 return V_028780_BLEND_DST_ALPHA
;
302 case PIPE_BLENDFACTOR_DST_COLOR
:
303 return V_028780_BLEND_DST_COLOR
;
304 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
305 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
306 case PIPE_BLENDFACTOR_CONST_COLOR
:
307 return V_028780_BLEND_CONSTANT_COLOR
;
308 case PIPE_BLENDFACTOR_CONST_ALPHA
:
309 return V_028780_BLEND_CONSTANT_ALPHA
;
310 case PIPE_BLENDFACTOR_ZERO
:
311 return V_028780_BLEND_ZERO
;
312 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
313 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
314 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
315 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
316 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
317 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
318 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
319 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
320 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
322 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
324 case PIPE_BLENDFACTOR_SRC1_COLOR
:
325 return V_028780_BLEND_SRC1_COLOR
;
326 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
327 return V_028780_BLEND_SRC1_ALPHA
;
328 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
329 return V_028780_BLEND_INV_SRC1_COLOR
;
330 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
331 return V_028780_BLEND_INV_SRC1_ALPHA
;
333 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
340 static uint32_t si_translate_blend_opt_function(int blend_func
)
342 switch (blend_func
) {
344 return V_028760_OPT_COMB_ADD
;
345 case PIPE_BLEND_SUBTRACT
:
346 return V_028760_OPT_COMB_SUBTRACT
;
347 case PIPE_BLEND_REVERSE_SUBTRACT
:
348 return V_028760_OPT_COMB_REVSUBTRACT
;
350 return V_028760_OPT_COMB_MIN
;
352 return V_028760_OPT_COMB_MAX
;
354 return V_028760_OPT_COMB_BLEND_DISABLED
;
358 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
360 switch (blend_fact
) {
361 case PIPE_BLENDFACTOR_ZERO
:
362 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
363 case PIPE_BLENDFACTOR_ONE
:
364 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
365 case PIPE_BLENDFACTOR_SRC_COLOR
:
366 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
367 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
368 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
369 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
370 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
371 case PIPE_BLENDFACTOR_SRC_ALPHA
:
372 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
373 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
374 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
375 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
376 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
377 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
379 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
383 static void si_blend_check_commutativity(struct si_screen
*sscreen
, struct si_state_blend
*blend
,
384 enum pipe_blend_func func
, enum pipe_blendfactor src
,
385 enum pipe_blendfactor dst
, unsigned chanmask
)
387 /* Src factor is allowed when it does not depend on Dst */
388 static const uint32_t src_allowed
=
389 (1u << PIPE_BLENDFACTOR_ONE
) | (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
391 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
392 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
393 (1u << PIPE_BLENDFACTOR_ZERO
) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
394 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
395 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
398 if (dst
== PIPE_BLENDFACTOR_ONE
&& (src_allowed
& (1u << src
))) {
399 /* Addition is commutative, but floating point addition isn't
400 * associative: subtle changes can be introduced via different
403 * Out-of-order is also non-deterministic, which means that
404 * this breaks OpenGL invariance requirements. So only enable
405 * out-of-order additive blending if explicitly allowed by a
408 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
409 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
410 blend
->commutative_4bit
|= chanmask
;
415 * Get rid of DST in the blend factors by commuting the operands:
416 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
, unsigned *dst_factor
,
419 unsigned expected_dst
, unsigned replacement_src
)
421 if (*src_factor
== expected_dst
&& *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
422 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
423 *dst_factor
= replacement_src
;
425 /* Commuting the operands requires reversing subtractions. */
426 if (*func
== PIPE_BLEND_SUBTRACT
)
427 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
428 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
429 *func
= PIPE_BLEND_SUBTRACT
;
433 static bool si_blend_factor_uses_dst(unsigned factor
)
435 return factor
== PIPE_BLENDFACTOR_DST_COLOR
|| factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
436 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
437 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
|| factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
440 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
441 const struct pipe_blend_state
*state
, unsigned mode
)
443 struct si_context
*sctx
= (struct si_context
*)ctx
;
444 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
445 struct si_pm4_state
*pm4
= &blend
->pm4
;
446 uint32_t sx_mrt_blend_opt
[8] = {0};
447 uint32_t color_control
= 0;
448 bool logicop_enable
= state
->logicop_enable
&& state
->logicop_func
!= PIPE_LOGICOP_COPY
;
453 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
454 blend
->alpha_to_one
= state
->alpha_to_one
;
455 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
456 blend
->logicop_enable
= logicop_enable
;
458 unsigned num_shader_outputs
= state
->max_rt
+ 1; /* estimate */
459 if (blend
->dual_src_blend
)
460 num_shader_outputs
= MAX2(num_shader_outputs
, 2);
462 if (logicop_enable
) {
463 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
465 color_control
|= S_028808_ROP3(0xcc);
468 if (state
->alpha_to_coverage
&& state
->alpha_to_coverage_dither
) {
469 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
470 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
471 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
472 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
473 S_028B70_OFFSET_ROUND(1));
475 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
476 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
477 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
478 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
479 S_028B70_OFFSET_ROUND(0));
482 if (state
->alpha_to_coverage
)
483 blend
->need_src_alpha_4bit
|= 0xf;
485 blend
->cb_target_mask
= 0;
486 blend
->cb_target_enabled_4bit
= 0;
488 for (int i
= 0; i
< num_shader_outputs
; i
++) {
489 /* state->rt entries > 0 only written if independent blending */
490 const int j
= state
->independent_blend_enable
? i
: 0;
492 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
493 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
494 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
495 unsigned eqA
= state
->rt
[j
].alpha_func
;
496 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
497 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
499 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
500 unsigned blend_cntl
= 0;
502 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
503 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
505 /* Only set dual source blending for MRT0 to avoid a hang. */
506 if (i
>= 1 && blend
->dual_src_blend
) {
507 /* Vulkan does this for dual source blending. */
509 blend_cntl
|= S_028780_ENABLE(1);
511 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
515 /* Only addition and subtraction equations are supported with
516 * dual source blending.
518 if (blend
->dual_src_blend
&& (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
519 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
520 assert(!"Unsupported equation for dual source blending");
521 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
525 /* cb_render_state will disable unused ones */
526 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
527 if (state
->rt
[j
].colormask
)
528 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
530 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
531 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
535 si_blend_check_commutativity(sctx
->screen
, blend
, eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
536 si_blend_check_commutativity(sctx
->screen
, blend
, eqA
, srcA
, dstA
, 0x8 << (4 * i
));
538 /* Blending optimizations for RB+.
539 * These transformations don't change the behavior.
541 * First, get rid of DST in the blend factors:
542 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
544 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
, PIPE_BLENDFACTOR_DST_COLOR
,
545 PIPE_BLENDFACTOR_SRC_COLOR
);
546 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_COLOR
,
547 PIPE_BLENDFACTOR_SRC_COLOR
);
548 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_ALPHA
,
549 PIPE_BLENDFACTOR_SRC_ALPHA
);
551 /* Look up the ideal settings from tables. */
552 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
553 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
554 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
555 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
557 /* Handle interdependencies. */
558 if (si_blend_factor_uses_dst(srcRGB
))
559 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
560 if (si_blend_factor_uses_dst(srcA
))
561 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
563 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
564 (dstRGB
== PIPE_BLENDFACTOR_ZERO
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
565 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
566 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
568 /* Set the final value. */
569 sx_mrt_blend_opt
[i
] = S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
570 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
571 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
572 S_028760_ALPHA_SRC_OPT(srcA_opt
) | S_028760_ALPHA_DST_OPT(dstA_opt
) |
573 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
575 /* Set blend state. */
576 blend_cntl
|= S_028780_ENABLE(1);
577 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
578 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
579 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
581 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
582 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
583 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
584 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
585 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
587 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
589 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
591 if (sctx
->chip_class
>= GFX8
&& sctx
->chip_class
<= GFX10
)
592 blend
->dcc_msaa_corruption_4bit
|= 0xfu
<< (i
* 4);
594 /* This is only important for formats without alpha. */
595 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
596 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
597 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
598 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
599 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
602 if (sctx
->chip_class
>= GFX8
&& sctx
->chip_class
<= GFX10
&& logicop_enable
)
603 blend
->dcc_msaa_corruption_4bit
|= blend
->cb_target_enabled_4bit
;
605 if (blend
->cb_target_mask
) {
606 color_control
|= S_028808_MODE(mode
);
608 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
611 if (sctx
->screen
->info
.rbplus_allowed
) {
612 /* Disable RB+ blend optimizations for dual source blending.
615 if (blend
->dual_src_blend
) {
616 for (int i
= 0; i
< num_shader_outputs
; i
++) {
617 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
618 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
622 for (int i
= 0; i
< num_shader_outputs
; i
++)
623 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4, sx_mrt_blend_opt
[i
]);
625 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
626 if (blend
->dual_src_blend
|| logicop_enable
|| mode
== V_028808_CB_RESOLVE
)
627 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
630 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
634 static void *si_create_blend_state(struct pipe_context
*ctx
, const struct pipe_blend_state
*state
)
636 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
639 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
641 struct si_context
*sctx
= (struct si_context
*)ctx
;
642 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
643 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
646 blend
= (struct si_state_blend
*)sctx
->noop_blend
;
648 si_pm4_bind_state(sctx
, blend
, blend
);
650 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
651 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
652 (old_blend
->dcc_msaa_corruption_4bit
!= blend
->dcc_msaa_corruption_4bit
&&
653 sctx
->framebuffer
.nr_samples
>= 2 && sctx
->screen
->dcc_msaa_allowed
))
654 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
656 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
657 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
658 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
659 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
660 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
661 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
662 sctx
->do_update_shaders
= true;
664 if (sctx
->screen
->dpbb_allowed
&&
665 (old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
666 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
667 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
668 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
670 if (sctx
->screen
->has_out_of_order_rast
&&
671 ((old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
672 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
673 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
674 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
675 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
678 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
680 struct si_context
*sctx
= (struct si_context
*)ctx
;
682 if (sctx
->queued
.named
.blend
== state
)
683 si_bind_blend_state(ctx
, sctx
->noop_blend
);
685 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
688 static void si_set_blend_color(struct pipe_context
*ctx
, const struct pipe_blend_color
*state
)
690 struct si_context
*sctx
= (struct si_context
*)ctx
;
691 static const struct pipe_blend_color zeros
;
693 sctx
->blend_color
.state
= *state
;
694 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
695 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
698 static void si_emit_blend_color(struct si_context
*sctx
)
700 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
702 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
703 radeon_emit_array(cs
, (uint32_t *)sctx
->blend_color
.state
.color
, 4);
710 static void si_set_clip_state(struct pipe_context
*ctx
, const struct pipe_clip_state
*state
)
712 struct si_context
*sctx
= (struct si_context
*)ctx
;
713 struct pipe_constant_buffer cb
;
714 static const struct pipe_clip_state zeros
;
716 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
719 sctx
->clip_state
.state
= *state
;
720 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
721 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
724 cb
.user_buffer
= state
->ucp
;
725 cb
.buffer_offset
= 0;
726 cb
.buffer_size
= 4 * 4 * 8;
727 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
728 pipe_resource_reference(&cb
.buffer
, NULL
);
731 static void si_emit_clip_state(struct si_context
*sctx
)
733 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
735 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6 * 4);
736 radeon_emit_array(cs
, (uint32_t *)sctx
->clip_state
.state
.ucp
, 6 * 4);
739 static void si_emit_clip_regs(struct si_context
*sctx
)
741 struct si_shader
*vs
= si_get_vs_state(sctx
);
742 struct si_shader_selector
*vs_sel
= vs
->selector
;
743 struct si_shader_info
*info
= &vs_sel
->info
;
744 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
745 unsigned window_space
= info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
746 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
747 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
748 unsigned culldist_mask
= vs_sel
->culldist_mask
;
751 if (vs
->key
.opt
.clip_disable
) {
752 assert(!info
->culldist_writemask
);
756 total_mask
= clipdist_mask
| culldist_mask
;
758 /* Clip distances on points have no effect, so need to be implemented
759 * as cull distances. This applies for the clipvertex case as well.
761 * Setting this for primitives other than points should have no adverse
764 clipdist_mask
&= rs
->clip_plane_enable
;
765 culldist_mask
|= clipdist_mask
;
767 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
768 unsigned pa_cl_cntl
= S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
769 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) | clipdist_mask
|
770 (culldist_mask
<< 8);
772 if (sctx
->chip_class
>= GFX10
) {
773 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
774 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
, pa_cl_cntl
,
775 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
777 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
, SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
,
778 vs_sel
->pa_cl_vs_out_cntl
| pa_cl_cntl
);
780 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
, SI_TRACKED_PA_CL_CLIP_CNTL
,
781 rs
->pa_cl_clip_cntl
| ucp_mask
| S_028810_CLIP_DISABLE(window_space
));
783 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
784 sctx
->context_roll
= true;
788 * inferred state between framebuffer and rasterizer
790 static void si_update_poly_offset_state(struct si_context
*sctx
)
792 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
794 if (!rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
795 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
799 /* Use the user format, not db_render_format, so that the polygon
800 * offset behaves as expected by applications.
802 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
803 case PIPE_FORMAT_Z16_UNORM
:
804 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
806 default: /* 24-bit */
807 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
809 case PIPE_FORMAT_Z32_FLOAT
:
810 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
811 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
820 static uint32_t si_translate_fill(uint32_t func
)
823 case PIPE_POLYGON_MODE_FILL
:
824 return V_028814_X_DRAW_TRIANGLES
;
825 case PIPE_POLYGON_MODE_LINE
:
826 return V_028814_X_DRAW_LINES
;
827 case PIPE_POLYGON_MODE_POINT
:
828 return V_028814_X_DRAW_POINTS
;
831 return V_028814_X_DRAW_POINTS
;
835 static void *si_create_rs_state(struct pipe_context
*ctx
, const struct pipe_rasterizer_state
*state
)
837 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
838 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
839 struct si_pm4_state
*pm4
= &rs
->pm4
;
841 float psize_min
, psize_max
;
847 if (!state
->front_ccw
) {
848 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
849 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
851 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
852 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
854 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
855 rs
->provoking_vertex_first
= state
->flatshade_first
;
856 rs
->scissor_enable
= state
->scissor
;
857 rs
->clip_halfz
= state
->clip_halfz
;
858 rs
->two_side
= state
->light_twoside
;
859 rs
->multisample_enable
= state
->multisample
;
860 rs
->force_persample_interp
= state
->force_persample_interp
;
861 rs
->clip_plane_enable
= state
->clip_plane_enable
;
862 rs
->half_pixel_center
= state
->half_pixel_center
;
863 rs
->line_stipple_enable
= state
->line_stipple_enable
;
864 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
865 rs
->line_smooth
= state
->line_smooth
;
866 rs
->line_width
= state
->line_width
;
867 rs
->poly_smooth
= state
->poly_smooth
;
868 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
869 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
870 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
871 rs
->flatshade
= state
->flatshade
;
872 rs
->flatshade_first
= state
->flatshade_first
;
873 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
874 rs
->rasterizer_discard
= state
->rasterizer_discard
;
875 rs
->polygon_mode_enabled
=
876 (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
877 (state
->fill_back
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_BACK
));
878 rs
->polygon_mode_is_lines
=
879 (state
->fill_front
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
880 (state
->fill_back
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_BACK
));
881 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
882 ? S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
883 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
)
885 rs
->pa_cl_clip_cntl
= S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
886 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
887 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
888 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
889 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
892 pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
893 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
894 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
895 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
896 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
897 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
898 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
900 /* point size 12.4 fixed point */
901 tmp
= (unsigned)(state
->point_size
* 8.0);
902 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
904 if (state
->point_size_per_vertex
) {
905 psize_min
= util_get_min_point_size(state
);
906 psize_max
= SI_MAX_POINT_SIZE
;
908 /* Force the point size to be as if the vertex output was disabled. */
909 psize_min
= state
->point_size
;
910 psize_max
= state
->point_size
;
912 rs
->max_point_size
= psize_max
;
914 /* Divide by two, because 0.5 = 1 pixel. */
915 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
916 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/ 2)) |
917 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/ 2)));
919 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
920 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/ 2)));
922 pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
923 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
924 S_028A48_MSAA_ENABLE(state
->multisample
|| state
->poly_smooth
|| state
->line_smooth
) |
925 S_028A48_VPORT_SCISSOR_ENABLE(1) |
926 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
928 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
929 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
930 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
931 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
932 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
933 S_028814_FACE(!state
->front_ccw
) |
934 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
935 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
936 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
937 S_028814_POLY_MODE(rs
->polygon_mode_enabled
) |
938 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
939 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
941 if (!rs
->uses_poly_offset
)
944 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
945 if (!rs
->pm4_poly_offset
) {
950 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
951 for (i
= 0; i
< 3; i
++) {
952 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
953 float offset_units
= state
->offset_units
;
954 float offset_scale
= state
->offset_scale
* 16.0f
;
955 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
957 if (!state
->offset_units_unscaled
) {
959 case 0: /* 16-bit zbuffer */
960 offset_units
*= 4.0f
;
961 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
963 case 1: /* 24-bit zbuffer */
964 offset_units
*= 2.0f
;
965 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
967 case 2: /* 32-bit zbuffer */
968 offset_units
*= 1.0f
;
969 pa_su_poly_offset_db_fmt_cntl
=
970 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
975 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, fui(offset_scale
));
976 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
977 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
, fui(offset_scale
));
978 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
979 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, pa_su_poly_offset_db_fmt_cntl
);
985 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
987 struct si_context
*sctx
= (struct si_context
*)ctx
;
988 struct si_state_rasterizer
*old_rs
= (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
989 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
992 rs
= (struct si_state_rasterizer
*)sctx
->discard_rasterizer_state
;
994 if (old_rs
->multisample_enable
!= rs
->multisample_enable
) {
995 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
997 /* Update the small primitive filter workaround if necessary. */
998 if (sctx
->screen
->info
.has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1)
999 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1002 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1003 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1005 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1006 si_update_poly_offset_state(sctx
);
1008 if (old_rs
->scissor_enable
!= rs
->scissor_enable
)
1009 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1011 if (old_rs
->line_width
!= rs
->line_width
|| old_rs
->max_point_size
!= rs
->max_point_size
||
1012 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1013 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1015 if (old_rs
->clip_halfz
!= rs
->clip_halfz
)
1016 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1018 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1019 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1020 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1022 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1023 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1024 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1025 old_rs
->flatshade
!= rs
->flatshade
|| old_rs
->two_side
!= rs
->two_side
||
1026 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1027 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1028 old_rs
->poly_smooth
!= rs
->poly_smooth
|| old_rs
->line_smooth
!= rs
->line_smooth
||
1029 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1030 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1031 sctx
->do_update_shaders
= true;
1034 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1036 struct si_context
*sctx
= (struct si_context
*)ctx
;
1037 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1039 if (sctx
->queued
.named
.rasterizer
== state
)
1040 si_bind_rs_state(ctx
, sctx
->discard_rasterizer_state
);
1042 FREE(rs
->pm4_poly_offset
);
1043 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1047 * infeered state between dsa and stencil ref
1049 static void si_emit_stencil_ref(struct si_context
*sctx
)
1051 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1052 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1053 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1055 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1056 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1057 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1058 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) | S_028430_STENCILOPVAL(1));
1059 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1060 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1061 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1062 S_028434_STENCILOPVAL_BF(1));
1065 static void si_set_stencil_ref(struct pipe_context
*ctx
, const struct pipe_stencil_ref
*state
)
1067 struct si_context
*sctx
= (struct si_context
*)ctx
;
1069 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1072 sctx
->stencil_ref
.state
= *state
;
1073 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1080 static uint32_t si_translate_stencil_op(int s_op
)
1083 case PIPE_STENCIL_OP_KEEP
:
1084 return V_02842C_STENCIL_KEEP
;
1085 case PIPE_STENCIL_OP_ZERO
:
1086 return V_02842C_STENCIL_ZERO
;
1087 case PIPE_STENCIL_OP_REPLACE
:
1088 return V_02842C_STENCIL_REPLACE_TEST
;
1089 case PIPE_STENCIL_OP_INCR
:
1090 return V_02842C_STENCIL_ADD_CLAMP
;
1091 case PIPE_STENCIL_OP_DECR
:
1092 return V_02842C_STENCIL_SUB_CLAMP
;
1093 case PIPE_STENCIL_OP_INCR_WRAP
:
1094 return V_02842C_STENCIL_ADD_WRAP
;
1095 case PIPE_STENCIL_OP_DECR_WRAP
:
1096 return V_02842C_STENCIL_SUB_WRAP
;
1097 case PIPE_STENCIL_OP_INVERT
:
1098 return V_02842C_STENCIL_INVERT
;
1100 PRINT_ERR("Unknown stencil op %d", s_op
);
1107 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1109 return s
->enabled
&& s
->writemask
&&
1110 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
|| s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1111 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1114 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1116 /* REPLACE is normally order invariant, except when the stencil
1117 * reference value is written by the fragment shader. Tracking this
1118 * interaction does not seem worth the effort, so be conservative. */
1119 return op
!= PIPE_STENCIL_OP_INCR
&& op
!= PIPE_STENCIL_OP_DECR
&& op
!= PIPE_STENCIL_OP_REPLACE
;
1122 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1123 * invariant in the sense that the set of passing fragments as well as the
1124 * final stencil buffer result does not depend on the order of fragments. */
1125 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1127 return !state
->enabled
|| !state
->writemask
||
1128 /* The following assumes that Z writes are disabled. */
1129 (state
->func
== PIPE_FUNC_ALWAYS
&& si_order_invariant_stencil_op(state
->zpass_op
) &&
1130 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1131 (state
->func
== PIPE_FUNC_NEVER
&& si_order_invariant_stencil_op(state
->fail_op
));
1134 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1135 const struct pipe_depth_stencil_alpha_state
*state
)
1137 struct si_context
*sctx
= (struct si_context
*)ctx
;
1138 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1139 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1140 unsigned db_depth_control
;
1141 uint32_t db_stencil_control
= 0;
1147 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1148 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1149 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1150 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1153 S_028800_Z_ENABLE(state
->depth
.enabled
) | S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1154 S_028800_ZFUNC(state
->depth
.func
) | S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1157 if (state
->stencil
[0].enabled
) {
1158 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1159 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1160 db_stencil_control
|=
1161 S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1162 db_stencil_control
|=
1163 S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1164 db_stencil_control
|=
1165 S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1167 if (state
->stencil
[1].enabled
) {
1168 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1169 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1170 db_stencil_control
|=
1171 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1172 db_stencil_control
|=
1173 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1174 db_stencil_control
|=
1175 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1180 if (state
->alpha
.enabled
) {
1181 dsa
->alpha_func
= state
->alpha
.func
;
1183 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+ SI_SGPR_ALPHA_REF
* 4,
1184 fui(state
->alpha
.ref_value
));
1186 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1189 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1190 if (state
->stencil
[0].enabled
)
1191 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1192 if (state
->depth
.bounds_test
) {
1193 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1194 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1197 dsa
->depth_enabled
= state
->depth
.enabled
;
1198 dsa
->depth_write_enabled
= state
->depth
.enabled
&& state
->depth
.writemask
;
1199 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1200 dsa
->stencil_write_enabled
=
1201 state
->stencil
[0].enabled
&&
1202 (si_dsa_writes_stencil(&state
->stencil
[0]) || si_dsa_writes_stencil(&state
->stencil
[1]));
1203 dsa
->db_can_write
= dsa
->depth_write_enabled
|| dsa
->stencil_write_enabled
;
1205 bool zfunc_is_ordered
=
1206 state
->depth
.func
== PIPE_FUNC_NEVER
|| state
->depth
.func
== PIPE_FUNC_LESS
||
1207 state
->depth
.func
== PIPE_FUNC_LEQUAL
|| state
->depth
.func
== PIPE_FUNC_GREATER
||
1208 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1210 bool nozwrite_and_order_invariant_stencil
=
1211 !dsa
->db_can_write
||
1212 (!dsa
->depth_write_enabled
&& si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1213 si_order_invariant_stencil_state(&state
->stencil
[1]));
1215 dsa
->order_invariance
[1].zs
=
1216 nozwrite_and_order_invariant_stencil
|| (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1217 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1219 dsa
->order_invariance
[1].pass_set
=
1220 nozwrite_and_order_invariant_stencil
||
1221 (!dsa
->stencil_write_enabled
&&
1222 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
));
1223 dsa
->order_invariance
[0].pass_set
=
1224 !dsa
->depth_write_enabled
||
1225 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
);
1227 dsa
->order_invariance
[1].pass_last
= sctx
->screen
->assume_no_z_fights
&&
1228 !dsa
->stencil_write_enabled
&& dsa
->depth_write_enabled
&&
1230 dsa
->order_invariance
[0].pass_last
=
1231 sctx
->screen
->assume_no_z_fights
&& dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1236 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1238 struct si_context
*sctx
= (struct si_context
*)ctx
;
1239 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1240 struct si_state_dsa
*dsa
= state
;
1243 dsa
= (struct si_state_dsa
*)sctx
->noop_dsa
;
1245 si_pm4_bind_state(sctx
, dsa
, dsa
);
1247 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1248 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1249 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1250 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1253 if (old_dsa
->alpha_func
!= dsa
->alpha_func
)
1254 sctx
->do_update_shaders
= true;
1256 if (sctx
->screen
->dpbb_allowed
&& ((old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1257 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1258 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1259 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1261 if (sctx
->screen
->has_out_of_order_rast
&&
1262 (memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1263 sizeof(old_dsa
->order_invariance
))))
1264 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1267 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1269 struct si_context
*sctx
= (struct si_context
*)ctx
;
1271 if (sctx
->queued
.named
.dsa
== state
)
1272 si_bind_dsa_state(ctx
, sctx
->noop_dsa
);
1274 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1277 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1279 struct pipe_depth_stencil_alpha_state dsa
= {};
1281 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1284 /* DB RENDER STATE */
1286 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1288 struct si_context
*sctx
= (struct si_context
*)ctx
;
1290 /* Pipeline stat & streamout queries. */
1292 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1293 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1295 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1296 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1299 /* Occlusion queries. */
1300 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1301 sctx
->occlusion_queries_disabled
= !enable
;
1302 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1306 void si_set_occlusion_query_state(struct si_context
*sctx
, bool old_perfect_enable
)
1308 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1310 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1312 if (perfect_enable
!= old_perfect_enable
)
1313 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1316 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1318 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1320 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1321 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1323 st
->saved_ssbo_writable_mask
= 0;
1325 for (unsigned i
= 0; i
< 3; i
++) {
1326 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1327 (1u << si_get_shaderbuf_slot(i
)))
1328 st
->saved_ssbo_writable_mask
|= 1 << i
;
1332 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1334 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1336 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1337 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1339 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1340 st
->saved_ssbo_writable_mask
);
1341 for (unsigned i
= 0; i
< 3; ++i
)
1342 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1345 static void si_emit_db_render_state(struct si_context
*sctx
)
1347 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1348 unsigned db_shader_control
, db_render_control
, db_count_control
;
1349 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1351 /* DB_RENDER_CONTROL */
1352 if (sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
) {
1353 db_render_control
= S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1354 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1355 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1356 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1357 db_render_control
= S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1358 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1360 db_render_control
= S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1361 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1364 /* DB_COUNT_CONTROL (occlusion queries) */
1365 if (sctx
->num_occlusion_queries
> 0 && !sctx
->occlusion_queries_disabled
) {
1366 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1367 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1369 if (sctx
->chip_class
>= GFX7
) {
1370 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1372 /* Stoney doesn't increment occlusion query counters
1373 * if the sample rate is 16x. Use 8x sample rate instead.
1375 if (sctx
->family
== CHIP_STONEY
)
1376 log_sample_rate
= MIN2(log_sample_rate
, 3);
1378 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1379 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1380 S_028004_SAMPLE_RATE(log_sample_rate
) | S_028004_ZPASS_ENABLE(1) |
1381 S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
1383 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1384 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1387 /* Disable occlusion queries. */
1388 if (sctx
->chip_class
>= GFX7
) {
1389 db_count_control
= 0;
1391 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1395 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
, SI_TRACKED_DB_RENDER_CONTROL
,
1396 db_render_control
, db_count_control
);
1398 /* DB_RENDER_OVERRIDE2 */
1399 radeon_opt_set_context_reg(
1400 sctx
, R_028010_DB_RENDER_OVERRIDE2
, SI_TRACKED_DB_RENDER_OVERRIDE2
,
1401 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1402 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1403 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1405 db_shader_control
= sctx
->ps_db_shader_control
;
1407 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1408 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1409 db_shader_control
&= C_02880C_Z_ORDER
;
1410 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1413 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1414 if (!rs
->multisample_enable
)
1415 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1417 if (sctx
->screen
->info
.has_rbplus
&& !sctx
->screen
->info
.rbplus_allowed
)
1418 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1420 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
, SI_TRACKED_DB_SHADER_CONTROL
,
1423 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1424 sctx
->context_roll
= true;
1428 * format translation
1430 static uint32_t si_translate_colorformat(enum pipe_format format
)
1432 const struct util_format_description
*desc
= util_format_description(format
);
1434 return V_028C70_COLOR_INVALID
;
1436 #define HAS_SIZE(x, y, z, w) \
1437 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1438 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1440 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1441 return V_028C70_COLOR_10_11_11
;
1443 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1444 return V_028C70_COLOR_INVALID
;
1446 /* hw cannot support mixed formats (except depth/stencil, since
1447 * stencil is not written to). */
1448 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1449 return V_028C70_COLOR_INVALID
;
1451 switch (desc
->nr_channels
) {
1453 switch (desc
->channel
[0].size
) {
1455 return V_028C70_COLOR_8
;
1457 return V_028C70_COLOR_16
;
1459 return V_028C70_COLOR_32
;
1463 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1464 switch (desc
->channel
[0].size
) {
1466 return V_028C70_COLOR_8_8
;
1468 return V_028C70_COLOR_16_16
;
1470 return V_028C70_COLOR_32_32
;
1472 } else if (HAS_SIZE(8, 24, 0, 0)) {
1473 return V_028C70_COLOR_24_8
;
1474 } else if (HAS_SIZE(24, 8, 0, 0)) {
1475 return V_028C70_COLOR_8_24
;
1479 if (HAS_SIZE(5, 6, 5, 0)) {
1480 return V_028C70_COLOR_5_6_5
;
1481 } else if (HAS_SIZE(32, 8, 24, 0)) {
1482 return V_028C70_COLOR_X24_8_32_FLOAT
;
1486 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1487 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1488 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1489 switch (desc
->channel
[0].size
) {
1491 return V_028C70_COLOR_4_4_4_4
;
1493 return V_028C70_COLOR_8_8_8_8
;
1495 return V_028C70_COLOR_16_16_16_16
;
1497 return V_028C70_COLOR_32_32_32_32
;
1499 } else if (HAS_SIZE(5, 5, 5, 1)) {
1500 return V_028C70_COLOR_1_5_5_5
;
1501 } else if (HAS_SIZE(1, 5, 5, 5)) {
1502 return V_028C70_COLOR_5_5_5_1
;
1503 } else if (HAS_SIZE(10, 10, 10, 2)) {
1504 return V_028C70_COLOR_2_10_10_10
;
1508 return V_028C70_COLOR_INVALID
;
1511 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1513 if (SI_BIG_ENDIAN
) {
1514 switch (colorformat
) {
1515 /* 8-bit buffers. */
1516 case V_028C70_COLOR_8
:
1517 return V_028C70_ENDIAN_NONE
;
1519 /* 16-bit buffers. */
1520 case V_028C70_COLOR_5_6_5
:
1521 case V_028C70_COLOR_1_5_5_5
:
1522 case V_028C70_COLOR_4_4_4_4
:
1523 case V_028C70_COLOR_16
:
1524 case V_028C70_COLOR_8_8
:
1525 return V_028C70_ENDIAN_8IN16
;
1527 /* 32-bit buffers. */
1528 case V_028C70_COLOR_8_8_8_8
:
1529 case V_028C70_COLOR_2_10_10_10
:
1530 case V_028C70_COLOR_8_24
:
1531 case V_028C70_COLOR_24_8
:
1532 case V_028C70_COLOR_16_16
:
1533 return V_028C70_ENDIAN_8IN32
;
1535 /* 64-bit buffers. */
1536 case V_028C70_COLOR_16_16_16_16
:
1537 return V_028C70_ENDIAN_8IN16
;
1539 case V_028C70_COLOR_32_32
:
1540 return V_028C70_ENDIAN_8IN32
;
1542 /* 128-bit buffers. */
1543 case V_028C70_COLOR_32_32_32_32
:
1544 return V_028C70_ENDIAN_8IN32
;
1546 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1549 return V_028C70_ENDIAN_NONE
;
1553 static uint32_t si_translate_dbformat(enum pipe_format format
)
1556 case PIPE_FORMAT_Z16_UNORM
:
1557 return V_028040_Z_16
;
1558 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1559 case PIPE_FORMAT_X8Z24_UNORM
:
1560 case PIPE_FORMAT_Z24X8_UNORM
:
1561 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1562 return V_028040_Z_24
; /* deprecated on AMD GCN */
1563 case PIPE_FORMAT_Z32_FLOAT
:
1564 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1565 return V_028040_Z_32_FLOAT
;
1567 return V_028040_Z_INVALID
;
1572 * Texture translation
1575 static uint32_t si_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
1576 const struct util_format_description
*desc
,
1579 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1580 bool uniform
= true;
1583 assert(sscreen
->info
.chip_class
<= GFX9
);
1585 /* Colorspace (return non-RGB formats directly). */
1586 switch (desc
->colorspace
) {
1587 /* Depth stencil formats */
1588 case UTIL_FORMAT_COLORSPACE_ZS
:
1590 case PIPE_FORMAT_Z16_UNORM
:
1591 return V_008F14_IMG_DATA_FORMAT_16
;
1592 case PIPE_FORMAT_X24S8_UINT
:
1593 case PIPE_FORMAT_S8X24_UINT
:
1595 * Implemented as an 8_8_8_8 data format to fix texture
1596 * gathers in stencil sampling. This affects at least
1597 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1599 if (sscreen
->info
.chip_class
<= GFX8
)
1600 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1602 if (format
== PIPE_FORMAT_X24S8_UINT
)
1603 return V_008F14_IMG_DATA_FORMAT_8_24
;
1605 return V_008F14_IMG_DATA_FORMAT_24_8
;
1606 case PIPE_FORMAT_Z24X8_UNORM
:
1607 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1608 return V_008F14_IMG_DATA_FORMAT_8_24
;
1609 case PIPE_FORMAT_X8Z24_UNORM
:
1610 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1611 return V_008F14_IMG_DATA_FORMAT_24_8
;
1612 case PIPE_FORMAT_S8_UINT
:
1613 return V_008F14_IMG_DATA_FORMAT_8
;
1614 case PIPE_FORMAT_Z32_FLOAT
:
1615 return V_008F14_IMG_DATA_FORMAT_32
;
1616 case PIPE_FORMAT_X32_S8X24_UINT
:
1617 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1618 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1623 case UTIL_FORMAT_COLORSPACE_YUV
:
1624 goto out_unknown
; /* TODO */
1626 case UTIL_FORMAT_COLORSPACE_SRGB
:
1627 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1635 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1636 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1640 case PIPE_FORMAT_RGTC1_SNORM
:
1641 case PIPE_FORMAT_LATC1_SNORM
:
1642 case PIPE_FORMAT_RGTC1_UNORM
:
1643 case PIPE_FORMAT_LATC1_UNORM
:
1644 return V_008F14_IMG_DATA_FORMAT_BC4
;
1645 case PIPE_FORMAT_RGTC2_SNORM
:
1646 case PIPE_FORMAT_LATC2_SNORM
:
1647 case PIPE_FORMAT_RGTC2_UNORM
:
1648 case PIPE_FORMAT_LATC2_UNORM
:
1649 return V_008F14_IMG_DATA_FORMAT_BC5
;
1655 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1656 (sscreen
->info
.family
== CHIP_STONEY
|| sscreen
->info
.family
== CHIP_VEGA10
||
1657 sscreen
->info
.family
== CHIP_RAVEN
)) {
1659 case PIPE_FORMAT_ETC1_RGB8
:
1660 case PIPE_FORMAT_ETC2_RGB8
:
1661 case PIPE_FORMAT_ETC2_SRGB8
:
1662 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1663 case PIPE_FORMAT_ETC2_RGB8A1
:
1664 case PIPE_FORMAT_ETC2_SRGB8A1
:
1665 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1666 case PIPE_FORMAT_ETC2_RGBA8
:
1667 case PIPE_FORMAT_ETC2_SRGBA8
:
1668 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1669 case PIPE_FORMAT_ETC2_R11_UNORM
:
1670 case PIPE_FORMAT_ETC2_R11_SNORM
:
1671 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1672 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1673 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1674 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1680 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1681 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1685 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1686 case PIPE_FORMAT_BPTC_SRGBA
:
1687 return V_008F14_IMG_DATA_FORMAT_BC7
;
1688 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1689 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1690 return V_008F14_IMG_DATA_FORMAT_BC6
;
1696 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1698 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1699 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1700 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1701 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1702 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1703 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1709 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1710 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1714 case PIPE_FORMAT_DXT1_RGB
:
1715 case PIPE_FORMAT_DXT1_RGBA
:
1716 case PIPE_FORMAT_DXT1_SRGB
:
1717 case PIPE_FORMAT_DXT1_SRGBA
:
1718 return V_008F14_IMG_DATA_FORMAT_BC1
;
1719 case PIPE_FORMAT_DXT3_RGBA
:
1720 case PIPE_FORMAT_DXT3_SRGBA
:
1721 return V_008F14_IMG_DATA_FORMAT_BC2
;
1722 case PIPE_FORMAT_DXT5_RGBA
:
1723 case PIPE_FORMAT_DXT5_SRGBA
:
1724 return V_008F14_IMG_DATA_FORMAT_BC3
;
1730 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1731 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1732 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1733 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1736 /* R8G8Bx_SNORM - TODO CxV8U8 */
1738 /* hw cannot support mixed formats (except depth/stencil, since only
1740 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1743 /* See whether the components are of the same size. */
1744 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1745 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1748 /* Non-uniform formats. */
1750 switch (desc
->nr_channels
) {
1752 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 6 &&
1753 desc
->channel
[2].size
== 5) {
1754 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1758 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 5 &&
1759 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 1) {
1760 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1762 if (desc
->channel
[0].size
== 1 && desc
->channel
[1].size
== 5 &&
1763 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 5) {
1764 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1766 if (desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1767 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2) {
1768 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1775 if (first_non_void
< 0 || first_non_void
> 3)
1778 /* uniform formats */
1779 switch (desc
->channel
[first_non_void
].size
) {
1781 switch (desc
->nr_channels
) {
1782 #if 0 /* Not supported for render targets */
1784 return V_008F14_IMG_DATA_FORMAT_4_4
;
1787 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1791 switch (desc
->nr_channels
) {
1793 return V_008F14_IMG_DATA_FORMAT_8
;
1795 return V_008F14_IMG_DATA_FORMAT_8_8
;
1797 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1801 switch (desc
->nr_channels
) {
1803 return V_008F14_IMG_DATA_FORMAT_16
;
1805 return V_008F14_IMG_DATA_FORMAT_16_16
;
1807 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1811 switch (desc
->nr_channels
) {
1813 return V_008F14_IMG_DATA_FORMAT_32
;
1815 return V_008F14_IMG_DATA_FORMAT_32_32
;
1816 #if 0 /* Not supported for render targets */
1818 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1821 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1829 static unsigned si_tex_wrap(unsigned wrap
)
1833 case PIPE_TEX_WRAP_REPEAT
:
1834 return V_008F30_SQ_TEX_WRAP
;
1835 case PIPE_TEX_WRAP_CLAMP
:
1836 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1837 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1838 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1839 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1840 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1841 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1842 return V_008F30_SQ_TEX_MIRROR
;
1843 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1844 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1845 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1846 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1847 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1848 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1852 static unsigned si_tex_mipfilter(unsigned filter
)
1855 case PIPE_TEX_MIPFILTER_NEAREST
:
1856 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1857 case PIPE_TEX_MIPFILTER_LINEAR
:
1858 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1860 case PIPE_TEX_MIPFILTER_NONE
:
1861 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1865 static unsigned si_tex_compare(unsigned compare
)
1869 case PIPE_FUNC_NEVER
:
1870 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1871 case PIPE_FUNC_LESS
:
1872 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1873 case PIPE_FUNC_EQUAL
:
1874 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1875 case PIPE_FUNC_LEQUAL
:
1876 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1877 case PIPE_FUNC_GREATER
:
1878 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1879 case PIPE_FUNC_NOTEQUAL
:
1880 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1881 case PIPE_FUNC_GEQUAL
:
1882 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1883 case PIPE_FUNC_ALWAYS
:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1888 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
, unsigned view_target
,
1889 unsigned nr_samples
)
1891 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1893 if (view_target
== PIPE_TEXTURE_CUBE
|| view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1894 res_target
= view_target
;
1895 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1896 else if (res_target
== PIPE_TEXTURE_CUBE
|| res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1897 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1899 /* GFX9 allocates 1D textures as 2D. */
1900 if ((res_target
== PIPE_TEXTURE_1D
|| res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1901 sscreen
->info
.chip_class
== GFX9
&&
1902 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1903 if (res_target
== PIPE_TEXTURE_1D
)
1904 res_target
= PIPE_TEXTURE_2D
;
1906 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1909 switch (res_target
) {
1911 case PIPE_TEXTURE_1D
:
1912 return V_008F1C_SQ_RSRC_IMG_1D
;
1913 case PIPE_TEXTURE_1D_ARRAY
:
1914 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1915 case PIPE_TEXTURE_2D
:
1916 case PIPE_TEXTURE_RECT
:
1917 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
: V_008F1C_SQ_RSRC_IMG_2D
;
1918 case PIPE_TEXTURE_2D_ARRAY
:
1919 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1920 case PIPE_TEXTURE_3D
:
1921 return V_008F1C_SQ_RSRC_IMG_3D
;
1922 case PIPE_TEXTURE_CUBE
:
1923 case PIPE_TEXTURE_CUBE_ARRAY
:
1924 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1929 * Format support testing
1932 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1934 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1936 if (sscreen
->info
.chip_class
>= GFX10
) {
1937 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
1938 if (!fmt
->img_format
|| fmt
->buffers_only
)
1943 const struct util_format_description
*desc
= util_format_description(format
);
1947 return si_translate_texformat(screen
, format
, desc
,
1948 util_format_get_first_non_void_channel(format
)) != ~0U;
1951 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1952 const struct util_format_description
*desc
,
1957 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
1959 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1960 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1962 assert(first_non_void
>= 0);
1964 if (desc
->nr_channels
== 4 && desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1965 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2)
1966 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1968 /* See whether the components are of the same size. */
1969 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1970 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1971 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1974 switch (desc
->channel
[first_non_void
].size
) {
1976 switch (desc
->nr_channels
) {
1978 case 3: /* 3 loads */
1979 return V_008F0C_BUF_DATA_FORMAT_8
;
1981 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1983 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1987 switch (desc
->nr_channels
) {
1989 case 3: /* 3 loads */
1990 return V_008F0C_BUF_DATA_FORMAT_16
;
1992 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1994 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1998 switch (desc
->nr_channels
) {
2000 return V_008F0C_BUF_DATA_FORMAT_32
;
2002 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2004 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2006 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2010 /* Legacy double formats. */
2011 switch (desc
->nr_channels
) {
2012 case 1: /* 1 load */
2013 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2014 case 2: /* 1 load */
2015 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2016 case 3: /* 3 loads */
2017 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2018 case 4: /* 2 loads */
2019 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2024 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2027 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2028 const struct util_format_description
*desc
,
2031 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2033 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2034 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2036 assert(first_non_void
>= 0);
2038 switch (desc
->channel
[first_non_void
].type
) {
2039 case UTIL_FORMAT_TYPE_SIGNED
:
2040 case UTIL_FORMAT_TYPE_FIXED
:
2041 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2042 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2043 else if (desc
->channel
[first_non_void
].normalized
)
2044 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2046 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2048 case UTIL_FORMAT_TYPE_UNSIGNED
:
2049 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2050 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2051 else if (desc
->channel
[first_non_void
].normalized
)
2052 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2054 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2056 case UTIL_FORMAT_TYPE_FLOAT
:
2058 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2062 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2065 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2066 const struct util_format_description
*desc
;
2068 unsigned data_format
;
2070 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_VERTEX_BUFFER
)) ==
2073 desc
= util_format_description(format
);
2077 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2078 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2079 * for read-only access (with caveats surrounding bounds checks), but
2080 * obviously fails for write access which we have to implement for
2081 * shader images. Luckily, OpenGL doesn't expect this to be supported
2082 * anyway, and so the only impact is on PBO uploads / downloads, which
2083 * shouldn't be expected to be fast for GL_RGB anyway.
2085 if (desc
->block
.bits
== 3 * 8 || desc
->block
.bits
== 3 * 16) {
2086 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2087 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2093 if (sscreen
->info
.chip_class
>= GFX10
) {
2094 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2095 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2100 first_non_void
= util_format_get_first_non_void_channel(format
);
2101 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2102 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2108 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2110 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2111 si_translate_colorswap(format
, false) != ~0U;
2114 static bool si_is_zs_format_supported(enum pipe_format format
)
2116 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2119 static bool si_is_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2120 enum pipe_texture_target target
, unsigned sample_count
,
2121 unsigned storage_sample_count
, unsigned usage
)
2123 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2124 unsigned retval
= 0;
2126 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2127 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2131 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2134 if (sample_count
> 1) {
2135 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2138 /* Only power-of-two sample counts are supported. */
2139 if (!util_is_power_of_two_or_zero(sample_count
) ||
2140 !util_is_power_of_two_or_zero(storage_sample_count
))
2143 /* MSAA support without framebuffer attachments. */
2144 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2147 if (!sscreen
->info
.has_eqaa_surface_allocator
|| util_format_is_depth_or_stencil(format
)) {
2148 /* Color without EQAA or depth/stencil. */
2149 if (sample_count
> 8 || sample_count
!= storage_sample_count
)
2152 /* Color with EQAA. */
2153 if (sample_count
> 16 || storage_sample_count
> 8)
2158 if (usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
)) {
2159 if (target
== PIPE_BUFFER
) {
2160 retval
|= si_is_vertex_format_supported(
2161 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
));
2163 if (si_is_sampler_format_supported(screen
, format
))
2164 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
);
2168 if ((usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2169 PIPE_BIND_SHARED
| PIPE_BIND_BLENDABLE
)) &&
2170 si_is_colorbuffer_format_supported(format
)) {
2171 retval
|= usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2173 if (!util_format_is_pure_integer(format
) && !util_format_is_depth_or_stencil(format
))
2174 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2177 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) && si_is_zs_format_supported(format
)) {
2178 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2181 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2182 retval
|= si_is_vertex_format_supported(screen
, format
, PIPE_BIND_VERTEX_BUFFER
);
2185 if ((usage
& PIPE_BIND_LINEAR
) && !util_format_is_compressed(format
) &&
2186 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2187 retval
|= PIPE_BIND_LINEAR
;
2189 return retval
== usage
;
2193 * framebuffer handling
2196 static void si_choose_spi_color_formats(struct si_surface
*surf
, unsigned format
, unsigned swap
,
2197 unsigned ntype
, bool is_depth
)
2199 /* Alpha is needed for alpha-to-coverage.
2200 * Blending may be with or without alpha.
2202 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2203 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2204 unsigned blend
= 0; /* supports blending, but may not export alpha */
2205 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2207 /* Choose the SPI color formats. These are required values for RB+.
2208 * Other chips have multiple choices, though they are not necessarily better.
2211 case V_028C70_COLOR_5_6_5
:
2212 case V_028C70_COLOR_1_5_5_5
:
2213 case V_028C70_COLOR_5_5_5_1
:
2214 case V_028C70_COLOR_4_4_4_4
:
2215 case V_028C70_COLOR_10_11_11
:
2216 case V_028C70_COLOR_11_11_10
:
2217 case V_028C70_COLOR_8
:
2218 case V_028C70_COLOR_8_8
:
2219 case V_028C70_COLOR_8_8_8_8
:
2220 case V_028C70_COLOR_10_10_10_2
:
2221 case V_028C70_COLOR_2_10_10_10
:
2222 if (ntype
== V_028C70_NUMBER_UINT
)
2223 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2224 else if (ntype
== V_028C70_NUMBER_SINT
)
2225 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2227 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2230 case V_028C70_COLOR_16
:
2231 case V_028C70_COLOR_16_16
:
2232 case V_028C70_COLOR_16_16_16_16
:
2233 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) {
2234 /* UNORM16 and SNORM16 don't support blending */
2235 if (ntype
== V_028C70_NUMBER_UNORM
)
2236 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2238 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2240 /* Use 32 bits per channel for blending. */
2241 if (format
== V_028C70_COLOR_16
) {
2242 if (swap
== V_028C70_SWAP_STD
) { /* R */
2243 blend
= V_028714_SPI_SHADER_32_R
;
2244 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2245 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2246 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2249 } else if (format
== V_028C70_COLOR_16_16
) {
2250 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2251 blend
= V_028714_SPI_SHADER_32_GR
;
2252 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2253 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2254 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2257 } else /* 16_16_16_16 */
2258 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2259 } else if (ntype
== V_028C70_NUMBER_UINT
)
2260 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2261 else if (ntype
== V_028C70_NUMBER_SINT
)
2262 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2263 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2264 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2269 case V_028C70_COLOR_32
:
2270 if (swap
== V_028C70_SWAP_STD
) { /* R */
2271 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2272 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2273 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2274 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2279 case V_028C70_COLOR_32_32
:
2280 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2281 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2282 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2283 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2284 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2289 case V_028C70_COLOR_32_32_32_32
:
2290 case V_028C70_COLOR_8_24
:
2291 case V_028C70_COLOR_24_8
:
2292 case V_028C70_COLOR_X24_8_32_FLOAT
:
2293 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2301 /* The DB->CB copy needs 32_ABGR. */
2303 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2305 surf
->spi_shader_col_format
= normal
;
2306 surf
->spi_shader_col_format_alpha
= alpha
;
2307 surf
->spi_shader_col_format_blend
= blend
;
2308 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2311 static void si_initialize_color_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2313 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2314 unsigned color_info
, color_attrib
;
2315 unsigned format
, swap
, ntype
, endian
;
2316 const struct util_format_description
*desc
;
2318 unsigned blend_clamp
= 0, blend_bypass
= 0;
2320 desc
= util_format_description(surf
->base
.format
);
2321 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2322 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2326 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2327 ntype
= V_028C70_NUMBER_FLOAT
;
2329 ntype
= V_028C70_NUMBER_UNORM
;
2330 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2331 ntype
= V_028C70_NUMBER_SRGB
;
2332 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2333 if (desc
->channel
[firstchan
].pure_integer
) {
2334 ntype
= V_028C70_NUMBER_SINT
;
2336 assert(desc
->channel
[firstchan
].normalized
);
2337 ntype
= V_028C70_NUMBER_SNORM
;
2339 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2340 if (desc
->channel
[firstchan
].pure_integer
) {
2341 ntype
= V_028C70_NUMBER_UINT
;
2343 assert(desc
->channel
[firstchan
].normalized
);
2344 ntype
= V_028C70_NUMBER_UNORM
;
2349 format
= si_translate_colorformat(surf
->base
.format
);
2350 if (format
== V_028C70_COLOR_INVALID
) {
2351 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2353 assert(format
!= V_028C70_COLOR_INVALID
);
2354 swap
= si_translate_colorswap(surf
->base
.format
, false);
2355 endian
= si_colorformat_endian_swap(format
);
2357 /* blend clamp should be set for all NORM/SRGB types */
2358 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
2359 ntype
== V_028C70_NUMBER_SRGB
)
2362 /* set blend bypass according to docs if SINT/UINT or
2363 8/24 COLOR variants */
2364 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2365 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2366 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2371 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2372 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_8_8
||
2373 format
== V_028C70_COLOR_8_8_8_8
)
2374 surf
->color_is_int8
= true;
2375 else if (format
== V_028C70_COLOR_10_10_10_2
|| format
== V_028C70_COLOR_2_10_10_10
)
2376 surf
->color_is_int10
= true;
2380 S_028C70_FORMAT(format
) | S_028C70_COMP_SWAP(swap
) | S_028C70_BLEND_CLAMP(blend_clamp
) |
2381 S_028C70_BLEND_BYPASS(blend_bypass
) | S_028C70_SIMPLE_FLOAT(1) |
2382 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&& ntype
!= V_028C70_NUMBER_SNORM
&&
2383 ntype
!= V_028C70_NUMBER_SRGB
&& format
!= V_028C70_COLOR_8_24
&&
2384 format
!= V_028C70_COLOR_24_8
) |
2385 S_028C70_NUMBER_TYPE(ntype
) | S_028C70_ENDIAN(endian
);
2387 /* Intensity is implemented as Red, so treat it that way. */
2388 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2389 util_format_is_intensity(surf
->base
.format
));
2391 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2392 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2393 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2395 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) | S_028C74_NUM_FRAGMENTS(log_fragments
);
2397 if (tex
->surface
.fmask_offset
) {
2398 color_info
|= S_028C70_COMPRESSION(1);
2399 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2401 if (sctx
->chip_class
== GFX6
) {
2402 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2403 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2408 if (sctx
->chip_class
>= GFX10
) {
2409 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2411 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2412 64 for APU because all of our APUs to date use DIMMs which have
2413 a request granularity size of 64B while all other chips have a
2415 if (!sctx
->screen
->info
.has_dedicated_vram
)
2416 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2418 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2419 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
) |
2420 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2421 S_028C78_INDEPENDENT_64B_BLOCKS(tex
->surface
.u
.gfx9
.dcc
.independent_64B_blocks
) |
2422 S_028C78_INDEPENDENT_128B_BLOCKS(tex
->surface
.u
.gfx9
.dcc
.independent_128B_blocks
);
2423 } else if (sctx
->chip_class
>= GFX8
) {
2424 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2425 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2427 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2428 64 for APU because all of our APUs to date use DIMMs which have
2429 a request granularity size of 64B while all other chips have a
2431 if (!sctx
->screen
->info
.has_dedicated_vram
)
2432 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2434 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2435 if (tex
->surface
.bpe
== 1)
2436 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2437 else if (tex
->surface
.bpe
== 2)
2438 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2441 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2442 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2443 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2446 /* This must be set for fast clear to work without FMASK. */
2447 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2448 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2449 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2452 /* GFX10 field has the same base shift as the GFX6 field */
2453 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2454 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2455 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2457 if (sctx
->chip_class
>= GFX10
) {
2458 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2460 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2461 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2462 S_028EE0_RESOURCE_LEVEL(1);
2463 } else if (sctx
->chip_class
== GFX9
) {
2464 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2465 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2466 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2469 if (sctx
->chip_class
>= GFX9
) {
2470 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2471 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2472 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2475 surf
->cb_color_view
= color_view
;
2476 surf
->cb_color_info
= color_info
;
2477 surf
->cb_color_attrib
= color_attrib
;
2479 /* Determine pixel shader export format */
2480 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2482 surf
->color_initialized
= true;
2485 static void si_init_depth_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2487 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2488 unsigned level
= surf
->base
.u
.tex
.level
;
2489 unsigned format
, stencil_format
;
2490 uint32_t z_info
, s_info
;
2492 format
= si_translate_dbformat(tex
->db_render_format
);
2493 stencil_format
= tex
->surface
.has_stencil
? V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2495 assert(format
!= V_028040_Z_INVALID
);
2496 if (format
== V_028040_Z_INVALID
)
2497 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2499 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2500 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2501 surf
->db_htile_data_base
= 0;
2502 surf
->db_htile_surface
= 0;
2504 if (sctx
->chip_class
>= GFX10
) {
2505 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2506 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2509 if (sctx
->chip_class
>= GFX9
) {
2510 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2511 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2512 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2513 z_info
= S_028038_FORMAT(format
) |
2514 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2515 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2516 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2517 s_info
= S_02803C_FORMAT(stencil_format
) |
2518 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2520 if (sctx
->chip_class
== GFX9
) {
2521 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2522 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2524 surf
->db_depth_view
|= S_028008_MIPID(level
);
2525 surf
->db_depth_size
=
2526 S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) | S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2528 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2529 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) | S_028038_ALLOW_EXPCLEAR(1);
2531 if (tex
->tc_compatible_htile
) {
2532 unsigned max_zplanes
= 4;
2534 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&& tex
->buffer
.b
.b
.nr_samples
> 1)
2537 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
2539 if (sctx
->chip_class
>= GFX10
) {
2540 z_info
|= S_028040_ITERATE_FLUSH(1);
2541 s_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
2543 z_info
|= S_028038_ITERATE_FLUSH(1);
2544 s_info
|= S_02803C_ITERATE_FLUSH(1);
2548 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2549 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2550 * See that for explanation.
2552 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2554 /* Use all HTILE for depth if there's no stencil. */
2555 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2558 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2559 surf
->db_htile_surface
=
2560 S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
2561 if (sctx
->chip_class
== GFX9
) {
2562 surf
->db_htile_surface
|= S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2567 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2569 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2571 surf
->db_depth_base
=
2572 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2573 surf
->db_stencil_base
=
2574 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2577 S_028040_FORMAT(format
) | S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2578 s_info
= S_028044_FORMAT(stencil_format
);
2579 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2581 if (sctx
->chip_class
>= GFX7
) {
2582 struct radeon_info
*info
= &sctx
->screen
->info
;
2583 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2584 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2585 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2586 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2587 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2588 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2590 surf
->db_depth_info
|= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2591 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2592 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2593 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2594 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2595 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2596 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2597 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2599 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2600 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2601 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2602 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2605 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2606 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2607 surf
->db_depth_slice
=
2608 S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
* levelinfo
->nblk_y
) / 64 - 1);
2610 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2611 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1);
2613 if (tex
->surface
.has_stencil
) {
2614 /* Workaround: For a not yet understood reason, the
2615 * combination of MSAA, fast stencil clear and stencil
2616 * decompress messes with subsequent stencil buffer
2617 * uses. Problem was reproduced on Verde, Bonaire,
2618 * Tonga, and Carrizo.
2620 * Disabling EXPCLEAR works around the problem.
2622 * Check piglit's arb_texture_multisample-stencil-clear
2623 * test if you want to try changing this.
2625 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2626 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2627 } else if (!tex
->tc_compatible_htile
) {
2628 /* Use all of the htile_buffer for depth if there's no stencil.
2629 * This must not be set when TC-compatible HTILE is enabled
2632 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2635 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2636 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2638 if (tex
->tc_compatible_htile
) {
2639 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2641 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2642 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2643 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2644 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2645 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2647 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2652 surf
->db_z_info
= z_info
;
2653 surf
->db_stencil_info
= s_info
;
2655 surf
->depth_initialized
= true;
2658 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2660 if (sctx
->decompression_enabled
)
2663 if (sctx
->framebuffer
.state
.zsbuf
) {
2664 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2665 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2667 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2669 if (tex
->surface
.has_stencil
)
2670 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2673 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2674 while (compressed_cb_mask
) {
2675 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2676 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2677 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2679 if (tex
->surface
.fmask_offset
) {
2680 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2681 tex
->fmask_is_identity
= false;
2683 if (tex
->dcc_gather_statistics
)
2684 tex
->separate_dcc_dirty
= true;
2688 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2690 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2691 struct si_surface
*surf
= NULL
;
2692 struct si_texture
*tex
;
2694 if (!state
->cbufs
[i
])
2696 surf
= (struct si_surface
*)state
->cbufs
[i
];
2697 tex
= (struct si_texture
*)surf
->base
.texture
;
2699 p_atomic_dec(&tex
->framebuffers_bound
);
2703 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2704 const struct pipe_framebuffer_state
*state
)
2706 struct si_context
*sctx
= (struct si_context
*)ctx
;
2707 struct si_surface
*surf
= NULL
;
2708 struct si_texture
*tex
;
2709 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2710 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2711 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2712 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2713 bool old_has_stencil
=
2715 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2716 bool unbound
= false;
2719 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2720 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2721 * We could implement the full workaround here, but it's a useless case.
2723 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2724 unreachable("the framebuffer shouldn't have zero area");
2728 si_update_fb_dirtiness_after_rendering(sctx
);
2730 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2731 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2734 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2735 if (tex
->dcc_gather_statistics
)
2736 vi_separate_dcc_stop_query(sctx
, tex
);
2739 /* Disable DCC if the formats are incompatible. */
2740 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2741 if (!state
->cbufs
[i
])
2744 surf
= (struct si_surface
*)state
->cbufs
[i
];
2745 tex
= (struct si_texture
*)surf
->base
.texture
;
2747 if (!surf
->dcc_incompatible
)
2750 /* Since the DCC decompression calls back into set_framebuffer-
2751 * _state, we need to unbind the framebuffer, so that
2752 * vi_separate_dcc_stop_query isn't called twice with the same
2756 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2760 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2761 if (!si_texture_disable_dcc(sctx
, tex
))
2762 si_decompress_dcc(sctx
, tex
);
2764 surf
->dcc_incompatible
= false;
2767 /* Only flush TC when changing the framebuffer state, because
2768 * the only client not using TC that can change textures is
2771 * Wait for compute shaders because of possible transitions:
2772 * - FB write -> shader read
2773 * - shader write -> FB read
2775 * DB caches are flushed on demand (using si_decompress_textures).
2777 * When MSAA is enabled, CB and TC caches are flushed on demand
2778 * (after FMASK decompression). Shader write -> FB read transitions
2779 * cannot happen for MSAA textures, because MSAA shader images are
2782 * Only flush and wait for CB if there is actually a bound color buffer.
2784 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2785 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2786 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2787 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2790 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2792 /* u_blitter doesn't invoke depth decompression when it does multiple
2793 * blits in a row, but the only case when it matters for DB is when
2794 * doing generate_mipmap. So here we flush DB manually between
2795 * individual generate_mipmap blits.
2796 * Note that lower mipmap levels aren't compressed.
2798 if (sctx
->generate_mipmap_for_depth
) {
2799 si_make_DB_shader_coherent(sctx
, 1, false, sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2800 } else if (sctx
->chip_class
== GFX9
) {
2801 /* It appears that DB metadata "leaks" in a sequence of:
2803 * - DCC decompress for shader image writes (with DB disabled)
2804 * - render with DEPTH_BEFORE_SHADER=1
2805 * Flushing DB metadata works around the problem.
2807 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2810 /* Take the maximum of the old and new count. If the new count is lower,
2811 * dirtying is needed to disable the unbound colorbuffers.
2813 sctx
->framebuffer
.dirty_cbufs
|=
2814 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2815 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2817 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2818 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2820 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2821 sctx
->framebuffer
.spi_shader_col_format
= 0;
2822 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2823 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2824 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2825 sctx
->framebuffer
.color_is_int8
= 0;
2826 sctx
->framebuffer
.color_is_int10
= 0;
2828 sctx
->framebuffer
.compressed_cb_mask
= 0;
2829 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2830 sctx
->framebuffer
.displayable_dcc_cb_mask
= 0;
2831 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2832 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2833 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2834 sctx
->framebuffer
.any_dst_linear
= false;
2835 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2836 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2837 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2838 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2840 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2841 if (!state
->cbufs
[i
])
2844 surf
= (struct si_surface
*)state
->cbufs
[i
];
2845 tex
= (struct si_texture
*)surf
->base
.texture
;
2847 if (!surf
->color_initialized
) {
2848 si_initialize_color_surface(sctx
, surf
);
2851 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2852 sctx
->framebuffer
.spi_shader_col_format
|= surf
->spi_shader_col_format
<< (i
* 4);
2853 sctx
->framebuffer
.spi_shader_col_format_alpha
|= surf
->spi_shader_col_format_alpha
<< (i
* 4);
2854 sctx
->framebuffer
.spi_shader_col_format_blend
|= surf
->spi_shader_col_format_blend
<< (i
* 4);
2855 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|= surf
->spi_shader_col_format_blend_alpha
2858 if (surf
->color_is_int8
)
2859 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2860 if (surf
->color_is_int10
)
2861 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2863 if (tex
->surface
.fmask_offset
)
2864 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2866 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2868 if (tex
->surface
.dcc_offset
)
2869 sctx
->framebuffer
.displayable_dcc_cb_mask
|= 1 << i
;
2871 /* Don't update nr_color_samples for non-AA buffers.
2872 * (e.g. destination of MSAA resolve)
2874 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2875 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2876 sctx
->framebuffer
.nr_color_samples
=
2877 MIN2(sctx
->framebuffer
.nr_color_samples
, tex
->buffer
.b
.b
.nr_storage_samples
);
2878 sctx
->framebuffer
.nr_color_samples
= MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2881 if (tex
->surface
.is_linear
)
2882 sctx
->framebuffer
.any_dst_linear
= true;
2884 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
2885 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2887 if (sctx
->chip_class
>= GFX9
&& !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
2888 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
2891 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2893 p_atomic_inc(&tex
->framebuffers_bound
);
2895 if (tex
->dcc_gather_statistics
) {
2896 /* Dirty tracking must be enabled for DCC usage analysis. */
2897 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2898 vi_separate_dcc_start_query(sctx
, tex
);
2901 /* Update the minimum but don't keep 0. */
2902 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2903 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2904 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
2907 /* For optimal DCC performance. */
2908 if (sctx
->chip_class
>= GFX10
)
2909 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
2911 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
2913 struct si_texture
*zstex
= NULL
;
2916 surf
= (struct si_surface
*)state
->zsbuf
;
2917 zstex
= (struct si_texture
*)surf
->base
.texture
;
2919 if (!surf
->depth_initialized
) {
2920 si_init_depth_surface(sctx
, surf
);
2923 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
, PIPE_MASK_ZS
))
2924 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2926 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2928 /* Update the minimum but don't keep 0. */
2929 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2930 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2931 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
2934 si_update_ps_colorbuf0_slot(sctx
);
2935 si_update_poly_offset_state(sctx
);
2936 si_update_ngg_small_prim_precision(sctx
);
2937 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2938 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2940 if (sctx
->screen
->dpbb_allowed
)
2941 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2943 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2944 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2946 if (sctx
->screen
->has_out_of_order_rast
&&
2947 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2948 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2949 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2950 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2952 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2953 struct pipe_constant_buffer constbuf
= {0};
2955 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2956 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2958 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2960 /* Set sample locations as fragment shader constants. */
2961 switch (sctx
->framebuffer
.nr_samples
) {
2963 constbuf
.buffer_offset
= 0;
2966 constbuf
.buffer_offset
=
2967 (ubyte
*)sctx
->sample_positions
.x2
- (ubyte
*)sctx
->sample_positions
.x1
;
2970 constbuf
.buffer_offset
=
2971 (ubyte
*)sctx
->sample_positions
.x4
- (ubyte
*)sctx
->sample_positions
.x1
;
2974 constbuf
.buffer_offset
=
2975 (ubyte
*)sctx
->sample_positions
.x8
- (ubyte
*)sctx
->sample_positions
.x1
;
2978 constbuf
.buffer_offset
=
2979 (ubyte
*)sctx
->sample_positions
.x16
- (ubyte
*)sctx
->sample_positions
.x1
;
2982 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx
->framebuffer
.nr_samples
);
2985 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2986 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2988 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
2991 sctx
->do_update_shaders
= true;
2993 if (!sctx
->decompression_enabled
) {
2994 /* Prevent textures decompression when the framebuffer state
2995 * changes come from the decompression passes themselves.
2997 sctx
->need_check_render_feedback
= true;
3001 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3003 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3004 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3005 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3006 struct si_texture
*tex
= NULL
;
3007 struct si_surface
*cb
= NULL
;
3008 unsigned cb_color_info
= 0;
3011 for (i
= 0; i
< nr_cbufs
; i
++) {
3012 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3013 unsigned cb_color_attrib
;
3015 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3018 cb
= (struct si_surface
*)state
->cbufs
[i
];
3020 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3021 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3025 tex
= (struct si_texture
*)cb
->base
.texture
;
3026 radeon_add_to_buffer_list(
3027 sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
3028 tex
->buffer
.b
.b
.nr_samples
> 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA
: RADEON_PRIO_COLOR_BUFFER
);
3030 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3031 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3032 RADEON_PRIO_SEPARATE_META
);
3035 if (tex
->dcc_separate_buffer
)
3036 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->dcc_separate_buffer
,
3037 RADEON_USAGE_READWRITE
, RADEON_PRIO_SEPARATE_META
);
3039 /* Compute mutable surface parameters. */
3040 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3042 cb_color_cmask
= tex
->cmask_base_address_reg
;
3044 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3045 cb_color_attrib
= cb
->cb_color_attrib
;
3047 if (cb
->base
.u
.tex
.level
> 0)
3048 cb_color_info
&= C_028C70_FAST_CLEAR
;
3050 if (tex
->surface
.fmask_offset
) {
3051 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
) >> 8;
3052 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3056 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3057 bool is_msaa_resolve_dst
= state
->cbufs
[0] && state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3058 state
->cbufs
[1] == &cb
->base
&&
3059 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3061 if (!is_msaa_resolve_dst
)
3062 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3065 ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) + tex
->surface
.dcc_offset
) >>
3068 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3069 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3070 cb_dcc_base
|= dcc_tile_swizzle
;
3073 if (sctx
->chip_class
>= GFX10
) {
3074 unsigned cb_color_attrib3
;
3076 /* Set mutable surface parameters. */
3077 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3078 cb_color_base
|= tex
->surface
.tile_swizzle
;
3079 if (!tex
->surface
.fmask_offset
)
3080 cb_color_fmask
= cb_color_base
;
3081 if (cb
->base
.u
.tex
.level
> 0)
3082 cb_color_cmask
= cb_color_base
;
3084 cb_color_attrib3
= cb
->cb_color_attrib3
|
3085 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3086 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3087 S_028EE0_CMASK_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3088 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3090 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3091 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3092 radeon_emit(cs
, 0); /* hole */
3093 radeon_emit(cs
, 0); /* hole */
3094 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3095 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3096 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3097 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3098 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3099 radeon_emit(cs
, 0); /* hole */
3100 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3101 radeon_emit(cs
, 0); /* hole */
3102 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3103 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3104 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3106 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4, cb_color_base
>> 32);
3107 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3108 cb_color_cmask
>> 32);
3109 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3110 cb_color_fmask
>> 32);
3111 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4, cb_dcc_base
>> 32);
3112 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4, cb
->cb_color_attrib2
);
3113 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4, cb_color_attrib3
);
3114 } else if (sctx
->chip_class
== GFX9
) {
3115 struct gfx9_surf_meta_flags meta
;
3117 if (tex
->surface
.dcc_offset
)
3118 meta
= tex
->surface
.u
.gfx9
.dcc
;
3120 meta
= tex
->surface
.u
.gfx9
.cmask
;
3122 /* Set mutable surface parameters. */
3123 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3124 cb_color_base
|= tex
->surface
.tile_swizzle
;
3125 if (!tex
->surface
.fmask_offset
)
3126 cb_color_fmask
= cb_color_base
;
3127 if (cb
->base
.u
.tex
.level
> 0)
3128 cb_color_cmask
= cb_color_base
;
3129 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3130 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3131 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3132 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3134 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3135 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3136 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3137 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3138 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3139 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3140 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3141 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3142 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3143 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3144 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3145 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3146 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3147 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3148 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3149 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3151 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3152 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3154 /* Compute mutable surface parameters (GFX6-GFX8). */
3155 const struct legacy_surf_level
*level_info
=
3156 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3157 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3158 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3160 cb_color_base
+= level_info
->offset
>> 8;
3161 /* Only macrotiled modes can set tile swizzle. */
3162 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3163 cb_color_base
|= tex
->surface
.tile_swizzle
;
3165 if (!tex
->surface
.fmask_offset
)
3166 cb_color_fmask
= cb_color_base
;
3167 if (cb
->base
.u
.tex
.level
> 0)
3168 cb_color_cmask
= cb_color_base
;
3170 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3172 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3173 slice_tile_max
= level_info
->nblk_x
* level_info
->nblk_y
/ 64 - 1;
3174 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3176 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3177 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3178 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3180 if (tex
->surface
.fmask_offset
) {
3181 if (sctx
->chip_class
>= GFX7
)
3183 S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3185 S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3186 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3188 /* This must be set for fast clear to work without FMASK. */
3189 if (sctx
->chip_class
>= GFX7
)
3190 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3191 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3192 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3195 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3196 sctx
->chip_class
>= GFX8
? 14 : 13);
3197 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3198 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3199 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3200 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3201 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3202 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3203 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3204 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3205 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3206 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3207 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3208 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3209 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3211 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3212 radeon_emit(cs
, cb_dcc_base
);
3216 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3217 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3220 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3221 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3222 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3224 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
3225 zb
->base
.texture
->nr_samples
> 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3226 : RADEON_PRIO_DEPTH_BUFFER
);
3228 if (sctx
->chip_class
>= GFX10
) {
3229 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3230 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3232 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3233 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3234 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3235 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3236 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3237 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3238 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3239 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3240 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3242 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3243 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3244 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3245 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3246 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3247 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3248 } else if (sctx
->chip_class
== GFX9
) {
3249 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3250 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3252 S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3253 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3255 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3256 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3257 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3258 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3259 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3260 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3261 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3262 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3263 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3264 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3265 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3267 S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3269 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3270 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3271 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3273 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3275 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3276 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3277 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3278 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3279 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3280 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3281 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3282 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3283 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3284 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3285 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3288 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3289 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3290 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3292 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3293 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3294 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3295 if (sctx
->chip_class
== GFX9
)
3296 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3298 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3300 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3301 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3304 /* Framebuffer dimensions. */
3305 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3306 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3307 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3309 if (sctx
->screen
->dfsm_allowed
) {
3310 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3311 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3314 sctx
->framebuffer
.dirty_cbufs
= 0;
3315 sctx
->framebuffer
.dirty_zsbuf
= false;
3318 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3320 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3321 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3322 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3323 bool has_msaa_sample_loc_bug
= sctx
->screen
->info
.has_msaa_sample_loc_bug
;
3325 /* Smoothing (only possible with nr_samples == 1) uses the same
3326 * sample locations as the MSAA it simulates.
3328 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3329 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3331 /* On Polaris, the small primitive filter uses the sample locations
3332 * even when MSAA is off, so we need to make sure they're set to 0.
3334 * GFX10 uses sample locations unconditionally, so they always need
3337 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
|| sctx
->chip_class
>= GFX10
) &&
3338 nr_samples
!= sctx
->sample_locs_num_samples
) {
3339 sctx
->sample_locs_num_samples
= nr_samples
;
3340 si_emit_sample_locations(cs
, nr_samples
);
3343 if (sctx
->family
>= CHIP_POLARIS10
) {
3344 unsigned small_prim_filter_cntl
=
3345 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3347 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3349 /* The alternative of setting sample locations to 0 would
3350 * require a DB flush to avoid Z errors, see
3351 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3353 if (has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1 && !rs
->multisample_enable
)
3354 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3356 radeon_opt_set_context_reg(sctx
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3357 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
, small_prim_filter_cntl
);
3360 /* The exclusion bits can be set to improve rasterization efficiency
3361 * if no sample lies on the pixel boundary (-8 sample offset).
3363 bool exclusion
= sctx
->chip_class
>= GFX7
&& (!rs
->multisample_enable
|| nr_samples
!= 16);
3364 radeon_opt_set_context_reg(
3365 sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3366 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3369 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3371 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3372 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3374 if (!sctx
->screen
->has_out_of_order_rast
)
3377 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3379 colormask
&= blend
->cb_target_enabled_4bit
;
3381 /* Conservative: No logic op. */
3382 if (colormask
&& blend
->logicop_enable
)
3385 struct si_dsa_order_invariance dsa_order_invariant
= {.zs
= true,
3387 .pass_last
= false};
3389 if (sctx
->framebuffer
.state
.zsbuf
) {
3390 struct si_texture
*zstex
= (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3391 bool has_stencil
= zstex
->surface
.has_stencil
;
3392 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3393 if (!dsa_order_invariant
.zs
)
3396 /* The set of PS invocations is always order invariant,
3397 * except when early Z/S tests are requested. */
3398 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.writes_memory
&&
3399 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3400 !dsa_order_invariant
.pass_set
)
3403 if (sctx
->num_perfect_occlusion_queries
!= 0 && !dsa_order_invariant
.pass_set
)
3410 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3413 /* Only commutative blending. */
3414 if (blendmask
& ~blend
->commutative_4bit
)
3417 if (!dsa_order_invariant
.pass_set
)
3421 if (colormask
& ~blendmask
) {
3422 if (!dsa_order_invariant
.pass_last
)
3429 static void si_emit_msaa_config(struct si_context
*sctx
)
3431 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3432 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3433 /* 33% faster rendering to linear color buffers */
3434 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3435 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3436 unsigned sc_mode_cntl_1
=
3437 S_028A4C_WALK_SIZE(dst_is_linear
) | S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3438 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3439 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3440 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3442 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3443 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3444 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3445 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) |
3446 S_028804_INTERPOLATE_COMP_Z(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3447 unsigned coverage_samples
, color_samples
, z_samples
;
3448 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3450 /* S: Coverage samples (up to 16x):
3451 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3452 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3454 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3455 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3456 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3457 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3458 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3461 * F: Color samples (up to 8x, must be <= coverage samples):
3462 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3463 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3465 * Can be anything between coverage and color samples:
3466 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3467 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3468 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3469 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3470 * # All are currently set the same as coverage samples.
3472 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3473 * flag for undefined color samples. A shader-based resolve must handle unknowns
3474 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3475 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3476 * useful. The CB resolve always drops unknowns.
3478 * Sensible AA configurations:
3479 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3480 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3481 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3482 * EQAA 8s 8z 8f = 8x MSAA
3483 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3484 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3485 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3486 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3487 * EQAA 4s 4z 4f = 4x MSAA
3488 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3489 * EQAA 2s 2z 2f = 2x MSAA
3491 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3492 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3493 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3495 if (sctx
->framebuffer
.state
.zsbuf
) {
3496 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3497 z_samples
= MAX2(1, z_samples
);
3499 z_samples
= coverage_samples
;
3501 } else if (sctx
->smoothing_enabled
) {
3502 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3504 coverage_samples
= color_samples
= z_samples
= 1;
3507 /* Required by OpenGL line rasterization.
3509 * TODO: We should also enable perpendicular endcaps for AA lines,
3510 * but that requires implementing line stippling in the pixel
3511 * shader. SC can only do line stippling with axis-aligned
3514 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3515 unsigned sc_aa_config
= 0;
3517 if (coverage_samples
> 1) {
3518 /* distance from the pixel center, indexed by log2(nr_samples) */
3519 static unsigned max_dist
[] = {
3526 unsigned log_samples
= util_logbase2(coverage_samples
);
3527 unsigned log_z_samples
= util_logbase2(z_samples
);
3528 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3529 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3531 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3532 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3533 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3534 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3536 if (sctx
->framebuffer
.nr_samples
> 1) {
3537 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3538 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3539 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3540 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3541 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3542 } else if (sctx
->smoothing_enabled
) {
3543 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3547 unsigned initial_cdw
= cs
->current
.cdw
;
3549 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3550 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
, SI_TRACKED_PA_SC_LINE_CNTL
,
3551 sc_line_cntl
, sc_aa_config
);
3552 /* R_028804_DB_EQAA */
3553 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
, db_eqaa
);
3554 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3555 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
, SI_TRACKED_PA_SC_MODE_CNTL_1
,
3558 if (initial_cdw
!= cs
->current
.cdw
) {
3559 sctx
->context_roll
= true;
3561 /* GFX9: Flush DFSM when the AA mode changes. */
3562 if (sctx
->screen
->dfsm_allowed
) {
3563 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3564 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3569 void si_update_ps_iter_samples(struct si_context
*sctx
)
3571 if (sctx
->framebuffer
.nr_samples
> 1)
3572 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3573 if (sctx
->screen
->dpbb_allowed
)
3574 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3577 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3579 struct si_context
*sctx
= (struct si_context
*)ctx
;
3581 /* The hardware can only do sample shading with 2^n samples. */
3582 min_samples
= util_next_power_of_two(min_samples
);
3584 if (sctx
->ps_iter_samples
== min_samples
)
3587 sctx
->ps_iter_samples
= min_samples
;
3588 sctx
->do_update_shaders
= true;
3590 si_update_ps_iter_samples(sctx
);
3598 * Build the sampler view descriptor for a buffer texture.
3599 * @param state 256-bit descriptor; only the high 128 bits are filled in
3601 void si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3602 enum pipe_format format
, unsigned offset
, unsigned size
,
3605 const struct util_format_description
*desc
;
3607 unsigned num_records
;
3609 desc
= util_format_description(format
);
3610 stride
= desc
->block
.bits
/ 8;
3612 num_records
= size
/ stride
;
3613 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3615 /* The NUM_RECORDS field has a different meaning depending on the chip,
3616 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3619 * - If STRIDE == 0, it's in byte units.
3620 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3623 * - For SMEM and STRIDE == 0, it's in byte units.
3624 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3625 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3626 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3627 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3628 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3629 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3630 * That way the same descriptor can be used by both SMEM and VMEM.
3633 * - For SMEM and STRIDE == 0, it's in byte units.
3634 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3635 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3636 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3638 if (screen
->info
.chip_class
== GFX8
)
3639 num_records
*= stride
;
3642 state
[5] = S_008F04_STRIDE(stride
);
3643 state
[6] = num_records
;
3644 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3645 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3646 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3647 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3649 if (screen
->info
.chip_class
>= GFX10
) {
3650 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3652 /* OOB_SELECT chooses the out-of-bounds check:
3653 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3654 * - 1: index >= NUM_RECORDS
3655 * - 2: NUM_RECORDS == 0
3656 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3657 * else: swizzle_address >= NUM_RECORDS
3659 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3660 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET
) |
3661 S_008F0C_RESOURCE_LEVEL(1);
3664 unsigned num_format
, data_format
;
3666 first_non_void
= util_format_get_first_non_void_channel(format
);
3667 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3668 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3670 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
3674 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3676 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3678 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3679 /* For the pre-defined border color values (white, opaque
3680 * black, transparent black), the only thing that matters is
3681 * that the alpha channel winds up in the correct place
3682 * (because the RGB channels are all the same) so either of
3683 * these enumerations will work.
3685 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3686 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3688 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3689 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3690 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3691 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3693 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3694 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3695 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3696 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3697 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3704 * Build the sampler view descriptor for a texture.
3706 static void gfx10_make_texture_descriptor(
3707 struct si_screen
*screen
, struct si_texture
*tex
, bool sampler
, enum pipe_texture_target target
,
3708 enum pipe_format pipe_format
, const unsigned char state_swizzle
[4], unsigned first_level
,
3709 unsigned last_level
, unsigned first_layer
, unsigned last_layer
, unsigned width
, unsigned height
,
3710 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3712 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3713 const struct util_format_description
*desc
;
3714 unsigned img_format
;
3715 unsigned char swizzle
[4];
3719 desc
= util_format_description(pipe_format
);
3720 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3722 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3723 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3724 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3725 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3726 bool is_stencil
= false;
3728 switch (pipe_format
) {
3729 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3730 case PIPE_FORMAT_X32_S8X24_UINT
:
3731 case PIPE_FORMAT_X8Z24_UNORM
:
3732 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3735 case PIPE_FORMAT_X24S8_UINT
:
3737 * X24S8 is implemented as an 8_8_8_8 data format, to
3738 * fix texture gathers. This affects at least
3739 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3741 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3745 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3746 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3749 if (tex
->upgraded_depth
&& !is_stencil
) {
3750 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3751 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3754 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3757 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3758 /* For the purpose of shader images, treat cube maps as 2D
3761 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3763 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3766 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3768 depth
= res
->array_size
;
3769 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3770 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3771 depth
= res
->array_size
;
3772 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3773 depth
= res
->array_size
/ 6;
3776 state
[1] = S_00A004_FORMAT(img_format
) | S_00A004_WIDTH_LO(width
- 1);
3777 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3778 S_00A008_RESOURCE_LEVEL(1);
3780 S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3781 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3782 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3783 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3784 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ? 0 : first_level
) |
3785 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
) : last_level
) |
3786 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) | S_00A00C_TYPE(type
);
3787 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3788 * to know the total number of layers.
3791 S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
) ? depth
- 1 : last_layer
) |
3792 S_00A010_BASE_ARRAY(first_layer
);
3793 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3794 S_00A014_MAX_MIP(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
)
3795 : tex
->buffer
.b
.b
.last_level
) |
3796 S_00A014_PERF_MOD(4);
3800 if (tex
->surface
.dcc_offset
) {
3801 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
3802 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
) |
3803 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
3806 /* Initialize the sampler view for FMASK. */
3807 if (tex
->surface
.fmask_offset
) {
3810 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
3812 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3813 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3815 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
3818 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
3821 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
3824 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
3827 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
3830 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
3833 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
3836 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
3839 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
3842 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
3845 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
3848 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
3851 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
3854 unreachable("invalid nr_samples");
3857 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3858 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) | S_00A004_FORMAT(format
) |
3859 S_00A004_WIDTH_LO(width
- 1);
3860 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3861 S_00A008_RESOURCE_LEVEL(1);
3863 S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3864 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3865 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3866 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3867 fmask_state
[4] = S_00A010_DEPTH(last_layer
) | S_00A010_BASE_ARRAY(first_layer
);
3869 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
3875 * Build the sampler view descriptor for a texture (SI-GFX9).
3877 static void si_make_texture_descriptor(struct si_screen
*screen
, struct si_texture
*tex
,
3878 bool sampler
, enum pipe_texture_target target
,
3879 enum pipe_format pipe_format
,
3880 const unsigned char state_swizzle
[4], unsigned first_level
,
3881 unsigned last_level
, unsigned first_layer
,
3882 unsigned last_layer
, unsigned width
, unsigned height
,
3883 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3885 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3886 const struct util_format_description
*desc
;
3887 unsigned char swizzle
[4];
3889 unsigned num_format
, data_format
, type
, num_samples
;
3892 desc
= util_format_description(pipe_format
);
3894 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
? MAX2(1, res
->nr_samples
)
3895 : MAX2(1, res
->nr_storage_samples
);
3897 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3898 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3899 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3900 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3902 switch (pipe_format
) {
3903 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3904 case PIPE_FORMAT_X32_S8X24_UINT
:
3905 case PIPE_FORMAT_X8Z24_UNORM
:
3906 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3908 case PIPE_FORMAT_X24S8_UINT
:
3910 * X24S8 is implemented as an 8_8_8_8 data format, to
3911 * fix texture gathers. This affects at least
3912 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3914 if (screen
->info
.chip_class
<= GFX8
)
3915 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3917 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3920 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3923 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3926 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3928 switch (pipe_format
) {
3929 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3930 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3933 if (first_non_void
< 0) {
3934 if (util_format_is_compressed(pipe_format
)) {
3935 switch (pipe_format
) {
3936 case PIPE_FORMAT_DXT1_SRGB
:
3937 case PIPE_FORMAT_DXT1_SRGBA
:
3938 case PIPE_FORMAT_DXT3_SRGBA
:
3939 case PIPE_FORMAT_DXT5_SRGBA
:
3940 case PIPE_FORMAT_BPTC_SRGBA
:
3941 case PIPE_FORMAT_ETC2_SRGB8
:
3942 case PIPE_FORMAT_ETC2_SRGB8A1
:
3943 case PIPE_FORMAT_ETC2_SRGBA8
:
3944 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3946 case PIPE_FORMAT_RGTC1_SNORM
:
3947 case PIPE_FORMAT_LATC1_SNORM
:
3948 case PIPE_FORMAT_RGTC2_SNORM
:
3949 case PIPE_FORMAT_LATC2_SNORM
:
3950 case PIPE_FORMAT_ETC2_R11_SNORM
:
3951 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3952 /* implies float, so use SNORM/UNORM to determine
3953 whether data is signed or not */
3954 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3955 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3958 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3961 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3962 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3964 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3966 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3967 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3969 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3971 switch (desc
->channel
[first_non_void
].type
) {
3972 case UTIL_FORMAT_TYPE_FLOAT
:
3973 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3975 case UTIL_FORMAT_TYPE_SIGNED
:
3976 if (desc
->channel
[first_non_void
].normalized
)
3977 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3978 else if (desc
->channel
[first_non_void
].pure_integer
)
3979 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3981 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3983 case UTIL_FORMAT_TYPE_UNSIGNED
:
3984 if (desc
->channel
[first_non_void
].normalized
)
3985 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3986 else if (desc
->channel
[first_non_void
].pure_integer
)
3987 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3989 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3994 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3995 if (data_format
== ~0) {
3999 /* S8 with Z32 HTILE needs a special format. */
4000 if (screen
->info
.chip_class
== GFX9
&& pipe_format
== PIPE_FORMAT_S8_UINT
&&
4001 tex
->tc_compatible_htile
)
4002 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4004 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4005 (screen
->info
.chip_class
<= GFX8
&& res
->target
== PIPE_TEXTURE_3D
))) {
4006 /* For the purpose of shader images, treat cube maps and 3D
4007 * textures as 2D arrays. For 3D textures, the address
4008 * calculations for mipmaps are different, so we rely on the
4009 * caller to effectively disable mipmaps.
4011 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4013 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4015 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4018 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4020 depth
= res
->array_size
;
4021 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4022 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4023 depth
= res
->array_size
;
4024 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4025 depth
= res
->array_size
/ 6;
4028 state
[1] = (S_008F14_DATA_FORMAT(data_format
) | S_008F14_NUM_FORMAT(num_format
));
4029 state
[2] = (S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1) | S_008F18_PERF_MOD(4));
4030 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4031 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4032 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4033 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4034 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4035 S_008F1C_LAST_LEVEL(num_samples
> 1 ? util_logbase2(num_samples
) : last_level
) |
4036 S_008F1C_TYPE(type
));
4038 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4042 if (screen
->info
.chip_class
== GFX9
) {
4043 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4045 /* Depth is the the last accessible layer on Gfx9.
4046 * The hw doesn't need to know the total number of layers.
4048 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4049 state
[4] |= S_008F20_DEPTH(depth
- 1);
4051 state
[4] |= S_008F20_DEPTH(last_layer
);
4053 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4054 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ? util_logbase2(num_samples
)
4055 : tex
->buffer
.b
.b
.last_level
);
4057 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4058 state
[4] |= S_008F20_DEPTH(depth
- 1);
4059 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4062 if (tex
->surface
.dcc_offset
) {
4063 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4065 /* The last dword is unused by hw. The shader uses it to clear
4066 * bits in the first dword of sampler state.
4068 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4069 if (first_level
== last_level
)
4070 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4072 state
[7] = 0xffffffff;
4076 /* Initialize the sampler view for FMASK. */
4077 if (tex
->surface
.fmask_offset
) {
4078 uint32_t data_format
, num_format
;
4080 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
4082 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4083 if (screen
->info
.chip_class
== GFX9
) {
4084 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4085 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4087 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4090 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4093 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4096 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4099 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4102 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4105 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4108 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4111 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4114 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4117 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4120 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4123 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4126 unreachable("invalid nr_samples");
4129 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4131 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4134 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4137 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4140 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4143 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4146 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4149 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4152 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4155 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4158 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4161 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4164 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4167 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4170 unreachable("invalid nr_samples");
4172 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4176 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4177 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) | S_008F14_DATA_FORMAT(data_format
) |
4178 S_008F14_NUM_FORMAT(num_format
);
4179 fmask_state
[2] = S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1);
4181 S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4182 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4183 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4185 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4189 if (screen
->info
.chip_class
== GFX9
) {
4190 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4192 S_008F20_DEPTH(last_layer
) | S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4193 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4194 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4196 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4197 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4198 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4199 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4205 * Create a sampler view.
4207 * @param ctx context
4208 * @param texture texture
4209 * @param state sampler view template
4210 * @param width0 width0 override (for compressed textures as int)
4211 * @param height0 height0 override (for compressed textures as int)
4212 * @param force_level set the base address to the level (for compressed textures)
4214 struct pipe_sampler_view
*si_create_sampler_view_custom(struct pipe_context
*ctx
,
4215 struct pipe_resource
*texture
,
4216 const struct pipe_sampler_view
*state
,
4217 unsigned width0
, unsigned height0
,
4218 unsigned force_level
)
4220 struct si_context
*sctx
= (struct si_context
*)ctx
;
4221 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4222 struct si_texture
*tex
= (struct si_texture
*)texture
;
4223 unsigned base_level
, first_level
, last_level
;
4224 unsigned char state_swizzle
[4];
4225 unsigned height
, depth
, width
;
4226 unsigned last_layer
= state
->u
.tex
.last_layer
;
4227 enum pipe_format pipe_format
;
4228 const struct legacy_surf_level
*surflevel
;
4233 /* initialize base object */
4234 view
->base
= *state
;
4235 view
->base
.texture
= NULL
;
4236 view
->base
.reference
.count
= 1;
4237 view
->base
.context
= ctx
;
4240 pipe_resource_reference(&view
->base
.texture
, texture
);
4242 if (state
->format
== PIPE_FORMAT_X24S8_UINT
|| state
->format
== PIPE_FORMAT_S8X24_UINT
||
4243 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
|| state
->format
== PIPE_FORMAT_S8_UINT
)
4244 view
->is_stencil_sampler
= true;
4246 /* Buffer resource. */
4247 if (texture
->target
== PIPE_BUFFER
) {
4248 si_make_buffer_descriptor(sctx
->screen
, si_resource(texture
), state
->format
,
4249 state
->u
.buf
.offset
, state
->u
.buf
.size
, view
->state
);
4253 state_swizzle
[0] = state
->swizzle_r
;
4254 state_swizzle
[1] = state
->swizzle_g
;
4255 state_swizzle
[2] = state
->swizzle_b
;
4256 state_swizzle
[3] = state
->swizzle_a
;
4259 first_level
= state
->u
.tex
.first_level
;
4260 last_level
= state
->u
.tex
.last_level
;
4263 depth
= texture
->depth0
;
4265 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4266 assert(force_level
== first_level
&& force_level
== last_level
);
4267 base_level
= force_level
;
4270 width
= u_minify(width
, force_level
);
4271 height
= u_minify(height
, force_level
);
4272 depth
= u_minify(depth
, force_level
);
4275 /* This is not needed if state trackers set last_layer correctly. */
4276 if (state
->target
== PIPE_TEXTURE_1D
|| state
->target
== PIPE_TEXTURE_2D
||
4277 state
->target
== PIPE_TEXTURE_RECT
|| state
->target
== PIPE_TEXTURE_CUBE
)
4278 last_layer
= state
->u
.tex
.first_layer
;
4280 /* Texturing with separate depth and stencil. */
4281 pipe_format
= state
->format
;
4283 /* Depth/stencil texturing sometimes needs separate texture. */
4284 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4285 if (!tex
->flushed_depth_texture
&& !si_init_flushed_depth_texture(ctx
, texture
)) {
4286 pipe_resource_reference(&view
->base
.texture
, NULL
);
4291 assert(tex
->flushed_depth_texture
);
4293 /* Override format for the case where the flushed texture
4294 * contains only Z or only S.
4296 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4297 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4299 tex
= tex
->flushed_depth_texture
;
4302 surflevel
= tex
->surface
.u
.legacy
.level
;
4304 if (tex
->db_compatible
) {
4305 if (!view
->is_stencil_sampler
)
4306 pipe_format
= tex
->db_render_format
;
4308 switch (pipe_format
) {
4309 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4310 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4312 case PIPE_FORMAT_X8Z24_UNORM
:
4313 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4314 /* Z24 is always stored like this for DB
4317 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4319 case PIPE_FORMAT_X24S8_UINT
:
4320 case PIPE_FORMAT_S8X24_UINT
:
4321 case PIPE_FORMAT_X32_S8X24_UINT
:
4322 pipe_format
= PIPE_FORMAT_S8_UINT
;
4323 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4329 view
->dcc_incompatible
=
4330 vi_dcc_formats_are_incompatible(texture
, state
->u
.tex
.first_level
, state
->format
);
4332 sctx
->screen
->make_texture_descriptor(
4333 sctx
->screen
, tex
, true, state
->target
, pipe_format
, state_swizzle
, first_level
, last_level
,
4334 state
->u
.tex
.first_layer
, last_layer
, width
, height
, depth
, view
->state
, view
->fmask_state
);
4336 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4337 view
->is_integer
= false;
4339 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4340 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4343 /* Whether the number format is {U,S}{SCALED,INT} */
4344 view
->is_integer
= (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4345 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4346 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4350 view
->base_level_info
= &surflevel
[base_level
];
4351 view
->base_level
= base_level
;
4352 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4356 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
4357 struct pipe_resource
*texture
,
4358 const struct pipe_sampler_view
*state
)
4360 return si_create_sampler_view_custom(ctx
, texture
, state
, texture
? texture
->width0
: 0,
4361 texture
? texture
->height0
: 0, 0);
4364 static void si_sampler_view_destroy(struct pipe_context
*ctx
, struct pipe_sampler_view
*state
)
4366 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4368 pipe_resource_reference(&state
->texture
, NULL
);
4372 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4374 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4375 (linear_filter
&& (wrap
== PIPE_TEX_WRAP_CLAMP
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4378 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4379 const struct pipe_sampler_state
*state
,
4380 const union pipe_color_union
*color
, bool is_integer
)
4382 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4383 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4385 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4386 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4387 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4388 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4390 #define simple_border_types(elt) \
4392 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 0) \
4393 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4394 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 1) \
4395 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4396 if (color->elt[0] == 1 && color->elt[1] == 1 && color->elt[2] == 1 && color->elt[3] == 1) \
4397 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4401 simple_border_types(ui
);
4403 simple_border_types(f
);
4405 #undef simple_border_types
4409 /* Check if the border has been uploaded already. */
4410 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4411 if (memcmp(&sctx
->border_color_table
[i
], color
, sizeof(*color
)) == 0)
4414 if (i
>= SI_MAX_BORDER_COLORS
) {
4415 /* Getting 4096 unique border colors is very unlikely. */
4416 fprintf(stderr
, "radeonsi: The border color table is full. "
4417 "Any new border colors will be just black. "
4418 "Please file a bug.\n");
4419 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4422 if (i
== sctx
->border_color_count
) {
4423 /* Upload a new border color. */
4424 memcpy(&sctx
->border_color_table
[i
], color
, sizeof(*color
));
4425 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
], color
, sizeof(*color
));
4426 sctx
->border_color_count
++;
4429 return S_008F3C_BORDER_COLOR_PTR(i
) |
4430 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4433 static inline int S_FIXED(float value
, unsigned frac_bits
)
4435 return value
* (1 << frac_bits
);
4438 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4440 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4441 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4442 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4444 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4445 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4448 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4461 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4462 const struct pipe_sampler_state
*state
)
4464 struct si_context
*sctx
= (struct si_context
*)ctx
;
4465 struct si_screen
*sscreen
= sctx
->screen
;
4466 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4467 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
: state
->max_anisotropy
;
4468 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4469 union pipe_color_union clamped_border_color
;
4476 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4479 (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) | S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4480 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) | S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4481 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4482 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4483 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4484 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4485 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4486 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4487 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4488 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4489 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4490 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4491 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4492 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4493 S_008F38_MIP_POINT_PRECLAMP(0));
4494 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4496 if (sscreen
->info
.chip_class
>= GFX10
) {
4497 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4499 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4500 S_008F38_FILTER_PREC_FIX(1) |
4501 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4504 /* Create sampler resource for integer textures. */
4505 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4506 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4508 /* Create sampler resource for upgraded depth textures. */
4509 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4511 for (unsigned i
= 0; i
< 4; ++i
) {
4512 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4513 * when the border color is 1.0. */
4514 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4517 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4518 if (sscreen
->info
.chip_class
<= GFX9
)
4519 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4521 rstate
->upgraded_depth_val
[3] =
4522 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4528 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4530 struct si_context
*sctx
= (struct si_context
*)ctx
;
4532 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4535 sctx
->sample_mask
= sample_mask
;
4536 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4539 static void si_emit_sample_mask(struct si_context
*sctx
)
4541 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4542 unsigned mask
= sctx
->sample_mask
;
4544 /* Needed for line and polygon smoothing as well as for the Polaris
4545 * small primitive filter. We expect the state tracker to take care of
4548 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4549 (mask
& 1 && sctx
->blitter
->running
));
4551 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4552 radeon_emit(cs
, mask
| (mask
<< 16));
4553 radeon_emit(cs
, mask
| (mask
<< 16));
4556 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4559 struct si_sampler_state
*s
= state
;
4561 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4568 * Vertex elements & buffers
4571 struct si_fast_udiv_info32
si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4573 struct util_fast_udiv_info info
= util_compute_fast_udiv_info(D
, num_bits
, 32);
4575 struct si_fast_udiv_info32 result
= {
4584 static void *si_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
4585 const struct pipe_vertex_element
*elements
)
4587 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4588 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4589 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4590 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4591 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4592 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4593 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4594 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4595 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4598 assert(count
<= SI_MAX_ATTRIBS
);
4604 unsigned alloc_count
=
4605 count
> sscreen
->num_vbos_in_user_sgprs
? count
- sscreen
->num_vbos_in_user_sgprs
: 0;
4606 v
->vb_desc_list_alloc_size
= align(alloc_count
* 16, SI_CPDMA_ALIGNMENT
);
4608 for (i
= 0; i
< count
; ++i
) {
4609 const struct util_format_description
*desc
;
4610 const struct util_format_channel_description
*channel
;
4612 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4614 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4619 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4620 if (instance_divisor
) {
4621 v
->uses_instance_divisors
= true;
4623 if (instance_divisor
== 1) {
4624 v
->instance_divisor_is_one
|= 1u << i
;
4626 v
->instance_divisor_is_fetched
|= 1u << i
;
4627 divisor_factors
[i
] = si_compute_fast_udiv_info32(instance_divisor
, 32);
4631 if (!used
[vbo_index
]) {
4632 v
->first_vb_use_mask
|= 1 << i
;
4633 used
[vbo_index
] = true;
4636 desc
= util_format_description(elements
[i
].src_format
);
4637 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4638 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4640 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4641 v
->src_offset
[i
] = elements
[i
].src_offset
;
4642 v
->vertex_buffer_index
[i
] = vbo_index
;
4644 bool always_fix
= false;
4645 union si_vs_fix_fetch fix_fetch
;
4646 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4649 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4652 switch (channel
->type
) {
4653 case UTIL_FORMAT_TYPE_FLOAT
:
4654 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4656 case UTIL_FORMAT_TYPE_FIXED
:
4657 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4659 case UTIL_FORMAT_TYPE_SIGNED
: {
4660 if (channel
->pure_integer
)
4661 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4662 else if (channel
->normalized
)
4663 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4665 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4668 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4669 if (channel
->pure_integer
)
4670 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4671 else if (channel
->normalized
)
4672 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4674 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4678 unreachable("bad format type");
4681 switch (elements
[i
].src_format
) {
4682 case PIPE_FORMAT_R11G11B10_FLOAT
:
4683 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4686 unreachable("bad other format");
4690 if (desc
->channel
[0].size
== 10) {
4691 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4692 log_hw_load_size
= 2;
4694 /* The hardware always treats the 2-bit alpha channel as
4695 * unsigned, so a shader workaround is needed. The affected
4696 * chips are GFX8 and older except Stoney (GFX8.1).
4698 always_fix
= sscreen
->info
.chip_class
<= GFX8
&& sscreen
->info
.family
!= CHIP_STONEY
&&
4699 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4700 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4701 fix_fetch
.u
.log_size
= 3; /* special encoding */
4702 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4703 log_hw_load_size
= 2;
4705 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4706 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4709 * - doubles (multiple loads + truncate to float)
4710 * - 32-bit requiring a conversion
4712 always_fix
= (fix_fetch
.u
.log_size
== 3) ||
4713 (fix_fetch
.u
.log_size
== 2 && fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4714 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4715 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4717 /* Also fixup 8_8_8 and 16_16_16. */
4718 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4720 log_hw_load_size
= fix_fetch
.u
.log_size
;
4724 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4725 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4726 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4727 fix_fetch
.u
.reverse
= 1;
4730 /* Force the workaround for unaligned access here already if the
4731 * offset relative to the vertex buffer base is unaligned.
4733 * There is a theoretical case in which this is too conservative:
4734 * if the vertex buffer's offset is also unaligned in just the
4735 * right way, we end up with an aligned address after all.
4736 * However, this case should be extremely rare in practice (it
4737 * won't happen in well-behaved applications), and taking it
4738 * into account would complicate the fast path (where everything
4739 * is nicely aligned).
4741 bool check_alignment
= log_hw_load_size
>= 1 && (sscreen
->info
.chip_class
== GFX6
||
4742 sscreen
->info
.chip_class
== GFX10
);
4743 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4745 if (check_alignment
&& (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
4748 if (always_fix
|| check_alignment
|| opencode
)
4749 v
->fix_fetch
[i
] = fix_fetch
.bits
;
4752 v
->fix_fetch_opencode
|= 1 << i
;
4753 if (opencode
|| always_fix
)
4754 v
->fix_fetch_always
|= 1 << i
;
4756 if (check_alignment
&& !opencode
) {
4757 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
4759 v
->fix_fetch_unaligned
|= 1 << i
;
4760 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
4761 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
4764 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
4765 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
4766 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
4767 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
4769 if (sscreen
->info
.chip_class
>= GFX10
) {
4770 const struct gfx10_format
*fmt
= &gfx10_format_table
[elements
[i
].src_format
];
4771 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
4772 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) | S_008F0C_RESOURCE_LEVEL(1);
4774 unsigned data_format
, num_format
;
4775 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4776 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4777 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
4781 if (v
->instance_divisor_is_fetched
) {
4782 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
4784 v
->instance_divisor_factor_buffer
= (struct si_resource
*)pipe_buffer_create(
4785 &sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, num_divisors
* sizeof(divisor_factors
[0]));
4786 if (!v
->instance_divisor_factor_buffer
) {
4791 sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
4792 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
4797 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4799 struct si_context
*sctx
= (struct si_context
*)ctx
;
4800 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4801 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4803 sctx
->vertex_elements
= v
;
4804 sctx
->num_vertex_elements
= v
? v
->count
: 0;
4806 if (sctx
->num_vertex_elements
) {
4807 sctx
->vertex_buffers_dirty
= true;
4809 sctx
->vertex_buffer_pointer_dirty
= false;
4810 sctx
->vertex_buffer_user_sgprs_dirty
= false;
4813 if (v
&& (!old
|| old
->count
!= v
->count
||
4814 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4815 /* we don't check which divisors changed */
4816 v
->uses_instance_divisors
||
4817 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) &
4818 sctx
->vertex_buffer_unaligned
||
4819 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
4820 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
4821 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
4822 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4823 * functions of fix_fetch and the src_offset alignment.
4824 * If they change and fix_fetch doesn't, it must be due to different
4825 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4826 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
4827 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4828 sctx
->do_update_shaders
= true;
4830 if (v
&& v
->instance_divisor_is_fetched
) {
4831 struct pipe_constant_buffer cb
;
4833 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
4834 cb
.user_buffer
= NULL
;
4835 cb
.buffer_offset
= 0;
4836 cb
.buffer_size
= 0xffffffff;
4837 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4841 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4843 struct si_context
*sctx
= (struct si_context
*)ctx
;
4844 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4846 if (sctx
->vertex_elements
== state
) {
4847 sctx
->vertex_elements
= NULL
;
4848 sctx
->num_vertex_elements
= 0;
4850 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
4854 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
4855 const struct pipe_vertex_buffer
*buffers
)
4857 struct si_context
*sctx
= (struct si_context
*)ctx
;
4858 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4859 unsigned updated_mask
= u_bit_consecutive(start_slot
, count
);
4860 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
4861 uint32_t unaligned
= 0;
4864 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4867 for (i
= 0; i
< count
; i
++) {
4868 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4869 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4870 struct pipe_resource
*buf
= src
->buffer
.resource
;
4871 unsigned slot_bit
= 1 << (start_slot
+ i
);
4873 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4874 dsti
->buffer_offset
= src
->buffer_offset
;
4875 dsti
->stride
= src
->stride
;
4877 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
4878 unaligned
|= slot_bit
;
4880 si_context_add_resource_size(sctx
, buf
);
4882 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4885 for (i
= 0; i
< count
; i
++) {
4886 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4888 unaligned
&= ~updated_mask
;
4890 sctx
->vertex_buffers_dirty
= true;
4891 sctx
->vertex_buffer_unaligned
= (orig_unaligned
& ~updated_mask
) | unaligned
;
4893 /* Check whether alignment may have changed in a way that requires
4894 * shader changes. This check is conservative: a vertex buffer can only
4895 * trigger a shader change if the misalignment amount changes (e.g.
4896 * from byte-aligned to short-aligned), but we only keep track of
4897 * whether buffers are at least dword-aligned, since that should always
4898 * be the case in well-behaved applications anyway.
4900 if (sctx
->vertex_elements
&& (sctx
->vertex_elements
->vb_alignment_check_mask
&
4901 (unaligned
| orig_unaligned
) & updated_mask
))
4902 sctx
->do_update_shaders
= true;
4909 static void si_set_tess_state(struct pipe_context
*ctx
, const float default_outer_level
[4],
4910 const float default_inner_level
[2])
4912 struct si_context
*sctx
= (struct si_context
*)ctx
;
4913 struct pipe_constant_buffer cb
;
4916 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4917 memcpy(array
+ 4, default_inner_level
, sizeof(float) * 2);
4920 cb
.user_buffer
= NULL
;
4921 cb
.buffer_size
= sizeof(array
);
4923 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
, (void *)array
, sizeof(array
),
4926 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4927 pipe_resource_reference(&cb
.buffer
, NULL
);
4930 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4932 struct si_context
*sctx
= (struct si_context
*)ctx
;
4934 si_update_fb_dirtiness_after_rendering(sctx
);
4936 /* Multisample surfaces are flushed in si_decompress_textures. */
4937 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
4938 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4939 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
4940 sctx
->framebuffer
.all_DCC_pipe_aligned
);
4944 /* This only ensures coherency for shader image/buffer stores. */
4945 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4947 struct si_context
*sctx
= (struct si_context
*)ctx
;
4949 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
4952 /* Subsequent commands must wait for all shader invocations to
4954 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
4956 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4957 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
| SI_CONTEXT_INV_VCACHE
;
4959 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
| PIPE_BARRIER_SHADER_BUFFER
| PIPE_BARRIER_TEXTURE
|
4960 PIPE_BARRIER_IMAGE
| PIPE_BARRIER_STREAMOUT_BUFFER
| PIPE_BARRIER_GLOBAL_BUFFER
)) {
4961 /* As far as I can tell, L1 contents are written back to L2
4962 * automatically at end of shader, but the contents of other
4963 * L1 caches might still be stale. */
4964 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
4967 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4968 /* Indices are read through TC L2 since GFX8.
4971 if (sctx
->screen
->info
.chip_class
<= GFX7
)
4972 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4975 /* MSAA color, any depth and any stencil are flushed in
4976 * si_decompress_textures when needed.
4978 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&& sctx
->framebuffer
.uncompressed_cb_mask
) {
4979 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4981 if (sctx
->chip_class
<= GFX8
)
4982 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4985 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4986 if (sctx
->screen
->info
.chip_class
<= GFX8
&& flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4987 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4990 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4992 struct pipe_blend_state blend
;
4994 memset(&blend
, 0, sizeof(blend
));
4995 blend
.independent_blend_enable
= true;
4996 blend
.rt
[0].colormask
= 0xf;
4997 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5000 static void si_init_config(struct si_context
*sctx
);
5002 void si_init_state_compute_functions(struct si_context
*sctx
)
5004 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5005 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5006 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5007 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5008 sctx
->b
.memory_barrier
= si_memory_barrier
;
5011 void si_init_state_functions(struct si_context
*sctx
)
5013 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5014 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5015 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5016 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5017 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5018 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5019 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5020 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5021 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5022 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5023 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5025 sctx
->b
.create_blend_state
= si_create_blend_state
;
5026 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5027 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5028 sctx
->b
.set_blend_color
= si_set_blend_color
;
5030 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5031 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5032 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5034 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5035 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5036 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5038 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5039 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5040 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5041 sctx
->custom_blend_eliminate_fastclear
=
5042 si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5043 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5045 sctx
->b
.set_clip_state
= si_set_clip_state
;
5046 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5048 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5050 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5052 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5053 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5054 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5055 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5057 sctx
->b
.texture_barrier
= si_texture_barrier
;
5058 sctx
->b
.set_min_samples
= si_set_min_samples
;
5059 sctx
->b
.set_tess_state
= si_set_tess_state
;
5061 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5063 si_init_config(sctx
);
5066 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5068 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5070 if (sscreen
->info
.chip_class
>= GFX10
) {
5071 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5073 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5077 static void si_set_grbm_gfx_index(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned value
)
5079 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
: R_00802C_GRBM_GFX_INDEX
;
5080 si_pm4_set_reg(pm4
, reg
, value
);
5083 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned se
)
5085 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5086 si_set_grbm_gfx_index(sctx
, pm4
,
5087 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) : S_030800_SE_INDEX(se
)) |
5088 S_030800_SH_BROADCAST_WRITES(1) |
5089 S_030800_INSTANCE_BROADCAST_WRITES(1));
5092 static void si_write_harvested_raster_configs(struct si_context
*sctx
, struct si_pm4_state
*pm4
,
5093 unsigned raster_config
, unsigned raster_config_1
)
5095 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5096 unsigned raster_config_se
[4];
5099 ac_get_harvested_configs(&sctx
->screen
->info
, raster_config
, &raster_config_1
, raster_config_se
);
5101 for (se
= 0; se
< num_se
; se
++) {
5102 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5103 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5105 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5107 if (sctx
->chip_class
>= GFX7
) {
5108 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5112 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5114 struct si_screen
*sscreen
= sctx
->screen
;
5115 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5116 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5117 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5118 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5120 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5121 /* Always use the default config when all backends are enabled
5122 * (or when we failed to determine the enabled backends).
5124 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config
);
5125 if (sctx
->chip_class
>= GFX7
)
5126 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5128 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5132 static void si_init_config(struct si_context
*sctx
)
5134 struct si_screen
*sscreen
= sctx
->screen
;
5135 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5136 bool has_clear_state
= sscreen
->info
.has_clear_state
;
5137 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5142 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5143 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
5144 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5145 si_pm4_cmd_end(pm4
, false);
5147 if (has_clear_state
) {
5148 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5149 si_pm4_cmd_add(pm4
, 0);
5150 si_pm4_cmd_end(pm4
, false);
5153 if (sctx
->chip_class
<= GFX8
)
5154 si_set_raster_config(sctx
, pm4
);
5156 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5157 if (!has_clear_state
)
5158 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5160 /* FIXME calculate these values somehow ??? */
5161 if (sctx
->chip_class
<= GFX8
) {
5162 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5163 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5166 if (!has_clear_state
) {
5167 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5168 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5169 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5172 if (sscreen
->info
.chip_class
<= GFX9
)
5173 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5174 if (!has_clear_state
)
5175 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5176 if (sctx
->chip_class
< GFX7
)
5177 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
,
5178 S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1));
5180 /* CLEAR_STATE doesn't restore these correctly. */
5181 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5182 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5183 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5185 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5186 * I don't know why. Deduced by trial and error.
5188 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5189 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5190 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5191 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5192 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5193 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5196 if (!has_clear_state
) {
5197 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5198 S_028230_ER_TRI(0xA) | S_028230_ER_POINT(0xA) | S_028230_ER_RECT(0xA) |
5199 /* Required by DX10_DIAMOND_TEST_ENA: */
5200 S_028230_ER_LINE_LR(0x1A) | S_028230_ER_LINE_RL(0x26) |
5201 S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA));
5202 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5203 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5204 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5205 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5206 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5209 if (sctx
->chip_class
>= GFX10
) {
5210 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5211 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5212 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5213 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5214 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5215 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5216 } else if (sctx
->chip_class
== GFX9
) {
5217 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5218 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5219 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5221 /* These registers, when written, also overwrite the CLEAR_STATE
5222 * context, so we can't rely on CLEAR_STATE setting them.
5223 * It would be an issue if there was another UMD changing them.
5225 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5226 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5227 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5230 if (sctx
->chip_class
>= GFX7
) {
5231 if (sctx
->chip_class
>= GFX10
) {
5232 /* Logical CUs 16 - 31 */
5233 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
, S_00B404_CU_EN(0xffff));
5234 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
, S_00B104_CU_EN(0xffff));
5235 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
, S_00B004_CU_EN(0xffff));
5238 if (sctx
->chip_class
>= GFX9
) {
5239 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5240 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5242 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5243 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5244 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_WAVE_LIMIT(0x3F));
5245 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5246 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5248 /* If this is 0, Bonaire can hang even if GS isn't being used.
5249 * Other chips are unaffected. These are suboptimal values,
5250 * but we don't use on-chip GS.
5252 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5253 S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4));
5256 /* Compute LATE_ALLOC_VS.LIMIT. */
5257 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5258 unsigned late_alloc_wave64
= 0; /* The limit is per SH. */
5259 unsigned cu_mask_vs
= 0xffff;
5260 unsigned cu_mask_gs
= 0xffff;
5262 if (sctx
->chip_class
>= GFX10
) {
5263 /* For Wave32, the hw will launch twice the number of late
5264 * alloc waves, so 1 == 2x wave32.
5266 if (!sscreen
->info
.use_late_alloc
) {
5267 late_alloc_wave64
= 0;
5268 } else if (num_cu_per_sh
<= 6) {
5269 late_alloc_wave64
= num_cu_per_sh
- 2;
5271 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5273 /* CU2 & CU3 disabled because of the dual CU design */
5274 /* Late alloc is not used for NGG on Navi14 due to a hw bug. */
5275 cu_mask_vs
= 0xfff3;
5276 cu_mask_gs
= sscreen
->use_ngg
&& sctx
->family
!= CHIP_NAVI14
? 0xfff3 : 0xffff;
5279 if (!sscreen
->info
.use_late_alloc
) {
5280 late_alloc_wave64
= 0;
5281 } else if (num_cu_per_sh
<= 4) {
5282 /* Too few available compute units per SH. Disallowing
5283 * VS to run on one CU could hurt us more than late VS
5284 * allocation would help.
5286 * 2 is the highest safe number that allows us to keep
5289 late_alloc_wave64
= 2;
5291 /* This is a good initial value, allowing 1 late_alloc
5292 * wave per SIMD on num_cu - 2.
5294 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5297 if (late_alloc_wave64
> 2)
5298 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5301 /* VS can't execute on one CU if the limit is > 2. */
5302 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5303 S_00B118_CU_EN(cu_mask_vs
) | S_00B118_WAVE_LIMIT(0x3F));
5304 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(late_alloc_wave64
));
5306 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5307 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5309 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5310 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5313 if (sctx
->chip_class
>= GFX10
) {
5314 /* Break up a pixel wave if it contains deallocs for more than
5315 * half the parameter cache.
5317 * To avoid a deadlock where pixel waves aren't launched
5318 * because they're waiting for more pixels while the frontend
5319 * is stuck waiting for PC space, the maximum allowed value is
5320 * the size of the PC minus the largest possible allocation for
5321 * a single primitive shader subgroup.
5323 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
, S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5324 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5326 if (!has_clear_state
) {
5327 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5328 sscreen
->info
.pa_sc_tile_steering_override
);
5331 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
5332 unsigned meta_write_policy
, meta_read_policy
;
5333 /* TODO: investigate whether LRU improves performance on other chips too */
5334 if (sscreen
->info
.num_render_backends
<= 4) {
5335 meta_write_policy
= V_02807C_CACHE_LRU_WR
; /* cache writes */
5336 meta_read_policy
= V_02807C_CACHE_LRU_RD
; /* cache reads */
5338 meta_write_policy
= V_02807C_CACHE_STREAM_WR
; /* write combine */
5339 meta_read_policy
= V_02807C_CACHE_NOA_RD
; /* don't cache reads */
5342 si_pm4_set_reg(pm4
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
5343 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5344 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5345 S_02807C_HTILE_WR_POLICY(meta_write_policy
) |
5346 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5347 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5348 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5349 S_02807C_HTILE_RD_POLICY(meta_read_policy
));
5352 pm4
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
5353 S_028410_CMASK_WR_POLICY(meta_write_policy
) | S_028410_FMASK_WR_POLICY(meta_write_policy
) |
5354 S_028410_DCC_WR_POLICY(meta_write_policy
) |
5355 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5356 S_028410_CMASK_RD_POLICY(meta_read_policy
) |
5357 S_028410_FMASK_RD_POLICY(meta_read_policy
) | S_028410_DCC_RD_POLICY(meta_read_policy
) |
5358 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
5359 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5361 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5362 S_00B0C0_SOFT_GROUPING_EN(1) | S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5363 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5366 if (sctx
->chip_class
>= GFX9
) {
5367 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
,
5368 S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) |
5369 S_028B50_DONUT_SPLIT(24) | S_028B50_TRAP_SPLIT(6));
5370 } else if (sctx
->chip_class
>= GFX8
) {
5371 unsigned vgt_tess_distribution
;
5373 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) |
5374 S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT(16);
5376 /* Testing with Unigine Heaven extreme tesselation yielded best results
5377 * with TRAP_SPLIT = 3.
5379 if (sctx
->family
== CHIP_FIJI
|| sctx
->family
>= CHIP_POLARIS10
)
5380 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5382 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5383 } else if (!has_clear_state
) {
5384 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5385 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5388 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5389 if (sctx
->chip_class
>= GFX7
) {
5390 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, S_028084_ADDRESS(border_color_va
>> 40));
5392 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
, RADEON_PRIO_BORDER_COLORS
);
5394 if (sctx
->chip_class
>= GFX9
) {
5395 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5396 S_028C48_MAX_ALLOC_COUNT(sscreen
->info
.pbb_max_alloc_count
- 1) |
5397 S_028C48_MAX_PRIM_PER_BATCH(1023));
5398 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5399 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5400 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5403 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5404 sctx
->init_config
= pm4
;