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radeonsi: set better tessellation tunables on gfx9 and gfx10
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/format/u_format.h"
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit &
86 blend->cb_target_mask;
87 unsigned i;
88
89 /* Avoid a hang that happens when dual source blending is enabled
90 * but there is not enough color outputs. This is undefined behavior,
91 * so disable color writes completely.
92 *
93 * Reproducible with Unigine Heaven 4.0 and drirc missing.
94 */
95 if (blend->dual_src_blend &&
96 sctx->ps_shader.cso &&
97 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
98 cb_target_mask = 0;
99
100 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
101 * I think we don't have to do anything between IBs.
102 */
103 if (sctx->screen->dpbb_allowed &&
104 sctx->last_cb_target_mask != cb_target_mask) {
105 sctx->last_cb_target_mask = cb_target_mask;
106
107 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
108 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
109 }
110
111 unsigned initial_cdw = cs->current.cdw;
112 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
113 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
114
115 if (sctx->chip_class >= GFX8) {
116 /* DCC MSAA workaround.
117 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
118 * COMBINER_DISABLE, but that would be more complicated.
119 */
120 bool oc_disable = blend->dcc_msaa_corruption_4bit & cb_target_mask &&
121 sctx->framebuffer.nr_samples >= 2;
122 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
123
124 radeon_opt_set_context_reg(
125 sctx, R_028424_CB_DCC_CONTROL,
126 SI_TRACKED_CB_DCC_CONTROL,
127 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
128 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
129 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
130 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->info.has_dcc_constant_encode));
131 }
132
133 /* RB+ register settings. */
134 if (sctx->screen->info.rbplus_allowed) {
135 unsigned spi_shader_col_format =
136 sctx->ps_shader.cso ?
137 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
138 unsigned sx_ps_downconvert = 0;
139 unsigned sx_blend_opt_epsilon = 0;
140 unsigned sx_blend_opt_control = 0;
141
142 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
143 struct si_surface *surf =
144 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
145 unsigned format, swap, spi_format, colormask;
146 bool has_alpha, has_rgb;
147
148 if (!surf) {
149 /* If the color buffer is not set, the driver sets 32_R
150 * as the SPI color format, because the hw doesn't allow
151 * holes between color outputs, so also set this to
152 * enable RB+.
153 */
154 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
155 continue;
156 }
157
158 format = G_028C70_FORMAT(surf->cb_color_info);
159 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
160 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
161 colormask = (cb_target_mask >> (i * 4)) & 0xf;
162
163 /* Set if RGB and A are present. */
164 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
165
166 if (format == V_028C70_COLOR_8 ||
167 format == V_028C70_COLOR_16 ||
168 format == V_028C70_COLOR_32)
169 has_rgb = !has_alpha;
170 else
171 has_rgb = true;
172
173 /* Check the colormask and export format. */
174 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
175 has_rgb = false;
176 if (!(colormask & PIPE_MASK_A))
177 has_alpha = false;
178
179 if (spi_format == V_028714_SPI_SHADER_ZERO) {
180 has_rgb = false;
181 has_alpha = false;
182 }
183
184 /* Disable value checking for disabled channels. */
185 if (!has_rgb)
186 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
187 if (!has_alpha)
188 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
189
190 /* Enable down-conversion for 32bpp and smaller formats. */
191 switch (format) {
192 case V_028C70_COLOR_8:
193 case V_028C70_COLOR_8_8:
194 case V_028C70_COLOR_8_8_8_8:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
198 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_5_6_5:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_1_5_5_5:
212 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
214 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
215 }
216 break;
217
218 case V_028C70_COLOR_4_4_4_4:
219 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
220 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
221 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
222 }
223 break;
224
225 case V_028C70_COLOR_32:
226 if (swap == V_028C70_SWAP_STD &&
227 spi_format == V_028714_SPI_SHADER_32_R)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
229 else if (swap == V_028C70_SWAP_ALT_REV &&
230 spi_format == V_028714_SPI_SHADER_32_AR)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
232 break;
233
234 case V_028C70_COLOR_16:
235 case V_028C70_COLOR_16_16:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
240 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
241 if (swap == V_028C70_SWAP_STD ||
242 swap == V_028C70_SWAP_STD_REV)
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
244 else
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
246 }
247 break;
248
249 case V_028C70_COLOR_10_11_11:
250 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
251 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
252 break;
253
254 case V_028C70_COLOR_2_10_10_10:
255 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
256 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
257 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
258 }
259 break;
260 }
261 }
262
263 /* If there are no color outputs, the first color export is
264 * always enabled as 32_R, so also set this to enable RB+.
265 */
266 if (!sx_ps_downconvert)
267 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
268
269 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
270 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
271 SI_TRACKED_SX_PS_DOWNCONVERT,
272 sx_ps_downconvert, sx_blend_opt_epsilon,
273 sx_blend_opt_control);
274 }
275 if (initial_cdw != cs->current.cdw)
276 sctx->context_roll = true;
277 }
278
279 /*
280 * Blender functions
281 */
282
283 static uint32_t si_translate_blend_function(int blend_func)
284 {
285 switch (blend_func) {
286 case PIPE_BLEND_ADD:
287 return V_028780_COMB_DST_PLUS_SRC;
288 case PIPE_BLEND_SUBTRACT:
289 return V_028780_COMB_SRC_MINUS_DST;
290 case PIPE_BLEND_REVERSE_SUBTRACT:
291 return V_028780_COMB_DST_MINUS_SRC;
292 case PIPE_BLEND_MIN:
293 return V_028780_COMB_MIN_DST_SRC;
294 case PIPE_BLEND_MAX:
295 return V_028780_COMB_MAX_DST_SRC;
296 default:
297 PRINT_ERR("Unknown blend function %d\n", blend_func);
298 assert(0);
299 break;
300 }
301 return 0;
302 }
303
304 static uint32_t si_translate_blend_factor(int blend_fact)
305 {
306 switch (blend_fact) {
307 case PIPE_BLENDFACTOR_ONE:
308 return V_028780_BLEND_ONE;
309 case PIPE_BLENDFACTOR_SRC_COLOR:
310 return V_028780_BLEND_SRC_COLOR;
311 case PIPE_BLENDFACTOR_SRC_ALPHA:
312 return V_028780_BLEND_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_DST_ALPHA:
314 return V_028780_BLEND_DST_ALPHA;
315 case PIPE_BLENDFACTOR_DST_COLOR:
316 return V_028780_BLEND_DST_COLOR;
317 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
318 return V_028780_BLEND_SRC_ALPHA_SATURATE;
319 case PIPE_BLENDFACTOR_CONST_COLOR:
320 return V_028780_BLEND_CONSTANT_COLOR;
321 case PIPE_BLENDFACTOR_CONST_ALPHA:
322 return V_028780_BLEND_CONSTANT_ALPHA;
323 case PIPE_BLENDFACTOR_ZERO:
324 return V_028780_BLEND_ZERO;
325 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
326 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
329 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
330 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
331 case PIPE_BLENDFACTOR_INV_DST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
333 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
335 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
337 case PIPE_BLENDFACTOR_SRC1_COLOR:
338 return V_028780_BLEND_SRC1_COLOR;
339 case PIPE_BLENDFACTOR_SRC1_ALPHA:
340 return V_028780_BLEND_SRC1_ALPHA;
341 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
342 return V_028780_BLEND_INV_SRC1_COLOR;
343 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
344 return V_028780_BLEND_INV_SRC1_ALPHA;
345 default:
346 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
347 assert(0);
348 break;
349 }
350 return 0;
351 }
352
353 static uint32_t si_translate_blend_opt_function(int blend_func)
354 {
355 switch (blend_func) {
356 case PIPE_BLEND_ADD:
357 return V_028760_OPT_COMB_ADD;
358 case PIPE_BLEND_SUBTRACT:
359 return V_028760_OPT_COMB_SUBTRACT;
360 case PIPE_BLEND_REVERSE_SUBTRACT:
361 return V_028760_OPT_COMB_REVSUBTRACT;
362 case PIPE_BLEND_MIN:
363 return V_028760_OPT_COMB_MIN;
364 case PIPE_BLEND_MAX:
365 return V_028760_OPT_COMB_MAX;
366 default:
367 return V_028760_OPT_COMB_BLEND_DISABLED;
368 }
369 }
370
371 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
372 {
373 switch (blend_fact) {
374 case PIPE_BLENDFACTOR_ZERO:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
376 case PIPE_BLENDFACTOR_ONE:
377 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
378 case PIPE_BLENDFACTOR_SRC_COLOR:
379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
380 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
381 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
382 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
383 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
384 case PIPE_BLENDFACTOR_SRC_ALPHA:
385 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
386 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
387 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
388 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
389 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
390 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
391 default:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
393 }
394 }
395
396 static void si_blend_check_commutativity(struct si_screen *sscreen,
397 struct si_state_blend *blend,
398 enum pipe_blend_func func,
399 enum pipe_blendfactor src,
400 enum pipe_blendfactor dst,
401 unsigned chanmask)
402 {
403 /* Src factor is allowed when it does not depend on Dst */
404 static const uint32_t src_allowed =
405 (1u << PIPE_BLENDFACTOR_ONE) |
406 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
407 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
408 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
409 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
410 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
411 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
412 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
413 (1u << PIPE_BLENDFACTOR_ZERO) |
414 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
417 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
420
421 if (dst == PIPE_BLENDFACTOR_ONE &&
422 (src_allowed & (1u << src))) {
423 /* Addition is commutative, but floating point addition isn't
424 * associative: subtle changes can be introduced via different
425 * rounding.
426 *
427 * Out-of-order is also non-deterministic, which means that
428 * this breaks OpenGL invariance requirements. So only enable
429 * out-of-order additive blending if explicitly allowed by a
430 * setting.
431 */
432 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
433 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
434 blend->commutative_4bit |= chanmask;
435 }
436 }
437
438 /**
439 * Get rid of DST in the blend factors by commuting the operands:
440 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
441 */
442 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
443 unsigned *dst_factor, unsigned expected_dst,
444 unsigned replacement_src)
445 {
446 if (*src_factor == expected_dst &&
447 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
448 *src_factor = PIPE_BLENDFACTOR_ZERO;
449 *dst_factor = replacement_src;
450
451 /* Commuting the operands requires reversing subtractions. */
452 if (*func == PIPE_BLEND_SUBTRACT)
453 *func = PIPE_BLEND_REVERSE_SUBTRACT;
454 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
455 *func = PIPE_BLEND_SUBTRACT;
456 }
457 }
458
459 static bool si_blend_factor_uses_dst(unsigned factor)
460 {
461 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
462 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
463 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
464 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
465 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
466 }
467
468 static void *si_create_blend_state_mode(struct pipe_context *ctx,
469 const struct pipe_blend_state *state,
470 unsigned mode)
471 {
472 struct si_context *sctx = (struct si_context*)ctx;
473 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
474 struct si_pm4_state *pm4 = &blend->pm4;
475 uint32_t sx_mrt_blend_opt[8] = {0};
476 uint32_t color_control = 0;
477 bool logicop_enable = state->logicop_enable &&
478 state->logicop_func != PIPE_LOGICOP_COPY;
479
480 if (!blend)
481 return NULL;
482
483 blend->alpha_to_coverage = state->alpha_to_coverage;
484 blend->alpha_to_one = state->alpha_to_one;
485 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
486 blend->logicop_enable = logicop_enable;
487
488 if (logicop_enable) {
489 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
490 } else {
491 color_control |= S_028808_ROP3(0xcc);
492 }
493
494 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
495 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
496 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
497 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
498 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
499 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
500 S_028B70_OFFSET_ROUND(1));
501
502 if (state->alpha_to_coverage)
503 blend->need_src_alpha_4bit |= 0xf;
504
505 blend->cb_target_mask = 0;
506 blend->cb_target_enabled_4bit = 0;
507
508 for (int i = 0; i < 8; i++) {
509 /* state->rt entries > 0 only written if independent blending */
510 const int j = state->independent_blend_enable ? i : 0;
511
512 unsigned eqRGB = state->rt[j].rgb_func;
513 unsigned srcRGB = state->rt[j].rgb_src_factor;
514 unsigned dstRGB = state->rt[j].rgb_dst_factor;
515 unsigned eqA = state->rt[j].alpha_func;
516 unsigned srcA = state->rt[j].alpha_src_factor;
517 unsigned dstA = state->rt[j].alpha_dst_factor;
518
519 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
520 unsigned blend_cntl = 0;
521
522 sx_mrt_blend_opt[i] =
523 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
524 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
525
526 /* Only set dual source blending for MRT0 to avoid a hang. */
527 if (i >= 1 && blend->dual_src_blend) {
528 /* Vulkan does this for dual source blending. */
529 if (i == 1)
530 blend_cntl |= S_028780_ENABLE(1);
531
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 continue;
534 }
535
536 /* Only addition and subtraction equations are supported with
537 * dual source blending.
538 */
539 if (blend->dual_src_blend &&
540 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
541 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
542 assert(!"Unsupported equation for dual source blending");
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
544 continue;
545 }
546
547 /* cb_render_state will disable unused ones */
548 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
549 if (state->rt[j].colormask)
550 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
551
552 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
553 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
554 continue;
555 }
556
557 si_blend_check_commutativity(sctx->screen, blend,
558 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
559 si_blend_check_commutativity(sctx->screen, blend,
560 eqA, srcA, dstA, 0x8 << (4 * i));
561
562 /* Blending optimizations for RB+.
563 * These transformations don't change the behavior.
564 *
565 * First, get rid of DST in the blend factors:
566 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
567 */
568 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
569 PIPE_BLENDFACTOR_DST_COLOR,
570 PIPE_BLENDFACTOR_SRC_COLOR);
571 si_blend_remove_dst(&eqA, &srcA, &dstA,
572 PIPE_BLENDFACTOR_DST_COLOR,
573 PIPE_BLENDFACTOR_SRC_COLOR);
574 si_blend_remove_dst(&eqA, &srcA, &dstA,
575 PIPE_BLENDFACTOR_DST_ALPHA,
576 PIPE_BLENDFACTOR_SRC_ALPHA);
577
578 /* Look up the ideal settings from tables. */
579 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
580 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
581 srcA_opt = si_translate_blend_opt_factor(srcA, true);
582 dstA_opt = si_translate_blend_opt_factor(dstA, true);
583
584 /* Handle interdependencies. */
585 if (si_blend_factor_uses_dst(srcRGB))
586 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
587 if (si_blend_factor_uses_dst(srcA))
588 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
589
590 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
591 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
592 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
593 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
594 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
595
596 /* Set the final value. */
597 sx_mrt_blend_opt[i] =
598 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
599 S_028760_COLOR_DST_OPT(dstRGB_opt) |
600 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
601 S_028760_ALPHA_SRC_OPT(srcA_opt) |
602 S_028760_ALPHA_DST_OPT(dstA_opt) |
603 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
604
605 /* Set blend state. */
606 blend_cntl |= S_028780_ENABLE(1);
607 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
608 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
609 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
610
611 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
612 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
613 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
614 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
615 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
616 }
617 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
618
619 blend->blend_enable_4bit |= 0xfu << (i * 4);
620
621 if (sctx->chip_class >= GFX8 && sctx->family <= CHIP_NAVI14)
622 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
623
624 /* This is only important for formats without alpha. */
625 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
626 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
627 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
628 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
629 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
630 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
631 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
632 }
633
634 if (sctx->chip_class >= GFX8 && sctx->family <= CHIP_NAVI14 && logicop_enable)
635 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
636
637 if (blend->cb_target_mask) {
638 color_control |= S_028808_MODE(mode);
639 } else {
640 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
641 }
642
643 if (sctx->screen->info.rbplus_allowed) {
644 /* Disable RB+ blend optimizations for dual source blending.
645 * Vulkan does this.
646 */
647 if (blend->dual_src_blend) {
648 for (int i = 0; i < 8; i++) {
649 sx_mrt_blend_opt[i] =
650 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
651 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
652 }
653 }
654
655 for (int i = 0; i < 8; i++)
656 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
657 sx_mrt_blend_opt[i]);
658
659 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
660 if (blend->dual_src_blend || logicop_enable ||
661 mode == V_028808_CB_RESOLVE)
662 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
663 }
664
665 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
666 return blend;
667 }
668
669 static void *si_create_blend_state(struct pipe_context *ctx,
670 const struct pipe_blend_state *state)
671 {
672 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
673 }
674
675 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
676 {
677 struct si_context *sctx = (struct si_context *)ctx;
678 struct si_state_blend *old_blend = sctx->queued.named.blend;
679 struct si_state_blend *blend = (struct si_state_blend *)state;
680
681 if (!blend)
682 blend = (struct si_state_blend *)sctx->noop_blend;
683
684 si_pm4_bind_state(sctx, blend, blend);
685
686 if (old_blend->cb_target_mask != blend->cb_target_mask ||
687 old_blend->dual_src_blend != blend->dual_src_blend ||
688 (old_blend->dcc_msaa_corruption_4bit != blend->dcc_msaa_corruption_4bit &&
689 sctx->framebuffer.nr_samples >= 2 &&
690 sctx->screen->dcc_msaa_allowed))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
692
693 if (old_blend->cb_target_mask != blend->cb_target_mask ||
694 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
695 old_blend->alpha_to_one != blend->alpha_to_one ||
696 old_blend->dual_src_blend != blend->dual_src_blend ||
697 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
698 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
699 sctx->do_update_shaders = true;
700
701 if (sctx->screen->dpbb_allowed &&
702 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
703 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
704 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
705 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
706
707 if (sctx->screen->has_out_of_order_rast &&
708 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
709 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
710 old_blend->commutative_4bit != blend->commutative_4bit ||
711 old_blend->logicop_enable != blend->logicop_enable)))
712 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
713 }
714
715 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718
719 if (sctx->queued.named.blend == state)
720 si_bind_blend_state(ctx, sctx->noop_blend);
721
722 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
723 }
724
725 static void si_set_blend_color(struct pipe_context *ctx,
726 const struct pipe_blend_color *state)
727 {
728 struct si_context *sctx = (struct si_context *)ctx;
729 static const struct pipe_blend_color zeros;
730
731 sctx->blend_color.state = *state;
732 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
733 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
734 }
735
736 static void si_emit_blend_color(struct si_context *sctx)
737 {
738 struct radeon_cmdbuf *cs = sctx->gfx_cs;
739
740 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
741 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
742 }
743
744 /*
745 * Clipping
746 */
747
748 static void si_set_clip_state(struct pipe_context *ctx,
749 const struct pipe_clip_state *state)
750 {
751 struct si_context *sctx = (struct si_context *)ctx;
752 struct pipe_constant_buffer cb;
753 static const struct pipe_clip_state zeros;
754
755 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
756 return;
757
758 sctx->clip_state.state = *state;
759 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
760 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
761
762 cb.buffer = NULL;
763 cb.user_buffer = state->ucp;
764 cb.buffer_offset = 0;
765 cb.buffer_size = 4*4*8;
766 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
767 pipe_resource_reference(&cb.buffer, NULL);
768 }
769
770 static void si_emit_clip_state(struct si_context *sctx)
771 {
772 struct radeon_cmdbuf *cs = sctx->gfx_cs;
773
774 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
775 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
776 }
777
778 static void si_emit_clip_regs(struct si_context *sctx)
779 {
780 struct si_shader *vs = si_get_vs_state(sctx);
781 struct si_shader_selector *vs_sel = vs->selector;
782 struct si_shader_info *info = &vs_sel->info;
783 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
784 unsigned window_space =
785 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
786 unsigned clipdist_mask = vs_sel->clipdist_mask;
787 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
788 unsigned culldist_mask = vs_sel->culldist_mask;
789 unsigned total_mask;
790
791 if (vs->key.opt.clip_disable) {
792 assert(!info->culldist_writemask);
793 clipdist_mask = 0;
794 culldist_mask = 0;
795 }
796 total_mask = clipdist_mask | culldist_mask;
797
798 /* Clip distances on points have no effect, so need to be implemented
799 * as cull distances. This applies for the clipvertex case as well.
800 *
801 * Setting this for primitives other than points should have no adverse
802 * effects.
803 */
804 clipdist_mask &= rs->clip_plane_enable;
805 culldist_mask |= clipdist_mask;
806
807 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
808 unsigned pa_cl_cntl = S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
809 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
810 clipdist_mask | (culldist_mask << 8);
811
812 if (sctx->chip_class >= GFX10) {
813 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
814 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL,
815 pa_cl_cntl,
816 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
817 } else {
818 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
819 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL,
820 vs_sel->pa_cl_vs_out_cntl | pa_cl_cntl);
821 }
822 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
823 SI_TRACKED_PA_CL_CLIP_CNTL,
824 rs->pa_cl_clip_cntl |
825 ucp_mask |
826 S_028810_CLIP_DISABLE(window_space));
827
828 if (initial_cdw != sctx->gfx_cs->current.cdw)
829 sctx->context_roll = true;
830 }
831
832 /*
833 * inferred state between framebuffer and rasterizer
834 */
835 static void si_update_poly_offset_state(struct si_context *sctx)
836 {
837 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
838
839 if (!rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
840 si_pm4_bind_state(sctx, poly_offset, NULL);
841 return;
842 }
843
844 /* Use the user format, not db_render_format, so that the polygon
845 * offset behaves as expected by applications.
846 */
847 switch (sctx->framebuffer.state.zsbuf->texture->format) {
848 case PIPE_FORMAT_Z16_UNORM:
849 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
850 break;
851 default: /* 24-bit */
852 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
853 break;
854 case PIPE_FORMAT_Z32_FLOAT:
855 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
856 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
857 break;
858 }
859 }
860
861 /*
862 * Rasterizer
863 */
864
865 static uint32_t si_translate_fill(uint32_t func)
866 {
867 switch(func) {
868 case PIPE_POLYGON_MODE_FILL:
869 return V_028814_X_DRAW_TRIANGLES;
870 case PIPE_POLYGON_MODE_LINE:
871 return V_028814_X_DRAW_LINES;
872 case PIPE_POLYGON_MODE_POINT:
873 return V_028814_X_DRAW_POINTS;
874 default:
875 assert(0);
876 return V_028814_X_DRAW_POINTS;
877 }
878 }
879
880 static void *si_create_rs_state(struct pipe_context *ctx,
881 const struct pipe_rasterizer_state *state)
882 {
883 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
884 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
885 struct si_pm4_state *pm4 = &rs->pm4;
886 unsigned tmp, i;
887 float psize_min, psize_max;
888
889 if (!rs) {
890 return NULL;
891 }
892
893 if (!state->front_ccw) {
894 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
895 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
896 } else {
897 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
898 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
899 }
900 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
901 rs->provoking_vertex_first = state->flatshade_first;
902 rs->scissor_enable = state->scissor;
903 rs->clip_halfz = state->clip_halfz;
904 rs->two_side = state->light_twoside;
905 rs->multisample_enable = state->multisample;
906 rs->force_persample_interp = state->force_persample_interp;
907 rs->clip_plane_enable = state->clip_plane_enable;
908 rs->half_pixel_center = state->half_pixel_center;
909 rs->line_stipple_enable = state->line_stipple_enable;
910 rs->poly_stipple_enable = state->poly_stipple_enable;
911 rs->line_smooth = state->line_smooth;
912 rs->line_width = state->line_width;
913 rs->poly_smooth = state->poly_smooth;
914 rs->uses_poly_offset = state->offset_point || state->offset_line ||
915 state->offset_tri;
916 rs->clamp_fragment_color = state->clamp_fragment_color;
917 rs->clamp_vertex_color = state->clamp_vertex_color;
918 rs->flatshade = state->flatshade;
919 rs->flatshade_first = state->flatshade_first;
920 rs->sprite_coord_enable = state->sprite_coord_enable;
921 rs->rasterizer_discard = state->rasterizer_discard;
922 rs->polygon_mode_enabled = (state->fill_front != PIPE_POLYGON_MODE_FILL &&
923 !(state->cull_face & PIPE_FACE_FRONT)) ||
924 (state->fill_back != PIPE_POLYGON_MODE_FILL &&
925 !(state->cull_face & PIPE_FACE_BACK));
926 rs->polygon_mode_is_lines = (state->fill_front == PIPE_POLYGON_MODE_LINE &&
927 !(state->cull_face & PIPE_FACE_FRONT)) ||
928 (state->fill_back == PIPE_POLYGON_MODE_LINE &&
929 !(state->cull_face & PIPE_FACE_BACK));
930 rs->pa_sc_line_stipple = state->line_stipple_enable ?
931 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
932 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
933 rs->pa_cl_clip_cntl =
934 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
935 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
936 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
937 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
938 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
939
940 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
941 S_0286D4_FLAT_SHADE_ENA(1) |
942 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
943 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
944 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
945 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
946 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
947 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
948
949 /* point size 12.4 fixed point */
950 tmp = (unsigned)(state->point_size * 8.0);
951 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
952
953 if (state->point_size_per_vertex) {
954 psize_min = util_get_min_point_size(state);
955 psize_max = SI_MAX_POINT_SIZE;
956 } else {
957 /* Force the point size to be as if the vertex output was disabled. */
958 psize_min = state->point_size;
959 psize_max = state->point_size;
960 }
961 rs->max_point_size = psize_max;
962
963 /* Divide by two, because 0.5 = 1 pixel. */
964 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
965 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
966 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
967
968 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
969 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
970 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
971 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
972 S_028A48_MSAA_ENABLE(state->multisample ||
973 state->poly_smooth ||
974 state->line_smooth) |
975 S_028A48_VPORT_SCISSOR_ENABLE(1) |
976 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
977
978 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
979 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
980 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
981 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
982 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
983 S_028814_FACE(!state->front_ccw) |
984 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
985 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
986 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
987 S_028814_POLY_MODE(rs->polygon_mode_enabled) |
988 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
989 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
990
991 if (!rs->uses_poly_offset)
992 return rs;
993
994 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
995 if (!rs->pm4_poly_offset) {
996 FREE(rs);
997 return NULL;
998 }
999
1000 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1001 for (i = 0; i < 3; i++) {
1002 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
1003 float offset_units = state->offset_units;
1004 float offset_scale = state->offset_scale * 16.0f;
1005 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1006
1007 if (!state->offset_units_unscaled) {
1008 switch (i) {
1009 case 0: /* 16-bit zbuffer */
1010 offset_units *= 4.0f;
1011 pa_su_poly_offset_db_fmt_cntl =
1012 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1013 break;
1014 case 1: /* 24-bit zbuffer */
1015 offset_units *= 2.0f;
1016 pa_su_poly_offset_db_fmt_cntl =
1017 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1018 break;
1019 case 2: /* 32-bit zbuffer */
1020 offset_units *= 1.0f;
1021 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1022 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1023 break;
1024 }
1025 }
1026
1027 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1028 fui(offset_scale));
1029 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1030 fui(offset_units));
1031 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1032 fui(offset_scale));
1033 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1034 fui(offset_units));
1035 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1036 pa_su_poly_offset_db_fmt_cntl);
1037 }
1038
1039 return rs;
1040 }
1041
1042 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1043 {
1044 struct si_context *sctx = (struct si_context *)ctx;
1045 struct si_state_rasterizer *old_rs =
1046 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1047 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1048
1049 if (!rs)
1050 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
1051
1052 if (old_rs->multisample_enable != rs->multisample_enable) {
1053 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1054
1055 /* Update the small primitive filter workaround if necessary. */
1056 if (sctx->screen->info.has_msaa_sample_loc_bug &&
1057 sctx->framebuffer.nr_samples > 1)
1058 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1059 }
1060
1061 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1062 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1063
1064 si_pm4_bind_state(sctx, rasterizer, rs);
1065 si_update_poly_offset_state(sctx);
1066
1067 if (old_rs->scissor_enable != rs->scissor_enable)
1068 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1069
1070 if (old_rs->line_width != rs->line_width ||
1071 old_rs->max_point_size != rs->max_point_size ||
1072 old_rs->half_pixel_center != rs->half_pixel_center)
1073 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1074
1075 if (old_rs->clip_halfz != rs->clip_halfz)
1076 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1077
1078 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1079 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1080 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1081
1082 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1083 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1084 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1085 old_rs->flatshade != rs->flatshade ||
1086 old_rs->two_side != rs->two_side ||
1087 old_rs->multisample_enable != rs->multisample_enable ||
1088 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1089 old_rs->poly_smooth != rs->poly_smooth ||
1090 old_rs->line_smooth != rs->line_smooth ||
1091 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1092 old_rs->force_persample_interp != rs->force_persample_interp)
1093 sctx->do_update_shaders = true;
1094 }
1095
1096 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1097 {
1098 struct si_context *sctx = (struct si_context *)ctx;
1099 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1100
1101 if (sctx->queued.named.rasterizer == state)
1102 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1103
1104 FREE(rs->pm4_poly_offset);
1105 si_pm4_delete_state(sctx, rasterizer, rs);
1106 }
1107
1108 /*
1109 * infeered state between dsa and stencil ref
1110 */
1111 static void si_emit_stencil_ref(struct si_context *sctx)
1112 {
1113 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1114 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1115 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1116
1117 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1118 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1119 S_028430_STENCILMASK(dsa->valuemask[0]) |
1120 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1121 S_028430_STENCILOPVAL(1));
1122 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1123 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1124 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1125 S_028434_STENCILOPVAL_BF(1));
1126 }
1127
1128 static void si_set_stencil_ref(struct pipe_context *ctx,
1129 const struct pipe_stencil_ref *state)
1130 {
1131 struct si_context *sctx = (struct si_context *)ctx;
1132
1133 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1134 return;
1135
1136 sctx->stencil_ref.state = *state;
1137 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1138 }
1139
1140
1141 /*
1142 * DSA
1143 */
1144
1145 static uint32_t si_translate_stencil_op(int s_op)
1146 {
1147 switch (s_op) {
1148 case PIPE_STENCIL_OP_KEEP:
1149 return V_02842C_STENCIL_KEEP;
1150 case PIPE_STENCIL_OP_ZERO:
1151 return V_02842C_STENCIL_ZERO;
1152 case PIPE_STENCIL_OP_REPLACE:
1153 return V_02842C_STENCIL_REPLACE_TEST;
1154 case PIPE_STENCIL_OP_INCR:
1155 return V_02842C_STENCIL_ADD_CLAMP;
1156 case PIPE_STENCIL_OP_DECR:
1157 return V_02842C_STENCIL_SUB_CLAMP;
1158 case PIPE_STENCIL_OP_INCR_WRAP:
1159 return V_02842C_STENCIL_ADD_WRAP;
1160 case PIPE_STENCIL_OP_DECR_WRAP:
1161 return V_02842C_STENCIL_SUB_WRAP;
1162 case PIPE_STENCIL_OP_INVERT:
1163 return V_02842C_STENCIL_INVERT;
1164 default:
1165 PRINT_ERR("Unknown stencil op %d", s_op);
1166 assert(0);
1167 break;
1168 }
1169 return 0;
1170 }
1171
1172 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1173 {
1174 return s->enabled && s->writemask &&
1175 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1176 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1177 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1178 }
1179
1180 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1181 {
1182 /* REPLACE is normally order invariant, except when the stencil
1183 * reference value is written by the fragment shader. Tracking this
1184 * interaction does not seem worth the effort, so be conservative. */
1185 return op != PIPE_STENCIL_OP_INCR &&
1186 op != PIPE_STENCIL_OP_DECR &&
1187 op != PIPE_STENCIL_OP_REPLACE;
1188 }
1189
1190 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1191 * invariant in the sense that the set of passing fragments as well as the
1192 * final stencil buffer result does not depend on the order of fragments. */
1193 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1194 {
1195 return !state->enabled || !state->writemask ||
1196 /* The following assumes that Z writes are disabled. */
1197 (state->func == PIPE_FUNC_ALWAYS &&
1198 si_order_invariant_stencil_op(state->zpass_op) &&
1199 si_order_invariant_stencil_op(state->zfail_op)) ||
1200 (state->func == PIPE_FUNC_NEVER &&
1201 si_order_invariant_stencil_op(state->fail_op));
1202 }
1203
1204 static void *si_create_dsa_state(struct pipe_context *ctx,
1205 const struct pipe_depth_stencil_alpha_state *state)
1206 {
1207 struct si_context *sctx = (struct si_context *)ctx;
1208 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1209 struct si_pm4_state *pm4 = &dsa->pm4;
1210 unsigned db_depth_control;
1211 uint32_t db_stencil_control = 0;
1212
1213 if (!dsa) {
1214 return NULL;
1215 }
1216
1217 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1218 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1219 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1220 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1221
1222 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1223 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1224 S_028800_ZFUNC(state->depth.func) |
1225 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1226
1227 /* stencil */
1228 if (state->stencil[0].enabled) {
1229 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1230 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1231 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1232 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1233 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1234
1235 if (state->stencil[1].enabled) {
1236 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1237 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1238 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1239 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1240 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1241 }
1242 }
1243
1244 /* alpha */
1245 if (state->alpha.enabled) {
1246 dsa->alpha_func = state->alpha.func;
1247
1248 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1249 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1250 } else {
1251 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1252 }
1253
1254 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1255 if (state->stencil[0].enabled)
1256 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1257 if (state->depth.bounds_test) {
1258 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1259 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1260 }
1261
1262 dsa->depth_enabled = state->depth.enabled;
1263 dsa->depth_write_enabled = state->depth.enabled &&
1264 state->depth.writemask;
1265 dsa->stencil_enabled = state->stencil[0].enabled;
1266 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1267 (si_dsa_writes_stencil(&state->stencil[0]) ||
1268 si_dsa_writes_stencil(&state->stencil[1]));
1269 dsa->db_can_write = dsa->depth_write_enabled ||
1270 dsa->stencil_write_enabled;
1271
1272 bool zfunc_is_ordered =
1273 state->depth.func == PIPE_FUNC_NEVER ||
1274 state->depth.func == PIPE_FUNC_LESS ||
1275 state->depth.func == PIPE_FUNC_LEQUAL ||
1276 state->depth.func == PIPE_FUNC_GREATER ||
1277 state->depth.func == PIPE_FUNC_GEQUAL;
1278
1279 bool nozwrite_and_order_invariant_stencil =
1280 !dsa->db_can_write ||
1281 (!dsa->depth_write_enabled &&
1282 si_order_invariant_stencil_state(&state->stencil[0]) &&
1283 si_order_invariant_stencil_state(&state->stencil[1]));
1284
1285 dsa->order_invariance[1].zs =
1286 nozwrite_and_order_invariant_stencil ||
1287 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1288 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1289
1290 dsa->order_invariance[1].pass_set =
1291 nozwrite_and_order_invariant_stencil ||
1292 (!dsa->stencil_write_enabled &&
1293 (state->depth.func == PIPE_FUNC_ALWAYS ||
1294 state->depth.func == PIPE_FUNC_NEVER));
1295 dsa->order_invariance[0].pass_set =
1296 !dsa->depth_write_enabled ||
1297 (state->depth.func == PIPE_FUNC_ALWAYS ||
1298 state->depth.func == PIPE_FUNC_NEVER);
1299
1300 dsa->order_invariance[1].pass_last =
1301 sctx->screen->assume_no_z_fights &&
1302 !dsa->stencil_write_enabled &&
1303 dsa->depth_write_enabled && zfunc_is_ordered;
1304 dsa->order_invariance[0].pass_last =
1305 sctx->screen->assume_no_z_fights &&
1306 dsa->depth_write_enabled && zfunc_is_ordered;
1307
1308 return dsa;
1309 }
1310
1311 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1312 {
1313 struct si_context *sctx = (struct si_context *)ctx;
1314 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1315 struct si_state_dsa *dsa = state;
1316
1317 if (!dsa)
1318 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1319
1320 si_pm4_bind_state(sctx, dsa, dsa);
1321
1322 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1323 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1324 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1325 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1326 }
1327
1328 if (old_dsa->alpha_func != dsa->alpha_func)
1329 sctx->do_update_shaders = true;
1330
1331 if (sctx->screen->dpbb_allowed &&
1332 ((old_dsa->depth_enabled != dsa->depth_enabled ||
1333 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1334 old_dsa->db_can_write != dsa->db_can_write)))
1335 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1336
1337 if (sctx->screen->has_out_of_order_rast &&
1338 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1339 sizeof(old_dsa->order_invariance))))
1340 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1341 }
1342
1343 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1344 {
1345 struct si_context *sctx = (struct si_context *)ctx;
1346
1347 if (sctx->queued.named.dsa == state)
1348 si_bind_dsa_state(ctx, sctx->noop_dsa);
1349
1350 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1351 }
1352
1353 static void *si_create_db_flush_dsa(struct si_context *sctx)
1354 {
1355 struct pipe_depth_stencil_alpha_state dsa = {};
1356
1357 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1358 }
1359
1360 /* DB RENDER STATE */
1361
1362 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1363 {
1364 struct si_context *sctx = (struct si_context*)ctx;
1365
1366 /* Pipeline stat & streamout queries. */
1367 if (enable) {
1368 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1369 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1370 } else {
1371 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1372 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1373 }
1374
1375 /* Occlusion queries. */
1376 if (sctx->occlusion_queries_disabled != !enable) {
1377 sctx->occlusion_queries_disabled = !enable;
1378 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1379 }
1380 }
1381
1382 void si_set_occlusion_query_state(struct si_context *sctx,
1383 bool old_perfect_enable)
1384 {
1385 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1386
1387 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1388
1389 if (perfect_enable != old_perfect_enable)
1390 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1391 }
1392
1393 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1394 {
1395 st->saved_compute = sctx->cs_shader_state.program;
1396
1397 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1398 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1399
1400 st->saved_ssbo_writable_mask = 0;
1401
1402 for (unsigned i = 0; i < 3; i++) {
1403 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1404 (1u << si_get_shaderbuf_slot(i)))
1405 st->saved_ssbo_writable_mask |= 1 << i;
1406 }
1407 }
1408
1409 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1410 {
1411 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1412
1413 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1414 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1415
1416 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1417 st->saved_ssbo_writable_mask);
1418 for (unsigned i = 0; i < 3; ++i)
1419 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1420 }
1421
1422 static void si_emit_db_render_state(struct si_context *sctx)
1423 {
1424 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1425 unsigned db_shader_control, db_render_control, db_count_control;
1426 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1427
1428 /* DB_RENDER_CONTROL */
1429 if (sctx->dbcb_depth_copy_enabled ||
1430 sctx->dbcb_stencil_copy_enabled) {
1431 db_render_control =
1432 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1433 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1434 S_028000_COPY_CENTROID(1) |
1435 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1436 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1437 db_render_control =
1438 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1439 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1440 } else {
1441 db_render_control =
1442 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1443 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1444 }
1445
1446 /* DB_COUNT_CONTROL (occlusion queries) */
1447 if (sctx->num_occlusion_queries > 0 &&
1448 !sctx->occlusion_queries_disabled) {
1449 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1450 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1451
1452 if (sctx->chip_class >= GFX7) {
1453 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1454
1455 /* Stoney doesn't increment occlusion query counters
1456 * if the sample rate is 16x. Use 8x sample rate instead.
1457 */
1458 if (sctx->family == CHIP_STONEY)
1459 log_sample_rate = MIN2(log_sample_rate, 3);
1460
1461 db_count_control =
1462 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1463 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1464 S_028004_SAMPLE_RATE(log_sample_rate) |
1465 S_028004_ZPASS_ENABLE(1) |
1466 S_028004_SLICE_EVEN_ENABLE(1) |
1467 S_028004_SLICE_ODD_ENABLE(1);
1468 } else {
1469 db_count_control =
1470 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1471 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1472 }
1473 } else {
1474 /* Disable occlusion queries. */
1475 if (sctx->chip_class >= GFX7) {
1476 db_count_control = 0;
1477 } else {
1478 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1479 }
1480 }
1481
1482 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1483 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1484 db_count_control);
1485
1486 /* DB_RENDER_OVERRIDE2 */
1487 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1488 SI_TRACKED_DB_RENDER_OVERRIDE2,
1489 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1490 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1491 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1492
1493 db_shader_control = sctx->ps_db_shader_control;
1494
1495 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1496 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1497 db_shader_control &= C_02880C_Z_ORDER;
1498 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1499 }
1500
1501 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1502 if (!rs->multisample_enable)
1503 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1504
1505 if (sctx->screen->info.has_rbplus &&
1506 !sctx->screen->info.rbplus_allowed)
1507 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1508
1509 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1510 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1511
1512 if (initial_cdw != sctx->gfx_cs->current.cdw)
1513 sctx->context_roll = true;
1514 }
1515
1516 /*
1517 * format translation
1518 */
1519 static uint32_t si_translate_colorformat(enum pipe_format format)
1520 {
1521 const struct util_format_description *desc = util_format_description(format);
1522 if (!desc)
1523 return V_028C70_COLOR_INVALID;
1524
1525 #define HAS_SIZE(x,y,z,w) \
1526 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1527 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1528
1529 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1530 return V_028C70_COLOR_10_11_11;
1531
1532 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1533 return V_028C70_COLOR_INVALID;
1534
1535 /* hw cannot support mixed formats (except depth/stencil, since
1536 * stencil is not written to). */
1537 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1538 return V_028C70_COLOR_INVALID;
1539
1540 switch (desc->nr_channels) {
1541 case 1:
1542 switch (desc->channel[0].size) {
1543 case 8:
1544 return V_028C70_COLOR_8;
1545 case 16:
1546 return V_028C70_COLOR_16;
1547 case 32:
1548 return V_028C70_COLOR_32;
1549 }
1550 break;
1551 case 2:
1552 if (desc->channel[0].size == desc->channel[1].size) {
1553 switch (desc->channel[0].size) {
1554 case 8:
1555 return V_028C70_COLOR_8_8;
1556 case 16:
1557 return V_028C70_COLOR_16_16;
1558 case 32:
1559 return V_028C70_COLOR_32_32;
1560 }
1561 } else if (HAS_SIZE(8,24,0,0)) {
1562 return V_028C70_COLOR_24_8;
1563 } else if (HAS_SIZE(24,8,0,0)) {
1564 return V_028C70_COLOR_8_24;
1565 }
1566 break;
1567 case 3:
1568 if (HAS_SIZE(5,6,5,0)) {
1569 return V_028C70_COLOR_5_6_5;
1570 } else if (HAS_SIZE(32,8,24,0)) {
1571 return V_028C70_COLOR_X24_8_32_FLOAT;
1572 }
1573 break;
1574 case 4:
1575 if (desc->channel[0].size == desc->channel[1].size &&
1576 desc->channel[0].size == desc->channel[2].size &&
1577 desc->channel[0].size == desc->channel[3].size) {
1578 switch (desc->channel[0].size) {
1579 case 4:
1580 return V_028C70_COLOR_4_4_4_4;
1581 case 8:
1582 return V_028C70_COLOR_8_8_8_8;
1583 case 16:
1584 return V_028C70_COLOR_16_16_16_16;
1585 case 32:
1586 return V_028C70_COLOR_32_32_32_32;
1587 }
1588 } else if (HAS_SIZE(5,5,5,1)) {
1589 return V_028C70_COLOR_1_5_5_5;
1590 } else if (HAS_SIZE(1,5,5,5)) {
1591 return V_028C70_COLOR_5_5_5_1;
1592 } else if (HAS_SIZE(10,10,10,2)) {
1593 return V_028C70_COLOR_2_10_10_10;
1594 }
1595 break;
1596 }
1597 return V_028C70_COLOR_INVALID;
1598 }
1599
1600 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1601 {
1602 if (SI_BIG_ENDIAN) {
1603 switch(colorformat) {
1604 /* 8-bit buffers. */
1605 case V_028C70_COLOR_8:
1606 return V_028C70_ENDIAN_NONE;
1607
1608 /* 16-bit buffers. */
1609 case V_028C70_COLOR_5_6_5:
1610 case V_028C70_COLOR_1_5_5_5:
1611 case V_028C70_COLOR_4_4_4_4:
1612 case V_028C70_COLOR_16:
1613 case V_028C70_COLOR_8_8:
1614 return V_028C70_ENDIAN_8IN16;
1615
1616 /* 32-bit buffers. */
1617 case V_028C70_COLOR_8_8_8_8:
1618 case V_028C70_COLOR_2_10_10_10:
1619 case V_028C70_COLOR_8_24:
1620 case V_028C70_COLOR_24_8:
1621 case V_028C70_COLOR_16_16:
1622 return V_028C70_ENDIAN_8IN32;
1623
1624 /* 64-bit buffers. */
1625 case V_028C70_COLOR_16_16_16_16:
1626 return V_028C70_ENDIAN_8IN16;
1627
1628 case V_028C70_COLOR_32_32:
1629 return V_028C70_ENDIAN_8IN32;
1630
1631 /* 128-bit buffers. */
1632 case V_028C70_COLOR_32_32_32_32:
1633 return V_028C70_ENDIAN_8IN32;
1634 default:
1635 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1636 }
1637 } else {
1638 return V_028C70_ENDIAN_NONE;
1639 }
1640 }
1641
1642 static uint32_t si_translate_dbformat(enum pipe_format format)
1643 {
1644 switch (format) {
1645 case PIPE_FORMAT_Z16_UNORM:
1646 return V_028040_Z_16;
1647 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1648 case PIPE_FORMAT_X8Z24_UNORM:
1649 case PIPE_FORMAT_Z24X8_UNORM:
1650 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1651 return V_028040_Z_24; /* deprecated on AMD GCN */
1652 case PIPE_FORMAT_Z32_FLOAT:
1653 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1654 return V_028040_Z_32_FLOAT;
1655 default:
1656 return V_028040_Z_INVALID;
1657 }
1658 }
1659
1660 /*
1661 * Texture translation
1662 */
1663
1664 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1665 enum pipe_format format,
1666 const struct util_format_description *desc,
1667 int first_non_void)
1668 {
1669 struct si_screen *sscreen = (struct si_screen*)screen;
1670 bool uniform = true;
1671 int i;
1672
1673 assert(sscreen->info.chip_class <= GFX9);
1674
1675 /* Colorspace (return non-RGB formats directly). */
1676 switch (desc->colorspace) {
1677 /* Depth stencil formats */
1678 case UTIL_FORMAT_COLORSPACE_ZS:
1679 switch (format) {
1680 case PIPE_FORMAT_Z16_UNORM:
1681 return V_008F14_IMG_DATA_FORMAT_16;
1682 case PIPE_FORMAT_X24S8_UINT:
1683 case PIPE_FORMAT_S8X24_UINT:
1684 /*
1685 * Implemented as an 8_8_8_8 data format to fix texture
1686 * gathers in stencil sampling. This affects at least
1687 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1688 */
1689 if (sscreen->info.chip_class <= GFX8)
1690 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1691
1692 if (format == PIPE_FORMAT_X24S8_UINT)
1693 return V_008F14_IMG_DATA_FORMAT_8_24;
1694 else
1695 return V_008F14_IMG_DATA_FORMAT_24_8;
1696 case PIPE_FORMAT_Z24X8_UNORM:
1697 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1698 return V_008F14_IMG_DATA_FORMAT_8_24;
1699 case PIPE_FORMAT_X8Z24_UNORM:
1700 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1701 return V_008F14_IMG_DATA_FORMAT_24_8;
1702 case PIPE_FORMAT_S8_UINT:
1703 return V_008F14_IMG_DATA_FORMAT_8;
1704 case PIPE_FORMAT_Z32_FLOAT:
1705 return V_008F14_IMG_DATA_FORMAT_32;
1706 case PIPE_FORMAT_X32_S8X24_UINT:
1707 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1708 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1709 default:
1710 goto out_unknown;
1711 }
1712
1713 case UTIL_FORMAT_COLORSPACE_YUV:
1714 goto out_unknown; /* TODO */
1715
1716 case UTIL_FORMAT_COLORSPACE_SRGB:
1717 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1718 goto out_unknown;
1719 break;
1720
1721 default:
1722 break;
1723 }
1724
1725 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1726 if (!sscreen->info.has_format_bc1_through_bc7)
1727 goto out_unknown;
1728
1729 switch (format) {
1730 case PIPE_FORMAT_RGTC1_SNORM:
1731 case PIPE_FORMAT_LATC1_SNORM:
1732 case PIPE_FORMAT_RGTC1_UNORM:
1733 case PIPE_FORMAT_LATC1_UNORM:
1734 return V_008F14_IMG_DATA_FORMAT_BC4;
1735 case PIPE_FORMAT_RGTC2_SNORM:
1736 case PIPE_FORMAT_LATC2_SNORM:
1737 case PIPE_FORMAT_RGTC2_UNORM:
1738 case PIPE_FORMAT_LATC2_UNORM:
1739 return V_008F14_IMG_DATA_FORMAT_BC5;
1740 default:
1741 goto out_unknown;
1742 }
1743 }
1744
1745 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1746 (sscreen->info.family == CHIP_STONEY ||
1747 sscreen->info.family == CHIP_VEGA10 ||
1748 sscreen->info.family == CHIP_RAVEN)) {
1749 switch (format) {
1750 case PIPE_FORMAT_ETC1_RGB8:
1751 case PIPE_FORMAT_ETC2_RGB8:
1752 case PIPE_FORMAT_ETC2_SRGB8:
1753 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1754 case PIPE_FORMAT_ETC2_RGB8A1:
1755 case PIPE_FORMAT_ETC2_SRGB8A1:
1756 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1757 case PIPE_FORMAT_ETC2_RGBA8:
1758 case PIPE_FORMAT_ETC2_SRGBA8:
1759 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1760 case PIPE_FORMAT_ETC2_R11_UNORM:
1761 case PIPE_FORMAT_ETC2_R11_SNORM:
1762 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1763 case PIPE_FORMAT_ETC2_RG11_UNORM:
1764 case PIPE_FORMAT_ETC2_RG11_SNORM:
1765 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1766 default:
1767 goto out_unknown;
1768 }
1769 }
1770
1771 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1772 if (!sscreen->info.has_format_bc1_through_bc7)
1773 goto out_unknown;
1774
1775 switch (format) {
1776 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1777 case PIPE_FORMAT_BPTC_SRGBA:
1778 return V_008F14_IMG_DATA_FORMAT_BC7;
1779 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1780 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1781 return V_008F14_IMG_DATA_FORMAT_BC6;
1782 default:
1783 goto out_unknown;
1784 }
1785 }
1786
1787 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1788 switch (format) {
1789 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1790 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1791 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1792 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1793 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1794 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1795 default:
1796 goto out_unknown;
1797 }
1798 }
1799
1800 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1801 if (!sscreen->info.has_format_bc1_through_bc7)
1802 goto out_unknown;
1803
1804 switch (format) {
1805 case PIPE_FORMAT_DXT1_RGB:
1806 case PIPE_FORMAT_DXT1_RGBA:
1807 case PIPE_FORMAT_DXT1_SRGB:
1808 case PIPE_FORMAT_DXT1_SRGBA:
1809 return V_008F14_IMG_DATA_FORMAT_BC1;
1810 case PIPE_FORMAT_DXT3_RGBA:
1811 case PIPE_FORMAT_DXT3_SRGBA:
1812 return V_008F14_IMG_DATA_FORMAT_BC2;
1813 case PIPE_FORMAT_DXT5_RGBA:
1814 case PIPE_FORMAT_DXT5_SRGBA:
1815 return V_008F14_IMG_DATA_FORMAT_BC3;
1816 default:
1817 goto out_unknown;
1818 }
1819 }
1820
1821 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1822 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1823 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1824 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1825 }
1826
1827 /* R8G8Bx_SNORM - TODO CxV8U8 */
1828
1829 /* hw cannot support mixed formats (except depth/stencil, since only
1830 * depth is read).*/
1831 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1832 goto out_unknown;
1833
1834 /* See whether the components are of the same size. */
1835 for (i = 1; i < desc->nr_channels; i++) {
1836 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1837 }
1838
1839 /* Non-uniform formats. */
1840 if (!uniform) {
1841 switch(desc->nr_channels) {
1842 case 3:
1843 if (desc->channel[0].size == 5 &&
1844 desc->channel[1].size == 6 &&
1845 desc->channel[2].size == 5) {
1846 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1847 }
1848 goto out_unknown;
1849 case 4:
1850 if (desc->channel[0].size == 5 &&
1851 desc->channel[1].size == 5 &&
1852 desc->channel[2].size == 5 &&
1853 desc->channel[3].size == 1) {
1854 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1855 }
1856 if (desc->channel[0].size == 1 &&
1857 desc->channel[1].size == 5 &&
1858 desc->channel[2].size == 5 &&
1859 desc->channel[3].size == 5) {
1860 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1861 }
1862 if (desc->channel[0].size == 10 &&
1863 desc->channel[1].size == 10 &&
1864 desc->channel[2].size == 10 &&
1865 desc->channel[3].size == 2) {
1866 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1867 }
1868 goto out_unknown;
1869 }
1870 goto out_unknown;
1871 }
1872
1873 if (first_non_void < 0 || first_non_void > 3)
1874 goto out_unknown;
1875
1876 /* uniform formats */
1877 switch (desc->channel[first_non_void].size) {
1878 case 4:
1879 switch (desc->nr_channels) {
1880 #if 0 /* Not supported for render targets */
1881 case 2:
1882 return V_008F14_IMG_DATA_FORMAT_4_4;
1883 #endif
1884 case 4:
1885 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1886 }
1887 break;
1888 case 8:
1889 switch (desc->nr_channels) {
1890 case 1:
1891 return V_008F14_IMG_DATA_FORMAT_8;
1892 case 2:
1893 return V_008F14_IMG_DATA_FORMAT_8_8;
1894 case 4:
1895 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1896 }
1897 break;
1898 case 16:
1899 switch (desc->nr_channels) {
1900 case 1:
1901 return V_008F14_IMG_DATA_FORMAT_16;
1902 case 2:
1903 return V_008F14_IMG_DATA_FORMAT_16_16;
1904 case 4:
1905 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1906 }
1907 break;
1908 case 32:
1909 switch (desc->nr_channels) {
1910 case 1:
1911 return V_008F14_IMG_DATA_FORMAT_32;
1912 case 2:
1913 return V_008F14_IMG_DATA_FORMAT_32_32;
1914 #if 0 /* Not supported for render targets */
1915 case 3:
1916 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1917 #endif
1918 case 4:
1919 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1920 }
1921 }
1922
1923 out_unknown:
1924 return ~0;
1925 }
1926
1927 static unsigned si_tex_wrap(unsigned wrap)
1928 {
1929 switch (wrap) {
1930 default:
1931 case PIPE_TEX_WRAP_REPEAT:
1932 return V_008F30_SQ_TEX_WRAP;
1933 case PIPE_TEX_WRAP_CLAMP:
1934 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1935 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1936 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1937 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1938 return V_008F30_SQ_TEX_CLAMP_BORDER;
1939 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1940 return V_008F30_SQ_TEX_MIRROR;
1941 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1942 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1943 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1944 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1945 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1946 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1947 }
1948 }
1949
1950 static unsigned si_tex_mipfilter(unsigned filter)
1951 {
1952 switch (filter) {
1953 case PIPE_TEX_MIPFILTER_NEAREST:
1954 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1955 case PIPE_TEX_MIPFILTER_LINEAR:
1956 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1957 default:
1958 case PIPE_TEX_MIPFILTER_NONE:
1959 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1960 }
1961 }
1962
1963 static unsigned si_tex_compare(unsigned compare)
1964 {
1965 switch (compare) {
1966 default:
1967 case PIPE_FUNC_NEVER:
1968 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1969 case PIPE_FUNC_LESS:
1970 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1971 case PIPE_FUNC_EQUAL:
1972 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1973 case PIPE_FUNC_LEQUAL:
1974 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1975 case PIPE_FUNC_GREATER:
1976 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1977 case PIPE_FUNC_NOTEQUAL:
1978 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1979 case PIPE_FUNC_GEQUAL:
1980 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1981 case PIPE_FUNC_ALWAYS:
1982 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1983 }
1984 }
1985
1986 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1987 unsigned view_target, unsigned nr_samples)
1988 {
1989 unsigned res_target = tex->buffer.b.b.target;
1990
1991 if (view_target == PIPE_TEXTURE_CUBE ||
1992 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1993 res_target = view_target;
1994 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1995 else if (res_target == PIPE_TEXTURE_CUBE ||
1996 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1997 res_target = PIPE_TEXTURE_2D_ARRAY;
1998
1999 /* GFX9 allocates 1D textures as 2D. */
2000 if ((res_target == PIPE_TEXTURE_1D ||
2001 res_target == PIPE_TEXTURE_1D_ARRAY) &&
2002 sscreen->info.chip_class == GFX9 &&
2003 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
2004 if (res_target == PIPE_TEXTURE_1D)
2005 res_target = PIPE_TEXTURE_2D;
2006 else
2007 res_target = PIPE_TEXTURE_2D_ARRAY;
2008 }
2009
2010 switch (res_target) {
2011 default:
2012 case PIPE_TEXTURE_1D:
2013 return V_008F1C_SQ_RSRC_IMG_1D;
2014 case PIPE_TEXTURE_1D_ARRAY:
2015 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2016 case PIPE_TEXTURE_2D:
2017 case PIPE_TEXTURE_RECT:
2018 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
2019 V_008F1C_SQ_RSRC_IMG_2D;
2020 case PIPE_TEXTURE_2D_ARRAY:
2021 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
2022 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2023 case PIPE_TEXTURE_3D:
2024 return V_008F1C_SQ_RSRC_IMG_3D;
2025 case PIPE_TEXTURE_CUBE:
2026 case PIPE_TEXTURE_CUBE_ARRAY:
2027 return V_008F1C_SQ_RSRC_IMG_CUBE;
2028 }
2029 }
2030
2031 /*
2032 * Format support testing
2033 */
2034
2035 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2036 {
2037 struct si_screen *sscreen = (struct si_screen *)screen;
2038
2039 if (sscreen->info.chip_class >= GFX10) {
2040 const struct gfx10_format *fmt = &gfx10_format_table[format];
2041 if (!fmt->img_format || fmt->buffers_only)
2042 return false;
2043 return true;
2044 }
2045
2046 const struct util_format_description *desc = util_format_description(format);
2047 if (!desc)
2048 return false;
2049
2050 return si_translate_texformat(screen, format, desc,
2051 util_format_get_first_non_void_channel(format)) != ~0U;
2052 }
2053
2054 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2055 const struct util_format_description *desc,
2056 int first_non_void)
2057 {
2058 int i;
2059
2060 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2061
2062 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2063 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2064
2065 assert(first_non_void >= 0);
2066
2067 if (desc->nr_channels == 4 &&
2068 desc->channel[0].size == 10 &&
2069 desc->channel[1].size == 10 &&
2070 desc->channel[2].size == 10 &&
2071 desc->channel[3].size == 2)
2072 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2073
2074 /* See whether the components are of the same size. */
2075 for (i = 0; i < desc->nr_channels; i++) {
2076 if (desc->channel[first_non_void].size != desc->channel[i].size)
2077 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2078 }
2079
2080 switch (desc->channel[first_non_void].size) {
2081 case 8:
2082 switch (desc->nr_channels) {
2083 case 1:
2084 case 3: /* 3 loads */
2085 return V_008F0C_BUF_DATA_FORMAT_8;
2086 case 2:
2087 return V_008F0C_BUF_DATA_FORMAT_8_8;
2088 case 4:
2089 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2090 }
2091 break;
2092 case 16:
2093 switch (desc->nr_channels) {
2094 case 1:
2095 case 3: /* 3 loads */
2096 return V_008F0C_BUF_DATA_FORMAT_16;
2097 case 2:
2098 return V_008F0C_BUF_DATA_FORMAT_16_16;
2099 case 4:
2100 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2101 }
2102 break;
2103 case 32:
2104 switch (desc->nr_channels) {
2105 case 1:
2106 return V_008F0C_BUF_DATA_FORMAT_32;
2107 case 2:
2108 return V_008F0C_BUF_DATA_FORMAT_32_32;
2109 case 3:
2110 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2111 case 4:
2112 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2113 }
2114 break;
2115 case 64:
2116 /* Legacy double formats. */
2117 switch (desc->nr_channels) {
2118 case 1: /* 1 load */
2119 return V_008F0C_BUF_DATA_FORMAT_32_32;
2120 case 2: /* 1 load */
2121 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2122 case 3: /* 3 loads */
2123 return V_008F0C_BUF_DATA_FORMAT_32_32;
2124 case 4: /* 2 loads */
2125 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2126 }
2127 break;
2128 }
2129
2130 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2131 }
2132
2133 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2134 const struct util_format_description *desc,
2135 int first_non_void)
2136 {
2137 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2138
2139 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2140 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2141
2142 assert(first_non_void >= 0);
2143
2144 switch (desc->channel[first_non_void].type) {
2145 case UTIL_FORMAT_TYPE_SIGNED:
2146 case UTIL_FORMAT_TYPE_FIXED:
2147 if (desc->channel[first_non_void].size >= 32 ||
2148 desc->channel[first_non_void].pure_integer)
2149 return V_008F0C_BUF_NUM_FORMAT_SINT;
2150 else if (desc->channel[first_non_void].normalized)
2151 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2152 else
2153 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2154 break;
2155 case UTIL_FORMAT_TYPE_UNSIGNED:
2156 if (desc->channel[first_non_void].size >= 32 ||
2157 desc->channel[first_non_void].pure_integer)
2158 return V_008F0C_BUF_NUM_FORMAT_UINT;
2159 else if (desc->channel[first_non_void].normalized)
2160 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2161 else
2162 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2163 break;
2164 case UTIL_FORMAT_TYPE_FLOAT:
2165 default:
2166 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2167 }
2168 }
2169
2170 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2171 enum pipe_format format,
2172 unsigned usage)
2173 {
2174 struct si_screen *sscreen = (struct si_screen *)screen;
2175 const struct util_format_description *desc;
2176 int first_non_void;
2177 unsigned data_format;
2178
2179 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2180 PIPE_BIND_SAMPLER_VIEW |
2181 PIPE_BIND_VERTEX_BUFFER)) == 0);
2182
2183 desc = util_format_description(format);
2184 if (!desc)
2185 return 0;
2186
2187 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2188 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2189 * for read-only access (with caveats surrounding bounds checks), but
2190 * obviously fails for write access which we have to implement for
2191 * shader images. Luckily, OpenGL doesn't expect this to be supported
2192 * anyway, and so the only impact is on PBO uploads / downloads, which
2193 * shouldn't be expected to be fast for GL_RGB anyway.
2194 */
2195 if (desc->block.bits == 3 * 8 ||
2196 desc->block.bits == 3 * 16) {
2197 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2198 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2199 if (!usage)
2200 return 0;
2201 }
2202 }
2203
2204 if (sscreen->info.chip_class >= GFX10) {
2205 const struct gfx10_format *fmt = &gfx10_format_table[format];
2206 if (!fmt->img_format || fmt->img_format >= 128)
2207 return 0;
2208 return usage;
2209 }
2210
2211 first_non_void = util_format_get_first_non_void_channel(format);
2212 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2213 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2214 return 0;
2215
2216 return usage;
2217 }
2218
2219 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2220 {
2221 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2222 si_translate_colorswap(format, false) != ~0U;
2223 }
2224
2225 static bool si_is_zs_format_supported(enum pipe_format format)
2226 {
2227 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2228 }
2229
2230 static bool si_is_format_supported(struct pipe_screen *screen,
2231 enum pipe_format format,
2232 enum pipe_texture_target target,
2233 unsigned sample_count,
2234 unsigned storage_sample_count,
2235 unsigned usage)
2236 {
2237 struct si_screen *sscreen = (struct si_screen *)screen;
2238 unsigned retval = 0;
2239
2240 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2241 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2242 return false;
2243 }
2244
2245 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2246 return false;
2247
2248 if (sample_count > 1) {
2249 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2250 return false;
2251
2252 /* Only power-of-two sample counts are supported. */
2253 if (!util_is_power_of_two_or_zero(sample_count) ||
2254 !util_is_power_of_two_or_zero(storage_sample_count))
2255 return false;
2256
2257 /* MSAA support without framebuffer attachments. */
2258 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2259 return true;
2260
2261 if (!sscreen->info.has_eqaa_surface_allocator ||
2262 util_format_is_depth_or_stencil(format)) {
2263 /* Color without EQAA or depth/stencil. */
2264 if (sample_count > 8 ||
2265 sample_count != storage_sample_count)
2266 return false;
2267 } else {
2268 /* Color with EQAA. */
2269 if (sample_count > 16 ||
2270 storage_sample_count > 8)
2271 return false;
2272 }
2273 }
2274
2275 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2276 PIPE_BIND_SHADER_IMAGE)) {
2277 if (target == PIPE_BUFFER) {
2278 retval |= si_is_vertex_format_supported(
2279 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2280 PIPE_BIND_SHADER_IMAGE));
2281 } else {
2282 if (si_is_sampler_format_supported(screen, format))
2283 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2284 PIPE_BIND_SHADER_IMAGE);
2285 }
2286 }
2287
2288 if ((usage & (PIPE_BIND_RENDER_TARGET |
2289 PIPE_BIND_DISPLAY_TARGET |
2290 PIPE_BIND_SCANOUT |
2291 PIPE_BIND_SHARED |
2292 PIPE_BIND_BLENDABLE)) &&
2293 si_is_colorbuffer_format_supported(format)) {
2294 retval |= usage &
2295 (PIPE_BIND_RENDER_TARGET |
2296 PIPE_BIND_DISPLAY_TARGET |
2297 PIPE_BIND_SCANOUT |
2298 PIPE_BIND_SHARED);
2299 if (!util_format_is_pure_integer(format) &&
2300 !util_format_is_depth_or_stencil(format))
2301 retval |= usage & PIPE_BIND_BLENDABLE;
2302 }
2303
2304 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2305 si_is_zs_format_supported(format)) {
2306 retval |= PIPE_BIND_DEPTH_STENCIL;
2307 }
2308
2309 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2310 retval |= si_is_vertex_format_supported(screen, format,
2311 PIPE_BIND_VERTEX_BUFFER);
2312 }
2313
2314 if ((usage & PIPE_BIND_LINEAR) &&
2315 !util_format_is_compressed(format) &&
2316 !(usage & PIPE_BIND_DEPTH_STENCIL))
2317 retval |= PIPE_BIND_LINEAR;
2318
2319 return retval == usage;
2320 }
2321
2322 /*
2323 * framebuffer handling
2324 */
2325
2326 static void si_choose_spi_color_formats(struct si_surface *surf,
2327 unsigned format, unsigned swap,
2328 unsigned ntype, bool is_depth)
2329 {
2330 /* Alpha is needed for alpha-to-coverage.
2331 * Blending may be with or without alpha.
2332 */
2333 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2334 unsigned alpha = 0; /* exports alpha, but may not support blending */
2335 unsigned blend = 0; /* supports blending, but may not export alpha */
2336 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2337
2338 /* Choose the SPI color formats. These are required values for RB+.
2339 * Other chips have multiple choices, though they are not necessarily better.
2340 */
2341 switch (format) {
2342 case V_028C70_COLOR_5_6_5:
2343 case V_028C70_COLOR_1_5_5_5:
2344 case V_028C70_COLOR_5_5_5_1:
2345 case V_028C70_COLOR_4_4_4_4:
2346 case V_028C70_COLOR_10_11_11:
2347 case V_028C70_COLOR_11_11_10:
2348 case V_028C70_COLOR_8:
2349 case V_028C70_COLOR_8_8:
2350 case V_028C70_COLOR_8_8_8_8:
2351 case V_028C70_COLOR_10_10_10_2:
2352 case V_028C70_COLOR_2_10_10_10:
2353 if (ntype == V_028C70_NUMBER_UINT)
2354 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2355 else if (ntype == V_028C70_NUMBER_SINT)
2356 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2357 else
2358 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2359 break;
2360
2361 case V_028C70_COLOR_16:
2362 case V_028C70_COLOR_16_16:
2363 case V_028C70_COLOR_16_16_16_16:
2364 if (ntype == V_028C70_NUMBER_UNORM ||
2365 ntype == V_028C70_NUMBER_SNORM) {
2366 /* UNORM16 and SNORM16 don't support blending */
2367 if (ntype == V_028C70_NUMBER_UNORM)
2368 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2369 else
2370 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2371
2372 /* Use 32 bits per channel for blending. */
2373 if (format == V_028C70_COLOR_16) {
2374 if (swap == V_028C70_SWAP_STD) { /* R */
2375 blend = V_028714_SPI_SHADER_32_R;
2376 blend_alpha = V_028714_SPI_SHADER_32_AR;
2377 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2378 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2379 else
2380 assert(0);
2381 } else if (format == V_028C70_COLOR_16_16) {
2382 if (swap == V_028C70_SWAP_STD) { /* RG */
2383 blend = V_028714_SPI_SHADER_32_GR;
2384 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2385 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2386 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2387 else
2388 assert(0);
2389 } else /* 16_16_16_16 */
2390 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2391 } else if (ntype == V_028C70_NUMBER_UINT)
2392 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2393 else if (ntype == V_028C70_NUMBER_SINT)
2394 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2395 else if (ntype == V_028C70_NUMBER_FLOAT)
2396 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2397 else
2398 assert(0);
2399 break;
2400
2401 case V_028C70_COLOR_32:
2402 if (swap == V_028C70_SWAP_STD) { /* R */
2403 blend = normal = V_028714_SPI_SHADER_32_R;
2404 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2405 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2406 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2407 else
2408 assert(0);
2409 break;
2410
2411 case V_028C70_COLOR_32_32:
2412 if (swap == V_028C70_SWAP_STD) { /* RG */
2413 blend = normal = V_028714_SPI_SHADER_32_GR;
2414 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2415 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2416 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2417 else
2418 assert(0);
2419 break;
2420
2421 case V_028C70_COLOR_32_32_32_32:
2422 case V_028C70_COLOR_8_24:
2423 case V_028C70_COLOR_24_8:
2424 case V_028C70_COLOR_X24_8_32_FLOAT:
2425 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2426 break;
2427
2428 default:
2429 assert(0);
2430 return;
2431 }
2432
2433 /* The DB->CB copy needs 32_ABGR. */
2434 if (is_depth)
2435 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2436
2437 surf->spi_shader_col_format = normal;
2438 surf->spi_shader_col_format_alpha = alpha;
2439 surf->spi_shader_col_format_blend = blend;
2440 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2441 }
2442
2443 static void si_initialize_color_surface(struct si_context *sctx,
2444 struct si_surface *surf)
2445 {
2446 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2447 unsigned color_info, color_attrib;
2448 unsigned format, swap, ntype, endian;
2449 const struct util_format_description *desc;
2450 int firstchan;
2451 unsigned blend_clamp = 0, blend_bypass = 0;
2452
2453 desc = util_format_description(surf->base.format);
2454 for (firstchan = 0; firstchan < 4; firstchan++) {
2455 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2456 break;
2457 }
2458 }
2459 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2460 ntype = V_028C70_NUMBER_FLOAT;
2461 } else {
2462 ntype = V_028C70_NUMBER_UNORM;
2463 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2464 ntype = V_028C70_NUMBER_SRGB;
2465 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2466 if (desc->channel[firstchan].pure_integer) {
2467 ntype = V_028C70_NUMBER_SINT;
2468 } else {
2469 assert(desc->channel[firstchan].normalized);
2470 ntype = V_028C70_NUMBER_SNORM;
2471 }
2472 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2473 if (desc->channel[firstchan].pure_integer) {
2474 ntype = V_028C70_NUMBER_UINT;
2475 } else {
2476 assert(desc->channel[firstchan].normalized);
2477 ntype = V_028C70_NUMBER_UNORM;
2478 }
2479 }
2480 }
2481
2482 format = si_translate_colorformat(surf->base.format);
2483 if (format == V_028C70_COLOR_INVALID) {
2484 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2485 }
2486 assert(format != V_028C70_COLOR_INVALID);
2487 swap = si_translate_colorswap(surf->base.format, false);
2488 endian = si_colorformat_endian_swap(format);
2489
2490 /* blend clamp should be set for all NORM/SRGB types */
2491 if (ntype == V_028C70_NUMBER_UNORM ||
2492 ntype == V_028C70_NUMBER_SNORM ||
2493 ntype == V_028C70_NUMBER_SRGB)
2494 blend_clamp = 1;
2495
2496 /* set blend bypass according to docs if SINT/UINT or
2497 8/24 COLOR variants */
2498 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2499 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2500 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2501 blend_clamp = 0;
2502 blend_bypass = 1;
2503 }
2504
2505 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2506 if (format == V_028C70_COLOR_8 ||
2507 format == V_028C70_COLOR_8_8 ||
2508 format == V_028C70_COLOR_8_8_8_8)
2509 surf->color_is_int8 = true;
2510 else if (format == V_028C70_COLOR_10_10_10_2 ||
2511 format == V_028C70_COLOR_2_10_10_10)
2512 surf->color_is_int10 = true;
2513 }
2514
2515 color_info = S_028C70_FORMAT(format) |
2516 S_028C70_COMP_SWAP(swap) |
2517 S_028C70_BLEND_CLAMP(blend_clamp) |
2518 S_028C70_BLEND_BYPASS(blend_bypass) |
2519 S_028C70_SIMPLE_FLOAT(1) |
2520 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2521 ntype != V_028C70_NUMBER_SNORM &&
2522 ntype != V_028C70_NUMBER_SRGB &&
2523 format != V_028C70_COLOR_8_24 &&
2524 format != V_028C70_COLOR_24_8) |
2525 S_028C70_NUMBER_TYPE(ntype) |
2526 S_028C70_ENDIAN(endian);
2527
2528 /* Intensity is implemented as Red, so treat it that way. */
2529 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2530 util_format_is_intensity(surf->base.format));
2531
2532 if (tex->buffer.b.b.nr_samples > 1) {
2533 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2534 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2535
2536 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2537 S_028C74_NUM_FRAGMENTS(log_fragments);
2538
2539 if (tex->surface.fmask_offset) {
2540 color_info |= S_028C70_COMPRESSION(1);
2541 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2542
2543 if (sctx->chip_class == GFX6) {
2544 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2545 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2546 }
2547 }
2548 }
2549
2550 if (sctx->chip_class >= GFX10) {
2551 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2552
2553 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2554 64 for APU because all of our APUs to date use DIMMs which have
2555 a request granularity size of 64B while all other chips have a
2556 32B request size */
2557 if (!sctx->screen->info.has_dedicated_vram)
2558 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2559
2560 surf->cb_dcc_control =
2561 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2562 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
2563 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2564 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2565 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2566 } else if (sctx->chip_class >= GFX8) {
2567 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2568 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2569
2570 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2571 64 for APU because all of our APUs to date use DIMMs which have
2572 a request granularity size of 64B while all other chips have a
2573 32B request size */
2574 if (!sctx->screen->info.has_dedicated_vram)
2575 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2576
2577 if (tex->buffer.b.b.nr_storage_samples > 1) {
2578 if (tex->surface.bpe == 1)
2579 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2580 else if (tex->surface.bpe == 2)
2581 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2582 }
2583
2584 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2585 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2586 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2587 }
2588
2589 /* This must be set for fast clear to work without FMASK. */
2590 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2591 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2592 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2593 }
2594
2595 /* GFX10 field has the same base shift as the GFX6 field */
2596 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2597 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2598 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2599
2600 if (sctx->chip_class >= GFX10) {
2601 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2602
2603 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2604 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2605 S_028EE0_RESOURCE_LEVEL(1);
2606 } else if (sctx->chip_class == GFX9) {
2607 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2608 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2609 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2610 }
2611
2612 if (sctx->chip_class >= GFX9) {
2613 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2614 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2615 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2616 }
2617
2618 surf->cb_color_view = color_view;
2619 surf->cb_color_info = color_info;
2620 surf->cb_color_attrib = color_attrib;
2621
2622 /* Determine pixel shader export format */
2623 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2624
2625 surf->color_initialized = true;
2626 }
2627
2628 static void si_init_depth_surface(struct si_context *sctx,
2629 struct si_surface *surf)
2630 {
2631 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2632 unsigned level = surf->base.u.tex.level;
2633 unsigned format, stencil_format;
2634 uint32_t z_info, s_info;
2635
2636 format = si_translate_dbformat(tex->db_render_format);
2637 stencil_format = tex->surface.has_stencil ?
2638 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2639
2640 assert(format != V_028040_Z_INVALID);
2641 if (format == V_028040_Z_INVALID)
2642 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2643
2644 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2645 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2646 surf->db_htile_data_base = 0;
2647 surf->db_htile_surface = 0;
2648
2649 if (sctx->chip_class >= GFX10) {
2650 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2651 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2652 }
2653
2654 if (sctx->chip_class >= GFX9) {
2655 assert(tex->surface.u.gfx9.surf_offset == 0);
2656 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2657 surf->db_stencil_base = (tex->buffer.gpu_address +
2658 tex->surface.u.gfx9.stencil_offset) >> 8;
2659 z_info = S_028038_FORMAT(format) |
2660 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2661 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2662 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2663 s_info = S_02803C_FORMAT(stencil_format) |
2664 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2665
2666 if (sctx->chip_class == GFX9) {
2667 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2668 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2669 }
2670 surf->db_depth_view |= S_028008_MIPID(level);
2671 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2672 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2673
2674 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2675 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2676 S_028038_ALLOW_EXPCLEAR(1);
2677
2678 if (tex->tc_compatible_htile) {
2679 unsigned max_zplanes = 4;
2680
2681 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2682 tex->buffer.b.b.nr_samples > 1)
2683 max_zplanes = 2;
2684
2685 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
2686
2687 if (sctx->chip_class >= GFX10) {
2688 z_info |= S_028040_ITERATE_FLUSH(1);
2689 s_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled);
2690 } else {
2691 z_info |= S_028038_ITERATE_FLUSH(1);
2692 s_info |= S_02803C_ITERATE_FLUSH(1);
2693 }
2694 }
2695
2696 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2697 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2698 * See that for explanation.
2699 */
2700 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2701 } else {
2702 /* Use all HTILE for depth if there's no stencil. */
2703 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2704 }
2705
2706 surf->db_htile_data_base = (tex->buffer.gpu_address +
2707 tex->surface.htile_offset) >> 8;
2708 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2709 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
2710 if (sctx->chip_class == GFX9) {
2711 surf->db_htile_surface |=
2712 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2713 }
2714 }
2715 } else {
2716 /* GFX6-GFX8 */
2717 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2718
2719 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2720
2721 surf->db_depth_base = (tex->buffer.gpu_address +
2722 tex->surface.u.legacy.level[level].offset) >> 8;
2723 surf->db_stencil_base = (tex->buffer.gpu_address +
2724 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2725
2726 z_info = S_028040_FORMAT(format) |
2727 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2728 s_info = S_028044_FORMAT(stencil_format);
2729 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2730
2731 if (sctx->chip_class >= GFX7) {
2732 struct radeon_info *info = &sctx->screen->info;
2733 unsigned index = tex->surface.u.legacy.tiling_index[level];
2734 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2735 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2736 unsigned tile_mode = info->si_tile_mode_array[index];
2737 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2738 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2739
2740 surf->db_depth_info |=
2741 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2742 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2743 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2744 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2745 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2746 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2747 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2748 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2749 } else {
2750 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2751 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2752 tile_mode_index = si_tile_mode_index(tex, level, true);
2753 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2754 }
2755
2756 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2757 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2758 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2759 levelinfo->nblk_y) / 64 - 1);
2760
2761 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2762 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2763 S_028040_ALLOW_EXPCLEAR(1);
2764
2765 if (tex->surface.has_stencil) {
2766 /* Workaround: For a not yet understood reason, the
2767 * combination of MSAA, fast stencil clear and stencil
2768 * decompress messes with subsequent stencil buffer
2769 * uses. Problem was reproduced on Verde, Bonaire,
2770 * Tonga, and Carrizo.
2771 *
2772 * Disabling EXPCLEAR works around the problem.
2773 *
2774 * Check piglit's arb_texture_multisample-stencil-clear
2775 * test if you want to try changing this.
2776 */
2777 if (tex->buffer.b.b.nr_samples <= 1)
2778 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2779 } else if (!tex->tc_compatible_htile) {
2780 /* Use all of the htile_buffer for depth if there's no stencil.
2781 * This must not be set when TC-compatible HTILE is enabled
2782 * due to a hw bug.
2783 */
2784 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2785 }
2786
2787 surf->db_htile_data_base = (tex->buffer.gpu_address +
2788 tex->surface.htile_offset) >> 8;
2789 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2790
2791 if (tex->tc_compatible_htile) {
2792 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2793
2794 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2795 if (tex->buffer.b.b.nr_samples <= 1)
2796 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2797 else if (tex->buffer.b.b.nr_samples <= 4)
2798 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2799 else
2800 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2801 }
2802 }
2803 }
2804
2805 surf->db_z_info = z_info;
2806 surf->db_stencil_info = s_info;
2807
2808 surf->depth_initialized = true;
2809 }
2810
2811 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2812 {
2813 if (sctx->decompression_enabled)
2814 return;
2815
2816 if (sctx->framebuffer.state.zsbuf) {
2817 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2818 struct si_texture *tex = (struct si_texture *)surf->texture;
2819
2820 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2821
2822 if (tex->surface.has_stencil)
2823 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2824 }
2825
2826 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2827 while (compressed_cb_mask) {
2828 unsigned i = u_bit_scan(&compressed_cb_mask);
2829 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2830 struct si_texture *tex = (struct si_texture*)surf->texture;
2831
2832 if (tex->surface.fmask_offset) {
2833 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2834 tex->fmask_is_identity = false;
2835 }
2836 if (tex->dcc_gather_statistics)
2837 tex->separate_dcc_dirty = true;
2838 }
2839 }
2840
2841 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2842 {
2843 for (int i = 0; i < state->nr_cbufs; ++i) {
2844 struct si_surface *surf = NULL;
2845 struct si_texture *tex;
2846
2847 if (!state->cbufs[i])
2848 continue;
2849 surf = (struct si_surface*)state->cbufs[i];
2850 tex = (struct si_texture*)surf->base.texture;
2851
2852 p_atomic_dec(&tex->framebuffers_bound);
2853 }
2854 }
2855
2856 static void si_set_framebuffer_state(struct pipe_context *ctx,
2857 const struct pipe_framebuffer_state *state)
2858 {
2859 struct si_context *sctx = (struct si_context *)ctx;
2860 struct si_surface *surf = NULL;
2861 struct si_texture *tex;
2862 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2863 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2864 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2865 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2866 bool old_has_stencil =
2867 old_has_zsbuf &&
2868 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2869 bool unbound = false;
2870 int i;
2871
2872 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2873 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2874 * We could implement the full workaround here, but it's a useless case.
2875 */
2876 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2877 unreachable("the framebuffer shouldn't have zero area");
2878 return;
2879 }
2880
2881 si_update_fb_dirtiness_after_rendering(sctx);
2882
2883 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2884 if (!sctx->framebuffer.state.cbufs[i])
2885 continue;
2886
2887 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2888 if (tex->dcc_gather_statistics)
2889 vi_separate_dcc_stop_query(sctx, tex);
2890 }
2891
2892 /* Disable DCC if the formats are incompatible. */
2893 for (i = 0; i < state->nr_cbufs; i++) {
2894 if (!state->cbufs[i])
2895 continue;
2896
2897 surf = (struct si_surface*)state->cbufs[i];
2898 tex = (struct si_texture*)surf->base.texture;
2899
2900 if (!surf->dcc_incompatible)
2901 continue;
2902
2903 /* Since the DCC decompression calls back into set_framebuffer-
2904 * _state, we need to unbind the framebuffer, so that
2905 * vi_separate_dcc_stop_query isn't called twice with the same
2906 * color buffer.
2907 */
2908 if (!unbound) {
2909 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2910 unbound = true;
2911 }
2912
2913 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2914 if (!si_texture_disable_dcc(sctx, tex))
2915 si_decompress_dcc(sctx, tex);
2916
2917 surf->dcc_incompatible = false;
2918 }
2919
2920 /* Only flush TC when changing the framebuffer state, because
2921 * the only client not using TC that can change textures is
2922 * the framebuffer.
2923 *
2924 * Wait for compute shaders because of possible transitions:
2925 * - FB write -> shader read
2926 * - shader write -> FB read
2927 *
2928 * DB caches are flushed on demand (using si_decompress_textures).
2929 *
2930 * When MSAA is enabled, CB and TC caches are flushed on demand
2931 * (after FMASK decompression). Shader write -> FB read transitions
2932 * cannot happen for MSAA textures, because MSAA shader images are
2933 * not supported.
2934 *
2935 * Only flush and wait for CB if there is actually a bound color buffer.
2936 */
2937 if (sctx->framebuffer.uncompressed_cb_mask) {
2938 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2939 sctx->framebuffer.CB_has_shader_readable_metadata,
2940 sctx->framebuffer.all_DCC_pipe_aligned);
2941 }
2942
2943 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2944
2945 /* u_blitter doesn't invoke depth decompression when it does multiple
2946 * blits in a row, but the only case when it matters for DB is when
2947 * doing generate_mipmap. So here we flush DB manually between
2948 * individual generate_mipmap blits.
2949 * Note that lower mipmap levels aren't compressed.
2950 */
2951 if (sctx->generate_mipmap_for_depth) {
2952 si_make_DB_shader_coherent(sctx, 1, false,
2953 sctx->framebuffer.DB_has_shader_readable_metadata);
2954 } else if (sctx->chip_class == GFX9) {
2955 /* It appears that DB metadata "leaks" in a sequence of:
2956 * - depth clear
2957 * - DCC decompress for shader image writes (with DB disabled)
2958 * - render with DEPTH_BEFORE_SHADER=1
2959 * Flushing DB metadata works around the problem.
2960 */
2961 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2962 }
2963
2964 /* Take the maximum of the old and new count. If the new count is lower,
2965 * dirtying is needed to disable the unbound colorbuffers.
2966 */
2967 sctx->framebuffer.dirty_cbufs |=
2968 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2969 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2970
2971 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2972 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2973
2974 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2975 sctx->framebuffer.spi_shader_col_format = 0;
2976 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2977 sctx->framebuffer.spi_shader_col_format_blend = 0;
2978 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2979 sctx->framebuffer.color_is_int8 = 0;
2980 sctx->framebuffer.color_is_int10 = 0;
2981
2982 sctx->framebuffer.compressed_cb_mask = 0;
2983 sctx->framebuffer.uncompressed_cb_mask = 0;
2984 sctx->framebuffer.displayable_dcc_cb_mask = 0;
2985 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2986 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2987 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2988 sctx->framebuffer.any_dst_linear = false;
2989 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2990 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2991 sctx->framebuffer.all_DCC_pipe_aligned = true;
2992 sctx->framebuffer.min_bytes_per_pixel = 0;
2993
2994 for (i = 0; i < state->nr_cbufs; i++) {
2995 if (!state->cbufs[i])
2996 continue;
2997
2998 surf = (struct si_surface*)state->cbufs[i];
2999 tex = (struct si_texture*)surf->base.texture;
3000
3001 if (!surf->color_initialized) {
3002 si_initialize_color_surface(sctx, surf);
3003 }
3004
3005 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
3006 sctx->framebuffer.spi_shader_col_format |=
3007 surf->spi_shader_col_format << (i * 4);
3008 sctx->framebuffer.spi_shader_col_format_alpha |=
3009 surf->spi_shader_col_format_alpha << (i * 4);
3010 sctx->framebuffer.spi_shader_col_format_blend |=
3011 surf->spi_shader_col_format_blend << (i * 4);
3012 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
3013 surf->spi_shader_col_format_blend_alpha << (i * 4);
3014
3015 if (surf->color_is_int8)
3016 sctx->framebuffer.color_is_int8 |= 1 << i;
3017 if (surf->color_is_int10)
3018 sctx->framebuffer.color_is_int10 |= 1 << i;
3019
3020 if (tex->surface.fmask_offset)
3021 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3022 else
3023 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
3024
3025 if (tex->surface.dcc_offset)
3026 sctx->framebuffer.displayable_dcc_cb_mask |= 1 << i;
3027
3028 /* Don't update nr_color_samples for non-AA buffers.
3029 * (e.g. destination of MSAA resolve)
3030 */
3031 if (tex->buffer.b.b.nr_samples >= 2 &&
3032 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3033 sctx->framebuffer.nr_color_samples =
3034 MIN2(sctx->framebuffer.nr_color_samples,
3035 tex->buffer.b.b.nr_storage_samples);
3036 sctx->framebuffer.nr_color_samples =
3037 MAX2(1, sctx->framebuffer.nr_color_samples);
3038 }
3039
3040 if (tex->surface.is_linear)
3041 sctx->framebuffer.any_dst_linear = true;
3042
3043 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3044 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3045
3046 if (sctx->chip_class >= GFX9 &&
3047 !tex->surface.u.gfx9.dcc.pipe_aligned)
3048 sctx->framebuffer.all_DCC_pipe_aligned = false;
3049 }
3050
3051 si_context_add_resource_size(sctx, surf->base.texture);
3052
3053 p_atomic_inc(&tex->framebuffers_bound);
3054
3055 if (tex->dcc_gather_statistics) {
3056 /* Dirty tracking must be enabled for DCC usage analysis. */
3057 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3058 vi_separate_dcc_start_query(sctx, tex);
3059 }
3060
3061 /* Update the minimum but don't keep 0. */
3062 if (!sctx->framebuffer.min_bytes_per_pixel ||
3063 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3064 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
3065 }
3066
3067 /* For optimal DCC performance. */
3068 if (sctx->chip_class >= GFX10)
3069 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
3070 else
3071 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
3072
3073 struct si_texture *zstex = NULL;
3074
3075 if (state->zsbuf) {
3076 surf = (struct si_surface*)state->zsbuf;
3077 zstex = (struct si_texture*)surf->base.texture;
3078
3079 if (!surf->depth_initialized) {
3080 si_init_depth_surface(sctx, surf);
3081 }
3082
3083 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level,
3084 PIPE_MASK_ZS))
3085 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3086
3087 si_context_add_resource_size(sctx, surf->base.texture);
3088
3089 /* Update the minimum but don't keep 0. */
3090 if (!sctx->framebuffer.min_bytes_per_pixel ||
3091 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3092 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
3093 }
3094
3095 si_update_ps_colorbuf0_slot(sctx);
3096 si_update_poly_offset_state(sctx);
3097 si_update_ngg_small_prim_precision(sctx);
3098 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3099 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3100
3101 if (sctx->screen->dpbb_allowed)
3102 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3103
3104 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3105 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3106
3107 if (sctx->screen->has_out_of_order_rast &&
3108 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3109 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3110 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3111 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3112
3113 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3114 struct pipe_constant_buffer constbuf = {0};
3115
3116 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3117 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3118
3119 constbuf.buffer = sctx->sample_pos_buffer;
3120
3121 /* Set sample locations as fragment shader constants. */
3122 switch (sctx->framebuffer.nr_samples) {
3123 case 1:
3124 constbuf.buffer_offset = 0;
3125 break;
3126 case 2:
3127 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3128 (ubyte*)sctx->sample_positions.x1;
3129 break;
3130 case 4:
3131 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3132 (ubyte*)sctx->sample_positions.x1;
3133 break;
3134 case 8:
3135 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3136 (ubyte*)sctx->sample_positions.x1;
3137 break;
3138 case 16:
3139 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3140 (ubyte*)sctx->sample_positions.x1;
3141 break;
3142 default:
3143 PRINT_ERR("Requested an invalid number of samples %i.\n",
3144 sctx->framebuffer.nr_samples);
3145 assert(0);
3146 }
3147 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3148 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3149
3150 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3151 }
3152
3153 sctx->do_update_shaders = true;
3154
3155 if (!sctx->decompression_enabled) {
3156 /* Prevent textures decompression when the framebuffer state
3157 * changes come from the decompression passes themselves.
3158 */
3159 sctx->need_check_render_feedback = true;
3160 }
3161 }
3162
3163 static void si_emit_framebuffer_state(struct si_context *sctx)
3164 {
3165 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3166 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3167 unsigned i, nr_cbufs = state->nr_cbufs;
3168 struct si_texture *tex = NULL;
3169 struct si_surface *cb = NULL;
3170 unsigned cb_color_info = 0;
3171
3172 /* Colorbuffers. */
3173 for (i = 0; i < nr_cbufs; i++) {
3174 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3175 unsigned cb_color_attrib;
3176
3177 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3178 continue;
3179
3180 cb = (struct si_surface*)state->cbufs[i];
3181 if (!cb) {
3182 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3183 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3184 continue;
3185 }
3186
3187 tex = (struct si_texture *)cb->base.texture;
3188 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3189 &tex->buffer, RADEON_USAGE_READWRITE,
3190 tex->buffer.b.b.nr_samples > 1 ?
3191 RADEON_PRIO_COLOR_BUFFER_MSAA :
3192 RADEON_PRIO_COLOR_BUFFER);
3193
3194 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3195 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3196 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3197 RADEON_PRIO_SEPARATE_META);
3198 }
3199
3200 if (tex->dcc_separate_buffer)
3201 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3202 tex->dcc_separate_buffer,
3203 RADEON_USAGE_READWRITE,
3204 RADEON_PRIO_SEPARATE_META);
3205
3206 /* Compute mutable surface parameters. */
3207 cb_color_base = tex->buffer.gpu_address >> 8;
3208 cb_color_fmask = 0;
3209 cb_color_cmask = tex->cmask_base_address_reg;
3210 cb_dcc_base = 0;
3211 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3212 cb_color_attrib = cb->cb_color_attrib;
3213
3214 if (cb->base.u.tex.level > 0)
3215 cb_color_info &= C_028C70_FAST_CLEAR;
3216
3217 if (tex->surface.fmask_offset) {
3218 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
3219 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3220 }
3221
3222 /* Set up DCC. */
3223 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3224 bool is_msaa_resolve_dst = state->cbufs[0] &&
3225 state->cbufs[0]->texture->nr_samples > 1 &&
3226 state->cbufs[1] == &cb->base &&
3227 state->cbufs[1]->texture->nr_samples <= 1;
3228
3229 if (!is_msaa_resolve_dst)
3230 cb_color_info |= S_028C70_DCC_ENABLE(1);
3231
3232 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3233 tex->surface.dcc_offset) >> 8;
3234
3235 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3236 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
3237 cb_dcc_base |= dcc_tile_swizzle;
3238 }
3239
3240 if (sctx->chip_class >= GFX10) {
3241 unsigned cb_color_attrib3;
3242
3243 /* Set mutable surface parameters. */
3244 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3245 cb_color_base |= tex->surface.tile_swizzle;
3246 if (!tex->surface.fmask_offset)
3247 cb_color_fmask = cb_color_base;
3248 if (cb->base.u.tex.level > 0)
3249 cb_color_cmask = cb_color_base;
3250
3251 cb_color_attrib3 = cb->cb_color_attrib3 |
3252 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3253 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3254 S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3255 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
3256
3257 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3258 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3259 radeon_emit(cs, 0); /* hole */
3260 radeon_emit(cs, 0); /* hole */
3261 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3262 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3263 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3264 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3265 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3266 radeon_emit(cs, 0); /* hole */
3267 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3268 radeon_emit(cs, 0); /* hole */
3269 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3270 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3271 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3272
3273 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4,
3274 cb_color_base >> 32);
3275 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3276 cb_color_cmask >> 32);
3277 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3278 cb_color_fmask >> 32);
3279 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4,
3280 cb_dcc_base >> 32);
3281 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4,
3282 cb->cb_color_attrib2);
3283 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4,
3284 cb_color_attrib3);
3285 } else if (sctx->chip_class == GFX9) {
3286 struct gfx9_surf_meta_flags meta;
3287
3288 if (tex->surface.dcc_offset)
3289 meta = tex->surface.u.gfx9.dcc;
3290 else
3291 meta = tex->surface.u.gfx9.cmask;
3292
3293 /* Set mutable surface parameters. */
3294 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3295 cb_color_base |= tex->surface.tile_swizzle;
3296 if (!tex->surface.fmask_offset)
3297 cb_color_fmask = cb_color_base;
3298 if (cb->base.u.tex.level > 0)
3299 cb_color_cmask = cb_color_base;
3300 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3301 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3302 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3303 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3304
3305 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3306 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3307 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3308 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3309 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3310 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3311 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3312 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3313 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3314 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3315 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3316 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3317 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3318 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3319 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3320 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3321
3322 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3323 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3324 } else {
3325 /* Compute mutable surface parameters (GFX6-GFX8). */
3326 const struct legacy_surf_level *level_info =
3327 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3328 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3329 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3330
3331 cb_color_base += level_info->offset >> 8;
3332 /* Only macrotiled modes can set tile swizzle. */
3333 if (level_info->mode == RADEON_SURF_MODE_2D)
3334 cb_color_base |= tex->surface.tile_swizzle;
3335
3336 if (!tex->surface.fmask_offset)
3337 cb_color_fmask = cb_color_base;
3338 if (cb->base.u.tex.level > 0)
3339 cb_color_cmask = cb_color_base;
3340 if (cb_dcc_base)
3341 cb_dcc_base += level_info->dcc_offset >> 8;
3342
3343 pitch_tile_max = level_info->nblk_x / 8 - 1;
3344 slice_tile_max = level_info->nblk_x *
3345 level_info->nblk_y / 64 - 1;
3346 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3347
3348 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3349 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3350 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3351
3352 if (tex->surface.fmask_offset) {
3353 if (sctx->chip_class >= GFX7)
3354 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3355 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3356 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3357 } else {
3358 /* This must be set for fast clear to work without FMASK. */
3359 if (sctx->chip_class >= GFX7)
3360 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3361 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3362 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3363 }
3364
3365 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3366 sctx->chip_class >= GFX8 ? 14 : 13);
3367 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3368 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3369 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3370 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3371 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3372 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3373 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3374 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3375 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3376 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3377 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3378 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3379 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3380
3381 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3382 radeon_emit(cs, cb_dcc_base);
3383 }
3384 }
3385 for (; i < 8 ; i++)
3386 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3387 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3388
3389 /* ZS buffer. */
3390 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3391 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3392 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3393
3394 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3395 &tex->buffer, RADEON_USAGE_READWRITE,
3396 zb->base.texture->nr_samples > 1 ?
3397 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3398 RADEON_PRIO_DEPTH_BUFFER);
3399
3400 if (sctx->chip_class >= GFX10) {
3401 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3402 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3403
3404 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3405 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3406 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3407 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3408 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3409 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3410 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3411 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3412 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3413
3414 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
3415 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3416 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3417 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3418 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3419 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3420 } else if (sctx->chip_class == GFX9) {
3421 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3422 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3423 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3424 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3425
3426 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3427 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3428 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3429 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3430 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3431 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3432 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3433 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3434 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3435 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3436 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3437 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3438
3439 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3440 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3441 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3442 } else {
3443 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3444
3445 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3446 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3447 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3448 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3449 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3450 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3451 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3452 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3453 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3454 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3455 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3456 }
3457
3458 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3459 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3460 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3461
3462 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3463 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3464 } else if (sctx->framebuffer.dirty_zsbuf) {
3465 if (sctx->chip_class == GFX9)
3466 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3467 else
3468 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3469
3470 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3471 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3472 }
3473
3474 /* Framebuffer dimensions. */
3475 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3476 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3477 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3478
3479 if (sctx->screen->dfsm_allowed) {
3480 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3481 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3482 }
3483
3484 sctx->framebuffer.dirty_cbufs = 0;
3485 sctx->framebuffer.dirty_zsbuf = false;
3486 }
3487
3488 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3489 {
3490 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3491 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3492 unsigned nr_samples = sctx->framebuffer.nr_samples;
3493 bool has_msaa_sample_loc_bug = sctx->screen->info.has_msaa_sample_loc_bug;
3494
3495 /* Smoothing (only possible with nr_samples == 1) uses the same
3496 * sample locations as the MSAA it simulates.
3497 */
3498 if (nr_samples <= 1 && sctx->smoothing_enabled)
3499 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3500
3501 /* On Polaris, the small primitive filter uses the sample locations
3502 * even when MSAA is off, so we need to make sure they're set to 0.
3503 *
3504 * GFX10 uses sample locations unconditionally, so they always need
3505 * to be set up.
3506 */
3507 if ((nr_samples >= 2 || has_msaa_sample_loc_bug ||
3508 sctx->chip_class >= GFX10) &&
3509 nr_samples != sctx->sample_locs_num_samples) {
3510 sctx->sample_locs_num_samples = nr_samples;
3511 si_emit_sample_locations(cs, nr_samples);
3512 }
3513
3514 if (sctx->family >= CHIP_POLARIS10) {
3515 unsigned small_prim_filter_cntl =
3516 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3517 /* line bug */
3518 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3519
3520 /* The alternative of setting sample locations to 0 would
3521 * require a DB flush to avoid Z errors, see
3522 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3523 */
3524 if (has_msaa_sample_loc_bug &&
3525 sctx->framebuffer.nr_samples > 1 &&
3526 !rs->multisample_enable)
3527 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3528
3529 radeon_opt_set_context_reg(sctx,
3530 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3531 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3532 small_prim_filter_cntl);
3533 }
3534
3535 /* The exclusion bits can be set to improve rasterization efficiency
3536 * if no sample lies on the pixel boundary (-8 sample offset).
3537 */
3538 bool exclusion = sctx->chip_class >= GFX7 &&
3539 (!rs->multisample_enable || nr_samples != 16);
3540 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3541 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3542 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3543 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3544 }
3545
3546 static bool si_out_of_order_rasterization(struct si_context *sctx)
3547 {
3548 struct si_state_blend *blend = sctx->queued.named.blend;
3549 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3550
3551 if (!sctx->screen->has_out_of_order_rast)
3552 return false;
3553
3554 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3555
3556 colormask &= blend->cb_target_enabled_4bit;
3557
3558 /* Conservative: No logic op. */
3559 if (colormask && blend->logicop_enable)
3560 return false;
3561
3562 struct si_dsa_order_invariance dsa_order_invariant = {
3563 .zs = true, .pass_set = true, .pass_last = false
3564 };
3565
3566 if (sctx->framebuffer.state.zsbuf) {
3567 struct si_texture *zstex =
3568 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3569 bool has_stencil = zstex->surface.has_stencil;
3570 dsa_order_invariant = dsa->order_invariance[has_stencil];
3571 if (!dsa_order_invariant.zs)
3572 return false;
3573
3574 /* The set of PS invocations is always order invariant,
3575 * except when early Z/S tests are requested. */
3576 if (sctx->ps_shader.cso &&
3577 sctx->ps_shader.cso->info.writes_memory &&
3578 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3579 !dsa_order_invariant.pass_set)
3580 return false;
3581
3582 if (sctx->num_perfect_occlusion_queries != 0 &&
3583 !dsa_order_invariant.pass_set)
3584 return false;
3585 }
3586
3587 if (!colormask)
3588 return true;
3589
3590 unsigned blendmask = colormask & blend->blend_enable_4bit;
3591
3592 if (blendmask) {
3593 /* Only commutative blending. */
3594 if (blendmask & ~blend->commutative_4bit)
3595 return false;
3596
3597 if (!dsa_order_invariant.pass_set)
3598 return false;
3599 }
3600
3601 if (colormask & ~blendmask) {
3602 if (!dsa_order_invariant.pass_last)
3603 return false;
3604 }
3605
3606 return true;
3607 }
3608
3609 static void si_emit_msaa_config(struct si_context *sctx)
3610 {
3611 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3612 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3613 /* 33% faster rendering to linear color buffers */
3614 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3615 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3616 unsigned sc_mode_cntl_1 =
3617 S_028A4C_WALK_SIZE(dst_is_linear) |
3618 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3619 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3620 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3621 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3622 /* always 1: */
3623 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3624 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3625 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3626 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3627 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3628 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3629 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3630 S_028804_INCOHERENT_EQAA_READS(1) |
3631 S_028804_INTERPOLATE_COMP_Z(1) |
3632 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3633 unsigned coverage_samples, color_samples, z_samples;
3634 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3635
3636 /* S: Coverage samples (up to 16x):
3637 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3638 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3639 *
3640 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3641 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3642 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3643 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3644 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3645 * # Z samples).
3646 *
3647 * F: Color samples (up to 8x, must be <= coverage samples):
3648 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3649 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3650 *
3651 * Can be anything between coverage and color samples:
3652 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3653 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3654 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3655 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3656 * # All are currently set the same as coverage samples.
3657 *
3658 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3659 * flag for undefined color samples. A shader-based resolve must handle unknowns
3660 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3661 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3662 * useful. The CB resolve always drops unknowns.
3663 *
3664 * Sensible AA configurations:
3665 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3666 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3667 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3668 * EQAA 8s 8z 8f = 8x MSAA
3669 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3670 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3671 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3672 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3673 * EQAA 4s 4z 4f = 4x MSAA
3674 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3675 * EQAA 2s 2z 2f = 2x MSAA
3676 */
3677 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3678 coverage_samples = sctx->framebuffer.nr_samples;
3679 color_samples = sctx->framebuffer.nr_color_samples;
3680
3681 if (sctx->framebuffer.state.zsbuf) {
3682 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3683 z_samples = MAX2(1, z_samples);
3684 } else {
3685 z_samples = coverage_samples;
3686 }
3687 } else if (sctx->smoothing_enabled) {
3688 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3689 } else {
3690 coverage_samples = color_samples = z_samples = 1;
3691 }
3692
3693 /* Required by OpenGL line rasterization.
3694 *
3695 * TODO: We should also enable perpendicular endcaps for AA lines,
3696 * but that requires implementing line stippling in the pixel
3697 * shader. SC can only do line stippling with axis-aligned
3698 * endcaps.
3699 */
3700 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3701 unsigned sc_aa_config = 0;
3702
3703 if (coverage_samples > 1) {
3704 /* distance from the pixel center, indexed by log2(nr_samples) */
3705 static unsigned max_dist[] = {
3706 0, /* unused */
3707 4, /* 2x MSAA */
3708 6, /* 4x MSAA */
3709 7, /* 8x MSAA */
3710 8, /* 16x MSAA */
3711 };
3712 unsigned log_samples = util_logbase2(coverage_samples);
3713 unsigned log_z_samples = util_logbase2(z_samples);
3714 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3715 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3716
3717 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3718 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3719 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3720 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3721
3722 if (sctx->framebuffer.nr_samples > 1) {
3723 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3724 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3725 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3726 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3727 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3728 } else if (sctx->smoothing_enabled) {
3729 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3730 }
3731 }
3732
3733 unsigned initial_cdw = cs->current.cdw;
3734
3735 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3736 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3737 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3738 sc_aa_config);
3739 /* R_028804_DB_EQAA */
3740 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3741 db_eqaa);
3742 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3743 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3744 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3745
3746 if (initial_cdw != cs->current.cdw) {
3747 sctx->context_roll = true;
3748
3749 /* GFX9: Flush DFSM when the AA mode changes. */
3750 if (sctx->screen->dfsm_allowed) {
3751 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3752 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3753 }
3754 }
3755 }
3756
3757 void si_update_ps_iter_samples(struct si_context *sctx)
3758 {
3759 if (sctx->framebuffer.nr_samples > 1)
3760 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3761 if (sctx->screen->dpbb_allowed)
3762 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3763 }
3764
3765 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3766 {
3767 struct si_context *sctx = (struct si_context *)ctx;
3768
3769 /* The hardware can only do sample shading with 2^n samples. */
3770 min_samples = util_next_power_of_two(min_samples);
3771
3772 if (sctx->ps_iter_samples == min_samples)
3773 return;
3774
3775 sctx->ps_iter_samples = min_samples;
3776 sctx->do_update_shaders = true;
3777
3778 si_update_ps_iter_samples(sctx);
3779 }
3780
3781 /*
3782 * Samplers
3783 */
3784
3785 /**
3786 * Build the sampler view descriptor for a buffer texture.
3787 * @param state 256-bit descriptor; only the high 128 bits are filled in
3788 */
3789 void
3790 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3791 enum pipe_format format,
3792 unsigned offset, unsigned size,
3793 uint32_t *state)
3794 {
3795 const struct util_format_description *desc;
3796 unsigned stride;
3797 unsigned num_records;
3798
3799 desc = util_format_description(format);
3800 stride = desc->block.bits / 8;
3801
3802 num_records = size / stride;
3803 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3804
3805 /* The NUM_RECORDS field has a different meaning depending on the chip,
3806 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3807 *
3808 * GFX6-7,10:
3809 * - If STRIDE == 0, it's in byte units.
3810 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3811 *
3812 * GFX8:
3813 * - For SMEM and STRIDE == 0, it's in byte units.
3814 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3815 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3816 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3817 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3818 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3819 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3820 * That way the same descriptor can be used by both SMEM and VMEM.
3821 *
3822 * GFX9:
3823 * - For SMEM and STRIDE == 0, it's in byte units.
3824 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3825 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3826 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3827 */
3828 if (screen->info.chip_class == GFX8)
3829 num_records *= stride;
3830
3831 state[4] = 0;
3832 state[5] = S_008F04_STRIDE(stride);
3833 state[6] = num_records;
3834 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3835 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3836 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3837 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3838
3839 if (screen->info.chip_class >= GFX10) {
3840 const struct gfx10_format *fmt = &gfx10_format_table[format];
3841
3842 /* OOB_SELECT chooses the out-of-bounds check:
3843 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3844 * - 1: index >= NUM_RECORDS
3845 * - 2: NUM_RECORDS == 0
3846 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3847 * else: swizzle_address >= NUM_RECORDS
3848 */
3849 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3850 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) |
3851 S_008F0C_RESOURCE_LEVEL(1);
3852 } else {
3853 int first_non_void;
3854 unsigned num_format, data_format;
3855
3856 first_non_void = util_format_get_first_non_void_channel(format);
3857 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3858 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3859
3860 state[7] |= S_008F0C_NUM_FORMAT(num_format) |
3861 S_008F0C_DATA_FORMAT(data_format);
3862 }
3863 }
3864
3865 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3866 {
3867 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3868
3869 if (swizzle[3] == PIPE_SWIZZLE_X) {
3870 /* For the pre-defined border color values (white, opaque
3871 * black, transparent black), the only thing that matters is
3872 * that the alpha channel winds up in the correct place
3873 * (because the RGB channels are all the same) so either of
3874 * these enumerations will work.
3875 */
3876 if (swizzle[2] == PIPE_SWIZZLE_Y)
3877 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3878 else
3879 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3880 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3881 if (swizzle[1] == PIPE_SWIZZLE_Y)
3882 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3883 else
3884 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3885 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3886 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3887 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3888 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3889 }
3890
3891 return bc_swizzle;
3892 }
3893
3894 /**
3895 * Build the sampler view descriptor for a texture.
3896 */
3897 static void
3898 gfx10_make_texture_descriptor(struct si_screen *screen,
3899 struct si_texture *tex,
3900 bool sampler,
3901 enum pipe_texture_target target,
3902 enum pipe_format pipe_format,
3903 const unsigned char state_swizzle[4],
3904 unsigned first_level, unsigned last_level,
3905 unsigned first_layer, unsigned last_layer,
3906 unsigned width, unsigned height, unsigned depth,
3907 uint32_t *state,
3908 uint32_t *fmask_state)
3909 {
3910 struct pipe_resource *res = &tex->buffer.b.b;
3911 const struct util_format_description *desc;
3912 unsigned img_format;
3913 unsigned char swizzle[4];
3914 unsigned type;
3915 uint64_t va;
3916
3917 desc = util_format_description(pipe_format);
3918 img_format = gfx10_format_table[pipe_format].img_format;
3919
3920 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3921 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3922 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3923 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3924 bool is_stencil = false;
3925
3926 switch (pipe_format) {
3927 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3928 case PIPE_FORMAT_X32_S8X24_UINT:
3929 case PIPE_FORMAT_X8Z24_UNORM:
3930 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3931 is_stencil = true;
3932 break;
3933 case PIPE_FORMAT_X24S8_UINT:
3934 /*
3935 * X24S8 is implemented as an 8_8_8_8 data format, to
3936 * fix texture gathers. This affects at least
3937 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3938 */
3939 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3940 is_stencil = true;
3941 break;
3942 default:
3943 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3944 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3945 }
3946
3947 if (tex->upgraded_depth && !is_stencil) {
3948 assert(img_format == V_008F0C_IMG_FORMAT_32_FLOAT);
3949 img_format = V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP;
3950 }
3951 } else {
3952 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3953 }
3954
3955 if (!sampler &&
3956 (res->target == PIPE_TEXTURE_CUBE ||
3957 res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3958 /* For the purpose of shader images, treat cube maps as 2D
3959 * arrays.
3960 */
3961 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3962 } else {
3963 type = si_tex_dim(screen, tex, target, res->nr_samples);
3964 }
3965
3966 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3967 height = 1;
3968 depth = res->array_size;
3969 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3970 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3971 if (sampler || res->target != PIPE_TEXTURE_3D)
3972 depth = res->array_size;
3973 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3974 depth = res->array_size / 6;
3975
3976 state[0] = 0;
3977 state[1] = S_00A004_FORMAT(img_format) |
3978 S_00A004_WIDTH_LO(width - 1);
3979 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
3980 S_00A008_HEIGHT(height - 1) |
3981 S_00A008_RESOURCE_LEVEL(1);
3982 state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3983 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3984 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3985 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3986 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ?
3987 0 : first_level) |
3988 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ?
3989 util_logbase2(res->nr_samples) :
3990 last_level) |
3991 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) |
3992 S_00A00C_TYPE(type);
3993 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3994 * to know the total number of layers.
3995 */
3996 state[4] = S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler)
3997 ? depth - 1 : last_layer) |
3998 S_00A010_BASE_ARRAY(first_layer);
3999 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
4000 S_00A014_MAX_MIP(res->nr_samples > 1 ?
4001 util_logbase2(res->nr_samples) :
4002 tex->buffer.b.b.last_level) |
4003 S_00A014_PERF_MOD(4);
4004 state[6] = 0;
4005 state[7] = 0;
4006
4007 if (tex->surface.dcc_offset) {
4008 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
4009 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
4010 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4011 }
4012
4013 /* Initialize the sampler view for FMASK. */
4014 if (tex->surface.fmask_offset) {
4015 uint32_t format;
4016
4017 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4018
4019 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4020 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4021 case FMASK(2,1):
4022 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F1;
4023 break;
4024 case FMASK(2,2):
4025 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
4026 break;
4027 case FMASK(4,1):
4028 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F1;
4029 break;
4030 case FMASK(4,2):
4031 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F2;
4032 break;
4033 case FMASK(4,4):
4034 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
4035 break;
4036 case FMASK(8,1):
4037 format = V_008F0C_IMG_FORMAT_FMASK8_S8_F1;
4038 break;
4039 case FMASK(8,2):
4040 format = V_008F0C_IMG_FORMAT_FMASK16_S8_F2;
4041 break;
4042 case FMASK(8,4):
4043 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F4;
4044 break;
4045 case FMASK(8,8):
4046 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
4047 break;
4048 case FMASK(16,1):
4049 format = V_008F0C_IMG_FORMAT_FMASK16_S16_F1;
4050 break;
4051 case FMASK(16,2):
4052 format = V_008F0C_IMG_FORMAT_FMASK32_S16_F2;
4053 break;
4054 case FMASK(16,4):
4055 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F4;
4056 break;
4057 case FMASK(16,8):
4058 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F8;
4059 break;
4060 default:
4061 unreachable("invalid nr_samples");
4062 }
4063 #undef FMASK
4064 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4065 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
4066 S_00A004_FORMAT(format) |
4067 S_00A004_WIDTH_LO(width - 1);
4068 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
4069 S_00A008_HEIGHT(height - 1) |
4070 S_00A008_RESOURCE_LEVEL(1);
4071 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4072 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4073 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4074 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4075 S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
4076 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4077 fmask_state[4] = S_00A010_DEPTH(last_layer) |
4078 S_00A010_BASE_ARRAY(first_layer);
4079 fmask_state[5] = 0;
4080 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
4081 fmask_state[7] = 0;
4082 }
4083 }
4084
4085 /**
4086 * Build the sampler view descriptor for a texture (SI-GFX9).
4087 */
4088 static void
4089 si_make_texture_descriptor(struct si_screen *screen,
4090 struct si_texture *tex,
4091 bool sampler,
4092 enum pipe_texture_target target,
4093 enum pipe_format pipe_format,
4094 const unsigned char state_swizzle[4],
4095 unsigned first_level, unsigned last_level,
4096 unsigned first_layer, unsigned last_layer,
4097 unsigned width, unsigned height, unsigned depth,
4098 uint32_t *state,
4099 uint32_t *fmask_state)
4100 {
4101 struct pipe_resource *res = &tex->buffer.b.b;
4102 const struct util_format_description *desc;
4103 unsigned char swizzle[4];
4104 int first_non_void;
4105 unsigned num_format, data_format, type, num_samples;
4106 uint64_t va;
4107
4108 desc = util_format_description(pipe_format);
4109
4110 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
4111 MAX2(1, res->nr_samples) :
4112 MAX2(1, res->nr_storage_samples);
4113
4114 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4115 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4116 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4117 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4118
4119 switch (pipe_format) {
4120 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4121 case PIPE_FORMAT_X32_S8X24_UINT:
4122 case PIPE_FORMAT_X8Z24_UNORM:
4123 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4124 break;
4125 case PIPE_FORMAT_X24S8_UINT:
4126 /*
4127 * X24S8 is implemented as an 8_8_8_8 data format, to
4128 * fix texture gathers. This affects at least
4129 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4130 */
4131 if (screen->info.chip_class <= GFX8)
4132 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4133 else
4134 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4135 break;
4136 default:
4137 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4138 }
4139 } else {
4140 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4141 }
4142
4143 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4144
4145 switch (pipe_format) {
4146 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4147 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4148 break;
4149 default:
4150 if (first_non_void < 0) {
4151 if (util_format_is_compressed(pipe_format)) {
4152 switch (pipe_format) {
4153 case PIPE_FORMAT_DXT1_SRGB:
4154 case PIPE_FORMAT_DXT1_SRGBA:
4155 case PIPE_FORMAT_DXT3_SRGBA:
4156 case PIPE_FORMAT_DXT5_SRGBA:
4157 case PIPE_FORMAT_BPTC_SRGBA:
4158 case PIPE_FORMAT_ETC2_SRGB8:
4159 case PIPE_FORMAT_ETC2_SRGB8A1:
4160 case PIPE_FORMAT_ETC2_SRGBA8:
4161 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4162 break;
4163 case PIPE_FORMAT_RGTC1_SNORM:
4164 case PIPE_FORMAT_LATC1_SNORM:
4165 case PIPE_FORMAT_RGTC2_SNORM:
4166 case PIPE_FORMAT_LATC2_SNORM:
4167 case PIPE_FORMAT_ETC2_R11_SNORM:
4168 case PIPE_FORMAT_ETC2_RG11_SNORM:
4169 /* implies float, so use SNORM/UNORM to determine
4170 whether data is signed or not */
4171 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4172 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4173 break;
4174 default:
4175 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4176 break;
4177 }
4178 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4179 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4180 } else {
4181 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4182 }
4183 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4184 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4185 } else {
4186 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4187
4188 switch (desc->channel[first_non_void].type) {
4189 case UTIL_FORMAT_TYPE_FLOAT:
4190 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4191 break;
4192 case UTIL_FORMAT_TYPE_SIGNED:
4193 if (desc->channel[first_non_void].normalized)
4194 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4195 else if (desc->channel[first_non_void].pure_integer)
4196 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4197 else
4198 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4199 break;
4200 case UTIL_FORMAT_TYPE_UNSIGNED:
4201 if (desc->channel[first_non_void].normalized)
4202 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4203 else if (desc->channel[first_non_void].pure_integer)
4204 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4205 else
4206 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4207 }
4208 }
4209 }
4210
4211 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4212 if (data_format == ~0) {
4213 data_format = 0;
4214 }
4215
4216 /* S8 with Z32 HTILE needs a special format. */
4217 if (screen->info.chip_class == GFX9 &&
4218 pipe_format == PIPE_FORMAT_S8_UINT &&
4219 tex->tc_compatible_htile)
4220 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4221
4222 if (!sampler &&
4223 (res->target == PIPE_TEXTURE_CUBE ||
4224 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4225 (screen->info.chip_class <= GFX8 &&
4226 res->target == PIPE_TEXTURE_3D))) {
4227 /* For the purpose of shader images, treat cube maps and 3D
4228 * textures as 2D arrays. For 3D textures, the address
4229 * calculations for mipmaps are different, so we rely on the
4230 * caller to effectively disable mipmaps.
4231 */
4232 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4233
4234 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4235 } else {
4236 type = si_tex_dim(screen, tex, target, num_samples);
4237 }
4238
4239 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4240 height = 1;
4241 depth = res->array_size;
4242 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
4243 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4244 if (sampler || res->target != PIPE_TEXTURE_3D)
4245 depth = res->array_size;
4246 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4247 depth = res->array_size / 6;
4248
4249 state[0] = 0;
4250 state[1] = (S_008F14_DATA_FORMAT(data_format) |
4251 S_008F14_NUM_FORMAT(num_format));
4252 state[2] = (S_008F18_WIDTH(width - 1) |
4253 S_008F18_HEIGHT(height - 1) |
4254 S_008F18_PERF_MOD(4));
4255 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4256 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4257 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4258 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4259 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4260 S_008F1C_LAST_LEVEL(num_samples > 1 ?
4261 util_logbase2(num_samples) :
4262 last_level) |
4263 S_008F1C_TYPE(type));
4264 state[4] = 0;
4265 state[5] = S_008F24_BASE_ARRAY(first_layer);
4266 state[6] = 0;
4267 state[7] = 0;
4268
4269 if (screen->info.chip_class == GFX9) {
4270 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4271
4272 /* Depth is the the last accessible layer on Gfx9.
4273 * The hw doesn't need to know the total number of layers.
4274 */
4275 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4276 state[4] |= S_008F20_DEPTH(depth - 1);
4277 else
4278 state[4] |= S_008F20_DEPTH(last_layer);
4279
4280 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4281 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
4282 util_logbase2(num_samples) :
4283 tex->buffer.b.b.last_level);
4284 } else {
4285 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4286 state[4] |= S_008F20_DEPTH(depth - 1);
4287 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4288 }
4289
4290 if (tex->surface.dcc_offset) {
4291 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4292 } else {
4293 /* The last dword is unused by hw. The shader uses it to clear
4294 * bits in the first dword of sampler state.
4295 */
4296 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4297 if (first_level == last_level)
4298 state[7] = C_008F30_MAX_ANISO_RATIO;
4299 else
4300 state[7] = 0xffffffff;
4301 }
4302 }
4303
4304 /* Initialize the sampler view for FMASK. */
4305 if (tex->surface.fmask_offset) {
4306 uint32_t data_format, num_format;
4307
4308 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4309
4310 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4311 if (screen->info.chip_class == GFX9) {
4312 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4313 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4314 case FMASK(2,1):
4315 num_format = V_008F14_IMG_FMASK_8_2_1;
4316 break;
4317 case FMASK(2,2):
4318 num_format = V_008F14_IMG_FMASK_8_2_2;
4319 break;
4320 case FMASK(4,1):
4321 num_format = V_008F14_IMG_FMASK_8_4_1;
4322 break;
4323 case FMASK(4,2):
4324 num_format = V_008F14_IMG_FMASK_8_4_2;
4325 break;
4326 case FMASK(4,4):
4327 num_format = V_008F14_IMG_FMASK_8_4_4;
4328 break;
4329 case FMASK(8,1):
4330 num_format = V_008F14_IMG_FMASK_8_8_1;
4331 break;
4332 case FMASK(8,2):
4333 num_format = V_008F14_IMG_FMASK_16_8_2;
4334 break;
4335 case FMASK(8,4):
4336 num_format = V_008F14_IMG_FMASK_32_8_4;
4337 break;
4338 case FMASK(8,8):
4339 num_format = V_008F14_IMG_FMASK_32_8_8;
4340 break;
4341 case FMASK(16,1):
4342 num_format = V_008F14_IMG_FMASK_16_16_1;
4343 break;
4344 case FMASK(16,2):
4345 num_format = V_008F14_IMG_FMASK_32_16_2;
4346 break;
4347 case FMASK(16,4):
4348 num_format = V_008F14_IMG_FMASK_64_16_4;
4349 break;
4350 case FMASK(16,8):
4351 num_format = V_008F14_IMG_FMASK_64_16_8;
4352 break;
4353 default:
4354 unreachable("invalid nr_samples");
4355 }
4356 } else {
4357 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4358 case FMASK(2,1):
4359 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4360 break;
4361 case FMASK(2,2):
4362 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4363 break;
4364 case FMASK(4,1):
4365 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4366 break;
4367 case FMASK(4,2):
4368 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4369 break;
4370 case FMASK(4,4):
4371 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4372 break;
4373 case FMASK(8,1):
4374 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4375 break;
4376 case FMASK(8,2):
4377 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4378 break;
4379 case FMASK(8,4):
4380 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4381 break;
4382 case FMASK(8,8):
4383 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4384 break;
4385 case FMASK(16,1):
4386 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4387 break;
4388 case FMASK(16,2):
4389 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4390 break;
4391 case FMASK(16,4):
4392 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4393 break;
4394 case FMASK(16,8):
4395 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4396 break;
4397 default:
4398 unreachable("invalid nr_samples");
4399 }
4400 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4401 }
4402 #undef FMASK
4403
4404 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4405 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4406 S_008F14_DATA_FORMAT(data_format) |
4407 S_008F14_NUM_FORMAT(num_format);
4408 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4409 S_008F18_HEIGHT(height - 1);
4410 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4411 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4412 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4413 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4414 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4415 fmask_state[4] = 0;
4416 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4417 fmask_state[6] = 0;
4418 fmask_state[7] = 0;
4419
4420 if (screen->info.chip_class == GFX9) {
4421 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4422 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4423 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4424 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4425 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4426 } else {
4427 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4428 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4429 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4430 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4431 }
4432 }
4433 }
4434
4435 /**
4436 * Create a sampler view.
4437 *
4438 * @param ctx context
4439 * @param texture texture
4440 * @param state sampler view template
4441 * @param width0 width0 override (for compressed textures as int)
4442 * @param height0 height0 override (for compressed textures as int)
4443 * @param force_level set the base address to the level (for compressed textures)
4444 */
4445 struct pipe_sampler_view *
4446 si_create_sampler_view_custom(struct pipe_context *ctx,
4447 struct pipe_resource *texture,
4448 const struct pipe_sampler_view *state,
4449 unsigned width0, unsigned height0,
4450 unsigned force_level)
4451 {
4452 struct si_context *sctx = (struct si_context*)ctx;
4453 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4454 struct si_texture *tex = (struct si_texture*)texture;
4455 unsigned base_level, first_level, last_level;
4456 unsigned char state_swizzle[4];
4457 unsigned height, depth, width;
4458 unsigned last_layer = state->u.tex.last_layer;
4459 enum pipe_format pipe_format;
4460 const struct legacy_surf_level *surflevel;
4461
4462 if (!view)
4463 return NULL;
4464
4465 /* initialize base object */
4466 view->base = *state;
4467 view->base.texture = NULL;
4468 view->base.reference.count = 1;
4469 view->base.context = ctx;
4470
4471 assert(texture);
4472 pipe_resource_reference(&view->base.texture, texture);
4473
4474 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4475 state->format == PIPE_FORMAT_S8X24_UINT ||
4476 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4477 state->format == PIPE_FORMAT_S8_UINT)
4478 view->is_stencil_sampler = true;
4479
4480 /* Buffer resource. */
4481 if (texture->target == PIPE_BUFFER) {
4482 si_make_buffer_descriptor(sctx->screen,
4483 si_resource(texture),
4484 state->format,
4485 state->u.buf.offset,
4486 state->u.buf.size,
4487 view->state);
4488 return &view->base;
4489 }
4490
4491 state_swizzle[0] = state->swizzle_r;
4492 state_swizzle[1] = state->swizzle_g;
4493 state_swizzle[2] = state->swizzle_b;
4494 state_swizzle[3] = state->swizzle_a;
4495
4496 base_level = 0;
4497 first_level = state->u.tex.first_level;
4498 last_level = state->u.tex.last_level;
4499 width = width0;
4500 height = height0;
4501 depth = texture->depth0;
4502
4503 if (sctx->chip_class <= GFX8 && force_level) {
4504 assert(force_level == first_level &&
4505 force_level == last_level);
4506 base_level = force_level;
4507 first_level = 0;
4508 last_level = 0;
4509 width = u_minify(width, force_level);
4510 height = u_minify(height, force_level);
4511 depth = u_minify(depth, force_level);
4512 }
4513
4514 /* This is not needed if state trackers set last_layer correctly. */
4515 if (state->target == PIPE_TEXTURE_1D ||
4516 state->target == PIPE_TEXTURE_2D ||
4517 state->target == PIPE_TEXTURE_RECT ||
4518 state->target == PIPE_TEXTURE_CUBE)
4519 last_layer = state->u.tex.first_layer;
4520
4521 /* Texturing with separate depth and stencil. */
4522 pipe_format = state->format;
4523
4524 /* Depth/stencil texturing sometimes needs separate texture. */
4525 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4526 if (!tex->flushed_depth_texture &&
4527 !si_init_flushed_depth_texture(ctx, texture)) {
4528 pipe_resource_reference(&view->base.texture, NULL);
4529 FREE(view);
4530 return NULL;
4531 }
4532
4533 assert(tex->flushed_depth_texture);
4534
4535 /* Override format for the case where the flushed texture
4536 * contains only Z or only S.
4537 */
4538 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4539 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4540
4541 tex = tex->flushed_depth_texture;
4542 }
4543
4544 surflevel = tex->surface.u.legacy.level;
4545
4546 if (tex->db_compatible) {
4547 if (!view->is_stencil_sampler)
4548 pipe_format = tex->db_render_format;
4549
4550 switch (pipe_format) {
4551 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4552 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4553 break;
4554 case PIPE_FORMAT_X8Z24_UNORM:
4555 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4556 /* Z24 is always stored like this for DB
4557 * compatibility.
4558 */
4559 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4560 break;
4561 case PIPE_FORMAT_X24S8_UINT:
4562 case PIPE_FORMAT_S8X24_UINT:
4563 case PIPE_FORMAT_X32_S8X24_UINT:
4564 pipe_format = PIPE_FORMAT_S8_UINT;
4565 surflevel = tex->surface.u.legacy.stencil_level;
4566 break;
4567 default:;
4568 }
4569 }
4570
4571 view->dcc_incompatible =
4572 vi_dcc_formats_are_incompatible(texture,
4573 state->u.tex.first_level,
4574 state->format);
4575
4576 sctx->screen->make_texture_descriptor(sctx->screen, tex, true,
4577 state->target, pipe_format, state_swizzle,
4578 first_level, last_level,
4579 state->u.tex.first_layer, last_layer,
4580 width, height, depth,
4581 view->state, view->fmask_state);
4582
4583 const struct util_format_description *desc = util_format_description(pipe_format);
4584 view->is_integer = false;
4585
4586 for (unsigned i = 0; i < desc->nr_channels; ++i) {
4587 if (desc->channel[i].type == UTIL_FORMAT_TYPE_VOID)
4588 continue;
4589
4590 /* Whether the number format is {U,S}{SCALED,INT} */
4591 view->is_integer =
4592 (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
4593 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) &&
4594 (desc->channel[i].pure_integer || !desc->channel[i].normalized);
4595 break;
4596 }
4597
4598 view->base_level_info = &surflevel[base_level];
4599 view->base_level = base_level;
4600 view->block_width = util_format_get_blockwidth(pipe_format);
4601 return &view->base;
4602 }
4603
4604 static struct pipe_sampler_view *
4605 si_create_sampler_view(struct pipe_context *ctx,
4606 struct pipe_resource *texture,
4607 const struct pipe_sampler_view *state)
4608 {
4609 return si_create_sampler_view_custom(ctx, texture, state,
4610 texture ? texture->width0 : 0,
4611 texture ? texture->height0 : 0, 0);
4612 }
4613
4614 static void si_sampler_view_destroy(struct pipe_context *ctx,
4615 struct pipe_sampler_view *state)
4616 {
4617 struct si_sampler_view *view = (struct si_sampler_view *)state;
4618
4619 pipe_resource_reference(&state->texture, NULL);
4620 FREE(view);
4621 }
4622
4623 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4624 {
4625 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4626 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4627 (linear_filter &&
4628 (wrap == PIPE_TEX_WRAP_CLAMP ||
4629 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4630 }
4631
4632 static uint32_t si_translate_border_color(struct si_context *sctx,
4633 const struct pipe_sampler_state *state,
4634 const union pipe_color_union *color,
4635 bool is_integer)
4636 {
4637 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4638 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4639
4640 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4641 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4642 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4643 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4644
4645 #define simple_border_types(elt) \
4646 do { \
4647 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4648 color->elt[2] == 0 && color->elt[3] == 0) \
4649 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4650 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4651 color->elt[2] == 0 && color->elt[3] == 1) \
4652 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4653 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4654 color->elt[2] == 1 && color->elt[3] == 1) \
4655 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4656 } while (false)
4657
4658 if (is_integer)
4659 simple_border_types(ui);
4660 else
4661 simple_border_types(f);
4662
4663 #undef simple_border_types
4664
4665 int i;
4666
4667 /* Check if the border has been uploaded already. */
4668 for (i = 0; i < sctx->border_color_count; i++)
4669 if (memcmp(&sctx->border_color_table[i], color,
4670 sizeof(*color)) == 0)
4671 break;
4672
4673 if (i >= SI_MAX_BORDER_COLORS) {
4674 /* Getting 4096 unique border colors is very unlikely. */
4675 fprintf(stderr, "radeonsi: The border color table is full. "
4676 "Any new border colors will be just black. "
4677 "Please file a bug.\n");
4678 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4679 }
4680
4681 if (i == sctx->border_color_count) {
4682 /* Upload a new border color. */
4683 memcpy(&sctx->border_color_table[i], color,
4684 sizeof(*color));
4685 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4686 color, sizeof(*color));
4687 sctx->border_color_count++;
4688 }
4689
4690 return S_008F3C_BORDER_COLOR_PTR(i) |
4691 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4692 }
4693
4694 static inline int S_FIXED(float value, unsigned frac_bits)
4695 {
4696 return value * (1 << frac_bits);
4697 }
4698
4699 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4700 {
4701 if (filter == PIPE_TEX_FILTER_LINEAR)
4702 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4703 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4704 else
4705 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4706 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4707 }
4708
4709 static inline unsigned si_tex_aniso_filter(unsigned filter)
4710 {
4711 if (filter < 2)
4712 return 0;
4713 if (filter < 4)
4714 return 1;
4715 if (filter < 8)
4716 return 2;
4717 if (filter < 16)
4718 return 3;
4719 return 4;
4720 }
4721
4722 static void *si_create_sampler_state(struct pipe_context *ctx,
4723 const struct pipe_sampler_state *state)
4724 {
4725 struct si_context *sctx = (struct si_context *)ctx;
4726 struct si_screen *sscreen = sctx->screen;
4727 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4728 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4729 : state->max_anisotropy;
4730 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4731 union pipe_color_union clamped_border_color;
4732
4733 if (!rstate) {
4734 return NULL;
4735 }
4736
4737 #ifndef NDEBUG
4738 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4739 #endif
4740 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4741 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4742 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4743 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4744 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4745 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4746 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4747 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4748 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4749 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4750 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4751 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4752 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4753 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4754 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4755 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4756 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4757 S_008F38_MIP_POINT_PRECLAMP(0));
4758 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4759
4760 if (sscreen->info.chip_class >= GFX10) {
4761 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4762 } else {
4763 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4764 S_008F38_FILTER_PREC_FIX(1) |
4765 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8);
4766 }
4767
4768 /* Create sampler resource for integer textures. */
4769 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4770 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4771
4772 /* Create sampler resource for upgraded depth textures. */
4773 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4774
4775 for (unsigned i = 0; i < 4; ++i) {
4776 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4777 * when the border color is 1.0. */
4778 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4779 }
4780
4781 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4782 if (sscreen->info.chip_class <= GFX9)
4783 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4784 } else {
4785 rstate->upgraded_depth_val[3] =
4786 si_translate_border_color(sctx, state, &clamped_border_color, false);
4787 }
4788
4789 return rstate;
4790 }
4791
4792 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4793 {
4794 struct si_context *sctx = (struct si_context *)ctx;
4795
4796 if (sctx->sample_mask == (uint16_t)sample_mask)
4797 return;
4798
4799 sctx->sample_mask = sample_mask;
4800 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4801 }
4802
4803 static void si_emit_sample_mask(struct si_context *sctx)
4804 {
4805 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4806 unsigned mask = sctx->sample_mask;
4807
4808 /* Needed for line and polygon smoothing as well as for the Polaris
4809 * small primitive filter. We expect the state tracker to take care of
4810 * this for us.
4811 */
4812 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4813 (mask & 1 && sctx->blitter->running));
4814
4815 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4816 radeon_emit(cs, mask | (mask << 16));
4817 radeon_emit(cs, mask | (mask << 16));
4818 }
4819
4820 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4821 {
4822 #ifndef NDEBUG
4823 struct si_sampler_state *s = state;
4824
4825 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4826 s->magic = 0;
4827 #endif
4828 free(state);
4829 }
4830
4831 /*
4832 * Vertex elements & buffers
4833 */
4834
4835 struct si_fast_udiv_info32
4836 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4837 {
4838 struct util_fast_udiv_info info =
4839 util_compute_fast_udiv_info(D, num_bits, 32);
4840
4841 struct si_fast_udiv_info32 result = {
4842 info.multiplier,
4843 info.pre_shift,
4844 info.post_shift,
4845 info.increment,
4846 };
4847 return result;
4848 }
4849
4850 static void *si_create_vertex_elements(struct pipe_context *ctx,
4851 unsigned count,
4852 const struct pipe_vertex_element *elements)
4853 {
4854 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4855 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4856 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4857 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4858 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4859 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4860 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4861 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4862 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4863 int i;
4864
4865 assert(count <= SI_MAX_ATTRIBS);
4866 if (!v)
4867 return NULL;
4868
4869 v->count = count;
4870
4871 unsigned alloc_count = count > sscreen->num_vbos_in_user_sgprs ?
4872 count - sscreen->num_vbos_in_user_sgprs : 0;
4873 v->vb_desc_list_alloc_size = align(alloc_count * 16, SI_CPDMA_ALIGNMENT);
4874
4875 for (i = 0; i < count; ++i) {
4876 const struct util_format_description *desc;
4877 const struct util_format_channel_description *channel;
4878 int first_non_void;
4879 unsigned vbo_index = elements[i].vertex_buffer_index;
4880
4881 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4882 FREE(v);
4883 return NULL;
4884 }
4885
4886 unsigned instance_divisor = elements[i].instance_divisor;
4887 if (instance_divisor) {
4888 v->uses_instance_divisors = true;
4889
4890 if (instance_divisor == 1) {
4891 v->instance_divisor_is_one |= 1u << i;
4892 } else {
4893 v->instance_divisor_is_fetched |= 1u << i;
4894 divisor_factors[i] =
4895 si_compute_fast_udiv_info32(instance_divisor, 32);
4896 }
4897 }
4898
4899 if (!used[vbo_index]) {
4900 v->first_vb_use_mask |= 1 << i;
4901 used[vbo_index] = true;
4902 }
4903
4904 desc = util_format_description(elements[i].src_format);
4905 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4906 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4907
4908 v->format_size[i] = desc->block.bits / 8;
4909 v->src_offset[i] = elements[i].src_offset;
4910 v->vertex_buffer_index[i] = vbo_index;
4911
4912 bool always_fix = false;
4913 union si_vs_fix_fetch fix_fetch;
4914 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4915
4916 fix_fetch.bits = 0;
4917 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4918
4919 if (channel) {
4920 switch (channel->type) {
4921 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4922 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4923 case UTIL_FORMAT_TYPE_SIGNED: {
4924 if (channel->pure_integer)
4925 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4926 else if (channel->normalized)
4927 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4928 else
4929 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4930 break;
4931 }
4932 case UTIL_FORMAT_TYPE_UNSIGNED: {
4933 if (channel->pure_integer)
4934 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4935 else if (channel->normalized)
4936 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4937 else
4938 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4939 break;
4940 }
4941 default: unreachable("bad format type");
4942 }
4943 } else {
4944 switch (elements[i].src_format) {
4945 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4946 default: unreachable("bad other format");
4947 }
4948 }
4949
4950 if (desc->channel[0].size == 10) {
4951 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4952 log_hw_load_size = 2;
4953
4954 /* The hardware always treats the 2-bit alpha channel as
4955 * unsigned, so a shader workaround is needed. The affected
4956 * chips are GFX8 and older except Stoney (GFX8.1).
4957 */
4958 always_fix = sscreen->info.chip_class <= GFX8 &&
4959 sscreen->info.family != CHIP_STONEY &&
4960 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4961 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4962 fix_fetch.u.log_size = 3; /* special encoding */
4963 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4964 log_hw_load_size = 2;
4965 } else {
4966 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4967 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4968
4969 /* Always fix up:
4970 * - doubles (multiple loads + truncate to float)
4971 * - 32-bit requiring a conversion
4972 */
4973 always_fix =
4974 (fix_fetch.u.log_size == 3) ||
4975 (fix_fetch.u.log_size == 2 &&
4976 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4977 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4978 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4979
4980 /* Also fixup 8_8_8 and 16_16_16. */
4981 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4982 always_fix = true;
4983 log_hw_load_size = fix_fetch.u.log_size;
4984 }
4985 }
4986
4987 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4988 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4989 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4990 fix_fetch.u.reverse = 1;
4991 }
4992
4993 /* Force the workaround for unaligned access here already if the
4994 * offset relative to the vertex buffer base is unaligned.
4995 *
4996 * There is a theoretical case in which this is too conservative:
4997 * if the vertex buffer's offset is also unaligned in just the
4998 * right way, we end up with an aligned address after all.
4999 * However, this case should be extremely rare in practice (it
5000 * won't happen in well-behaved applications), and taking it
5001 * into account would complicate the fast path (where everything
5002 * is nicely aligned).
5003 */
5004 bool check_alignment =
5005 log_hw_load_size >= 1 &&
5006 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
5007 bool opencode = sscreen->options.vs_fetch_always_opencode;
5008
5009 if (check_alignment &&
5010 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
5011 opencode = true;
5012
5013 if (always_fix || check_alignment || opencode)
5014 v->fix_fetch[i] = fix_fetch.bits;
5015
5016 if (opencode)
5017 v->fix_fetch_opencode |= 1 << i;
5018 if (opencode || always_fix)
5019 v->fix_fetch_always |= 1 << i;
5020
5021 if (check_alignment && !opencode) {
5022 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
5023
5024 v->fix_fetch_unaligned |= 1 << i;
5025 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
5026 v->vb_alignment_check_mask |= 1 << vbo_index;
5027 }
5028
5029 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
5030 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
5031 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
5032 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
5033
5034 if (sscreen->info.chip_class >= GFX10) {
5035 const struct gfx10_format *fmt =
5036 &gfx10_format_table[elements[i].src_format];
5037 assert(fmt->img_format != 0 && fmt->img_format < 128);
5038 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
5039 S_008F0C_RESOURCE_LEVEL(1);
5040 } else {
5041 unsigned data_format, num_format;
5042 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
5043 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
5044 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
5045 S_008F0C_DATA_FORMAT(data_format);
5046 }
5047 }
5048
5049 if (v->instance_divisor_is_fetched) {
5050 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
5051
5052 v->instance_divisor_factor_buffer =
5053 (struct si_resource*)
5054 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
5055 num_divisors * sizeof(divisor_factors[0]));
5056 if (!v->instance_divisor_factor_buffer) {
5057 FREE(v);
5058 return NULL;
5059 }
5060 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
5061 NULL, PIPE_TRANSFER_WRITE);
5062 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
5063 }
5064 return v;
5065 }
5066
5067 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5068 {
5069 struct si_context *sctx = (struct si_context *)ctx;
5070 struct si_vertex_elements *old = sctx->vertex_elements;
5071 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5072
5073 sctx->vertex_elements = v;
5074 sctx->num_vertex_elements = v ? v->count : 0;
5075
5076 if (sctx->num_vertex_elements) {
5077 sctx->vertex_buffers_dirty = true;
5078 } else {
5079 sctx->vertex_buffer_pointer_dirty = false;
5080 sctx->vertex_buffer_user_sgprs_dirty = false;
5081 }
5082
5083 if (v &&
5084 (!old ||
5085 old->count != v->count ||
5086 old->uses_instance_divisors != v->uses_instance_divisors ||
5087 /* we don't check which divisors changed */
5088 v->uses_instance_divisors ||
5089 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
5090 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5091 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
5092 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
5093 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5094 * functions of fix_fetch and the src_offset alignment.
5095 * If they change and fix_fetch doesn't, it must be due to different
5096 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5097 old->fix_fetch_opencode != v->fix_fetch_opencode ||
5098 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
5099 sctx->do_update_shaders = true;
5100
5101 if (v && v->instance_divisor_is_fetched) {
5102 struct pipe_constant_buffer cb;
5103
5104 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5105 cb.user_buffer = NULL;
5106 cb.buffer_offset = 0;
5107 cb.buffer_size = 0xffffffff;
5108 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5109 }
5110 }
5111
5112 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5113 {
5114 struct si_context *sctx = (struct si_context *)ctx;
5115 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5116
5117 if (sctx->vertex_elements == state) {
5118 sctx->vertex_elements = NULL;
5119 sctx->num_vertex_elements = 0;
5120 }
5121 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
5122 FREE(state);
5123 }
5124
5125 static void si_set_vertex_buffers(struct pipe_context *ctx,
5126 unsigned start_slot, unsigned count,
5127 const struct pipe_vertex_buffer *buffers)
5128 {
5129 struct si_context *sctx = (struct si_context *)ctx;
5130 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5131 unsigned updated_mask = u_bit_consecutive(start_slot, count);
5132 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5133 uint32_t unaligned = 0;
5134 int i;
5135
5136 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
5137
5138 if (buffers) {
5139 for (i = 0; i < count; i++) {
5140 const struct pipe_vertex_buffer *src = buffers + i;
5141 struct pipe_vertex_buffer *dsti = dst + i;
5142 struct pipe_resource *buf = src->buffer.resource;
5143 unsigned slot_bit = 1 << (start_slot + i);
5144
5145 pipe_resource_reference(&dsti->buffer.resource, buf);
5146 dsti->buffer_offset = src->buffer_offset;
5147 dsti->stride = src->stride;
5148
5149 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5150 unaligned |= slot_bit;
5151
5152 si_context_add_resource_size(sctx, buf);
5153 if (buf)
5154 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
5155 }
5156 } else {
5157 for (i = 0; i < count; i++) {
5158 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5159 }
5160 unaligned &= ~updated_mask;
5161 }
5162 sctx->vertex_buffers_dirty = true;
5163 sctx->vertex_buffer_unaligned = (orig_unaligned & ~updated_mask) | unaligned;
5164
5165 /* Check whether alignment may have changed in a way that requires
5166 * shader changes. This check is conservative: a vertex buffer can only
5167 * trigger a shader change if the misalignment amount changes (e.g.
5168 * from byte-aligned to short-aligned), but we only keep track of
5169 * whether buffers are at least dword-aligned, since that should always
5170 * be the case in well-behaved applications anyway.
5171 */
5172 if (sctx->vertex_elements &&
5173 (sctx->vertex_elements->vb_alignment_check_mask &
5174 (unaligned | orig_unaligned) & updated_mask))
5175 sctx->do_update_shaders = true;
5176 }
5177
5178 /*
5179 * Misc
5180 */
5181
5182 static void si_set_tess_state(struct pipe_context *ctx,
5183 const float default_outer_level[4],
5184 const float default_inner_level[2])
5185 {
5186 struct si_context *sctx = (struct si_context *)ctx;
5187 struct pipe_constant_buffer cb;
5188 float array[8];
5189
5190 memcpy(array, default_outer_level, sizeof(float) * 4);
5191 memcpy(array+4, default_inner_level, sizeof(float) * 2);
5192
5193 cb.buffer = NULL;
5194 cb.user_buffer = NULL;
5195 cb.buffer_size = sizeof(array);
5196
5197 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
5198 (void*)array, sizeof(array),
5199 &cb.buffer_offset);
5200
5201 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5202 pipe_resource_reference(&cb.buffer, NULL);
5203 }
5204
5205 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5206 {
5207 struct si_context *sctx = (struct si_context *)ctx;
5208
5209 si_update_fb_dirtiness_after_rendering(sctx);
5210
5211 /* Multisample surfaces are flushed in si_decompress_textures. */
5212 if (sctx->framebuffer.uncompressed_cb_mask) {
5213 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5214 sctx->framebuffer.CB_has_shader_readable_metadata,
5215 sctx->framebuffer.all_DCC_pipe_aligned);
5216 }
5217 }
5218
5219 /* This only ensures coherency for shader image/buffer stores. */
5220 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5221 {
5222 struct si_context *sctx = (struct si_context *)ctx;
5223
5224 if (!(flags & ~PIPE_BARRIER_UPDATE))
5225 return;
5226
5227 /* Subsequent commands must wait for all shader invocations to
5228 * complete. */
5229 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
5230 SI_CONTEXT_CS_PARTIAL_FLUSH;
5231
5232 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5233 sctx->flags |= SI_CONTEXT_INV_SCACHE |
5234 SI_CONTEXT_INV_VCACHE;
5235
5236 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
5237 PIPE_BARRIER_SHADER_BUFFER |
5238 PIPE_BARRIER_TEXTURE |
5239 PIPE_BARRIER_IMAGE |
5240 PIPE_BARRIER_STREAMOUT_BUFFER |
5241 PIPE_BARRIER_GLOBAL_BUFFER)) {
5242 /* As far as I can tell, L1 contents are written back to L2
5243 * automatically at end of shader, but the contents of other
5244 * L1 caches might still be stale. */
5245 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5246 }
5247
5248 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5249 /* Indices are read through TC L2 since GFX8.
5250 * L1 isn't used.
5251 */
5252 if (sctx->screen->info.chip_class <= GFX7)
5253 sctx->flags |= SI_CONTEXT_WB_L2;
5254 }
5255
5256 /* MSAA color, any depth and any stencil are flushed in
5257 * si_decompress_textures when needed.
5258 */
5259 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
5260 sctx->framebuffer.uncompressed_cb_mask) {
5261 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5262
5263 if (sctx->chip_class <= GFX8)
5264 sctx->flags |= SI_CONTEXT_WB_L2;
5265 }
5266
5267 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5268 if (sctx->screen->info.chip_class <= GFX8 &&
5269 flags & PIPE_BARRIER_INDIRECT_BUFFER)
5270 sctx->flags |= SI_CONTEXT_WB_L2;
5271 }
5272
5273 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5274 {
5275 struct pipe_blend_state blend;
5276
5277 memset(&blend, 0, sizeof(blend));
5278 blend.independent_blend_enable = true;
5279 blend.rt[0].colormask = 0xf;
5280 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5281 }
5282
5283 static void si_init_config(struct si_context *sctx);
5284
5285 void si_init_state_compute_functions(struct si_context *sctx)
5286 {
5287 sctx->b.create_sampler_state = si_create_sampler_state;
5288 sctx->b.delete_sampler_state = si_delete_sampler_state;
5289 sctx->b.create_sampler_view = si_create_sampler_view;
5290 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5291 sctx->b.memory_barrier = si_memory_barrier;
5292 }
5293
5294 void si_init_state_functions(struct si_context *sctx)
5295 {
5296 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5297 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5298 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5299 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5300 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5301 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5302 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5303 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5304 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5305 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5306 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5307
5308 sctx->b.create_blend_state = si_create_blend_state;
5309 sctx->b.bind_blend_state = si_bind_blend_state;
5310 sctx->b.delete_blend_state = si_delete_blend_state;
5311 sctx->b.set_blend_color = si_set_blend_color;
5312
5313 sctx->b.create_rasterizer_state = si_create_rs_state;
5314 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5315 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5316
5317 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5318 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5319 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5320
5321 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5322 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5323 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5324 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5325 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5326
5327 sctx->b.set_clip_state = si_set_clip_state;
5328 sctx->b.set_stencil_ref = si_set_stencil_ref;
5329
5330 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5331
5332 sctx->b.set_sample_mask = si_set_sample_mask;
5333
5334 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5335 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5336 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5337 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5338
5339 sctx->b.texture_barrier = si_texture_barrier;
5340 sctx->b.set_min_samples = si_set_min_samples;
5341 sctx->b.set_tess_state = si_set_tess_state;
5342
5343 sctx->b.set_active_query_state = si_set_active_query_state;
5344
5345 si_init_config(sctx);
5346 }
5347
5348 void si_init_screen_state_functions(struct si_screen *sscreen)
5349 {
5350 sscreen->b.is_format_supported = si_is_format_supported;
5351
5352 if (sscreen->info.chip_class >= GFX10) {
5353 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5354 } else {
5355 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5356 }
5357 }
5358
5359 static void si_set_grbm_gfx_index(struct si_context *sctx,
5360 struct si_pm4_state *pm4, unsigned value)
5361 {
5362 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
5363 R_00802C_GRBM_GFX_INDEX;
5364 si_pm4_set_reg(pm4, reg, value);
5365 }
5366
5367 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
5368 struct si_pm4_state *pm4, unsigned se)
5369 {
5370 assert(se == ~0 || se < sctx->screen->info.max_se);
5371 si_set_grbm_gfx_index(sctx, pm4,
5372 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5373 S_030800_SE_INDEX(se)) |
5374 S_030800_SH_BROADCAST_WRITES(1) |
5375 S_030800_INSTANCE_BROADCAST_WRITES(1));
5376 }
5377
5378 static void
5379 si_write_harvested_raster_configs(struct si_context *sctx,
5380 struct si_pm4_state *pm4,
5381 unsigned raster_config,
5382 unsigned raster_config_1)
5383 {
5384 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5385 unsigned raster_config_se[4];
5386 unsigned se;
5387
5388 ac_get_harvested_configs(&sctx->screen->info,
5389 raster_config,
5390 &raster_config_1,
5391 raster_config_se);
5392
5393 for (se = 0; se < num_se; se++) {
5394 si_set_grbm_gfx_index_se(sctx, pm4, se);
5395 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5396 }
5397 si_set_grbm_gfx_index(sctx, pm4, ~0);
5398
5399 if (sctx->chip_class >= GFX7) {
5400 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5401 }
5402 }
5403
5404 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5405 {
5406 struct si_screen *sscreen = sctx->screen;
5407 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
5408 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5409 unsigned raster_config = sscreen->pa_sc_raster_config;
5410 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5411
5412 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5413 /* Always use the default config when all backends are enabled
5414 * (or when we failed to determine the enabled backends).
5415 */
5416 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5417 raster_config);
5418 if (sctx->chip_class >= GFX7)
5419 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5420 raster_config_1);
5421 } else {
5422 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5423 }
5424 }
5425
5426 static void si_init_config(struct si_context *sctx)
5427 {
5428 struct si_screen *sscreen = sctx->screen;
5429 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5430 bool has_clear_state = sscreen->info.has_clear_state;
5431 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5432
5433 if (!pm4)
5434 return;
5435
5436 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5437 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5438 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5439 si_pm4_cmd_end(pm4, false);
5440
5441 if (has_clear_state) {
5442 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5443 si_pm4_cmd_add(pm4, 0);
5444 si_pm4_cmd_end(pm4, false);
5445 }
5446
5447 if (sctx->chip_class <= GFX8)
5448 si_set_raster_config(sctx, pm4);
5449
5450 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5451 if (!has_clear_state)
5452 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5453
5454 /* FIXME calculate these values somehow ??? */
5455 if (sctx->chip_class <= GFX8) {
5456 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5457 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5458 }
5459
5460 if (!has_clear_state) {
5461 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5462 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5463 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5464 }
5465
5466 if (sscreen->info.chip_class <= GFX9)
5467 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5468 if (!has_clear_state)
5469 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5470 if (sctx->chip_class < GFX7)
5471 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5472 S_008A14_CLIP_VTX_REORDER_ENA(1));
5473
5474 /* CLEAR_STATE doesn't restore these correctly. */
5475 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5476 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5477 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5478
5479 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5480 * I don't know why. Deduced by trial and error.
5481 */
5482 if (sctx->chip_class <= GFX7 || !has_clear_state) {
5483 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5484 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5485 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5486 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5487 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5488 }
5489
5490 if (!has_clear_state) {
5491 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5492 S_028230_ER_TRI(0xA) |
5493 S_028230_ER_POINT(0xA) |
5494 S_028230_ER_RECT(0xA) |
5495 /* Required by DX10_DIAMOND_TEST_ENA: */
5496 S_028230_ER_LINE_LR(0x1A) |
5497 S_028230_ER_LINE_RL(0x26) |
5498 S_028230_ER_LINE_TB(0xA) |
5499 S_028230_ER_LINE_BT(0xA));
5500 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5501 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5502 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5503 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5504 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5505 }
5506
5507 if (sctx->chip_class >= GFX10) {
5508 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
5509 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5510 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5511 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5512 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
5513 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
5514 } else if (sctx->chip_class == GFX9) {
5515 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5516 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5517 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5518 } else {
5519 /* These registers, when written, also overwrite the CLEAR_STATE
5520 * context, so we can't rely on CLEAR_STATE setting them.
5521 * It would be an issue if there was another UMD changing them.
5522 */
5523 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5524 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5525 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5526 }
5527
5528 if (sctx->chip_class >= GFX7) {
5529 if (sctx->chip_class >= GFX10) {
5530 /* Logical CUs 16 - 31 */
5531 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
5532 S_00B404_CU_EN(0xffff));
5533 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
5534 S_00B104_CU_EN(0xffff));
5535 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
5536 S_00B004_CU_EN(0xffff));
5537 }
5538
5539 if (sctx->chip_class >= GFX9) {
5540 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5541 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5542 } else {
5543 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5544 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5545 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5546 S_00B41C_WAVE_LIMIT(0x3F));
5547 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5548 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5549
5550 /* If this is 0, Bonaire can hang even if GS isn't being used.
5551 * Other chips are unaffected. These are suboptimal values,
5552 * but we don't use on-chip GS.
5553 */
5554 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5555 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5556 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5557 }
5558
5559 /* Compute LATE_ALLOC_VS.LIMIT. */
5560 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5561 unsigned late_alloc_wave64 = 0; /* The limit is per SH. */
5562 unsigned cu_mask_vs = 0xffff;
5563 unsigned cu_mask_gs = 0xffff;
5564
5565 if (sctx->chip_class >= GFX10) {
5566 /* For Wave32, the hw will launch twice the number of late
5567 * alloc waves, so 1 == 2x wave32.
5568 */
5569 if (num_cu_per_sh <= 6) {
5570 late_alloc_wave64 = num_cu_per_sh - 2;
5571 } else {
5572 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
5573
5574 /* CU2 & CU3 disabled because of the dual CU design */
5575 /* Late alloc is not used for NGG on Navi14 due to a hw bug. */
5576 cu_mask_vs = 0xfff3;
5577 cu_mask_gs = sscreen->use_ngg &&
5578 sctx->family != CHIP_NAVI14 ? 0xfff3 : 0xffff;
5579 }
5580 } else {
5581 if (sctx->family == CHIP_KABINI) {
5582 late_alloc_wave64 = 0; /* Potential hang on Kabini. */
5583 } else if (num_cu_per_sh <= 4) {
5584 /* Too few available compute units per SH. Disallowing
5585 * VS to run on one CU could hurt us more than late VS
5586 * allocation would help.
5587 *
5588 * 2 is the highest safe number that allows us to keep
5589 * all CUs enabled.
5590 */
5591 late_alloc_wave64 = 2;
5592 } else {
5593 /* This is a good initial value, allowing 1 late_alloc
5594 * wave per SIMD on num_cu - 2.
5595 */
5596 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
5597 }
5598
5599 if (late_alloc_wave64 > 2)
5600 cu_mask_vs = 0xfffe; /* 1 CU disabled */
5601 }
5602
5603 /* VS can't execute on one CU if the limit is > 2. */
5604 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5605 S_00B118_CU_EN(cu_mask_vs) |
5606 S_00B118_WAVE_LIMIT(0x3F));
5607 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5608 S_00B11C_LIMIT(late_alloc_wave64));
5609
5610 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5611 S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
5612
5613 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5614 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5615 }
5616
5617 if (sctx->chip_class >= GFX10) {
5618 /* Break up a pixel wave if it contains deallocs for more than
5619 * half the parameter cache.
5620 *
5621 * To avoid a deadlock where pixel waves aren't launched
5622 * because they're waiting for more pixels while the frontend
5623 * is stuck waiting for PC space, the maximum allowed value is
5624 * the size of the PC minus the largest possible allocation for
5625 * a single primitive shader subgroup.
5626 */
5627 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5628 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5629 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5630
5631 if (!has_clear_state) {
5632 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5633 sscreen->info.pa_sc_tile_steering_override);
5634 }
5635
5636 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
5637 unsigned meta_write_policy, meta_read_policy;
5638 /* TODO: investigate whether LRU improves performance on other chips too */
5639 if (sscreen->info.num_render_backends <= 4) {
5640 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
5641 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
5642 } else {
5643 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
5644 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
5645 }
5646
5647 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5648 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5649 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5650 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
5651 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5652 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5653 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5654 S_02807C_HTILE_RD_POLICY(meta_read_policy));
5655
5656 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5657 S_028410_CMASK_WR_POLICY(meta_write_policy) |
5658 S_028410_FMASK_WR_POLICY(meta_write_policy) |
5659 S_028410_DCC_WR_POLICY(meta_write_policy) |
5660 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5661 S_028410_CMASK_RD_POLICY(meta_read_policy) |
5662 S_028410_FMASK_RD_POLICY(meta_read_policy) |
5663 S_028410_DCC_RD_POLICY(meta_read_policy) |
5664 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
5665 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
5666
5667 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
5668 S_00B0C0_SOFT_GROUPING_EN(1) |
5669 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5670 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
5671 }
5672
5673 if (sctx->chip_class >= GFX9) {
5674 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
5675 S_028B50_ACCUM_ISOLINE(40) |
5676 S_028B50_ACCUM_TRI(30) |
5677 S_028B50_ACCUM_QUAD(24) |
5678 S_028B50_DONUT_SPLIT(24) |
5679 S_028B50_TRAP_SPLIT(6));
5680 } else if (sctx->chip_class >= GFX8) {
5681 unsigned vgt_tess_distribution;
5682
5683 vgt_tess_distribution =
5684 S_028B50_ACCUM_ISOLINE(32) |
5685 S_028B50_ACCUM_TRI(11) |
5686 S_028B50_ACCUM_QUAD(11) |
5687 S_028B50_DONUT_SPLIT(16);
5688
5689 /* Testing with Unigine Heaven extreme tesselation yielded best results
5690 * with TRAP_SPLIT = 3.
5691 */
5692 if (sctx->family == CHIP_FIJI ||
5693 sctx->family >= CHIP_POLARIS10)
5694 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5695
5696 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5697 } else if (!has_clear_state) {
5698 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5699 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5700 }
5701
5702 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5703 if (sctx->chip_class >= GFX7) {
5704 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5705 S_028084_ADDRESS(border_color_va >> 40));
5706 }
5707 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5708 RADEON_PRIO_BORDER_COLORS);
5709
5710 if (sctx->chip_class >= GFX9) {
5711 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5712 S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) |
5713 S_028C48_MAX_PRIM_PER_BATCH(1023));
5714 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5715 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5716 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5717 }
5718
5719 si_pm4_upload_indirect_buffer(sctx, pm4);
5720 sctx->init_config = pm4;
5721 }