projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX, inline other fields
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_helpers.h"
38 #include "util/u_memory.h"
39
40 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
41 void (*emit)(struct si_context *ctx, struct r600_atom *state),
42 unsigned num_dw)
43 {
44 atom->emit = (void*)emit;
45 atom->num_dw = num_dw;
46 atom->dirty = false;
47 *list_elem = atom;
48 }
49
50 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
51 {
52 if (sscreen->b.chip_class == CIK &&
53 sscreen->b.info.cik_macrotile_mode_array_valid) {
54 unsigned index, tileb;
55
56 tileb = 8 * 8 * tex->surface.bpe;
57 tileb = MIN2(tex->surface.tile_split, tileb);
58
59 for (index = 0; tileb > 64; index++) {
60 tileb >>= 1;
61 }
62 assert(index < 16);
63
64 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
65 }
66
67 if (sscreen->b.chip_class == SI &&
68 sscreen->b.info.si_tile_mode_array_valid) {
69 /* Don't use stencil_tiling_index, because num_banks is always
70 * read from the depth mode. */
71 unsigned tile_mode_index = tex->surface.tiling_index[0];
72 assert(tile_mode_index < 32);
73
74 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
75 }
76
77 /* The old way. */
78 switch (sscreen->b.tiling_info.num_banks) {
79 case 2:
80 return V_02803C_ADDR_SURF_2_BANK;
81 case 4:
82 return V_02803C_ADDR_SURF_4_BANK;
83 case 8:
84 default:
85 return V_02803C_ADDR_SURF_8_BANK;
86 case 16:
87 return V_02803C_ADDR_SURF_16_BANK;
88 }
89 }
90
91 unsigned cik_tile_split(unsigned tile_split)
92 {
93 switch (tile_split) {
94 case 64:
95 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
96 break;
97 case 128:
98 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
99 break;
100 case 256:
101 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
102 break;
103 case 512:
104 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
105 break;
106 default:
107 case 1024:
108 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
109 break;
110 case 2048:
111 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
112 break;
113 case 4096:
114 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
115 break;
116 }
117 return tile_split;
118 }
119
120 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
121 {
122 switch (macro_tile_aspect) {
123 default:
124 case 1:
125 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
126 break;
127 case 2:
128 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
129 break;
130 case 4:
131 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
132 break;
133 case 8:
134 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
135 break;
136 }
137 return macro_tile_aspect;
138 }
139
140 unsigned cik_bank_wh(unsigned bankwh)
141 {
142 switch (bankwh) {
143 default:
144 case 1:
145 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
146 break;
147 case 2:
148 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
149 break;
150 case 4:
151 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
152 break;
153 case 8:
154 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
155 break;
156 }
157 return bankwh;
158 }
159
160 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
161 {
162 if (sscreen->b.info.si_tile_mode_array_valid) {
163 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
164
165 return G_009910_PIPE_CONFIG(gb_tile_mode);
166 }
167
168 /* This is probably broken for a lot of chips, but it's only used
169 * if the kernel cannot return the tile mode array for CIK. */
170 switch (sscreen->b.info.r600_num_tile_pipes) {
171 case 16:
172 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
173 case 8:
174 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
175 case 4:
176 default:
177 if (sscreen->b.info.r600_num_backends == 4)
178 return V_02803C_X_ADDR_SURF_P4_16X16;
179 else
180 return V_02803C_X_ADDR_SURF_P4_8X16;
181 case 2:
182 return V_02803C_ADDR_SURF_P2;
183 }
184 }
185
186 static unsigned si_map_swizzle(unsigned swizzle)
187 {
188 switch (swizzle) {
189 case UTIL_FORMAT_SWIZZLE_Y:
190 return V_008F0C_SQ_SEL_Y;
191 case UTIL_FORMAT_SWIZZLE_Z:
192 return V_008F0C_SQ_SEL_Z;
193 case UTIL_FORMAT_SWIZZLE_W:
194 return V_008F0C_SQ_SEL_W;
195 case UTIL_FORMAT_SWIZZLE_0:
196 return V_008F0C_SQ_SEL_0;
197 case UTIL_FORMAT_SWIZZLE_1:
198 return V_008F0C_SQ_SEL_1;
199 default: /* UTIL_FORMAT_SWIZZLE_X */
200 return V_008F0C_SQ_SEL_X;
201 }
202 }
203
204 static uint32_t S_FIXED(float value, uint32_t frac_bits)
205 {
206 return value * (1 << frac_bits);
207 }
208
209 /* 12.4 fixed-point */
210 static unsigned si_pack_float_12p4(float x)
211 {
212 return x <= 0 ? 0 :
213 x >= 4096 ? 0xffff : x * 16;
214 }
215
216 /*
217 * inferred framebuffer and blender state
218 */
219 static void si_update_fb_blend_state(struct si_context *sctx)
220 {
221 struct si_pm4_state *pm4;
222 struct si_state_blend *blend = sctx->queued.named.blend;
223 uint32_t mask;
224
225 if (blend == NULL)
226 return;
227
228 pm4 = si_pm4_alloc_state(sctx);
229 if (pm4 == NULL)
230 return;
231
232 mask = (1ULL << ((unsigned)sctx->framebuffer.state.nr_cbufs * 4)) - 1;
233 mask &= blend->cb_target_mask;
234 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
235
236 si_pm4_set_state(sctx, fb_blend, pm4);
237 }
238
239 /*
240 * Blender functions
241 */
242
243 static uint32_t si_translate_blend_function(int blend_func)
244 {
245 switch (blend_func) {
246 case PIPE_BLEND_ADD:
247 return V_028780_COMB_DST_PLUS_SRC;
248 case PIPE_BLEND_SUBTRACT:
249 return V_028780_COMB_SRC_MINUS_DST;
250 case PIPE_BLEND_REVERSE_SUBTRACT:
251 return V_028780_COMB_DST_MINUS_SRC;
252 case PIPE_BLEND_MIN:
253 return V_028780_COMB_MIN_DST_SRC;
254 case PIPE_BLEND_MAX:
255 return V_028780_COMB_MAX_DST_SRC;
256 default:
257 R600_ERR("Unknown blend function %d\n", blend_func);
258 assert(0);
259 break;
260 }
261 return 0;
262 }
263
264 static uint32_t si_translate_blend_factor(int blend_fact)
265 {
266 switch (blend_fact) {
267 case PIPE_BLENDFACTOR_ONE:
268 return V_028780_BLEND_ONE;
269 case PIPE_BLENDFACTOR_SRC_COLOR:
270 return V_028780_BLEND_SRC_COLOR;
271 case PIPE_BLENDFACTOR_SRC_ALPHA:
272 return V_028780_BLEND_SRC_ALPHA;
273 case PIPE_BLENDFACTOR_DST_ALPHA:
274 return V_028780_BLEND_DST_ALPHA;
275 case PIPE_BLENDFACTOR_DST_COLOR:
276 return V_028780_BLEND_DST_COLOR;
277 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
278 return V_028780_BLEND_SRC_ALPHA_SATURATE;
279 case PIPE_BLENDFACTOR_CONST_COLOR:
280 return V_028780_BLEND_CONSTANT_COLOR;
281 case PIPE_BLENDFACTOR_CONST_ALPHA:
282 return V_028780_BLEND_CONSTANT_ALPHA;
283 case PIPE_BLENDFACTOR_ZERO:
284 return V_028780_BLEND_ZERO;
285 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
286 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
287 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
288 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
289 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
290 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
291 case PIPE_BLENDFACTOR_INV_DST_COLOR:
292 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
293 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
294 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
295 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
296 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
297 case PIPE_BLENDFACTOR_SRC1_COLOR:
298 return V_028780_BLEND_SRC1_COLOR;
299 case PIPE_BLENDFACTOR_SRC1_ALPHA:
300 return V_028780_BLEND_SRC1_ALPHA;
301 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
302 return V_028780_BLEND_INV_SRC1_COLOR;
303 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
304 return V_028780_BLEND_INV_SRC1_ALPHA;
305 default:
306 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
307 assert(0);
308 break;
309 }
310 return 0;
311 }
312
313 static void *si_create_blend_state_mode(struct pipe_context *ctx,
314 const struct pipe_blend_state *state,
315 unsigned mode)
316 {
317 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
318 struct si_pm4_state *pm4 = &blend->pm4;
319
320 uint32_t color_control = 0;
321
322 if (blend == NULL)
323 return NULL;
324
325 blend->alpha_to_one = state->alpha_to_one;
326
327 if (state->logicop_enable) {
328 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
329 } else {
330 color_control |= S_028808_ROP3(0xcc);
331 }
332
333 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
334 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
335 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
336 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
337 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
338 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
339
340 blend->cb_target_mask = 0;
341 for (int i = 0; i < 8; i++) {
342 /* state->rt entries > 0 only written if independent blending */
343 const int j = state->independent_blend_enable ? i : 0;
344
345 unsigned eqRGB = state->rt[j].rgb_func;
346 unsigned srcRGB = state->rt[j].rgb_src_factor;
347 unsigned dstRGB = state->rt[j].rgb_dst_factor;
348 unsigned eqA = state->rt[j].alpha_func;
349 unsigned srcA = state->rt[j].alpha_src_factor;
350 unsigned dstA = state->rt[j].alpha_dst_factor;
351
352 unsigned blend_cntl = 0;
353
354 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
355 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
356
357 if (!state->rt[j].blend_enable) {
358 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
359 continue;
360 }
361
362 blend_cntl |= S_028780_ENABLE(1);
363 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
364 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
365 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
366
367 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
368 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
369 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
370 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
371 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
372 }
373 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
374 }
375
376 if (blend->cb_target_mask) {
377 color_control |= S_028808_MODE(mode);
378 } else {
379 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
380 }
381 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
382
383 return blend;
384 }
385
386 static void *si_create_blend_state(struct pipe_context *ctx,
387 const struct pipe_blend_state *state)
388 {
389 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
390 }
391
392 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
393 {
394 struct si_context *sctx = (struct si_context *)ctx;
395 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
396 si_update_fb_blend_state(sctx);
397 }
398
399 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
400 {
401 struct si_context *sctx = (struct si_context *)ctx;
402 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
403 }
404
405 static void si_set_blend_color(struct pipe_context *ctx,
406 const struct pipe_blend_color *state)
407 {
408 struct si_context *sctx = (struct si_context *)ctx;
409 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
410
411 if (pm4 == NULL)
412 return;
413
414 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
415 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
416 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
417 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
418
419 si_pm4_set_state(sctx, blend_color, pm4);
420 }
421
422 /*
423 * Clipping, scissors and viewport
424 */
425
426 static void si_set_clip_state(struct pipe_context *ctx,
427 const struct pipe_clip_state *state)
428 {
429 struct si_context *sctx = (struct si_context *)ctx;
430 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
431 struct pipe_constant_buffer cb;
432
433 if (pm4 == NULL)
434 return;
435
436 for (int i = 0; i < 6; i++) {
437 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
438 fui(state->ucp[i][0]));
439 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
440 fui(state->ucp[i][1]));
441 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
442 fui(state->ucp[i][2]));
443 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
444 fui(state->ucp[i][3]));
445 }
446
447 cb.buffer = NULL;
448 cb.user_buffer = state->ucp;
449 cb.buffer_offset = 0;
450 cb.buffer_size = 4*4*8;
451 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
452 pipe_resource_reference(&cb.buffer, NULL);
453
454 si_pm4_set_state(sctx, clip, pm4);
455 }
456
457 static void si_set_scissor_states(struct pipe_context *ctx,
458 unsigned start_slot,
459 unsigned num_scissors,
460 const struct pipe_scissor_state *state)
461 {
462 struct si_context *sctx = (struct si_context *)ctx;
463 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
464 struct si_pm4_state *pm4 = &scissor->pm4;
465
466 if (scissor == NULL)
467 return;
468
469 scissor->scissor = *state;
470 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
471 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
472 S_028250_WINDOW_OFFSET_DISABLE(1));
473 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
474 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
475
476 si_pm4_set_state(sctx, scissor, scissor);
477 }
478
479 static void si_set_viewport_states(struct pipe_context *ctx,
480 unsigned start_slot,
481 unsigned num_viewports,
482 const struct pipe_viewport_state *state)
483 {
484 struct si_context *sctx = (struct si_context *)ctx;
485 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
486 struct si_pm4_state *pm4 = &viewport->pm4;
487
488 if (viewport == NULL)
489 return;
490
491 viewport->viewport = *state;
492 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
493 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
494 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
495 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
496 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
497 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
498
499 si_pm4_set_state(sctx, viewport, viewport);
500 }
501
502 /*
503 * inferred state between framebuffer and rasterizer
504 */
505 static void si_update_fb_rs_state(struct si_context *sctx)
506 {
507 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
508 struct si_pm4_state *pm4;
509 float offset_units;
510
511 if (!rs || !sctx->framebuffer.state.zsbuf)
512 return;
513
514 offset_units = sctx->queued.named.rasterizer->offset_units;
515 switch (sctx->framebuffer.state.zsbuf->texture->format) {
516 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
517 case PIPE_FORMAT_X8Z24_UNORM:
518 case PIPE_FORMAT_Z24X8_UNORM:
519 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
520 offset_units *= 2.0f;
521 break;
522 case PIPE_FORMAT_Z32_FLOAT:
523 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
524 offset_units *= 1.0f;
525 break;
526 case PIPE_FORMAT_Z16_UNORM:
527 offset_units *= 4.0f;
528 break;
529 default:
530 return;
531 }
532
533 pm4 = si_pm4_alloc_state(sctx);
534
535 if (pm4 == NULL)
536 return;
537
538 /* FIXME some of those reg can be computed with cso */
539 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
540 fui(sctx->queued.named.rasterizer->offset_scale));
541 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
542 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
543 fui(sctx->queued.named.rasterizer->offset_scale));
544 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
545
546 si_pm4_set_state(sctx, fb_rs, pm4);
547 }
548
549 /*
550 * Rasterizer
551 */
552
553 static uint32_t si_translate_fill(uint32_t func)
554 {
555 switch(func) {
556 case PIPE_POLYGON_MODE_FILL:
557 return V_028814_X_DRAW_TRIANGLES;
558 case PIPE_POLYGON_MODE_LINE:
559 return V_028814_X_DRAW_LINES;
560 case PIPE_POLYGON_MODE_POINT:
561 return V_028814_X_DRAW_POINTS;
562 default:
563 assert(0);
564 return V_028814_X_DRAW_POINTS;
565 }
566 }
567
568 static void *si_create_rs_state(struct pipe_context *ctx,
569 const struct pipe_rasterizer_state *state)
570 {
571 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
572 struct si_pm4_state *pm4 = &rs->pm4;
573 unsigned tmp;
574 unsigned prov_vtx = 1, polygon_dual_mode;
575 float psize_min, psize_max;
576
577 if (rs == NULL) {
578 return NULL;
579 }
580
581 rs->two_side = state->light_twoside;
582 rs->multisample_enable = state->multisample;
583 rs->clip_plane_enable = state->clip_plane_enable;
584 rs->line_stipple_enable = state->line_stipple_enable;
585
586 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
587 state->fill_back != PIPE_POLYGON_MODE_FILL);
588
589 if (state->flatshade_first)
590 prov_vtx = 0;
591
592 rs->flatshade = state->flatshade;
593 rs->sprite_coord_enable = state->sprite_coord_enable;
594 rs->pa_sc_line_stipple = state->line_stipple_enable ?
595 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
596 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
597 rs->pa_su_sc_mode_cntl =
598 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
599 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
600 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
601 S_028814_FACE(!state->front_ccw) |
602 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
603 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
604 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
605 S_028814_POLY_MODE(polygon_dual_mode) |
606 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
607 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
608 rs->pa_cl_clip_cntl =
609 S_028810_PS_UCP_MODE(3) |
610 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
611 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
612 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
613 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
614
615 /* offset */
616 rs->offset_units = state->offset_units;
617 rs->offset_scale = state->offset_scale * 12.0f;
618
619 tmp = S_0286D4_FLAT_SHADE_ENA(1);
620 if (state->sprite_coord_enable) {
621 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
622 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
623 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
624 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
625 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
626 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
627 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
628 }
629 }
630 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
631
632 /* point size 12.4 fixed point */
633 tmp = (unsigned)(state->point_size * 8.0);
634 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
635
636 if (state->point_size_per_vertex) {
637 psize_min = util_get_min_point_size(state);
638 psize_max = 8192;
639 } else {
640 /* Force the point size to be as if the vertex output was disabled. */
641 psize_min = state->point_size;
642 psize_max = state->point_size;
643 }
644 /* Divide by two, because 0.5 = 1 pixel. */
645 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
646 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
647 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
648
649 tmp = (unsigned)state->line_width * 8;
650 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
651 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
652 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
653 S_028A48_MSAA_ENABLE(state->multisample) |
654 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
655
656 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
657 S_028BE4_PIX_CENTER(state->half_pixel_center) |
658 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
659
660 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
661
662 return rs;
663 }
664
665 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
666 {
667 struct si_context *sctx = (struct si_context *)ctx;
668 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
669
670 if (state == NULL)
671 return;
672
673 // TODO
674 sctx->sprite_coord_enable = rs->sprite_coord_enable;
675 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
676 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
677
678 si_pm4_bind_state(sctx, rasterizer, rs);
679 si_update_fb_rs_state(sctx);
680 }
681
682 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
683 {
684 struct si_context *sctx = (struct si_context *)ctx;
685 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
686 }
687
688 /*
689 * infeered state between dsa and stencil ref
690 */
691 static void si_update_dsa_stencil_ref(struct si_context *sctx)
692 {
693 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
694 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
695 struct si_state_dsa *dsa = sctx->queued.named.dsa;
696
697 if (pm4 == NULL)
698 return;
699
700 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
701 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
702 S_028430_STENCILMASK(dsa->valuemask[0]) |
703 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
704 S_028430_STENCILOPVAL(1));
705 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
706 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
707 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
708 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
709 S_028434_STENCILOPVAL_BF(1));
710
711 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
712 }
713
714 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
715 const struct pipe_stencil_ref *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718 sctx->stencil_ref = *state;
719 si_update_dsa_stencil_ref(sctx);
720 }
721
722
723 /*
724 * DSA
725 */
726
727 static uint32_t si_translate_stencil_op(int s_op)
728 {
729 switch (s_op) {
730 case PIPE_STENCIL_OP_KEEP:
731 return V_02842C_STENCIL_KEEP;
732 case PIPE_STENCIL_OP_ZERO:
733 return V_02842C_STENCIL_ZERO;
734 case PIPE_STENCIL_OP_REPLACE:
735 return V_02842C_STENCIL_REPLACE_TEST;
736 case PIPE_STENCIL_OP_INCR:
737 return V_02842C_STENCIL_ADD_CLAMP;
738 case PIPE_STENCIL_OP_DECR:
739 return V_02842C_STENCIL_SUB_CLAMP;
740 case PIPE_STENCIL_OP_INCR_WRAP:
741 return V_02842C_STENCIL_ADD_WRAP;
742 case PIPE_STENCIL_OP_DECR_WRAP:
743 return V_02842C_STENCIL_SUB_WRAP;
744 case PIPE_STENCIL_OP_INVERT:
745 return V_02842C_STENCIL_INVERT;
746 default:
747 R600_ERR("Unknown stencil op %d", s_op);
748 assert(0);
749 break;
750 }
751 return 0;
752 }
753
754 static void *si_create_dsa_state(struct pipe_context *ctx,
755 const struct pipe_depth_stencil_alpha_state *state)
756 {
757 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
758 struct si_pm4_state *pm4 = &dsa->pm4;
759 unsigned db_depth_control;
760 unsigned db_render_control;
761 uint32_t db_stencil_control = 0;
762
763 if (dsa == NULL) {
764 return NULL;
765 }
766
767 dsa->valuemask[0] = state->stencil[0].valuemask;
768 dsa->valuemask[1] = state->stencil[1].valuemask;
769 dsa->writemask[0] = state->stencil[0].writemask;
770 dsa->writemask[1] = state->stencil[1].writemask;
771
772 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
773 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
774 S_028800_ZFUNC(state->depth.func);
775
776 /* stencil */
777 if (state->stencil[0].enabled) {
778 db_depth_control |= S_028800_STENCIL_ENABLE(1);
779 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
780 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
781 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
782 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
783
784 if (state->stencil[1].enabled) {
785 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
786 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
787 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
788 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
789 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
790 }
791 }
792
793 /* alpha */
794 if (state->alpha.enabled) {
795 dsa->alpha_func = state->alpha.func;
796 dsa->alpha_ref = state->alpha.ref_value;
797
798 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
799 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
800 } else {
801 dsa->alpha_func = PIPE_FUNC_ALWAYS;
802 }
803
804 /* misc */
805 db_render_control = 0;
806 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
807 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
808 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
809
810 return dsa;
811 }
812
813 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
814 {
815 struct si_context *sctx = (struct si_context *)ctx;
816 struct si_state_dsa *dsa = state;
817
818 if (state == NULL)
819 return;
820
821 si_pm4_bind_state(sctx, dsa, dsa);
822 si_update_dsa_stencil_ref(sctx);
823 }
824
825 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
826 {
827 struct si_context *sctx = (struct si_context *)ctx;
828 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
829 }
830
831 static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth,
832 bool copy_stencil, int sample)
833 {
834 struct pipe_depth_stencil_alpha_state dsa;
835 struct si_state_dsa *state;
836
837 memset(&dsa, 0, sizeof(dsa));
838
839 state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
840 if (copy_depth || copy_stencil) {
841 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
842 S_028000_DEPTH_COPY(copy_depth) |
843 S_028000_STENCIL_COPY(copy_stencil) |
844 S_028000_COPY_CENTROID(1) |
845 S_028000_COPY_SAMPLE(sample));
846 } else {
847 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
848 S_028000_DEPTH_COMPRESS_DISABLE(1) |
849 S_028000_STENCIL_COMPRESS_DISABLE(1));
850 }
851
852 return state;
853 }
854
855 /*
856 * format translation
857 */
858 static uint32_t si_translate_colorformat(enum pipe_format format)
859 {
860 const struct util_format_description *desc = util_format_description(format);
861
862 #define HAS_SIZE(x,y,z,w) \
863 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
864 desc->channel[2].size == (z) && desc->channel[3].size == (w))
865
866 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
867 return V_028C70_COLOR_10_11_11;
868
869 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
870 return V_028C70_COLOR_INVALID;
871
872 switch (desc->nr_channels) {
873 case 1:
874 switch (desc->channel[0].size) {
875 case 8:
876 return V_028C70_COLOR_8;
877 case 16:
878 return V_028C70_COLOR_16;
879 case 32:
880 return V_028C70_COLOR_32;
881 }
882 break;
883 case 2:
884 if (desc->channel[0].size == desc->channel[1].size) {
885 switch (desc->channel[0].size) {
886 case 8:
887 return V_028C70_COLOR_8_8;
888 case 16:
889 return V_028C70_COLOR_16_16;
890 case 32:
891 return V_028C70_COLOR_32_32;
892 }
893 } else if (HAS_SIZE(8,24,0,0)) {
894 return V_028C70_COLOR_24_8;
895 } else if (HAS_SIZE(24,8,0,0)) {
896 return V_028C70_COLOR_8_24;
897 }
898 break;
899 case 3:
900 if (HAS_SIZE(5,6,5,0)) {
901 return V_028C70_COLOR_5_6_5;
902 } else if (HAS_SIZE(32,8,24,0)) {
903 return V_028C70_COLOR_X24_8_32_FLOAT;
904 }
905 break;
906 case 4:
907 if (desc->channel[0].size == desc->channel[1].size &&
908 desc->channel[0].size == desc->channel[2].size &&
909 desc->channel[0].size == desc->channel[3].size) {
910 switch (desc->channel[0].size) {
911 case 4:
912 return V_028C70_COLOR_4_4_4_4;
913 case 8:
914 return V_028C70_COLOR_8_8_8_8;
915 case 16:
916 return V_028C70_COLOR_16_16_16_16;
917 case 32:
918 return V_028C70_COLOR_32_32_32_32;
919 }
920 } else if (HAS_SIZE(5,5,5,1)) {
921 return V_028C70_COLOR_1_5_5_5;
922 } else if (HAS_SIZE(10,10,10,2)) {
923 return V_028C70_COLOR_2_10_10_10;
924 }
925 break;
926 }
927 return V_028C70_COLOR_INVALID;
928 }
929
930 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
931 {
932 if (SI_BIG_ENDIAN) {
933 switch(colorformat) {
934 /* 8-bit buffers. */
935 case V_028C70_COLOR_8:
936 return V_028C70_ENDIAN_NONE;
937
938 /* 16-bit buffers. */
939 case V_028C70_COLOR_5_6_5:
940 case V_028C70_COLOR_1_5_5_5:
941 case V_028C70_COLOR_4_4_4_4:
942 case V_028C70_COLOR_16:
943 case V_028C70_COLOR_8_8:
944 return V_028C70_ENDIAN_8IN16;
945
946 /* 32-bit buffers. */
947 case V_028C70_COLOR_8_8_8_8:
948 case V_028C70_COLOR_2_10_10_10:
949 case V_028C70_COLOR_8_24:
950 case V_028C70_COLOR_24_8:
951 case V_028C70_COLOR_16_16:
952 return V_028C70_ENDIAN_8IN32;
953
954 /* 64-bit buffers. */
955 case V_028C70_COLOR_16_16_16_16:
956 return V_028C70_ENDIAN_8IN16;
957
958 case V_028C70_COLOR_32_32:
959 return V_028C70_ENDIAN_8IN32;
960
961 /* 128-bit buffers. */
962 case V_028C70_COLOR_32_32_32_32:
963 return V_028C70_ENDIAN_8IN32;
964 default:
965 return V_028C70_ENDIAN_NONE; /* Unsupported. */
966 }
967 } else {
968 return V_028C70_ENDIAN_NONE;
969 }
970 }
971
972 /* Returns the size in bits of the widest component of a CB format */
973 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
974 {
975 switch(colorformat) {
976 case V_028C70_COLOR_4_4_4_4:
977 return 4;
978
979 case V_028C70_COLOR_1_5_5_5:
980 case V_028C70_COLOR_5_5_5_1:
981 return 5;
982
983 case V_028C70_COLOR_5_6_5:
984 return 6;
985
986 case V_028C70_COLOR_8:
987 case V_028C70_COLOR_8_8:
988 case V_028C70_COLOR_8_8_8_8:
989 return 8;
990
991 case V_028C70_COLOR_10_10_10_2:
992 case V_028C70_COLOR_2_10_10_10:
993 return 10;
994
995 case V_028C70_COLOR_10_11_11:
996 case V_028C70_COLOR_11_11_10:
997 return 11;
998
999 case V_028C70_COLOR_16:
1000 case V_028C70_COLOR_16_16:
1001 case V_028C70_COLOR_16_16_16_16:
1002 return 16;
1003
1004 case V_028C70_COLOR_8_24:
1005 case V_028C70_COLOR_24_8:
1006 return 24;
1007
1008 case V_028C70_COLOR_32:
1009 case V_028C70_COLOR_32_32:
1010 case V_028C70_COLOR_32_32_32_32:
1011 case V_028C70_COLOR_X24_8_32_FLOAT:
1012 return 32;
1013 }
1014
1015 assert(!"Unknown maximum component size");
1016 return 0;
1017 }
1018
1019 static uint32_t si_translate_dbformat(enum pipe_format format)
1020 {
1021 switch (format) {
1022 case PIPE_FORMAT_Z16_UNORM:
1023 return V_028040_Z_16;
1024 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1025 case PIPE_FORMAT_X8Z24_UNORM:
1026 case PIPE_FORMAT_Z24X8_UNORM:
1027 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1028 return V_028040_Z_24; /* deprecated on SI */
1029 case PIPE_FORMAT_Z32_FLOAT:
1030 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1031 return V_028040_Z_32_FLOAT;
1032 default:
1033 return V_028040_Z_INVALID;
1034 }
1035 }
1036
1037 /*
1038 * Texture translation
1039 */
1040
1041 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1042 enum pipe_format format,
1043 const struct util_format_description *desc,
1044 int first_non_void)
1045 {
1046 struct si_screen *sscreen = (struct si_screen*)screen;
1047 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1048 boolean uniform = TRUE;
1049 int i;
1050
1051 /* Colorspace (return non-RGB formats directly). */
1052 switch (desc->colorspace) {
1053 /* Depth stencil formats */
1054 case UTIL_FORMAT_COLORSPACE_ZS:
1055 switch (format) {
1056 case PIPE_FORMAT_Z16_UNORM:
1057 return V_008F14_IMG_DATA_FORMAT_16;
1058 case PIPE_FORMAT_X24S8_UINT:
1059 case PIPE_FORMAT_Z24X8_UNORM:
1060 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1061 return V_008F14_IMG_DATA_FORMAT_8_24;
1062 case PIPE_FORMAT_X8Z24_UNORM:
1063 case PIPE_FORMAT_S8X24_UINT:
1064 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1065 return V_008F14_IMG_DATA_FORMAT_24_8;
1066 case PIPE_FORMAT_S8_UINT:
1067 return V_008F14_IMG_DATA_FORMAT_8;
1068 case PIPE_FORMAT_Z32_FLOAT:
1069 return V_008F14_IMG_DATA_FORMAT_32;
1070 case PIPE_FORMAT_X32_S8X24_UINT:
1071 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1072 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1073 default:
1074 goto out_unknown;
1075 }
1076
1077 case UTIL_FORMAT_COLORSPACE_YUV:
1078 goto out_unknown; /* TODO */
1079
1080 case UTIL_FORMAT_COLORSPACE_SRGB:
1081 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1082 goto out_unknown;
1083 break;
1084
1085 default:
1086 break;
1087 }
1088
1089 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1090 if (!enable_s3tc)
1091 goto out_unknown;
1092
1093 switch (format) {
1094 case PIPE_FORMAT_RGTC1_SNORM:
1095 case PIPE_FORMAT_LATC1_SNORM:
1096 case PIPE_FORMAT_RGTC1_UNORM:
1097 case PIPE_FORMAT_LATC1_UNORM:
1098 return V_008F14_IMG_DATA_FORMAT_BC4;
1099 case PIPE_FORMAT_RGTC2_SNORM:
1100 case PIPE_FORMAT_LATC2_SNORM:
1101 case PIPE_FORMAT_RGTC2_UNORM:
1102 case PIPE_FORMAT_LATC2_UNORM:
1103 return V_008F14_IMG_DATA_FORMAT_BC5;
1104 default:
1105 goto out_unknown;
1106 }
1107 }
1108
1109 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1110 if (!enable_s3tc)
1111 goto out_unknown;
1112
1113 switch (format) {
1114 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1115 case PIPE_FORMAT_BPTC_SRGBA:
1116 return V_008F14_IMG_DATA_FORMAT_BC7;
1117 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1118 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1119 return V_008F14_IMG_DATA_FORMAT_BC6;
1120 default:
1121 goto out_unknown;
1122 }
1123 }
1124
1125 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1126 switch (format) {
1127 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1128 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1129 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1130 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1131 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1132 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1133 default:
1134 goto out_unknown;
1135 }
1136 }
1137
1138 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1139
1140 if (!enable_s3tc)
1141 goto out_unknown;
1142
1143 if (!util_format_s3tc_enabled) {
1144 goto out_unknown;
1145 }
1146
1147 switch (format) {
1148 case PIPE_FORMAT_DXT1_RGB:
1149 case PIPE_FORMAT_DXT1_RGBA:
1150 case PIPE_FORMAT_DXT1_SRGB:
1151 case PIPE_FORMAT_DXT1_SRGBA:
1152 return V_008F14_IMG_DATA_FORMAT_BC1;
1153 case PIPE_FORMAT_DXT3_RGBA:
1154 case PIPE_FORMAT_DXT3_SRGBA:
1155 return V_008F14_IMG_DATA_FORMAT_BC2;
1156 case PIPE_FORMAT_DXT5_RGBA:
1157 case PIPE_FORMAT_DXT5_SRGBA:
1158 return V_008F14_IMG_DATA_FORMAT_BC3;
1159 default:
1160 goto out_unknown;
1161 }
1162 }
1163
1164 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1165 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1166 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1167 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1168 }
1169
1170 /* R8G8Bx_SNORM - TODO CxV8U8 */
1171
1172 /* See whether the components are of the same size. */
1173 for (i = 1; i < desc->nr_channels; i++) {
1174 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1175 }
1176
1177 /* Non-uniform formats. */
1178 if (!uniform) {
1179 switch(desc->nr_channels) {
1180 case 3:
1181 if (desc->channel[0].size == 5 &&
1182 desc->channel[1].size == 6 &&
1183 desc->channel[2].size == 5) {
1184 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1185 }
1186 goto out_unknown;
1187 case 4:
1188 if (desc->channel[0].size == 5 &&
1189 desc->channel[1].size == 5 &&
1190 desc->channel[2].size == 5 &&
1191 desc->channel[3].size == 1) {
1192 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1193 }
1194 if (desc->channel[0].size == 10 &&
1195 desc->channel[1].size == 10 &&
1196 desc->channel[2].size == 10 &&
1197 desc->channel[3].size == 2) {
1198 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1199 }
1200 goto out_unknown;
1201 }
1202 goto out_unknown;
1203 }
1204
1205 if (first_non_void < 0 || first_non_void > 3)
1206 goto out_unknown;
1207
1208 /* uniform formats */
1209 switch (desc->channel[first_non_void].size) {
1210 case 4:
1211 switch (desc->nr_channels) {
1212 #if 0 /* Not supported for render targets */
1213 case 2:
1214 return V_008F14_IMG_DATA_FORMAT_4_4;
1215 #endif
1216 case 4:
1217 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1218 }
1219 break;
1220 case 8:
1221 switch (desc->nr_channels) {
1222 case 1:
1223 return V_008F14_IMG_DATA_FORMAT_8;
1224 case 2:
1225 return V_008F14_IMG_DATA_FORMAT_8_8;
1226 case 4:
1227 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1228 }
1229 break;
1230 case 16:
1231 switch (desc->nr_channels) {
1232 case 1:
1233 return V_008F14_IMG_DATA_FORMAT_16;
1234 case 2:
1235 return V_008F14_IMG_DATA_FORMAT_16_16;
1236 case 4:
1237 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1238 }
1239 break;
1240 case 32:
1241 switch (desc->nr_channels) {
1242 case 1:
1243 return V_008F14_IMG_DATA_FORMAT_32;
1244 case 2:
1245 return V_008F14_IMG_DATA_FORMAT_32_32;
1246 #if 0 /* Not supported for render targets */
1247 case 3:
1248 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1249 #endif
1250 case 4:
1251 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1252 }
1253 }
1254
1255 out_unknown:
1256 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1257 return ~0;
1258 }
1259
1260 static unsigned si_tex_wrap(unsigned wrap)
1261 {
1262 switch (wrap) {
1263 default:
1264 case PIPE_TEX_WRAP_REPEAT:
1265 return V_008F30_SQ_TEX_WRAP;
1266 case PIPE_TEX_WRAP_CLAMP:
1267 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1268 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1269 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1270 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1271 return V_008F30_SQ_TEX_CLAMP_BORDER;
1272 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1273 return V_008F30_SQ_TEX_MIRROR;
1274 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1275 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1276 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1277 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1278 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1279 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1280 }
1281 }
1282
1283 static unsigned si_tex_filter(unsigned filter)
1284 {
1285 switch (filter) {
1286 default:
1287 case PIPE_TEX_FILTER_NEAREST:
1288 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1289 case PIPE_TEX_FILTER_LINEAR:
1290 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1291 }
1292 }
1293
1294 static unsigned si_tex_mipfilter(unsigned filter)
1295 {
1296 switch (filter) {
1297 case PIPE_TEX_MIPFILTER_NEAREST:
1298 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1299 case PIPE_TEX_MIPFILTER_LINEAR:
1300 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1301 default:
1302 case PIPE_TEX_MIPFILTER_NONE:
1303 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1304 }
1305 }
1306
1307 static unsigned si_tex_compare(unsigned compare)
1308 {
1309 switch (compare) {
1310 default:
1311 case PIPE_FUNC_NEVER:
1312 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1313 case PIPE_FUNC_LESS:
1314 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1315 case PIPE_FUNC_EQUAL:
1316 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1317 case PIPE_FUNC_LEQUAL:
1318 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1319 case PIPE_FUNC_GREATER:
1320 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1321 case PIPE_FUNC_NOTEQUAL:
1322 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1323 case PIPE_FUNC_GEQUAL:
1324 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1325 case PIPE_FUNC_ALWAYS:
1326 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1327 }
1328 }
1329
1330 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1331 {
1332 switch (dim) {
1333 default:
1334 case PIPE_TEXTURE_1D:
1335 return V_008F1C_SQ_RSRC_IMG_1D;
1336 case PIPE_TEXTURE_1D_ARRAY:
1337 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1338 case PIPE_TEXTURE_2D:
1339 case PIPE_TEXTURE_RECT:
1340 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1341 V_008F1C_SQ_RSRC_IMG_2D;
1342 case PIPE_TEXTURE_2D_ARRAY:
1343 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1344 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1345 case PIPE_TEXTURE_3D:
1346 return V_008F1C_SQ_RSRC_IMG_3D;
1347 case PIPE_TEXTURE_CUBE:
1348 case PIPE_TEXTURE_CUBE_ARRAY:
1349 return V_008F1C_SQ_RSRC_IMG_CUBE;
1350 }
1351 }
1352
1353 /*
1354 * Format support testing
1355 */
1356
1357 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1358 {
1359 return si_translate_texformat(screen, format, util_format_description(format),
1360 util_format_get_first_non_void_channel(format)) != ~0U;
1361 }
1362
1363 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1364 const struct util_format_description *desc,
1365 int first_non_void)
1366 {
1367 unsigned type = desc->channel[first_non_void].type;
1368 int i;
1369
1370 if (type == UTIL_FORMAT_TYPE_FIXED)
1371 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1372
1373 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1374 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1375
1376 if (desc->nr_channels == 4 &&
1377 desc->channel[0].size == 10 &&
1378 desc->channel[1].size == 10 &&
1379 desc->channel[2].size == 10 &&
1380 desc->channel[3].size == 2)
1381 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1382
1383 /* See whether the components are of the same size. */
1384 for (i = 0; i < desc->nr_channels; i++) {
1385 if (desc->channel[first_non_void].size != desc->channel[i].size)
1386 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1387 }
1388
1389 switch (desc->channel[first_non_void].size) {
1390 case 8:
1391 switch (desc->nr_channels) {
1392 case 1:
1393 return V_008F0C_BUF_DATA_FORMAT_8;
1394 case 2:
1395 return V_008F0C_BUF_DATA_FORMAT_8_8;
1396 case 3:
1397 case 4:
1398 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1399 }
1400 break;
1401 case 16:
1402 switch (desc->nr_channels) {
1403 case 1:
1404 return V_008F0C_BUF_DATA_FORMAT_16;
1405 case 2:
1406 return V_008F0C_BUF_DATA_FORMAT_16_16;
1407 case 3:
1408 case 4:
1409 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1410 }
1411 break;
1412 case 32:
1413 /* From the Southern Islands ISA documentation about MTBUF:
1414 * 'Memory reads of data in memory that is 32 or 64 bits do not
1415 * undergo any format conversion.'
1416 */
1417 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1418 !desc->channel[first_non_void].pure_integer)
1419 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1420
1421 switch (desc->nr_channels) {
1422 case 1:
1423 return V_008F0C_BUF_DATA_FORMAT_32;
1424 case 2:
1425 return V_008F0C_BUF_DATA_FORMAT_32_32;
1426 case 3:
1427 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1428 case 4:
1429 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1430 }
1431 break;
1432 }
1433
1434 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1435 }
1436
1437 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1438 const struct util_format_description *desc,
1439 int first_non_void)
1440 {
1441 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1442 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1443
1444 switch (desc->channel[first_non_void].type) {
1445 case UTIL_FORMAT_TYPE_SIGNED:
1446 if (desc->channel[first_non_void].normalized)
1447 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1448 else if (desc->channel[first_non_void].pure_integer)
1449 return V_008F0C_BUF_NUM_FORMAT_SINT;
1450 else
1451 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1452 break;
1453 case UTIL_FORMAT_TYPE_UNSIGNED:
1454 if (desc->channel[first_non_void].normalized)
1455 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1456 else if (desc->channel[first_non_void].pure_integer)
1457 return V_008F0C_BUF_NUM_FORMAT_UINT;
1458 else
1459 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1460 break;
1461 case UTIL_FORMAT_TYPE_FLOAT:
1462 default:
1463 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1464 }
1465 }
1466
1467 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1468 {
1469 const struct util_format_description *desc;
1470 int first_non_void;
1471 unsigned data_format;
1472
1473 desc = util_format_description(format);
1474 first_non_void = util_format_get_first_non_void_channel(format);
1475 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1476 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1477 }
1478
1479 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1480 {
1481 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1482 r600_translate_colorswap(format) != ~0U;
1483 }
1484
1485 static bool si_is_zs_format_supported(enum pipe_format format)
1486 {
1487 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1488 }
1489
1490 boolean si_is_format_supported(struct pipe_screen *screen,
1491 enum pipe_format format,
1492 enum pipe_texture_target target,
1493 unsigned sample_count,
1494 unsigned usage)
1495 {
1496 struct si_screen *sscreen = (struct si_screen *)screen;
1497 unsigned retval = 0;
1498
1499 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1500 R600_ERR("r600: unsupported texture type %d\n", target);
1501 return FALSE;
1502 }
1503
1504 if (!util_format_is_supported(format, usage))
1505 return FALSE;
1506
1507 if (sample_count > 1) {
1508 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1509 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1510 return FALSE;
1511
1512 switch (sample_count) {
1513 case 2:
1514 case 4:
1515 case 8:
1516 break;
1517 default:
1518 return FALSE;
1519 }
1520 }
1521
1522 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1523 if (target == PIPE_BUFFER) {
1524 if (si_is_vertex_format_supported(screen, format))
1525 retval |= PIPE_BIND_SAMPLER_VIEW;
1526 } else {
1527 if (si_is_sampler_format_supported(screen, format))
1528 retval |= PIPE_BIND_SAMPLER_VIEW;
1529 }
1530 }
1531
1532 if ((usage & (PIPE_BIND_RENDER_TARGET |
1533 PIPE_BIND_DISPLAY_TARGET |
1534 PIPE_BIND_SCANOUT |
1535 PIPE_BIND_SHARED |
1536 PIPE_BIND_BLENDABLE)) &&
1537 si_is_colorbuffer_format_supported(format)) {
1538 retval |= usage &
1539 (PIPE_BIND_RENDER_TARGET |
1540 PIPE_BIND_DISPLAY_TARGET |
1541 PIPE_BIND_SCANOUT |
1542 PIPE_BIND_SHARED);
1543 if (!util_format_is_pure_integer(format) &&
1544 !util_format_is_depth_or_stencil(format))
1545 retval |= usage & PIPE_BIND_BLENDABLE;
1546 }
1547
1548 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1549 si_is_zs_format_supported(format)) {
1550 retval |= PIPE_BIND_DEPTH_STENCIL;
1551 }
1552
1553 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1554 si_is_vertex_format_supported(screen, format)) {
1555 retval |= PIPE_BIND_VERTEX_BUFFER;
1556 }
1557
1558 if (usage & PIPE_BIND_TRANSFER_READ)
1559 retval |= PIPE_BIND_TRANSFER_READ;
1560 if (usage & PIPE_BIND_TRANSFER_WRITE)
1561 retval |= PIPE_BIND_TRANSFER_WRITE;
1562
1563 return retval == usage;
1564 }
1565
1566 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1567 {
1568 unsigned tile_mode_index = 0;
1569
1570 if (stencil) {
1571 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1572 } else {
1573 tile_mode_index = rtex->surface.tiling_index[level];
1574 }
1575 return tile_mode_index;
1576 }
1577
1578 /*
1579 * framebuffer handling
1580 */
1581
1582 static void si_initialize_color_surface(struct si_context *sctx,
1583 struct r600_surface *surf)
1584 {
1585 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1586 unsigned level = surf->base.u.tex.level;
1587 uint64_t offset = rtex->surface.level[level].offset;
1588 unsigned pitch, slice;
1589 unsigned color_info, color_attrib, color_pitch, color_view;
1590 unsigned tile_mode_index;
1591 unsigned format, swap, ntype, endian;
1592 const struct util_format_description *desc;
1593 int i;
1594 unsigned blend_clamp = 0, blend_bypass = 0;
1595 unsigned max_comp_size;
1596
1597 /* Layered rendering doesn't work with LINEAR_GENERAL.
1598 * (LINEAR_ALIGNED and others work) */
1599 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1600 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1601 offset += rtex->surface.level[level].slice_size *
1602 surf->base.u.tex.first_layer;
1603 color_view = 0;
1604 } else {
1605 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1606 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1607 }
1608
1609 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1610 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1611 if (slice) {
1612 slice = slice - 1;
1613 }
1614
1615 tile_mode_index = si_tile_mode_index(rtex, level, false);
1616
1617 desc = util_format_description(surf->base.format);
1618 for (i = 0; i < 4; i++) {
1619 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1620 break;
1621 }
1622 }
1623 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1624 ntype = V_028C70_NUMBER_FLOAT;
1625 } else {
1626 ntype = V_028C70_NUMBER_UNORM;
1627 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1628 ntype = V_028C70_NUMBER_SRGB;
1629 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1630 if (desc->channel[i].pure_integer) {
1631 ntype = V_028C70_NUMBER_SINT;
1632 } else {
1633 assert(desc->channel[i].normalized);
1634 ntype = V_028C70_NUMBER_SNORM;
1635 }
1636 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1637 if (desc->channel[i].pure_integer) {
1638 ntype = V_028C70_NUMBER_UINT;
1639 } else {
1640 assert(desc->channel[i].normalized);
1641 ntype = V_028C70_NUMBER_UNORM;
1642 }
1643 }
1644 }
1645
1646 format = si_translate_colorformat(surf->base.format);
1647 if (format == V_028C70_COLOR_INVALID) {
1648 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1649 }
1650 assert(format != V_028C70_COLOR_INVALID);
1651 swap = r600_translate_colorswap(surf->base.format);
1652 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1653 endian = V_028C70_ENDIAN_NONE;
1654 } else {
1655 endian = si_colorformat_endian_swap(format);
1656 }
1657
1658 /* blend clamp should be set for all NORM/SRGB types */
1659 if (ntype == V_028C70_NUMBER_UNORM ||
1660 ntype == V_028C70_NUMBER_SNORM ||
1661 ntype == V_028C70_NUMBER_SRGB)
1662 blend_clamp = 1;
1663
1664 /* set blend bypass according to docs if SINT/UINT or
1665 8/24 COLOR variants */
1666 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1667 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1668 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1669 blend_clamp = 0;
1670 blend_bypass = 1;
1671 }
1672
1673 color_info = S_028C70_FORMAT(format) |
1674 S_028C70_COMP_SWAP(swap) |
1675 S_028C70_BLEND_CLAMP(blend_clamp) |
1676 S_028C70_BLEND_BYPASS(blend_bypass) |
1677 S_028C70_NUMBER_TYPE(ntype) |
1678 S_028C70_ENDIAN(endian);
1679
1680 color_pitch = S_028C64_TILE_MAX(pitch);
1681
1682 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1683 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1684
1685 if (rtex->resource.b.b.nr_samples > 1) {
1686 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1687
1688 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1689 S_028C74_NUM_FRAGMENTS(log_samples);
1690
1691 if (rtex->fmask.size) {
1692 color_info |= S_028C70_COMPRESSION(1);
1693 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1694
1695 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1696
1697 if (sctx->b.chip_class == SI) {
1698 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1699 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1700 }
1701 if (sctx->b.chip_class >= CIK) {
1702 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1703 }
1704 }
1705 }
1706
1707 offset += rtex->resource.gpu_address;
1708
1709 surf->cb_color_base = offset >> 8;
1710 surf->cb_color_pitch = color_pitch;
1711 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1712 surf->cb_color_view = color_view;
1713 surf->cb_color_info = color_info;
1714 surf->cb_color_attrib = color_attrib;
1715
1716 if (rtex->fmask.size) {
1717 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1718 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1719 } else {
1720 /* This must be set for fast clear to work without FMASK. */
1721 surf->cb_color_fmask = surf->cb_color_base;
1722 surf->cb_color_fmask_slice = surf->cb_color_slice;
1723 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1724
1725 if (sctx->b.chip_class == SI) {
1726 unsigned bankh = util_logbase2(rtex->surface.bankh);
1727 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1728 }
1729
1730 if (sctx->b.chip_class >= CIK) {
1731 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1732 }
1733 }
1734
1735 /* Determine pixel shader export format */
1736 max_comp_size = si_colorformat_max_comp_size(format);
1737 if (ntype == V_028C70_NUMBER_SRGB ||
1738 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1739 max_comp_size <= 10) ||
1740 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1741 surf->export_16bpc = true;
1742 }
1743
1744 surf->color_initialized = true;
1745 }
1746
1747 static void si_init_depth_surface(struct si_context *sctx,
1748 struct r600_surface *surf)
1749 {
1750 struct si_screen *sscreen = sctx->screen;
1751 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1752 unsigned level = surf->base.u.tex.level;
1753 struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
1754 unsigned format, tile_mode_index, array_mode;
1755 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1756 uint32_t z_info, s_info, db_depth_info;
1757 uint64_t z_offs, s_offs;
1758 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1759
1760 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1761 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1762 case PIPE_FORMAT_X8Z24_UNORM:
1763 case PIPE_FORMAT_Z24X8_UNORM:
1764 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1765 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1766 break;
1767 case PIPE_FORMAT_Z32_FLOAT:
1768 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1769 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1770 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1771 break;
1772 case PIPE_FORMAT_Z16_UNORM:
1773 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1774 break;
1775 default:
1776 assert(0);
1777 }
1778
1779 format = si_translate_dbformat(rtex->resource.b.b.format);
1780
1781 if (format == V_028040_Z_INVALID) {
1782 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1783 }
1784 assert(format != V_028040_Z_INVALID);
1785
1786 s_offs = z_offs = rtex->resource.gpu_address;
1787 z_offs += rtex->surface.level[level].offset;
1788 s_offs += rtex->surface.stencil_level[level].offset;
1789
1790 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1791
1792 z_info = S_028040_FORMAT(format);
1793 if (rtex->resource.b.b.nr_samples > 1) {
1794 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1795 }
1796
1797 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1798 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1799 else
1800 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1801
1802 if (sctx->b.chip_class >= CIK) {
1803 switch (rtex->surface.level[level].mode) {
1804 case RADEON_SURF_MODE_2D:
1805 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1806 break;
1807 case RADEON_SURF_MODE_1D:
1808 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1809 case RADEON_SURF_MODE_LINEAR:
1810 default:
1811 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1812 break;
1813 }
1814 tile_split = rtex->surface.tile_split;
1815 stile_split = rtex->surface.stencil_tile_split;
1816 macro_aspect = rtex->surface.mtilea;
1817 bankw = rtex->surface.bankw;
1818 bankh = rtex->surface.bankh;
1819 tile_split = cik_tile_split(tile_split);
1820 stile_split = cik_tile_split(stile_split);
1821 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1822 bankw = cik_bank_wh(bankw);
1823 bankh = cik_bank_wh(bankh);
1824 nbanks = si_num_banks(sscreen, rtex);
1825 tile_mode_index = si_tile_mode_index(rtex, level, false);
1826 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1827
1828 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1829 S_02803C_PIPE_CONFIG(pipe_config) |
1830 S_02803C_BANK_WIDTH(bankw) |
1831 S_02803C_BANK_HEIGHT(bankh) |
1832 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1833 S_02803C_NUM_BANKS(nbanks);
1834 z_info |= S_028040_TILE_SPLIT(tile_split);
1835 s_info |= S_028044_TILE_SPLIT(stile_split);
1836 } else {
1837 tile_mode_index = si_tile_mode_index(rtex, level, false);
1838 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1839 tile_mode_index = si_tile_mode_index(rtex, level, true);
1840 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1841 }
1842
1843 /* HiZ aka depth buffer htile */
1844 /* use htile only for first level */
1845 if (rtex->htile_buffer && !level) {
1846 const struct util_format_description *fmt_desc;
1847
1848 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1849
1850 /* This is optimal for the clear value of 1.0 and using
1851 * the LESS and LEQUAL test functions. Set this to 0
1852 * for the opposite case. This can only be changed when
1853 * clearing. */
1854 z_info |= S_028040_ZRANGE_PRECISION(1);
1855
1856 fmt_desc = util_format_description(rtex->resource.b.b.format);
1857 if (!util_format_has_stencil(fmt_desc)) {
1858 /* Use all of the htile_buffer for depth */
1859 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1860 }
1861
1862 uint64_t va = rtex->htile_buffer->gpu_address;
1863 db_htile_data_base = va >> 8;
1864 db_htile_surface = S_028ABC_FULL_CACHE(1);
1865 } else {
1866 db_htile_data_base = 0;
1867 db_htile_surface = 0;
1868 }
1869
1870 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1871
1872 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1873 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1874 surf->db_htile_data_base = db_htile_data_base;
1875 surf->db_depth_info = db_depth_info;
1876 surf->db_z_info = z_info;
1877 surf->db_stencil_info = s_info;
1878 surf->db_depth_base = z_offs >> 8;
1879 surf->db_stencil_base = s_offs >> 8;
1880 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1881 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1882 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1883 levelinfo->nblk_y) / 64 - 1);
1884 surf->db_htile_surface = db_htile_surface;
1885 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1886
1887 surf->depth_initialized = true;
1888 }
1889
1890 static void si_set_framebuffer_state(struct pipe_context *ctx,
1891 const struct pipe_framebuffer_state *state)
1892 {
1893 struct si_context *sctx = (struct si_context *)ctx;
1894 struct pipe_constant_buffer constbuf = {0};
1895 struct r600_surface *surf = NULL;
1896 struct r600_texture *rtex;
1897 int i;
1898
1899 if (sctx->framebuffer.state.nr_cbufs) {
1900 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1901 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1902 }
1903 if (sctx->framebuffer.state.zsbuf) {
1904 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
1905 R600_CONTEXT_FLUSH_AND_INV_DB_META;
1906 }
1907
1908 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
1909
1910 sctx->framebuffer.export_16bpc = 0;
1911 sctx->framebuffer.compressed_cb_mask = 0;
1912 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1913 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
1914 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1915 util_format_is_pure_integer(state->cbufs[0]->format);
1916
1917 for (i = 0; i < state->nr_cbufs; i++) {
1918 if (!state->cbufs[i])
1919 continue;
1920
1921 surf = (struct r600_surface*)state->cbufs[i];
1922 rtex = (struct r600_texture*)surf->base.texture;
1923
1924 if (!surf->color_initialized) {
1925 si_initialize_color_surface(sctx, surf);
1926 }
1927
1928 if (surf->export_16bpc) {
1929 sctx->framebuffer.export_16bpc |= 1 << i;
1930 }
1931
1932 if (rtex->fmask.size && rtex->cmask.size) {
1933 sctx->framebuffer.compressed_cb_mask |= 1 << i;
1934 }
1935 }
1936 /* Set the 16BPC export for possible dual-src blending. */
1937 if (i == 1 && surf && surf->export_16bpc) {
1938 sctx->framebuffer.export_16bpc |= 1 << 1;
1939 }
1940
1941 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
1942
1943 if (state->zsbuf) {
1944 surf = (struct r600_surface*)state->zsbuf;
1945
1946 if (!surf->depth_initialized) {
1947 si_init_depth_surface(sctx, surf);
1948 }
1949 }
1950
1951 si_update_fb_rs_state(sctx);
1952 si_update_fb_blend_state(sctx);
1953
1954 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
1955 sctx->framebuffer.atom.num_dw += state->zsbuf ? 23 : 4;
1956 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
1957 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
1958 sctx->framebuffer.atom.dirty = true;
1959 sctx->msaa_config.dirty = true;
1960
1961 /* Set sample locations as fragment shader constants. */
1962 switch (sctx->framebuffer.nr_samples) {
1963 case 1:
1964 constbuf.user_buffer = sctx->b.sample_locations_1x;
1965 break;
1966 case 2:
1967 constbuf.user_buffer = sctx->b.sample_locations_2x;
1968 break;
1969 case 4:
1970 constbuf.user_buffer = sctx->b.sample_locations_4x;
1971 break;
1972 case 8:
1973 constbuf.user_buffer = sctx->b.sample_locations_8x;
1974 break;
1975 case 16:
1976 constbuf.user_buffer = sctx->b.sample_locations_16x;
1977 break;
1978 default:
1979 assert(0);
1980 }
1981 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
1982 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
1983 SI_DRIVER_STATE_CONST_BUF, &constbuf);
1984 }
1985
1986 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
1987 {
1988 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
1989 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
1990 unsigned i, nr_cbufs = state->nr_cbufs;
1991 struct r600_texture *tex = NULL;
1992 struct r600_surface *cb = NULL;
1993
1994 /* Colorbuffers. */
1995 for (i = 0; i < nr_cbufs; i++) {
1996 cb = (struct r600_surface*)state->cbufs[i];
1997 if (!cb) {
1998 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1999 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2000 continue;
2001 }
2002
2003 tex = (struct r600_texture *)cb->base.texture;
2004 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2005 &tex->resource, RADEON_USAGE_READWRITE,
2006 tex->surface.nsamples > 1 ?
2007 RADEON_PRIO_COLOR_BUFFER_MSAA :
2008 RADEON_PRIO_COLOR_BUFFER);
2009
2010 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2011 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2012 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2013 RADEON_PRIO_COLOR_META);
2014 }
2015
2016 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2017 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2018 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2019 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2020 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2021 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2022 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2023 radeon_emit(cs, 0); /* R_028C78 unused */
2024 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2025 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2026 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2027 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2028 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2029 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2030 }
2031 /* set CB_COLOR1_INFO for possible dual-src blending */
2032 if (i == 1 && state->cbufs[0]) {
2033 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2034 cb->cb_color_info | tex->cb_color_info);
2035 i++;
2036 }
2037 for (; i < 8 ; i++) {
2038 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2039 }
2040
2041 /* ZS buffer. */
2042 if (state->zsbuf) {
2043 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2044 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2045
2046 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2047 &rtex->resource, RADEON_USAGE_READWRITE,
2048 zb->base.texture->nr_samples > 1 ?
2049 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2050 RADEON_PRIO_DEPTH_BUFFER);
2051
2052 if (zb->db_htile_data_base) {
2053 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2054 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2055 RADEON_PRIO_DEPTH_META);
2056 }
2057
2058 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2059 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2060
2061 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2062 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2063 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
2064 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2065 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2066 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2067 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2068 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2069 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2070 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2071
2072 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2073 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2074 zb->pa_su_poly_offset_db_fmt_cntl);
2075 } else {
2076 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2077 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2078 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2079 }
2080
2081 /* Framebuffer dimensions. */
2082 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2083 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2084 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2085
2086 cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples);
2087 }
2088
2089 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2090 {
2091 struct si_context *sctx = (struct si_context *)rctx;
2092 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2093
2094 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2095 sctx->ps_iter_samples);
2096 }
2097
2098 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2099
2100 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2101 {
2102 struct si_context *sctx = (struct si_context *)ctx;
2103
2104 if (sctx->ps_iter_samples == min_samples)
2105 return;
2106
2107 sctx->ps_iter_samples = min_samples;
2108
2109 if (sctx->framebuffer.nr_samples > 1)
2110 sctx->msaa_config.dirty = true;
2111 }
2112
2113 /*
2114 * shaders
2115 */
2116
2117 /* Compute the key for the hw shader variant */
2118 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2119 struct si_pipe_shader_selector *sel,
2120 union si_shader_key *key)
2121 {
2122 struct si_context *sctx = (struct si_context *)ctx;
2123 memset(key, 0, sizeof(*key));
2124
2125 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
2126 sctx->queued.named.rasterizer) {
2127 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2128 key->vs.ucps_enabled |= 0x2;
2129 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2130 key->vs.ucps_enabled |= 0x1;
2131 }
2132
2133 if (sel->type == PIPE_SHADER_VERTEX) {
2134 unsigned i;
2135 if (!sctx->vertex_elements)
2136 return;
2137
2138 for (i = 0; i < sctx->vertex_elements->count; ++i)
2139 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2140
2141 key->vs.as_es = sctx->gs_shader != NULL;
2142 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2143 if (sel->fs_write_all)
2144 key->ps.nr_cbufs = sctx->framebuffer.state.nr_cbufs;
2145 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
2146
2147 if (sctx->queued.named.rasterizer) {
2148 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2149 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2150 key->ps.interp_at_sample = sctx->framebuffer.nr_samples > 1 &&
2151 sctx->ps_iter_samples == sctx->framebuffer.nr_samples;
2152
2153 if (sctx->queued.named.blend) {
2154 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2155 sctx->queued.named.rasterizer->multisample_enable &&
2156 !sctx->framebuffer.cb0_is_integer;
2157 }
2158 }
2159 if (sctx->queued.named.dsa) {
2160 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2161
2162 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2163 if (sctx->framebuffer.cb0_is_integer)
2164 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2165 } else {
2166 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2167 }
2168 }
2169 }
2170
2171 /* Select the hw shader variant depending on the current state. */
2172 int si_shader_select(struct pipe_context *ctx,
2173 struct si_pipe_shader_selector *sel)
2174 {
2175 union si_shader_key key;
2176 struct si_pipe_shader * shader = NULL;
2177 int r;
2178
2179 si_shader_selector_key(ctx, sel, &key);
2180
2181 /* Check if we don't need to change anything.
2182 * This path is also used for most shaders that don't need multiple
2183 * variants, it will cost just a computation of the key and this
2184 * test. */
2185 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2186 return 0;
2187 }
2188
2189 /* lookup if we have other variants in the list */
2190 if (sel->num_shaders > 1) {
2191 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2192
2193 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2194 p = c;
2195 c = c->next_variant;
2196 }
2197
2198 if (c) {
2199 p->next_variant = c->next_variant;
2200 shader = c;
2201 }
2202 }
2203
2204 if (shader) {
2205 shader->next_variant = sel->current;
2206 sel->current = shader;
2207 } else {
2208 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2209 shader->selector = sel;
2210 shader->key = key;
2211
2212 shader->next_variant = sel->current;
2213 sel->current = shader;
2214 r = si_pipe_shader_create(ctx, shader);
2215 if (unlikely(r)) {
2216 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2217 sel->type, r);
2218 sel->current = NULL;
2219 FREE(shader);
2220 return r;
2221 }
2222 sel->num_shaders++;
2223 }
2224
2225 return 0;
2226 }
2227
2228 static void *si_create_shader_state(struct pipe_context *ctx,
2229 const struct pipe_shader_state *state,
2230 unsigned pipe_shader_type)
2231 {
2232 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2233 int r;
2234
2235 sel->type = pipe_shader_type;
2236 sel->tokens = tgsi_dup_tokens(state->tokens);
2237 sel->so = state->stream_output;
2238
2239 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2240 struct tgsi_shader_info info;
2241
2242 tgsi_scan_shader(state->tokens, &info);
2243 sel->fs_write_all = info.color0_writes_all_cbufs;
2244 }
2245
2246 r = si_shader_select(ctx, sel);
2247 if (r) {
2248 free(sel);
2249 return NULL;
2250 }
2251
2252 return sel;
2253 }
2254
2255 static void *si_create_fs_state(struct pipe_context *ctx,
2256 const struct pipe_shader_state *state)
2257 {
2258 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2259 }
2260
2261 static void *si_create_gs_state(struct pipe_context *ctx,
2262 const struct pipe_shader_state *state)
2263 {
2264 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
2265 }
2266
2267 static void *si_create_vs_state(struct pipe_context *ctx,
2268 const struct pipe_shader_state *state)
2269 {
2270 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2271 }
2272
2273 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2274 {
2275 struct si_context *sctx = (struct si_context *)ctx;
2276 struct si_pipe_shader_selector *sel = state;
2277
2278 if (sctx->vs_shader == sel)
2279 return;
2280
2281 if (!sel || !sel->current)
2282 return;
2283
2284 sctx->vs_shader = sel;
2285 }
2286
2287 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2288 {
2289 struct si_context *sctx = (struct si_context *)ctx;
2290 struct si_pipe_shader_selector *sel = state;
2291
2292 if (sctx->gs_shader == sel)
2293 return;
2294
2295 sctx->gs_shader = sel;
2296 }
2297
2298 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2299 {
2300 struct si_context *sctx = (struct si_context *)ctx;
2301 struct si_pipe_shader_selector *sel = state;
2302
2303 /* skip if supplied shader is one already in use */
2304 if (sctx->ps_shader == sel)
2305 return;
2306
2307 /* use dummy shader if supplied shader is corrupt */
2308 if (!sel || !sel->current)
2309 sel = sctx->dummy_pixel_shader;
2310
2311 sctx->ps_shader = sel;
2312 }
2313
2314 static void si_delete_shader_selector(struct pipe_context *ctx,
2315 struct si_pipe_shader_selector *sel)
2316 {
2317 struct si_context *sctx = (struct si_context *)ctx;
2318 struct si_pipe_shader *p = sel->current, *c;
2319
2320 while (p) {
2321 c = p->next_variant;
2322 if (sel->type == PIPE_SHADER_GEOMETRY)
2323 si_pm4_delete_state(sctx, gs, p->pm4);
2324 else if (sel->type == PIPE_SHADER_FRAGMENT)
2325 si_pm4_delete_state(sctx, ps, p->pm4);
2326 else if (p->key.vs.as_es)
2327 si_pm4_delete_state(sctx, es, p->pm4);
2328 else
2329 si_pm4_delete_state(sctx, vs, p->pm4);
2330 si_pipe_shader_destroy(ctx, p);
2331 free(p);
2332 p = c;
2333 }
2334
2335 free(sel->tokens);
2336 free(sel);
2337 }
2338
2339 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2340 {
2341 struct si_context *sctx = (struct si_context *)ctx;
2342 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2343
2344 if (sctx->vs_shader == sel) {
2345 sctx->vs_shader = NULL;
2346 }
2347
2348 si_delete_shader_selector(ctx, sel);
2349 }
2350
2351 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
2352 {
2353 struct si_context *sctx = (struct si_context *)ctx;
2354 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2355
2356 if (sctx->gs_shader == sel) {
2357 sctx->gs_shader = NULL;
2358 }
2359
2360 si_delete_shader_selector(ctx, sel);
2361 }
2362
2363 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2364 {
2365 struct si_context *sctx = (struct si_context *)ctx;
2366 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2367
2368 if (sctx->ps_shader == sel) {
2369 sctx->ps_shader = NULL;
2370 }
2371
2372 si_delete_shader_selector(ctx, sel);
2373 }
2374
2375 /*
2376 * Samplers
2377 */
2378
2379 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2380 struct pipe_resource *texture,
2381 const struct pipe_sampler_view *state)
2382 {
2383 struct si_context *sctx = (struct si_context*)ctx;
2384 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2385 struct r600_texture *tmp = (struct r600_texture*)texture;
2386 const struct util_format_description *desc;
2387 unsigned format, num_format;
2388 uint32_t pitch = 0;
2389 unsigned char state_swizzle[4], swizzle[4];
2390 unsigned height, depth, width;
2391 enum pipe_format pipe_format = state->format;
2392 struct radeon_surface_level *surflevel;
2393 int first_non_void;
2394 uint64_t va;
2395
2396 if (view == NULL)
2397 return NULL;
2398
2399 /* initialize base object */
2400 view->base = *state;
2401 view->base.texture = NULL;
2402 pipe_resource_reference(&view->base.texture, texture);
2403 view->base.reference.count = 1;
2404 view->base.context = ctx;
2405 view->resource = &tmp->resource;
2406
2407 /* Buffer resource. */
2408 if (texture->target == PIPE_BUFFER) {
2409 unsigned stride;
2410
2411 desc = util_format_description(state->format);
2412 first_non_void = util_format_get_first_non_void_channel(state->format);
2413 stride = desc->block.bits / 8;
2414 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2415 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2416 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2417
2418 view->state[0] = va;
2419 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2420 S_008F04_STRIDE(stride);
2421 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2422 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2423 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2424 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2425 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2426 S_008F0C_NUM_FORMAT(num_format) |
2427 S_008F0C_DATA_FORMAT(format);
2428
2429 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2430 return &view->base;
2431 }
2432
2433 state_swizzle[0] = state->swizzle_r;
2434 state_swizzle[1] = state->swizzle_g;
2435 state_swizzle[2] = state->swizzle_b;
2436 state_swizzle[3] = state->swizzle_a;
2437
2438 surflevel = tmp->surface.level;
2439
2440 /* Texturing with separate depth and stencil. */
2441 if (tmp->is_depth && !tmp->is_flushing_texture) {
2442 switch (pipe_format) {
2443 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2444 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2445 break;
2446 case PIPE_FORMAT_X8Z24_UNORM:
2447 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2448 /* Z24 is always stored like this. */
2449 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2450 break;
2451 case PIPE_FORMAT_X24S8_UINT:
2452 case PIPE_FORMAT_S8X24_UINT:
2453 case PIPE_FORMAT_X32_S8X24_UINT:
2454 pipe_format = PIPE_FORMAT_S8_UINT;
2455 surflevel = tmp->surface.stencil_level;
2456 break;
2457 default:;
2458 }
2459 }
2460
2461 desc = util_format_description(pipe_format);
2462
2463 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2464 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2465 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2466
2467 switch (pipe_format) {
2468 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2469 case PIPE_FORMAT_X24S8_UINT:
2470 case PIPE_FORMAT_X32_S8X24_UINT:
2471 case PIPE_FORMAT_X8Z24_UNORM:
2472 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2473 break;
2474 default:
2475 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2476 }
2477 } else {
2478 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2479 }
2480
2481 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2482
2483 switch (pipe_format) {
2484 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2485 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2486 break;
2487 default:
2488 if (first_non_void < 0) {
2489 if (util_format_is_compressed(pipe_format)) {
2490 switch (pipe_format) {
2491 case PIPE_FORMAT_DXT1_SRGB:
2492 case PIPE_FORMAT_DXT1_SRGBA:
2493 case PIPE_FORMAT_DXT3_SRGBA:
2494 case PIPE_FORMAT_DXT5_SRGBA:
2495 case PIPE_FORMAT_BPTC_SRGBA:
2496 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2497 break;
2498 case PIPE_FORMAT_RGTC1_SNORM:
2499 case PIPE_FORMAT_LATC1_SNORM:
2500 case PIPE_FORMAT_RGTC2_SNORM:
2501 case PIPE_FORMAT_LATC2_SNORM:
2502 /* implies float, so use SNORM/UNORM to determine
2503 whether data is signed or not */
2504 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2505 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2506 break;
2507 default:
2508 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2509 break;
2510 }
2511 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2512 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2513 } else {
2514 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2515 }
2516 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2517 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2518 } else {
2519 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2520
2521 switch (desc->channel[first_non_void].type) {
2522 case UTIL_FORMAT_TYPE_FLOAT:
2523 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2524 break;
2525 case UTIL_FORMAT_TYPE_SIGNED:
2526 if (desc->channel[first_non_void].normalized)
2527 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2528 else if (desc->channel[first_non_void].pure_integer)
2529 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2530 else
2531 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2532 break;
2533 case UTIL_FORMAT_TYPE_UNSIGNED:
2534 if (desc->channel[first_non_void].normalized)
2535 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2536 else if (desc->channel[first_non_void].pure_integer)
2537 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2538 else
2539 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2540 }
2541 }
2542 }
2543
2544 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2545 if (format == ~0) {
2546 format = 0;
2547 }
2548
2549 /* not supported any more */
2550 //endian = si_colorformat_endian_swap(format);
2551
2552 width = surflevel[0].npix_x;
2553 height = surflevel[0].npix_y;
2554 depth = surflevel[0].npix_z;
2555 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2556
2557 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2558 height = 1;
2559 depth = texture->array_size;
2560 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2561 depth = texture->array_size;
2562 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2563 depth = texture->array_size / 6;
2564
2565 va = tmp->resource.gpu_address + surflevel[0].offset;
2566 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2567
2568 view->state[0] = va >> 8;
2569 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2570 S_008F14_DATA_FORMAT(format) |
2571 S_008F14_NUM_FORMAT(num_format));
2572 view->state[2] = (S_008F18_WIDTH(width - 1) |
2573 S_008F18_HEIGHT(height - 1));
2574 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2575 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2576 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2577 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2578 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2579 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2580 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2581 util_logbase2(texture->nr_samples) :
2582 state->u.tex.last_level - tmp->mipmap_shift) |
2583 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2584 S_008F1C_POW2_PAD(texture->last_level > 0) |
2585 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2586 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2587 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2588 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2589 view->state[6] = 0;
2590 view->state[7] = 0;
2591
2592 /* Initialize the sampler view for FMASK. */
2593 if (tmp->fmask.size) {
2594 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2595 uint32_t fmask_format;
2596
2597 switch (texture->nr_samples) {
2598 case 2:
2599 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2600 break;
2601 case 4:
2602 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2603 break;
2604 case 8:
2605 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2606 break;
2607 default:
2608 assert(0);
2609 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2610 }
2611
2612 view->fmask_state[0] = va >> 8;
2613 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2614 S_008F14_DATA_FORMAT(fmask_format) |
2615 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2616 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2617 S_008F18_HEIGHT(height - 1);
2618 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2619 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2620 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2621 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2622 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2623 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2624 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2625 S_008F20_PITCH(tmp->fmask.pitch - 1);
2626 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2627 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2628 view->fmask_state[6] = 0;
2629 view->fmask_state[7] = 0;
2630 }
2631
2632 return &view->base;
2633 }
2634
2635 static void si_sampler_view_destroy(struct pipe_context *ctx,
2636 struct pipe_sampler_view *state)
2637 {
2638 struct si_pipe_sampler_view *view = (struct si_pipe_sampler_view *)state;
2639
2640 if (view->resource->b.b.target == PIPE_BUFFER)
2641 LIST_DELINIT(&view->list);
2642
2643 pipe_resource_reference(&state->texture, NULL);
2644 FREE(view);
2645 }
2646
2647 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2648 {
2649 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2650 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2651 (linear_filter &&
2652 (wrap == PIPE_TEX_WRAP_CLAMP ||
2653 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2654 }
2655
2656 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2657 {
2658 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2659 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2660
2661 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2662 state->border_color.ui[2] || state->border_color.ui[3]) &&
2663 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2664 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2665 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2666 }
2667
2668 static void *si_create_sampler_state(struct pipe_context *ctx,
2669 const struct pipe_sampler_state *state)
2670 {
2671 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2672 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2673 unsigned border_color_type;
2674
2675 if (rstate == NULL) {
2676 return NULL;
2677 }
2678
2679 if (sampler_state_needs_border_color(state))
2680 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2681 else
2682 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2683
2684 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2685 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2686 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2687 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2688 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2689 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2690 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2691 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2692 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2693 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2694 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2695 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2696 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2697 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2698
2699 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2700 memcpy(rstate->border_color, state->border_color.ui,
2701 sizeof(rstate->border_color));
2702 }
2703
2704 return rstate;
2705 }
2706
2707 /* Upload border colors and update the pointers in resource descriptors.
2708 * There can only be 4096 border colors per context.
2709 *
2710 * XXX: This is broken if the buffer gets reallocated.
2711 */
2712 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2713 void **states)
2714 {
2715 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2716 uint32_t *border_color_table = NULL;
2717 int i, j;
2718
2719 for (i = 0; i < count; i++) {
2720 if (rstates[i] &&
2721 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2722 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2723 if (!sctx->border_color_table ||
2724 ((sctx->border_color_offset + count - i) &
2725 C_008F3C_BORDER_COLOR_PTR)) {
2726 r600_resource_reference(&sctx->border_color_table, NULL);
2727 sctx->border_color_offset = 0;
2728
2729 sctx->border_color_table =
2730 si_resource_create_custom(&sctx->screen->b.b,
2731 PIPE_USAGE_DYNAMIC,
2732 4096 * 4 * 4);
2733 }
2734
2735 if (!border_color_table) {
2736 border_color_table =
2737 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2738 sctx->b.rings.gfx.cs,
2739 PIPE_TRANSFER_WRITE |
2740 PIPE_TRANSFER_UNSYNCHRONIZED);
2741 }
2742
2743 for (j = 0; j < 4; j++) {
2744 border_color_table[4 * sctx->border_color_offset + j] =
2745 util_le32_to_cpu(rstates[i]->border_color[j]);
2746 }
2747
2748 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2749 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2750 }
2751 }
2752
2753 if (border_color_table) {
2754 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2755
2756 uint64_t va_offset = sctx->border_color_table->gpu_address;
2757
2758 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2759 if (sctx->b.chip_class >= CIK)
2760 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2761 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2762 RADEON_PRIO_SHADER_DATA);
2763 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2764 }
2765 }
2766
2767 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2768 unsigned start, unsigned count,
2769 void **states)
2770 {
2771 struct si_context *sctx = (struct si_context *)ctx;
2772
2773 if (!count || shader >= SI_NUM_SHADERS)
2774 return;
2775
2776 si_set_border_colors(sctx, count, states);
2777 si_set_sampler_descriptors(sctx, shader, start, count, states);
2778 }
2779
2780 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2781 {
2782 struct si_context *sctx = (struct si_context *)ctx;
2783 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2784 struct si_pm4_state *pm4 = &state->pm4;
2785 uint16_t mask = sample_mask;
2786
2787 if (state == NULL)
2788 return;
2789
2790 state->sample_mask = mask;
2791 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2792 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2793
2794 si_pm4_set_state(sctx, sample_mask, state);
2795 }
2796
2797 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2798 {
2799 free(state);
2800 }
2801
2802 /*
2803 * Vertex elements & buffers
2804 */
2805
2806 static void *si_create_vertex_elements(struct pipe_context *ctx,
2807 unsigned count,
2808 const struct pipe_vertex_element *elements)
2809 {
2810 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2811 int i;
2812
2813 assert(count < PIPE_MAX_ATTRIBS);
2814 if (!v)
2815 return NULL;
2816
2817 v->count = count;
2818 for (i = 0; i < count; ++i) {
2819 const struct util_format_description *desc;
2820 unsigned data_format, num_format;
2821 int first_non_void;
2822
2823 desc = util_format_description(elements[i].src_format);
2824 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2825 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2826 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2827
2828 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2829 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2830 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2831 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2832 S_008F0C_NUM_FORMAT(num_format) |
2833 S_008F0C_DATA_FORMAT(data_format);
2834 v->format_size[i] = desc->block.bits / 8;
2835 }
2836 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2837
2838 return v;
2839 }
2840
2841 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2842 {
2843 struct si_context *sctx = (struct si_context *)ctx;
2844 struct si_vertex_element *v = (struct si_vertex_element*)state;
2845
2846 sctx->vertex_elements = v;
2847 sctx->vertex_buffers_dirty = true;
2848 }
2849
2850 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2851 {
2852 struct si_context *sctx = (struct si_context *)ctx;
2853
2854 if (sctx->vertex_elements == state)
2855 sctx->vertex_elements = NULL;
2856 FREE(state);
2857 }
2858
2859 static void si_set_vertex_buffers(struct pipe_context *ctx,
2860 unsigned start_slot, unsigned count,
2861 const struct pipe_vertex_buffer *buffers)
2862 {
2863 struct si_context *sctx = (struct si_context *)ctx;
2864 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2865 int i;
2866
2867 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2868
2869 if (buffers) {
2870 for (i = 0; i < count; i++) {
2871 const struct pipe_vertex_buffer *src = buffers + i;
2872 struct pipe_vertex_buffer *dsti = dst + i;
2873
2874 pipe_resource_reference(&dsti->buffer, src->buffer);
2875 dsti->buffer_offset = src->buffer_offset;
2876 dsti->stride = src->stride;
2877 }
2878 } else {
2879 for (i = 0; i < count; i++) {
2880 pipe_resource_reference(&dst[i].buffer, NULL);
2881 }
2882 }
2883 sctx->vertex_buffers_dirty = true;
2884 }
2885
2886 static void si_set_index_buffer(struct pipe_context *ctx,
2887 const struct pipe_index_buffer *ib)
2888 {
2889 struct si_context *sctx = (struct si_context *)ctx;
2890
2891 if (ib) {
2892 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2893 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2894 } else {
2895 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2896 }
2897 }
2898
2899 /*
2900 * Misc
2901 */
2902 static void si_set_polygon_stipple(struct pipe_context *ctx,
2903 const struct pipe_poly_stipple *state)
2904 {
2905 }
2906
2907 static void si_texture_barrier(struct pipe_context *ctx)
2908 {
2909 struct si_context *sctx = (struct si_context *)ctx;
2910
2911 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2912 R600_CONTEXT_FLUSH_AND_INV_CB;
2913 }
2914
2915 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2916 {
2917 struct pipe_blend_state blend;
2918
2919 memset(&blend, 0, sizeof(blend));
2920 blend.independent_blend_enable = true;
2921 blend.rt[0].colormask = 0xf;
2922 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2923 }
2924
2925 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2926 {
2927 /* XXX Turn this into a proper state. Right now the queries are
2928 * enabled in draw_vbo, which snoops r600_common_context to see
2929 * if any occlusion queries are active. */
2930 }
2931
2932 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2933 bool include_draw_vbo)
2934 {
2935 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2936 }
2937
2938 void si_init_state_functions(struct si_context *sctx)
2939 {
2940 int i;
2941
2942 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2943
2944 sctx->b.b.create_blend_state = si_create_blend_state;
2945 sctx->b.b.bind_blend_state = si_bind_blend_state;
2946 sctx->b.b.delete_blend_state = si_delete_blend_state;
2947 sctx->b.b.set_blend_color = si_set_blend_color;
2948
2949 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2950 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2951 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2952
2953 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2954 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2955 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2956
2957 for (i = 0; i < 8; i++) {
2958 sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i);
2959 sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i);
2960 sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i);
2961 }
2962 sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0);
2963 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2964 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2965 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2966
2967 sctx->b.b.set_clip_state = si_set_clip_state;
2968 sctx->b.b.set_scissor_states = si_set_scissor_states;
2969 sctx->b.b.set_viewport_states = si_set_viewport_states;
2970 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2971
2972 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2973 sctx->b.b.get_sample_position = cayman_get_sample_position;
2974
2975 sctx->b.b.create_vs_state = si_create_vs_state;
2976 sctx->b.b.create_fs_state = si_create_fs_state;
2977 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2978 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2979 sctx->b.b.delete_vs_state = si_delete_vs_shader;
2980 sctx->b.b.delete_fs_state = si_delete_ps_shader;
2981
2982 sctx->b.b.create_gs_state = si_create_gs_state;
2983 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2984 sctx->b.b.delete_gs_state = si_delete_gs_shader;
2985
2986 sctx->b.b.create_sampler_state = si_create_sampler_state;
2987 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2988 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2989
2990 sctx->b.b.create_sampler_view = si_create_sampler_view;
2991 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2992
2993 sctx->b.b.set_sample_mask = si_set_sample_mask;
2994
2995 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2996 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
2997 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
2998 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
2999 sctx->b.b.set_index_buffer = si_set_index_buffer;
3000
3001 sctx->b.b.texture_barrier = si_texture_barrier;
3002 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3003 sctx->b.b.set_min_samples = si_set_min_samples;
3004
3005 sctx->b.dma_copy = si_dma_copy;
3006 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3007 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3008
3009 sctx->b.b.draw_vbo = si_draw_vbo;
3010 }
3011
3012 void si_init_config(struct si_context *sctx)
3013 {
3014 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
3015
3016 if (pm4 == NULL)
3017 return;
3018
3019 si_cmd_context_control(pm4);
3020
3021 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3022 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3023 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3024 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3025 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3026 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3027 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3028 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3029 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3030 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3031 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3032 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3033
3034 /* FIXME calculate these values somehow ??? */
3035 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3036 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3037 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3038
3039 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3040 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3041 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3042 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3043
3044 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3045 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3046 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3047 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3048
3049 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3050 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3051 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3052 if (sctx->b.chip_class < CIK)
3053 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3054 S_008A14_CLIP_VTX_REORDER_ENA(1));
3055
3056 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3057 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3058
3059 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3060
3061 if (sctx->b.chip_class >= CIK) {
3062 switch (sctx->screen->b.family) {
3063 case CHIP_BONAIRE:
3064 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3065 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3066 break;
3067 case CHIP_HAWAII:
3068 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3069 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3070 break;
3071 case CHIP_KAVERI:
3072 /* XXX todo */
3073 case CHIP_KABINI:
3074 /* XXX todo */
3075 case CHIP_MULLINS:
3076 /* XXX todo */
3077 default:
3078 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3079 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3080 break;
3081 }
3082 } else {
3083 switch (sctx->screen->b.family) {
3084 case CHIP_TAHITI:
3085 case CHIP_PITCAIRN:
3086 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3087 break;
3088 case CHIP_VERDE:
3089 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3090 break;
3091 case CHIP_OLAND:
3092 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3093 break;
3094 case CHIP_HAINAN:
3095 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3096 break;
3097 default:
3098 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3099 break;
3100 }
3101 }
3102
3103 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3104 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3105 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3106 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3107 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3108 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3109 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3110
3111 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3112 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3113 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3114 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3115 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3116 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3117 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3118 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3119 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3120 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3121 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3122 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3123 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3124 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3125 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3126 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3127 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3128 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3129 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3130 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3131 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3132 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3133 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3134
3135 if (sctx->b.chip_class >= CIK) {
3136 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3137 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3138 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3139 }
3140
3141 si_pm4_set_state(sctx, init, pm4);
3142 }