2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "si_shader.h"
30 #include "../radeon/r600_cs.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_helpers.h"
38 #include "util/u_memory.h"
40 static uint32_t cik_num_banks(struct si_screen
*sscreen
, unsigned bpe
, unsigned tile_split
)
42 if (sscreen
->b
.info
.cik_macrotile_mode_array_valid
) {
43 unsigned index
, tileb
;
46 tileb
= MIN2(tile_split
, tileb
);
48 for (index
= 0; tileb
> 64; index
++) {
54 return (sscreen
->b
.info
.cik_macrotile_mode_array
[index
] >> 6) & 0x3;
58 switch (sscreen
->b
.tiling_info
.num_banks
) {
60 return V_02803C_ADDR_SURF_2_BANK
;
62 return V_02803C_ADDR_SURF_4_BANK
;
65 return V_02803C_ADDR_SURF_8_BANK
;
67 return V_02803C_ADDR_SURF_16_BANK
;
71 static unsigned cik_tile_split(unsigned tile_split
)
75 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_64B
;
78 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_128B
;
81 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_256B
;
84 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_512B
;
88 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_1KB
;
91 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_2KB
;
94 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_4KB
;
100 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect
)
102 switch (macro_tile_aspect
) {
105 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_1
;
108 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_2
;
111 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_4
;
114 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_8
;
117 return macro_tile_aspect
;
120 static unsigned cik_bank_wh(unsigned bankwh
)
125 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_1
;
128 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_2
;
131 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_4
;
134 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_8
;
140 static unsigned cik_db_pipe_config(struct si_screen
*sscreen
, unsigned tile_mode
)
142 if (sscreen
->b
.info
.si_tile_mode_array_valid
) {
143 uint32_t gb_tile_mode
= sscreen
->b
.info
.si_tile_mode_array
[tile_mode
];
145 return G_009910_PIPE_CONFIG(gb_tile_mode
);
148 /* This is probably broken for a lot of chips, but it's only used
149 * if the kernel cannot return the tile mode array for CIK. */
150 switch (sscreen
->b
.info
.r600_num_tile_pipes
) {
152 return V_02803C_X_ADDR_SURF_P16_32X32_16X16
;
154 return V_02803C_X_ADDR_SURF_P8_32X32_16X16
;
157 if (sscreen
->b
.info
.r600_num_backends
== 4)
158 return V_02803C_X_ADDR_SURF_P4_16X16
;
160 return V_02803C_X_ADDR_SURF_P4_8X16
;
162 return V_02803C_ADDR_SURF_P2
;
166 static unsigned si_map_swizzle(unsigned swizzle
)
169 case UTIL_FORMAT_SWIZZLE_Y
:
170 return V_008F0C_SQ_SEL_Y
;
171 case UTIL_FORMAT_SWIZZLE_Z
:
172 return V_008F0C_SQ_SEL_Z
;
173 case UTIL_FORMAT_SWIZZLE_W
:
174 return V_008F0C_SQ_SEL_W
;
175 case UTIL_FORMAT_SWIZZLE_0
:
176 return V_008F0C_SQ_SEL_0
;
177 case UTIL_FORMAT_SWIZZLE_1
:
178 return V_008F0C_SQ_SEL_1
;
179 default: /* UTIL_FORMAT_SWIZZLE_X */
180 return V_008F0C_SQ_SEL_X
;
184 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
186 return value
* (1 << frac_bits
);
189 /* 12.4 fixed-point */
190 static unsigned si_pack_float_12p4(float x
)
193 x
>= 4096 ? 0xffff : x
* 16;
197 * inferred framebuffer and blender state
199 static void si_update_fb_blend_state(struct si_context
*sctx
)
201 struct si_pm4_state
*pm4
;
202 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
208 pm4
= si_pm4_alloc_state(sctx
);
212 mask
= (1ULL << ((unsigned)sctx
->framebuffer
.nr_cbufs
* 4)) - 1;
213 mask
&= blend
->cb_target_mask
;
214 si_pm4_set_reg(pm4
, R_028238_CB_TARGET_MASK
, mask
);
216 si_pm4_set_state(sctx
, fb_blend
, pm4
);
223 static uint32_t si_translate_blend_function(int blend_func
)
225 switch (blend_func
) {
227 return V_028780_COMB_DST_PLUS_SRC
;
228 case PIPE_BLEND_SUBTRACT
:
229 return V_028780_COMB_SRC_MINUS_DST
;
230 case PIPE_BLEND_REVERSE_SUBTRACT
:
231 return V_028780_COMB_DST_MINUS_SRC
;
233 return V_028780_COMB_MIN_DST_SRC
;
235 return V_028780_COMB_MAX_DST_SRC
;
237 R600_ERR("Unknown blend function %d\n", blend_func
);
244 static uint32_t si_translate_blend_factor(int blend_fact
)
246 switch (blend_fact
) {
247 case PIPE_BLENDFACTOR_ONE
:
248 return V_028780_BLEND_ONE
;
249 case PIPE_BLENDFACTOR_SRC_COLOR
:
250 return V_028780_BLEND_SRC_COLOR
;
251 case PIPE_BLENDFACTOR_SRC_ALPHA
:
252 return V_028780_BLEND_SRC_ALPHA
;
253 case PIPE_BLENDFACTOR_DST_ALPHA
:
254 return V_028780_BLEND_DST_ALPHA
;
255 case PIPE_BLENDFACTOR_DST_COLOR
:
256 return V_028780_BLEND_DST_COLOR
;
257 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
258 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
259 case PIPE_BLENDFACTOR_CONST_COLOR
:
260 return V_028780_BLEND_CONSTANT_COLOR
;
261 case PIPE_BLENDFACTOR_CONST_ALPHA
:
262 return V_028780_BLEND_CONSTANT_ALPHA
;
263 case PIPE_BLENDFACTOR_ZERO
:
264 return V_028780_BLEND_ZERO
;
265 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
266 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
267 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
268 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
269 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
270 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
271 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
272 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
273 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
274 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
275 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
276 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
277 case PIPE_BLENDFACTOR_SRC1_COLOR
:
278 return V_028780_BLEND_SRC1_COLOR
;
279 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
280 return V_028780_BLEND_SRC1_ALPHA
;
281 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
282 return V_028780_BLEND_INV_SRC1_COLOR
;
283 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
284 return V_028780_BLEND_INV_SRC1_ALPHA
;
286 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
293 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
294 const struct pipe_blend_state
*state
,
297 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
298 struct si_pm4_state
*pm4
= &blend
->pm4
;
300 uint32_t color_control
= 0;
305 blend
->alpha_to_one
= state
->alpha_to_one
;
307 if (state
->logicop_enable
) {
308 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
310 color_control
|= S_028808_ROP3(0xcc);
313 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
314 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
315 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
316 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
317 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
318 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
320 blend
->cb_target_mask
= 0;
321 for (int i
= 0; i
< 8; i
++) {
322 /* state->rt entries > 0 only written if independent blending */
323 const int j
= state
->independent_blend_enable
? i
: 0;
325 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
326 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
327 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
328 unsigned eqA
= state
->rt
[j
].alpha_func
;
329 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
330 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
332 unsigned blend_cntl
= 0;
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 blend
->cb_target_mask
|= state
->rt
[j
].colormask
<< (4 * i
);
337 if (!state
->rt
[j
].blend_enable
) {
338 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
342 blend_cntl
|= S_028780_ENABLE(1);
343 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
344 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
345 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
347 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
348 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
349 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
350 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
351 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
353 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
356 if (blend
->cb_target_mask
) {
357 color_control
|= S_028808_MODE(mode
);
359 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
361 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
366 static void *si_create_blend_state(struct pipe_context
*ctx
,
367 const struct pipe_blend_state
*state
)
369 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
372 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
374 struct si_context
*sctx
= (struct si_context
*)ctx
;
375 si_pm4_bind_state(sctx
, blend
, (struct si_state_blend
*)state
);
376 si_update_fb_blend_state(sctx
);
379 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
381 struct si_context
*sctx
= (struct si_context
*)ctx
;
382 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
385 static void si_set_blend_color(struct pipe_context
*ctx
,
386 const struct pipe_blend_color
*state
)
388 struct si_context
*sctx
= (struct si_context
*)ctx
;
389 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
394 si_pm4_set_reg(pm4
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
395 si_pm4_set_reg(pm4
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
396 si_pm4_set_reg(pm4
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
397 si_pm4_set_reg(pm4
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
399 si_pm4_set_state(sctx
, blend_color
, pm4
);
403 * Clipping, scissors and viewport
406 static void si_set_clip_state(struct pipe_context
*ctx
,
407 const struct pipe_clip_state
*state
)
409 struct si_context
*sctx
= (struct si_context
*)ctx
;
410 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
411 struct pipe_constant_buffer cb
;
416 for (int i
= 0; i
< 6; i
++) {
417 si_pm4_set_reg(pm4
, R_0285BC_PA_CL_UCP_0_X
+ i
* 16,
418 fui(state
->ucp
[i
][0]));
419 si_pm4_set_reg(pm4
, R_0285C0_PA_CL_UCP_0_Y
+ i
* 16,
420 fui(state
->ucp
[i
][1]));
421 si_pm4_set_reg(pm4
, R_0285C4_PA_CL_UCP_0_Z
+ i
* 16,
422 fui(state
->ucp
[i
][2]));
423 si_pm4_set_reg(pm4
, R_0285C8_PA_CL_UCP_0_W
+ i
* 16,
424 fui(state
->ucp
[i
][3]));
428 cb
.user_buffer
= state
->ucp
;
429 cb
.buffer_offset
= 0;
430 cb
.buffer_size
= 4*4*8;
431 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, NUM_PIPE_CONST_BUFFERS
, &cb
);
432 pipe_resource_reference(&cb
.buffer
, NULL
);
434 si_pm4_set_state(sctx
, clip
, pm4
);
437 static void si_set_scissor_states(struct pipe_context
*ctx
,
439 unsigned num_scissors
,
440 const struct pipe_scissor_state
*state
)
442 struct si_context
*sctx
= (struct si_context
*)ctx
;
443 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
448 si_pm4_set_reg(pm4
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
,
449 S_028250_TL_X(state
->minx
) | S_028250_TL_Y(state
->miny
) |
450 S_028250_WINDOW_OFFSET_DISABLE(1));
451 si_pm4_set_reg(pm4
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
,
452 S_028254_BR_X(state
->maxx
) | S_028254_BR_Y(state
->maxy
));
454 si_pm4_set_state(sctx
, scissor
, pm4
);
457 static void si_set_viewport_states(struct pipe_context
*ctx
,
459 unsigned num_viewports
,
460 const struct pipe_viewport_state
*state
)
462 struct si_context
*sctx
= (struct si_context
*)ctx
;
463 struct si_state_viewport
*viewport
= CALLOC_STRUCT(si_state_viewport
);
464 struct si_pm4_state
*pm4
= &viewport
->pm4
;
466 if (viewport
== NULL
)
469 viewport
->viewport
= *state
;
470 si_pm4_set_reg(pm4
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
471 si_pm4_set_reg(pm4
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
472 si_pm4_set_reg(pm4
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
473 si_pm4_set_reg(pm4
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
474 si_pm4_set_reg(pm4
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
475 si_pm4_set_reg(pm4
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
477 si_pm4_set_state(sctx
, viewport
, viewport
);
481 * inferred state between framebuffer and rasterizer
483 static void si_update_fb_rs_state(struct si_context
*sctx
)
485 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
486 struct si_pm4_state
*pm4
;
489 if (!rs
|| !sctx
->framebuffer
.zsbuf
)
492 offset_units
= sctx
->queued
.named
.rasterizer
->offset_units
;
493 switch (sctx
->framebuffer
.zsbuf
->texture
->format
) {
494 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
495 case PIPE_FORMAT_X8Z24_UNORM
:
496 case PIPE_FORMAT_Z24X8_UNORM
:
497 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
498 offset_units
*= 2.0f
;
500 case PIPE_FORMAT_Z32_FLOAT
:
501 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
502 offset_units
*= 1.0f
;
504 case PIPE_FORMAT_Z16_UNORM
:
505 offset_units
*= 4.0f
;
511 pm4
= si_pm4_alloc_state(sctx
);
516 /* FIXME some of those reg can be computed with cso */
517 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
518 fui(sctx
->queued
.named
.rasterizer
->offset_scale
));
519 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
520 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
521 fui(sctx
->queued
.named
.rasterizer
->offset_scale
));
522 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
524 si_pm4_set_state(sctx
, fb_rs
, pm4
);
531 static uint32_t si_translate_fill(uint32_t func
)
534 case PIPE_POLYGON_MODE_FILL
:
535 return V_028814_X_DRAW_TRIANGLES
;
536 case PIPE_POLYGON_MODE_LINE
:
537 return V_028814_X_DRAW_LINES
;
538 case PIPE_POLYGON_MODE_POINT
:
539 return V_028814_X_DRAW_POINTS
;
542 return V_028814_X_DRAW_POINTS
;
546 static void *si_create_rs_state(struct pipe_context
*ctx
,
547 const struct pipe_rasterizer_state
*state
)
549 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
550 struct si_pm4_state
*pm4
= &rs
->pm4
;
552 unsigned prov_vtx
= 1, polygon_dual_mode
;
553 float psize_min
, psize_max
;
559 rs
->two_side
= state
->light_twoside
;
560 rs
->multisample_enable
= state
->multisample
;
561 rs
->clip_plane_enable
= state
->clip_plane_enable
;
562 rs
->line_stipple_enable
= state
->line_stipple_enable
;
564 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
565 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
567 if (state
->flatshade_first
)
570 rs
->flatshade
= state
->flatshade
;
571 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
572 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
573 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
574 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
575 rs
->pa_su_sc_mode_cntl
=
576 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
577 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
578 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
579 S_028814_FACE(!state
->front_ccw
) |
580 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
581 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
582 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
583 S_028814_POLY_MODE(polygon_dual_mode
) |
584 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
585 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
));
586 rs
->pa_cl_clip_cntl
=
587 S_028810_PS_UCP_MODE(3) |
588 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
589 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
590 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
591 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
594 rs
->offset_units
= state
->offset_units
;
595 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
597 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
598 if (state
->sprite_coord_enable
) {
599 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
600 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
601 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
602 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
603 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
);
604 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
605 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
608 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
610 /* point size 12.4 fixed point */
611 tmp
= (unsigned)(state
->point_size
* 8.0);
612 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
614 if (state
->point_size_per_vertex
) {
615 psize_min
= util_get_min_point_size(state
);
618 /* Force the point size to be as if the vertex output was disabled. */
619 psize_min
= state
->point_size
;
620 psize_max
= state
->point_size
;
622 /* Divide by two, because 0.5 = 1 pixel. */
623 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
624 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
625 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
627 tmp
= (unsigned)state
->line_width
* 8;
628 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
629 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
630 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
631 S_028A48_MSAA_ENABLE(state
->multisample
) |
632 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
));
634 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
635 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
636 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
638 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
643 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
645 struct si_context
*sctx
= (struct si_context
*)ctx
;
646 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
652 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
653 sctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
654 sctx
->pa_su_sc_mode_cntl
= rs
->pa_su_sc_mode_cntl
;
656 si_pm4_bind_state(sctx
, rasterizer
, rs
);
657 si_update_fb_rs_state(sctx
);
660 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
662 struct si_context
*sctx
= (struct si_context
*)ctx
;
663 si_pm4_delete_state(sctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
667 * infeered state between dsa and stencil ref
669 static void si_update_dsa_stencil_ref(struct si_context
*sctx
)
671 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
672 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
;
673 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
678 si_pm4_set_reg(pm4
, R_028430_DB_STENCILREFMASK
,
679 S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
680 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
681 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
682 S_028430_STENCILOPVAL(1));
683 si_pm4_set_reg(pm4
, R_028434_DB_STENCILREFMASK_BF
,
684 S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
685 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
686 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
687 S_028434_STENCILOPVAL_BF(1));
689 si_pm4_set_state(sctx
, dsa_stencil_ref
, pm4
);
692 static void si_set_pipe_stencil_ref(struct pipe_context
*ctx
,
693 const struct pipe_stencil_ref
*state
)
695 struct si_context
*sctx
= (struct si_context
*)ctx
;
696 sctx
->stencil_ref
= *state
;
697 si_update_dsa_stencil_ref(sctx
);
705 static uint32_t si_translate_stencil_op(int s_op
)
708 case PIPE_STENCIL_OP_KEEP
:
709 return V_02842C_STENCIL_KEEP
;
710 case PIPE_STENCIL_OP_ZERO
:
711 return V_02842C_STENCIL_ZERO
;
712 case PIPE_STENCIL_OP_REPLACE
:
713 return V_02842C_STENCIL_REPLACE_TEST
;
714 case PIPE_STENCIL_OP_INCR
:
715 return V_02842C_STENCIL_ADD_CLAMP
;
716 case PIPE_STENCIL_OP_DECR
:
717 return V_02842C_STENCIL_SUB_CLAMP
;
718 case PIPE_STENCIL_OP_INCR_WRAP
:
719 return V_02842C_STENCIL_ADD_WRAP
;
720 case PIPE_STENCIL_OP_DECR_WRAP
:
721 return V_02842C_STENCIL_SUB_WRAP
;
722 case PIPE_STENCIL_OP_INVERT
:
723 return V_02842C_STENCIL_INVERT
;
725 R600_ERR("Unknown stencil op %d", s_op
);
732 static void *si_create_dsa_state(struct pipe_context
*ctx
,
733 const struct pipe_depth_stencil_alpha_state
*state
)
735 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
736 struct si_pm4_state
*pm4
= &dsa
->pm4
;
737 unsigned db_depth_control
;
738 unsigned db_render_control
;
739 uint32_t db_stencil_control
= 0;
745 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
746 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
747 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
748 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
750 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
751 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
752 S_028800_ZFUNC(state
->depth
.func
);
755 if (state
->stencil
[0].enabled
) {
756 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
757 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
758 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
759 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
760 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
762 if (state
->stencil
[1].enabled
) {
763 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
764 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
765 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
766 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
767 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
772 if (state
->alpha
.enabled
) {
773 dsa
->alpha_func
= state
->alpha
.func
;
774 dsa
->alpha_ref
= state
->alpha
.ref_value
;
776 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
777 SI_SGPR_ALPHA_REF
* 4, fui(dsa
->alpha_ref
));
779 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
783 db_render_control
= 0;
784 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
785 si_pm4_set_reg(pm4
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
786 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
791 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
793 struct si_context
*sctx
= (struct si_context
*)ctx
;
794 struct si_state_dsa
*dsa
= state
;
799 si_pm4_bind_state(sctx
, dsa
, dsa
);
800 si_update_dsa_stencil_ref(sctx
);
803 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
805 struct si_context
*sctx
= (struct si_context
*)ctx
;
806 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
809 static void *si_create_db_flush_dsa(struct si_context
*sctx
, bool copy_depth
,
810 bool copy_stencil
, int sample
)
812 struct pipe_depth_stencil_alpha_state dsa
;
813 struct si_state_dsa
*state
;
815 memset(&dsa
, 0, sizeof(dsa
));
817 state
= sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
818 if (copy_depth
|| copy_stencil
) {
819 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
820 S_028000_DEPTH_COPY(copy_depth
) |
821 S_028000_STENCIL_COPY(copy_stencil
) |
822 S_028000_COPY_CENTROID(1) |
823 S_028000_COPY_SAMPLE(sample
));
825 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
826 S_028000_DEPTH_COMPRESS_DISABLE(1) |
827 S_028000_STENCIL_COMPRESS_DISABLE(1));
836 static uint32_t si_translate_colorformat(enum pipe_format format
)
838 const struct util_format_description
*desc
= util_format_description(format
);
840 #define HAS_SIZE(x,y,z,w) \
841 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
842 desc->channel[2].size == (z) && desc->channel[3].size == (w))
844 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
845 return V_028C70_COLOR_10_11_11
;
847 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
848 return V_028C70_COLOR_INVALID
;
850 switch (desc
->nr_channels
) {
852 switch (desc
->channel
[0].size
) {
854 return V_028C70_COLOR_8
;
856 return V_028C70_COLOR_16
;
858 return V_028C70_COLOR_32
;
862 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
863 switch (desc
->channel
[0].size
) {
865 return V_028C70_COLOR_8_8
;
867 return V_028C70_COLOR_16_16
;
869 return V_028C70_COLOR_32_32
;
871 } else if (HAS_SIZE(8,24,0,0)) {
872 return V_028C70_COLOR_24_8
;
873 } else if (HAS_SIZE(24,8,0,0)) {
874 return V_028C70_COLOR_8_24
;
878 if (HAS_SIZE(5,6,5,0)) {
879 return V_028C70_COLOR_5_6_5
;
880 } else if (HAS_SIZE(32,8,24,0)) {
881 return V_028C70_COLOR_X24_8_32_FLOAT
;
885 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
886 desc
->channel
[0].size
== desc
->channel
[2].size
&&
887 desc
->channel
[0].size
== desc
->channel
[3].size
) {
888 switch (desc
->channel
[0].size
) {
890 return V_028C70_COLOR_4_4_4_4
;
892 return V_028C70_COLOR_8_8_8_8
;
894 return V_028C70_COLOR_16_16_16_16
;
896 return V_028C70_COLOR_32_32_32_32
;
898 } else if (HAS_SIZE(5,5,5,1)) {
899 return V_028C70_COLOR_1_5_5_5
;
900 } else if (HAS_SIZE(10,10,10,2)) {
901 return V_028C70_COLOR_2_10_10_10
;
905 return V_028C70_COLOR_INVALID
;
908 static uint32_t si_translate_colorswap(enum pipe_format format
)
910 const struct util_format_description
*desc
= util_format_description(format
);
912 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
914 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
915 return V_028C70_SWAP_STD
;
917 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
920 switch (desc
->nr_channels
) {
922 if (HAS_SWIZZLE(0,X
))
923 return V_028C70_SWAP_STD
; /* X___ */
924 else if (HAS_SWIZZLE(3,X
))
925 return V_028C70_SWAP_ALT_REV
; /* ___X */
928 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
929 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
930 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
931 return V_028C70_SWAP_STD
; /* XY__ */
932 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
933 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
934 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
935 return V_028C70_SWAP_STD_REV
; /* YX__ */
936 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
937 return V_028C70_SWAP_ALT
; /* X__Y */
940 if (HAS_SWIZZLE(0,X
))
941 return V_028C70_SWAP_STD
; /* XYZ */
942 else if (HAS_SWIZZLE(0,Z
))
943 return V_028C70_SWAP_STD_REV
; /* ZYX */
946 /* check the middle channels, the 1st and 4th channel can be NONE */
947 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
))
948 return V_028C70_SWAP_STD
; /* XYZW */
949 else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
))
950 return V_028C70_SWAP_STD_REV
; /* WZYX */
951 else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
))
952 return V_028C70_SWAP_ALT
; /* ZYXW */
953 else if (HAS_SWIZZLE(1,X
) && HAS_SWIZZLE(2,Y
))
954 return V_028C70_SWAP_ALT_REV
; /* WXYZ */
960 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
963 switch(colorformat
) {
965 case V_028C70_COLOR_8
:
966 return V_028C70_ENDIAN_NONE
;
968 /* 16-bit buffers. */
969 case V_028C70_COLOR_5_6_5
:
970 case V_028C70_COLOR_1_5_5_5
:
971 case V_028C70_COLOR_4_4_4_4
:
972 case V_028C70_COLOR_16
:
973 case V_028C70_COLOR_8_8
:
974 return V_028C70_ENDIAN_8IN16
;
976 /* 32-bit buffers. */
977 case V_028C70_COLOR_8_8_8_8
:
978 case V_028C70_COLOR_2_10_10_10
:
979 case V_028C70_COLOR_8_24
:
980 case V_028C70_COLOR_24_8
:
981 case V_028C70_COLOR_16_16
:
982 return V_028C70_ENDIAN_8IN32
;
984 /* 64-bit buffers. */
985 case V_028C70_COLOR_16_16_16_16
:
986 return V_028C70_ENDIAN_8IN16
;
988 case V_028C70_COLOR_32_32
:
989 return V_028C70_ENDIAN_8IN32
;
991 /* 128-bit buffers. */
992 case V_028C70_COLOR_32_32_32_32
:
993 return V_028C70_ENDIAN_8IN32
;
995 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
998 return V_028C70_ENDIAN_NONE
;
1002 /* Returns the size in bits of the widest component of a CB format */
1003 static unsigned si_colorformat_max_comp_size(uint32_t colorformat
)
1005 switch(colorformat
) {
1006 case V_028C70_COLOR_4_4_4_4
:
1009 case V_028C70_COLOR_1_5_5_5
:
1010 case V_028C70_COLOR_5_5_5_1
:
1013 case V_028C70_COLOR_5_6_5
:
1016 case V_028C70_COLOR_8
:
1017 case V_028C70_COLOR_8_8
:
1018 case V_028C70_COLOR_8_8_8_8
:
1021 case V_028C70_COLOR_10_10_10_2
:
1022 case V_028C70_COLOR_2_10_10_10
:
1025 case V_028C70_COLOR_10_11_11
:
1026 case V_028C70_COLOR_11_11_10
:
1029 case V_028C70_COLOR_16
:
1030 case V_028C70_COLOR_16_16
:
1031 case V_028C70_COLOR_16_16_16_16
:
1034 case V_028C70_COLOR_8_24
:
1035 case V_028C70_COLOR_24_8
:
1038 case V_028C70_COLOR_32
:
1039 case V_028C70_COLOR_32_32
:
1040 case V_028C70_COLOR_32_32_32_32
:
1041 case V_028C70_COLOR_X24_8_32_FLOAT
:
1045 assert(!"Unknown maximum component size");
1049 static uint32_t si_translate_dbformat(enum pipe_format format
)
1052 case PIPE_FORMAT_Z16_UNORM
:
1053 return V_028040_Z_16
;
1054 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1055 case PIPE_FORMAT_X8Z24_UNORM
:
1056 case PIPE_FORMAT_Z24X8_UNORM
:
1057 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1058 return V_028040_Z_24
; /* deprecated on SI */
1059 case PIPE_FORMAT_Z32_FLOAT
:
1060 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1061 return V_028040_Z_32_FLOAT
;
1063 return V_028040_Z_INVALID
;
1068 * Texture translation
1071 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1072 enum pipe_format format
,
1073 const struct util_format_description
*desc
,
1076 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1077 bool enable_s3tc
= sscreen
->b
.info
.drm_minor
>= 31;
1078 boolean uniform
= TRUE
;
1081 /* Colorspace (return non-RGB formats directly). */
1082 switch (desc
->colorspace
) {
1083 /* Depth stencil formats */
1084 case UTIL_FORMAT_COLORSPACE_ZS
:
1086 case PIPE_FORMAT_Z16_UNORM
:
1087 return V_008F14_IMG_DATA_FORMAT_16
;
1088 case PIPE_FORMAT_X24S8_UINT
:
1089 case PIPE_FORMAT_Z24X8_UNORM
:
1090 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1091 return V_008F14_IMG_DATA_FORMAT_8_24
;
1092 case PIPE_FORMAT_X8Z24_UNORM
:
1093 case PIPE_FORMAT_S8X24_UINT
:
1094 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1095 return V_008F14_IMG_DATA_FORMAT_24_8
;
1096 case PIPE_FORMAT_S8_UINT
:
1097 return V_008F14_IMG_DATA_FORMAT_8
;
1098 case PIPE_FORMAT_Z32_FLOAT
:
1099 return V_008F14_IMG_DATA_FORMAT_32
;
1100 case PIPE_FORMAT_X32_S8X24_UINT
:
1101 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1102 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1107 case UTIL_FORMAT_COLORSPACE_YUV
:
1108 goto out_unknown
; /* TODO */
1110 case UTIL_FORMAT_COLORSPACE_SRGB
:
1111 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1119 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1124 case PIPE_FORMAT_RGTC1_SNORM
:
1125 case PIPE_FORMAT_LATC1_SNORM
:
1126 case PIPE_FORMAT_RGTC1_UNORM
:
1127 case PIPE_FORMAT_LATC1_UNORM
:
1128 return V_008F14_IMG_DATA_FORMAT_BC4
;
1129 case PIPE_FORMAT_RGTC2_SNORM
:
1130 case PIPE_FORMAT_LATC2_SNORM
:
1131 case PIPE_FORMAT_RGTC2_UNORM
:
1132 case PIPE_FORMAT_LATC2_UNORM
:
1133 return V_008F14_IMG_DATA_FORMAT_BC5
;
1139 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1144 if (!util_format_s3tc_enabled
) {
1149 case PIPE_FORMAT_DXT1_RGB
:
1150 case PIPE_FORMAT_DXT1_RGBA
:
1151 case PIPE_FORMAT_DXT1_SRGB
:
1152 case PIPE_FORMAT_DXT1_SRGBA
:
1153 return V_008F14_IMG_DATA_FORMAT_BC1
;
1154 case PIPE_FORMAT_DXT3_RGBA
:
1155 case PIPE_FORMAT_DXT3_SRGBA
:
1156 return V_008F14_IMG_DATA_FORMAT_BC2
;
1157 case PIPE_FORMAT_DXT5_RGBA
:
1158 case PIPE_FORMAT_DXT5_SRGBA
:
1159 return V_008F14_IMG_DATA_FORMAT_BC3
;
1165 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1166 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1167 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1168 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1171 /* R8G8Bx_SNORM - TODO CxV8U8 */
1173 /* See whether the components are of the same size. */
1174 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1175 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1178 /* Non-uniform formats. */
1180 switch(desc
->nr_channels
) {
1182 if (desc
->channel
[0].size
== 5 &&
1183 desc
->channel
[1].size
== 6 &&
1184 desc
->channel
[2].size
== 5) {
1185 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1189 if (desc
->channel
[0].size
== 5 &&
1190 desc
->channel
[1].size
== 5 &&
1191 desc
->channel
[2].size
== 5 &&
1192 desc
->channel
[3].size
== 1) {
1193 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1195 if (desc
->channel
[0].size
== 10 &&
1196 desc
->channel
[1].size
== 10 &&
1197 desc
->channel
[2].size
== 10 &&
1198 desc
->channel
[3].size
== 2) {
1199 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1206 if (first_non_void
< 0 || first_non_void
> 3)
1209 /* uniform formats */
1210 switch (desc
->channel
[first_non_void
].size
) {
1212 switch (desc
->nr_channels
) {
1213 #if 0 /* Not supported for render targets */
1215 return V_008F14_IMG_DATA_FORMAT_4_4
;
1218 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1222 switch (desc
->nr_channels
) {
1224 return V_008F14_IMG_DATA_FORMAT_8
;
1226 return V_008F14_IMG_DATA_FORMAT_8_8
;
1228 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1232 switch (desc
->nr_channels
) {
1234 return V_008F14_IMG_DATA_FORMAT_16
;
1236 return V_008F14_IMG_DATA_FORMAT_16_16
;
1238 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1242 switch (desc
->nr_channels
) {
1244 return V_008F14_IMG_DATA_FORMAT_32
;
1246 return V_008F14_IMG_DATA_FORMAT_32_32
;
1247 #if 0 /* Not supported for render targets */
1249 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1252 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1257 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1261 static unsigned si_tex_wrap(unsigned wrap
)
1265 case PIPE_TEX_WRAP_REPEAT
:
1266 return V_008F30_SQ_TEX_WRAP
;
1267 case PIPE_TEX_WRAP_CLAMP
:
1268 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1269 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1270 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1271 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1272 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1273 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1274 return V_008F30_SQ_TEX_MIRROR
;
1275 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1276 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1277 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1278 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1279 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1280 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1284 static unsigned si_tex_filter(unsigned filter
)
1288 case PIPE_TEX_FILTER_NEAREST
:
1289 return V_008F38_SQ_TEX_XY_FILTER_POINT
;
1290 case PIPE_TEX_FILTER_LINEAR
:
1291 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
1295 static unsigned si_tex_mipfilter(unsigned filter
)
1298 case PIPE_TEX_MIPFILTER_NEAREST
:
1299 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1300 case PIPE_TEX_MIPFILTER_LINEAR
:
1301 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1303 case PIPE_TEX_MIPFILTER_NONE
:
1304 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1308 static unsigned si_tex_compare(unsigned compare
)
1312 case PIPE_FUNC_NEVER
:
1313 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1314 case PIPE_FUNC_LESS
:
1315 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1316 case PIPE_FUNC_EQUAL
:
1317 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1318 case PIPE_FUNC_LEQUAL
:
1319 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1320 case PIPE_FUNC_GREATER
:
1321 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1322 case PIPE_FUNC_NOTEQUAL
:
1323 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1324 case PIPE_FUNC_GEQUAL
:
1325 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1326 case PIPE_FUNC_ALWAYS
:
1327 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1331 static unsigned si_tex_dim(unsigned dim
, unsigned nr_samples
)
1335 case PIPE_TEXTURE_1D
:
1336 return V_008F1C_SQ_RSRC_IMG_1D
;
1337 case PIPE_TEXTURE_1D_ARRAY
:
1338 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1339 case PIPE_TEXTURE_2D
:
1340 case PIPE_TEXTURE_RECT
:
1341 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1342 V_008F1C_SQ_RSRC_IMG_2D
;
1343 case PIPE_TEXTURE_2D_ARRAY
:
1344 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1345 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1346 case PIPE_TEXTURE_3D
:
1347 return V_008F1C_SQ_RSRC_IMG_3D
;
1348 case PIPE_TEXTURE_CUBE
:
1349 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1354 * Format support testing
1357 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1359 return si_translate_texformat(screen
, format
, util_format_description(format
),
1360 util_format_get_first_non_void_channel(format
)) != ~0U;
1363 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1364 const struct util_format_description
*desc
,
1367 unsigned type
= desc
->channel
[first_non_void
].type
;
1370 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1371 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1373 if (desc
->nr_channels
== 4 &&
1374 desc
->channel
[0].size
== 10 &&
1375 desc
->channel
[1].size
== 10 &&
1376 desc
->channel
[2].size
== 10 &&
1377 desc
->channel
[3].size
== 2)
1378 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1380 /* See whether the components are of the same size. */
1381 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1382 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1383 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1386 switch (desc
->channel
[first_non_void
].size
) {
1388 switch (desc
->nr_channels
) {
1390 return V_008F0C_BUF_DATA_FORMAT_8
;
1392 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1395 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1399 switch (desc
->nr_channels
) {
1401 return V_008F0C_BUF_DATA_FORMAT_16
;
1403 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1406 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1410 /* From the Southern Islands ISA documentation about MTBUF:
1411 * 'Memory reads of data in memory that is 32 or 64 bits do not
1412 * undergo any format conversion.'
1414 if (type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1415 !desc
->channel
[first_non_void
].pure_integer
)
1416 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1418 switch (desc
->nr_channels
) {
1420 return V_008F0C_BUF_DATA_FORMAT_32
;
1422 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1424 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1426 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1431 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1434 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1435 const struct util_format_description
*desc
,
1438 switch (desc
->channel
[first_non_void
].type
) {
1439 case UTIL_FORMAT_TYPE_SIGNED
:
1440 if (desc
->channel
[first_non_void
].normalized
)
1441 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1442 else if (desc
->channel
[first_non_void
].pure_integer
)
1443 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1445 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1447 case UTIL_FORMAT_TYPE_UNSIGNED
:
1448 if (desc
->channel
[first_non_void
].normalized
)
1449 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1450 else if (desc
->channel
[first_non_void
].pure_integer
)
1451 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1453 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1455 case UTIL_FORMAT_TYPE_FLOAT
:
1457 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1461 static bool si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1463 const struct util_format_description
*desc
;
1465 unsigned data_format
;
1467 desc
= util_format_description(format
);
1468 first_non_void
= util_format_get_first_non_void_channel(format
);
1469 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1470 return data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
;
1473 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1475 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1476 si_translate_colorswap(format
) != ~0U;
1479 static bool si_is_zs_format_supported(enum pipe_format format
)
1481 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1484 boolean
si_is_format_supported(struct pipe_screen
*screen
,
1485 enum pipe_format format
,
1486 enum pipe_texture_target target
,
1487 unsigned sample_count
,
1490 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1491 unsigned retval
= 0;
1493 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1494 R600_ERR("r600: unsupported texture type %d\n", target
);
1498 if (!util_format_is_supported(format
, usage
))
1501 if (sample_count
> 1) {
1502 if (HAVE_LLVM
< 0x0304)
1505 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1506 if (sscreen
->b
.chip_class
>= CIK
&& sscreen
->b
.info
.drm_minor
< 35)
1509 switch (sample_count
) {
1519 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
1520 if (target
== PIPE_BUFFER
) {
1521 if (si_is_vertex_format_supported(screen
, format
))
1522 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1524 if (si_is_sampler_format_supported(screen
, format
))
1525 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1529 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1530 PIPE_BIND_DISPLAY_TARGET
|
1532 PIPE_BIND_SHARED
)) &&
1533 si_is_colorbuffer_format_supported(format
)) {
1535 (PIPE_BIND_RENDER_TARGET
|
1536 PIPE_BIND_DISPLAY_TARGET
|
1541 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1542 si_is_zs_format_supported(format
)) {
1543 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1546 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
1547 si_is_vertex_format_supported(screen
, format
)) {
1548 retval
|= PIPE_BIND_VERTEX_BUFFER
;
1551 if (usage
& PIPE_BIND_TRANSFER_READ
)
1552 retval
|= PIPE_BIND_TRANSFER_READ
;
1553 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
1554 retval
|= PIPE_BIND_TRANSFER_WRITE
;
1556 return retval
== usage
;
1559 static unsigned si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
1561 unsigned tile_mode_index
= 0;
1564 tile_mode_index
= rtex
->surface
.stencil_tiling_index
[level
];
1566 tile_mode_index
= rtex
->surface
.tiling_index
[level
];
1568 return tile_mode_index
;
1572 * framebuffer handling
1575 static void si_initialize_color_surface(struct si_context
*sctx
,
1576 struct r600_surface
*surf
)
1578 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1579 unsigned level
= surf
->base
.u
.tex
.level
;
1580 uint64_t offset
= rtex
->surface
.level
[level
].offset
;
1581 unsigned pitch
, slice
;
1582 unsigned color_info
, color_attrib
, color_pitch
, color_view
;
1583 unsigned tile_mode_index
;
1584 unsigned format
, swap
, ntype
, endian
;
1585 const struct util_format_description
*desc
;
1587 unsigned blend_clamp
= 0, blend_bypass
= 0;
1588 unsigned max_comp_size
;
1590 /* Layered rendering doesn't work with LINEAR_GENERAL.
1591 * (LINEAR_ALIGNED and others work) */
1592 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
1593 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
1594 offset
+= rtex
->surface
.level
[level
].slice_size
*
1595 surf
->base
.u
.tex
.first_layer
;
1598 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1599 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1602 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1603 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1608 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1610 desc
= util_format_description(surf
->base
.format
);
1611 for (i
= 0; i
< 4; i
++) {
1612 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1616 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1617 ntype
= V_028C70_NUMBER_FLOAT
;
1619 ntype
= V_028C70_NUMBER_UNORM
;
1620 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1621 ntype
= V_028C70_NUMBER_SRGB
;
1622 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1623 if (desc
->channel
[i
].pure_integer
) {
1624 ntype
= V_028C70_NUMBER_SINT
;
1626 assert(desc
->channel
[i
].normalized
);
1627 ntype
= V_028C70_NUMBER_SNORM
;
1629 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1630 if (desc
->channel
[i
].pure_integer
) {
1631 ntype
= V_028C70_NUMBER_UINT
;
1633 assert(desc
->channel
[i
].normalized
);
1634 ntype
= V_028C70_NUMBER_UNORM
;
1639 format
= si_translate_colorformat(surf
->base
.format
);
1640 if (format
== V_028C70_COLOR_INVALID
) {
1641 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
1643 assert(format
!= V_028C70_COLOR_INVALID
);
1644 swap
= si_translate_colorswap(surf
->base
.format
);
1645 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1646 endian
= V_028C70_ENDIAN_NONE
;
1648 endian
= si_colorformat_endian_swap(format
);
1651 /* blend clamp should be set for all NORM/SRGB types */
1652 if (ntype
== V_028C70_NUMBER_UNORM
||
1653 ntype
== V_028C70_NUMBER_SNORM
||
1654 ntype
== V_028C70_NUMBER_SRGB
)
1657 /* set blend bypass according to docs if SINT/UINT or
1658 8/24 COLOR variants */
1659 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1660 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1661 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1666 color_info
= S_028C70_FORMAT(format
) |
1667 S_028C70_COMP_SWAP(swap
) |
1668 S_028C70_BLEND_CLAMP(blend_clamp
) |
1669 S_028C70_BLEND_BYPASS(blend_bypass
) |
1670 S_028C70_NUMBER_TYPE(ntype
) |
1671 S_028C70_ENDIAN(endian
);
1673 color_pitch
= S_028C64_TILE_MAX(pitch
);
1675 color_attrib
= S_028C74_TILE_MODE_INDEX(tile_mode_index
) |
1676 S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == UTIL_FORMAT_SWIZZLE_1
);
1678 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1679 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1681 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1682 S_028C74_NUM_FRAGMENTS(log_samples
);
1684 if (rtex
->fmask
.size
) {
1685 color_info
|= S_028C70_COMPRESSION(1);
1686 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
1688 color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(rtex
->fmask
.tile_mode_index
);
1690 if (sctx
->b
.chip_class
== SI
) {
1691 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1692 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1694 if (sctx
->b
.chip_class
>= CIK
) {
1695 color_pitch
|= S_028C64_FMASK_TILE_MAX(rtex
->fmask
.pitch
/ 8 - 1);
1700 if (rtex
->cmask
.size
) {
1701 color_info
|= S_028C70_FAST_CLEAR(1);
1704 offset
+= r600_resource_va(sctx
->b
.b
.screen
, surf
->base
.texture
);
1706 surf
->cb_color_base
= offset
>> 8;
1707 surf
->cb_color_pitch
= color_pitch
;
1708 surf
->cb_color_slice
= S_028C68_TILE_MAX(slice
);
1709 surf
->cb_color_view
= color_view
;
1710 surf
->cb_color_info
= color_info
;
1711 surf
->cb_color_attrib
= color_attrib
;
1713 if (rtex
->cmask
.size
) {
1714 surf
->cb_color_cmask
= (offset
+ rtex
->cmask
.offset
) >> 8;
1715 surf
->cb_color_cmask_slice
= S_028C80_TILE_MAX(rtex
->cmask
.slice_tile_max
);
1717 if (rtex
->fmask
.size
) {
1718 surf
->cb_color_fmask
= (offset
+ rtex
->fmask
.offset
) >> 8;
1719 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1722 /* Determine pixel shader export format */
1723 max_comp_size
= si_colorformat_max_comp_size(format
);
1724 if (ntype
== V_028C70_NUMBER_SRGB
||
1725 ((ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) &&
1726 max_comp_size
<= 10) ||
1727 (ntype
== V_028C70_NUMBER_FLOAT
&& max_comp_size
<= 16)) {
1728 surf
->export_16bpc
= true;
1731 surf
->color_initialized
= true;
1734 static void si_init_depth_surface(struct si_context
*sctx
,
1735 struct r600_surface
*surf
)
1737 struct si_screen
*sscreen
= sctx
->screen
;
1738 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1739 unsigned level
= surf
->base
.u
.tex
.level
;
1740 unsigned pitch
, slice
, format
, tile_mode_index
, array_mode
;
1741 unsigned macro_aspect
, tile_split
, stile_split
, bankh
, bankw
, nbanks
, pipe_config
;
1742 uint32_t z_info
, s_info
, db_depth_info
;
1743 uint64_t z_offs
, s_offs
;
1744 uint32_t db_htile_data_base
, db_htile_surface
, pa_su_poly_offset_db_fmt_cntl
;
1746 switch (sctx
->framebuffer
.zsbuf
->texture
->format
) {
1747 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1748 case PIPE_FORMAT_X8Z24_UNORM
:
1749 case PIPE_FORMAT_Z24X8_UNORM
:
1750 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1751 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1753 case PIPE_FORMAT_Z32_FLOAT
:
1754 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1755 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1756 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1758 case PIPE_FORMAT_Z16_UNORM
:
1759 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1765 format
= si_translate_dbformat(rtex
->resource
.b
.b
.format
);
1767 if (format
== V_028040_Z_INVALID
) {
1768 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
1770 assert(format
!= V_028040_Z_INVALID
);
1772 s_offs
= z_offs
= r600_resource_va(sctx
->b
.b
.screen
, surf
->base
.texture
);
1773 z_offs
+= rtex
->surface
.level
[level
].offset
;
1774 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
1776 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1777 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1782 db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
1784 z_info
= S_028040_FORMAT(format
);
1785 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1786 z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1789 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
1790 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
1792 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
1794 if (sctx
->b
.chip_class
>= CIK
) {
1795 switch (rtex
->surface
.level
[level
].mode
) {
1796 case RADEON_SURF_MODE_2D
:
1797 array_mode
= V_02803C_ARRAY_2D_TILED_THIN1
;
1799 case RADEON_SURF_MODE_1D
:
1800 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1801 case RADEON_SURF_MODE_LINEAR
:
1803 array_mode
= V_02803C_ARRAY_1D_TILED_THIN1
;
1806 tile_split
= rtex
->surface
.tile_split
;
1807 stile_split
= rtex
->surface
.stencil_tile_split
;
1808 macro_aspect
= rtex
->surface
.mtilea
;
1809 bankw
= rtex
->surface
.bankw
;
1810 bankh
= rtex
->surface
.bankh
;
1811 tile_split
= cik_tile_split(tile_split
);
1812 stile_split
= cik_tile_split(stile_split
);
1813 macro_aspect
= cik_macro_tile_aspect(macro_aspect
);
1814 bankw
= cik_bank_wh(bankw
);
1815 bankh
= cik_bank_wh(bankh
);
1816 nbanks
= cik_num_banks(sscreen
, rtex
->surface
.bpe
, rtex
->surface
.tile_split
);
1817 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1818 pipe_config
= cik_db_pipe_config(sscreen
, tile_mode_index
);
1820 db_depth_info
|= S_02803C_ARRAY_MODE(array_mode
) |
1821 S_02803C_PIPE_CONFIG(pipe_config
) |
1822 S_02803C_BANK_WIDTH(bankw
) |
1823 S_02803C_BANK_HEIGHT(bankh
) |
1824 S_02803C_MACRO_TILE_ASPECT(macro_aspect
) |
1825 S_02803C_NUM_BANKS(nbanks
);
1826 z_info
|= S_028040_TILE_SPLIT(tile_split
);
1827 s_info
|= S_028044_TILE_SPLIT(stile_split
);
1829 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1830 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
1831 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
1832 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
1835 /* HiZ aka depth buffer htile */
1836 /* use htile only for first level */
1837 if (rtex
->htile_buffer
&& !level
) {
1838 const struct util_format_description
*fmt_desc
;
1840 z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1842 /* This is optimal for the clear value of 1.0 and using
1843 * the LESS and LEQUAL test functions. Set this to 0
1844 * for the opposite case. This can only be changed when
1846 z_info
|= S_028040_ZRANGE_PRECISION(1);
1848 fmt_desc
= util_format_description(rtex
->resource
.b
.b
.format
);
1849 if (!util_format_has_stencil(fmt_desc
)) {
1850 /* Use all of the htile_buffer for depth */
1851 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1854 uint64_t va
= r600_resource_va(&sctx
->screen
->b
.b
, &rtex
->htile_buffer
->b
.b
);
1855 db_htile_data_base
= va
>> 8;
1856 db_htile_surface
= S_028ABC_FULL_CACHE(1);
1858 db_htile_data_base
= 0;
1859 db_htile_surface
= 0;
1862 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1863 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1864 surf
->db_htile_data_base
= db_htile_data_base
;
1865 surf
->db_depth_info
= db_depth_info
;
1866 surf
->db_z_info
= z_info
;
1867 surf
->db_stencil_info
= s_info
;
1868 surf
->db_depth_base
= z_offs
>> 8;
1869 surf
->db_stencil_base
= s_offs
>> 8;
1870 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(pitch
);
1871 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(slice
);
1872 surf
->db_htile_surface
= db_htile_surface
;
1873 surf
->pa_su_poly_offset_db_fmt_cntl
= pa_su_poly_offset_db_fmt_cntl
;
1875 surf
->depth_initialized
= true;
1878 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1879 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1880 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1881 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1882 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1885 * There are two locations (-4, 4), (4, -4). */
1886 static uint32_t sample_locs_2x
[] = {
1887 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1888 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1889 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1890 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1892 static unsigned max_dist_2x
= 4;
1894 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1895 static uint32_t sample_locs_4x
[] = {
1896 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1897 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1898 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1899 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1901 static unsigned max_dist_4x
= 6;
1902 /* Cayman/SI 8xMSAA */
1903 static uint32_t cm_sample_locs_8x
[] = {
1904 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1905 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1906 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1907 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1908 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1909 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1910 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1911 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1913 static unsigned cm_max_dist_8x
= 8;
1914 /* Cayman/SI 16xMSAA */
1915 static uint32_t cm_sample_locs_16x
[] = {
1916 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1917 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1918 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1919 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1920 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1921 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1922 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1923 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1924 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1925 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1926 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1927 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1928 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1929 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1930 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1931 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1933 static unsigned cm_max_dist_16x
= 8;
1935 static void si_get_sample_position(struct pipe_context
*ctx
,
1936 unsigned sample_count
,
1937 unsigned sample_index
,
1944 switch (sample_count
) {
1947 out_value
[0] = out_value
[1] = 0.5;
1950 offset
= 4 * (sample_index
* 2);
1951 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
1952 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1953 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1954 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1957 offset
= 4 * (sample_index
* 2);
1958 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
1959 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1960 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1961 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1964 offset
= 4 * (sample_index
% 4 * 2);
1965 index
= (sample_index
/ 4) * 4;
1966 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
1967 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1968 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1969 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1972 offset
= 4 * (sample_index
% 4 * 2);
1973 index
= (sample_index
/ 4) * 4;
1974 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
1975 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1976 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
1977 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1982 static void si_set_msaa_state(struct si_context
*sctx
, struct si_pm4_state
*pm4
, int nr_samples
)
1984 unsigned max_dist
= 0;
1986 switch (nr_samples
) {
1991 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
[0]);
1992 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
[1]);
1993 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
[2]);
1994 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
[3]);
1995 max_dist
= max_dist_2x
;
1998 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
[0]);
1999 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
[1]);
2000 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
[2]);
2001 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
[3]);
2002 max_dist
= max_dist_4x
;
2005 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, cm_sample_locs_8x
[0]);
2006 si_pm4_set_reg(pm4
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, cm_sample_locs_8x
[4]);
2007 si_pm4_set_reg(pm4
, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, 0);
2008 si_pm4_set_reg(pm4
, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, 0);
2009 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, cm_sample_locs_8x
[1]);
2010 si_pm4_set_reg(pm4
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, cm_sample_locs_8x
[5]);
2011 si_pm4_set_reg(pm4
, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, 0);
2012 si_pm4_set_reg(pm4
, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, 0);
2013 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, cm_sample_locs_8x
[2]);
2014 si_pm4_set_reg(pm4
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, cm_sample_locs_8x
[6]);
2015 si_pm4_set_reg(pm4
, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, 0);
2016 si_pm4_set_reg(pm4
, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, 0);
2017 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, cm_sample_locs_8x
[3]);
2018 si_pm4_set_reg(pm4
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, cm_sample_locs_8x
[7]);
2019 max_dist
= cm_max_dist_8x
;
2022 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, cm_sample_locs_16x
[0]);
2023 si_pm4_set_reg(pm4
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, cm_sample_locs_16x
[4]);
2024 si_pm4_set_reg(pm4
, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, cm_sample_locs_16x
[8]);
2025 si_pm4_set_reg(pm4
, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, cm_sample_locs_16x
[12]);
2026 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, cm_sample_locs_16x
[1]);
2027 si_pm4_set_reg(pm4
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, cm_sample_locs_16x
[5]);
2028 si_pm4_set_reg(pm4
, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, cm_sample_locs_16x
[9]);
2029 si_pm4_set_reg(pm4
, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, cm_sample_locs_16x
[13]);
2030 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, cm_sample_locs_16x
[2]);
2031 si_pm4_set_reg(pm4
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, cm_sample_locs_16x
[6]);
2032 si_pm4_set_reg(pm4
, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, cm_sample_locs_16x
[10]);
2033 si_pm4_set_reg(pm4
, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, cm_sample_locs_16x
[14]);
2034 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, cm_sample_locs_16x
[3]);
2035 si_pm4_set_reg(pm4
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, cm_sample_locs_16x
[7]);
2036 si_pm4_set_reg(pm4
, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
, cm_sample_locs_16x
[11]);
2037 si_pm4_set_reg(pm4
, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
, cm_sample_locs_16x
[15]);
2038 max_dist
= cm_max_dist_16x
;
2042 if (nr_samples
> 1) {
2043 unsigned log_samples
= util_logbase2(nr_samples
);
2045 si_pm4_set_reg(pm4
, R_028BDC_PA_SC_LINE_CNTL
,
2046 S_028BDC_LAST_PIXEL(1) |
2047 S_028BDC_EXPAND_LINE_WIDTH(1));
2048 si_pm4_set_reg(pm4
, R_028BE0_PA_SC_AA_CONFIG
,
2049 S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
2050 S_028BE0_MAX_SAMPLE_DIST(max_dist
) |
2051 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
));
2053 si_pm4_set_reg(pm4
, R_028804_DB_EQAA
,
2054 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
2055 S_028804_PS_ITER_SAMPLES(log_samples
) |
2056 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
2057 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
2058 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2059 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2061 si_pm4_set_reg(pm4
, R_028BDC_PA_SC_LINE_CNTL
, S_028BDC_LAST_PIXEL(1));
2062 si_pm4_set_reg(pm4
, R_028BE0_PA_SC_AA_CONFIG
, 0);
2064 si_pm4_set_reg(pm4
, R_028804_DB_EQAA
,
2065 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2066 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2070 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2071 const struct pipe_framebuffer_state
*state
)
2073 struct si_context
*sctx
= (struct si_context
*)ctx
;
2074 struct r600_surface
*surf
= NULL
;
2075 struct r600_texture
*rtex
;
2076 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2082 if (sctx
->framebuffer
.nr_cbufs
) {
2083 sctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
2084 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
2086 if (sctx
->framebuffer
.zsbuf
) {
2087 sctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
|
2088 R600_CONTEXT_FLUSH_AND_INV_DB_META
;
2091 util_copy_framebuffer_state(&sctx
->framebuffer
, state
);
2094 sctx
->export_16bpc
= 0;
2095 sctx
->fb_compressed_cb_mask
= 0;
2097 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2098 if (!state
->cbufs
[i
]) {
2099 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2100 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2104 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2105 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2107 if (!surf
->color_initialized
) {
2108 si_initialize_color_surface(sctx
, surf
);
2111 if (surf
->export_16bpc
) {
2112 sctx
->export_16bpc
|= 1 << i
;
2115 if (rtex
->fmask
.size
|| rtex
->cmask
.size
) {
2116 sctx
->fb_compressed_cb_mask
|= 1 << i
;
2119 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
2120 si_pm4_set_reg(pm4
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, surf
->cb_color_base
);
2121 si_pm4_set_reg(pm4
, R_028C64_CB_COLOR0_PITCH
+ i
* 0x3C, surf
->cb_color_pitch
);
2122 si_pm4_set_reg(pm4
, R_028C68_CB_COLOR0_SLICE
+ i
* 0x3C, surf
->cb_color_slice
);
2123 si_pm4_set_reg(pm4
, R_028C6C_CB_COLOR0_VIEW
+ i
* 0x3C, surf
->cb_color_view
);
2124 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, surf
->cb_color_info
);
2125 si_pm4_set_reg(pm4
, R_028C74_CB_COLOR0_ATTRIB
+ i
* 0x3C, surf
->cb_color_attrib
);
2126 si_pm4_set_reg(pm4
, R_028C7C_CB_COLOR0_CMASK
+ i
* 0x3C, surf
->cb_color_cmask
);
2127 si_pm4_set_reg(pm4
, R_028C80_CB_COLOR0_CMASK_SLICE
+ i
* 0x3C, surf
->cb_color_cmask_slice
);
2128 si_pm4_set_reg(pm4
, R_028C84_CB_COLOR0_FMASK
+ i
* 0x3C, surf
->cb_color_fmask
);
2129 si_pm4_set_reg(pm4
, R_028C88_CB_COLOR0_FMASK_SLICE
+ i
* 0x3C, surf
->cb_color_fmask_slice
);
2131 /* Set CB_COLOR1_INFO for possible dual-src blending. */
2132 if (i
== 1 && surf
) {
2133 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C, surf
->cb_color_info
);
2134 /* Also set the 16BPC export. */
2135 if (surf
->export_16bpc
) {
2136 sctx
->export_16bpc
|= 1 << 1;
2140 for (; i
< 8; i
++) {
2141 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2142 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2145 assert(!(sctx
->export_16bpc
& ~0xff));
2148 surf
= (struct r600_surface
*)state
->zsbuf
;
2149 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2151 if (!surf
->depth_initialized
) {
2152 si_init_depth_surface(sctx
, surf
);
2155 if (surf
->db_htile_data_base
) {
2156 si_pm4_add_bo(pm4
, rtex
->htile_buffer
, RADEON_USAGE_READWRITE
);
2158 si_pm4_set_reg(pm4
, R_028008_DB_DEPTH_VIEW
, surf
->db_depth_view
);
2159 si_pm4_set_reg(pm4
, R_028014_DB_HTILE_DATA_BASE
, surf
->db_htile_data_base
);
2161 si_pm4_set_reg(pm4
, R_02803C_DB_DEPTH_INFO
, surf
->db_depth_info
);
2162 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, surf
->db_z_info
);
2163 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, surf
->db_stencil_info
);
2164 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
2165 si_pm4_set_reg(pm4
, R_028048_DB_Z_READ_BASE
, surf
->db_depth_base
);
2166 si_pm4_set_reg(pm4
, R_02804C_DB_STENCIL_READ_BASE
, surf
->db_stencil_base
);
2167 si_pm4_set_reg(pm4
, R_028050_DB_Z_WRITE_BASE
, surf
->db_depth_base
);
2168 si_pm4_set_reg(pm4
, R_028054_DB_STENCIL_WRITE_BASE
, surf
->db_stencil_base
);
2169 si_pm4_set_reg(pm4
, R_028058_DB_DEPTH_SIZE
, surf
->db_depth_size
);
2170 si_pm4_set_reg(pm4
, R_02805C_DB_DEPTH_SLICE
, surf
->db_depth_slice
);
2172 si_pm4_set_reg(pm4
, R_028ABC_DB_HTILE_SURFACE
, surf
->db_htile_surface
);
2173 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2174 surf
->pa_su_poly_offset_db_fmt_cntl
);
2176 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, S_028040_FORMAT(V_028040_Z_INVALID
));
2177 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, S_028044_FORMAT(V_028044_STENCIL_INVALID
));
2180 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2181 si_pm4_set_reg(pm4
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2182 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2184 nr_samples
= util_framebuffer_get_num_samples(state
);
2186 si_set_msaa_state(sctx
, pm4
, nr_samples
);
2187 sctx
->fb_log_samples
= util_logbase2(nr_samples
);
2188 sctx
->fb_cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
2189 util_format_is_pure_integer(state
->cbufs
[0]->format
);
2191 si_pm4_set_state(sctx
, framebuffer
, pm4
);
2192 si_update_fb_rs_state(sctx
);
2193 si_update_fb_blend_state(sctx
);
2200 /* Compute the key for the hw shader variant */
2201 static INLINE
void si_shader_selector_key(struct pipe_context
*ctx
,
2202 struct si_pipe_shader_selector
*sel
,
2203 union si_shader_key
*key
)
2205 struct si_context
*sctx
= (struct si_context
*)ctx
;
2206 memset(key
, 0, sizeof(*key
));
2208 if ((sel
->type
== PIPE_SHADER_VERTEX
|| sel
->type
== PIPE_SHADER_GEOMETRY
) &&
2209 sctx
->queued
.named
.rasterizer
) {
2210 if (sctx
->queued
.named
.rasterizer
->clip_plane_enable
& 0xf0)
2211 key
->vs
.ucps_enabled
|= 0x2;
2212 if (sctx
->queued
.named
.rasterizer
->clip_plane_enable
& 0xf)
2213 key
->vs
.ucps_enabled
|= 0x1;
2216 if (sel
->type
== PIPE_SHADER_VERTEX
) {
2218 if (!sctx
->vertex_elements
)
2221 for (i
= 0; i
< sctx
->vertex_elements
->count
; ++i
)
2222 key
->vs
.instance_divisors
[i
] = sctx
->vertex_elements
->elements
[i
].instance_divisor
;
2224 key
->vs
.as_es
= sctx
->gs_shader
!= NULL
;
2225 } else if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
2226 if (sel
->fs_write_all
)
2227 key
->ps
.nr_cbufs
= sctx
->framebuffer
.nr_cbufs
;
2228 key
->ps
.export_16bpc
= sctx
->export_16bpc
;
2230 if (sctx
->queued
.named
.rasterizer
) {
2231 key
->ps
.color_two_side
= sctx
->queued
.named
.rasterizer
->two_side
;
2232 key
->ps
.flatshade
= sctx
->queued
.named
.rasterizer
->flatshade
;
2234 if (sctx
->queued
.named
.blend
) {
2235 key
->ps
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
2236 sctx
->queued
.named
.rasterizer
->multisample_enable
&&
2237 !sctx
->fb_cb0_is_integer
;
2240 if (sctx
->queued
.named
.dsa
) {
2241 key
->ps
.alpha_func
= sctx
->queued
.named
.dsa
->alpha_func
;
2243 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2244 if (sctx
->framebuffer
.nr_cbufs
&&
2245 sctx
->framebuffer
.cbufs
[0] &&
2246 util_format_is_pure_integer(sctx
->framebuffer
.cbufs
[0]->texture
->format
))
2247 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
2249 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
2254 /* Select the hw shader variant depending on the current state. */
2255 int si_shader_select(struct pipe_context
*ctx
,
2256 struct si_pipe_shader_selector
*sel
)
2258 union si_shader_key key
;
2259 struct si_pipe_shader
* shader
= NULL
;
2262 si_shader_selector_key(ctx
, sel
, &key
);
2264 /* Check if we don't need to change anything.
2265 * This path is also used for most shaders that don't need multiple
2266 * variants, it will cost just a computation of the key and this
2268 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
2272 /* lookup if we have other variants in the list */
2273 if (sel
->num_shaders
> 1) {
2274 struct si_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
2276 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
2278 c
= c
->next_variant
;
2282 p
->next_variant
= c
->next_variant
;
2288 shader
->next_variant
= sel
->current
;
2289 sel
->current
= shader
;
2291 shader
= CALLOC(1, sizeof(struct si_pipe_shader
));
2292 shader
->selector
= sel
;
2295 shader
->next_variant
= sel
->current
;
2296 sel
->current
= shader
;
2297 r
= si_pipe_shader_create(ctx
, shader
);
2299 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2301 sel
->current
= NULL
;
2311 static void *si_create_shader_state(struct pipe_context
*ctx
,
2312 const struct pipe_shader_state
*state
,
2313 unsigned pipe_shader_type
)
2315 struct si_pipe_shader_selector
*sel
= CALLOC_STRUCT(si_pipe_shader_selector
);
2318 sel
->type
= pipe_shader_type
;
2319 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2320 sel
->so
= state
->stream_output
;
2322 if (pipe_shader_type
== PIPE_SHADER_FRAGMENT
) {
2323 struct tgsi_shader_info info
;
2325 tgsi_scan_shader(state
->tokens
, &info
);
2326 sel
->fs_write_all
= info
.color0_writes_all_cbufs
;
2329 r
= si_shader_select(ctx
, sel
);
2338 static void *si_create_fs_state(struct pipe_context
*ctx
,
2339 const struct pipe_shader_state
*state
)
2341 return si_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
2344 #if HAVE_LLVM >= 0x0305
2346 static void *si_create_gs_state(struct pipe_context
*ctx
,
2347 const struct pipe_shader_state
*state
)
2349 return si_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
2354 static void *si_create_vs_state(struct pipe_context
*ctx
,
2355 const struct pipe_shader_state
*state
)
2357 return si_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
2360 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2362 struct si_context
*sctx
= (struct si_context
*)ctx
;
2363 struct si_pipe_shader_selector
*sel
= state
;
2365 if (sctx
->vs_shader
== sel
)
2368 if (!sel
|| !sel
->current
)
2371 sctx
->vs_shader
= sel
;
2374 #if HAVE_LLVM >= 0x0305
2376 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2378 struct si_context
*sctx
= (struct si_context
*)ctx
;
2379 struct si_pipe_shader_selector
*sel
= state
;
2381 if (sctx
->gs_shader
== sel
)
2384 sctx
->gs_shader
= sel
;
2389 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2391 struct si_context
*sctx
= (struct si_context
*)ctx
;
2392 struct si_pipe_shader_selector
*sel
= state
;
2394 if (sctx
->ps_shader
== sel
)
2397 if (!sel
|| !sel
->current
)
2398 sel
= sctx
->dummy_pixel_shader
;
2400 sctx
->ps_shader
= sel
;
2403 static void si_delete_shader_selector(struct pipe_context
*ctx
,
2404 struct si_pipe_shader_selector
*sel
)
2406 struct si_context
*sctx
= (struct si_context
*)ctx
;
2407 struct si_pipe_shader
*p
= sel
->current
, *c
;
2410 c
= p
->next_variant
;
2411 si_pm4_delete_state(sctx
, vs
, p
->pm4
);
2412 si_pipe_shader_destroy(ctx
, p
);
2421 static void si_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
2423 struct si_context
*sctx
= (struct si_context
*)ctx
;
2424 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2426 if (sctx
->vs_shader
== sel
) {
2427 sctx
->vs_shader
= NULL
;
2430 si_delete_shader_selector(ctx
, sel
);
2433 #if HAVE_LLVM >= 0x0305
2435 static void si_delete_gs_shader(struct pipe_context
*ctx
, void *state
)
2437 struct si_context
*sctx
= (struct si_context
*)ctx
;
2438 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2440 if (sctx
->gs_shader
== sel
) {
2441 sctx
->gs_shader
= NULL
;
2444 si_delete_shader_selector(ctx
, sel
);
2449 static void si_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
2451 struct si_context
*sctx
= (struct si_context
*)ctx
;
2452 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2454 if (sctx
->ps_shader
== sel
) {
2455 sctx
->ps_shader
= NULL
;
2458 si_delete_shader_selector(ctx
, sel
);
2465 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
2466 struct pipe_resource
*texture
,
2467 const struct pipe_sampler_view
*state
)
2469 struct si_pipe_sampler_view
*view
= CALLOC_STRUCT(si_pipe_sampler_view
);
2470 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
2471 const struct util_format_description
*desc
;
2472 unsigned format
, num_format
;
2474 unsigned char state_swizzle
[4], swizzle
[4];
2475 unsigned height
, depth
, width
;
2476 enum pipe_format pipe_format
= state
->format
;
2477 struct radeon_surface_level
*surflevel
;
2484 /* initialize base object */
2485 view
->base
= *state
;
2486 view
->base
.texture
= NULL
;
2487 pipe_resource_reference(&view
->base
.texture
, texture
);
2488 view
->base
.reference
.count
= 1;
2489 view
->base
.context
= ctx
;
2490 view
->resource
= &tmp
->resource
;
2492 /* Buffer resource. */
2493 if (texture
->target
== PIPE_BUFFER
) {
2496 desc
= util_format_description(state
->format
);
2497 first_non_void
= util_format_get_first_non_void_channel(state
->format
);
2498 stride
= desc
->block
.bits
/ 8;
2499 va
= r600_resource_va(ctx
->screen
, texture
) + state
->u
.buf
.first_element
*stride
;
2500 format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
2501 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
2503 view
->state
[0] = va
;
2504 view
->state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
2505 S_008F04_STRIDE(stride
);
2506 view
->state
[2] = state
->u
.buf
.last_element
+ 1 - state
->u
.buf
.first_element
;
2507 view
->state
[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2508 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2509 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2510 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2511 S_008F0C_NUM_FORMAT(num_format
) |
2512 S_008F0C_DATA_FORMAT(format
);
2516 state_swizzle
[0] = state
->swizzle_r
;
2517 state_swizzle
[1] = state
->swizzle_g
;
2518 state_swizzle
[2] = state
->swizzle_b
;
2519 state_swizzle
[3] = state
->swizzle_a
;
2521 surflevel
= tmp
->surface
.level
;
2523 /* Texturing with separate depth and stencil. */
2524 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
2525 switch (pipe_format
) {
2526 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2527 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
2529 case PIPE_FORMAT_X8Z24_UNORM
:
2530 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2531 /* Z24 is always stored like this. */
2532 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
2534 case PIPE_FORMAT_X24S8_UINT
:
2535 case PIPE_FORMAT_S8X24_UINT
:
2536 case PIPE_FORMAT_X32_S8X24_UINT
:
2537 pipe_format
= PIPE_FORMAT_S8_UINT
;
2538 surflevel
= tmp
->surface
.stencil_level
;
2544 desc
= util_format_description(pipe_format
);
2546 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2547 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2548 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2550 switch (pipe_format
) {
2551 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2552 case PIPE_FORMAT_X24S8_UINT
:
2553 case PIPE_FORMAT_X32_S8X24_UINT
:
2554 case PIPE_FORMAT_X8Z24_UNORM
:
2555 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2558 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2561 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2564 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2566 switch (pipe_format
) {
2567 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2568 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2571 if (first_non_void
< 0) {
2572 if (util_format_is_compressed(pipe_format
)) {
2573 switch (pipe_format
) {
2574 case PIPE_FORMAT_DXT1_SRGB
:
2575 case PIPE_FORMAT_DXT1_SRGBA
:
2576 case PIPE_FORMAT_DXT3_SRGBA
:
2577 case PIPE_FORMAT_DXT5_SRGBA
:
2578 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2580 case PIPE_FORMAT_RGTC1_SNORM
:
2581 case PIPE_FORMAT_LATC1_SNORM
:
2582 case PIPE_FORMAT_RGTC2_SNORM
:
2583 case PIPE_FORMAT_LATC2_SNORM
:
2584 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2587 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2591 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2593 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2594 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2596 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2598 switch (desc
->channel
[first_non_void
].type
) {
2599 case UTIL_FORMAT_TYPE_FLOAT
:
2600 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2602 case UTIL_FORMAT_TYPE_SIGNED
:
2603 if (desc
->channel
[first_non_void
].normalized
)
2604 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2605 else if (desc
->channel
[first_non_void
].pure_integer
)
2606 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2608 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2610 case UTIL_FORMAT_TYPE_UNSIGNED
:
2611 if (desc
->channel
[first_non_void
].normalized
)
2612 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2613 else if (desc
->channel
[first_non_void
].pure_integer
)
2614 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2616 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2621 format
= si_translate_texformat(ctx
->screen
, pipe_format
, desc
, first_non_void
);
2626 /* not supported any more */
2627 //endian = si_colorformat_endian_swap(format);
2629 width
= surflevel
[0].npix_x
;
2630 height
= surflevel
[0].npix_y
;
2631 depth
= surflevel
[0].npix_z
;
2632 pitch
= surflevel
[0].nblk_x
* util_format_get_blockwidth(pipe_format
);
2634 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
2636 depth
= texture
->array_size
;
2637 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
2638 depth
= texture
->array_size
;
2641 va
= r600_resource_va(ctx
->screen
, texture
);
2642 va
+= surflevel
[0].offset
;
2643 va
+= tmp
->mipmap_shift
* surflevel
[texture
->last_level
].slice_size
;
2644 view
->state
[0] = va
>> 8;
2645 view
->state
[1] = (S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2646 S_008F14_DATA_FORMAT(format
) |
2647 S_008F14_NUM_FORMAT(num_format
));
2648 view
->state
[2] = (S_008F18_WIDTH(width
- 1) |
2649 S_008F18_HEIGHT(height
- 1));
2650 view
->state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2651 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2652 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2653 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2654 S_008F1C_BASE_LEVEL(texture
->nr_samples
> 1 ?
2655 0 : state
->u
.tex
.first_level
- tmp
->mipmap_shift
) |
2656 S_008F1C_LAST_LEVEL(texture
->nr_samples
> 1 ?
2657 util_logbase2(texture
->nr_samples
) :
2658 state
->u
.tex
.last_level
- tmp
->mipmap_shift
) |
2659 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp
, 0, false)) |
2660 S_008F1C_POW2_PAD(texture
->last_level
> 0) |
2661 S_008F1C_TYPE(si_tex_dim(texture
->target
, texture
->nr_samples
)));
2662 view
->state
[4] = (S_008F20_DEPTH(depth
- 1) | S_008F20_PITCH(pitch
- 1));
2663 view
->state
[5] = (S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2664 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
));
2668 /* Initialize the sampler view for FMASK. */
2669 if (tmp
->fmask
.size
) {
2670 uint64_t va
= r600_resource_va(ctx
->screen
, texture
) + tmp
->fmask
.offset
;
2671 uint32_t fmask_format
;
2673 switch (texture
->nr_samples
) {
2675 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
2678 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
2681 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
2685 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
2688 view
->fmask_state
[0] = va
>> 8;
2689 view
->fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2690 S_008F14_DATA_FORMAT(fmask_format
) |
2691 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
2692 view
->fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
2693 S_008F18_HEIGHT(height
- 1);
2694 view
->fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
2695 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
2696 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
2697 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
2698 S_008F1C_TILING_INDEX(tmp
->fmask
.tile_mode_index
) |
2699 S_008F1C_TYPE(si_tex_dim(texture
->target
, 0));
2700 view
->fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
2701 S_008F20_PITCH(tmp
->fmask
.pitch
- 1);
2702 view
->fmask_state
[5] = S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2703 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
);
2704 view
->fmask_state
[6] = 0;
2705 view
->fmask_state
[7] = 0;
2711 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
2712 struct pipe_sampler_view
*state
)
2714 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
2716 pipe_resource_reference(&state
->texture
, NULL
);
2720 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2722 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2723 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2725 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2726 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2729 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2731 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2732 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2734 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2735 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2736 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2737 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2738 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2741 static void *si_create_sampler_state(struct pipe_context
*ctx
,
2742 const struct pipe_sampler_state
*state
)
2744 struct si_pipe_sampler_state
*rstate
= CALLOC_STRUCT(si_pipe_sampler_state
);
2745 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
2746 unsigned border_color_type
;
2748 if (rstate
== NULL
) {
2752 if (sampler_state_needs_border_color(state
))
2753 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
2755 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2757 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
2758 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
2759 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
2760 (state
->max_anisotropy
& 0x7) << 9 | /* XXX */
2761 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
2762 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
2763 aniso_flag_offset
<< 16 | /* XXX */
2764 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
));
2765 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
2766 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)));
2767 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
2768 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
)) |
2769 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
)) |
2770 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)));
2771 rstate
->val
[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
2773 if (border_color_type
== V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2774 memcpy(rstate
->border_color
, state
->border_color
.ui
,
2775 sizeof(rstate
->border_color
));
2781 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2782 * the si_set_sampler_view calls. LTO might help too. */
2783 static void si_set_sampler_views(struct pipe_context
*ctx
,
2784 unsigned shader
, unsigned start
,
2786 struct pipe_sampler_view
**views
)
2788 struct si_context
*sctx
= (struct si_context
*)ctx
;
2789 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
2790 struct si_pipe_sampler_view
**rviews
= (struct si_pipe_sampler_view
**)views
;
2793 if (shader
>= SI_NUM_SHADERS
)
2798 for (i
= 0; i
< count
; i
++) {
2800 samplers
->depth_texture_mask
&= ~(1 << i
);
2801 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2802 si_set_sampler_view(sctx
, shader
, i
, NULL
, NULL
);
2803 si_set_sampler_view(sctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2808 si_set_sampler_view(sctx
, shader
, i
, views
[i
], rviews
[i
]->state
);
2810 if (views
[i
]->texture
->target
!= PIPE_BUFFER
) {
2811 struct r600_texture
*rtex
=
2812 (struct r600_texture
*)views
[i
]->texture
;
2814 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
2815 samplers
->depth_texture_mask
|= 1 << i
;
2817 samplers
->depth_texture_mask
&= ~(1 << i
);
2819 if (rtex
->cmask
.size
|| rtex
->fmask
.size
) {
2820 samplers
->compressed_colortex_mask
|= 1 << i
;
2822 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2825 if (rtex
->fmask
.size
) {
2826 si_set_sampler_view(sctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2827 views
[i
], rviews
[i
]->fmask_state
);
2829 si_set_sampler_view(sctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2834 for (; i
< samplers
->n_views
; i
++) {
2835 samplers
->depth_texture_mask
&= ~(1 << i
);
2836 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2837 si_set_sampler_view(sctx
, shader
, i
, NULL
, NULL
);
2838 si_set_sampler_view(sctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2842 samplers
->n_views
= count
;
2843 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
2846 static void si_set_sampler_states(struct si_context
*sctx
,
2847 struct si_pm4_state
*pm4
,
2848 unsigned count
, void **states
,
2849 struct si_textures_info
*samplers
,
2850 unsigned user_data_reg
)
2852 struct si_pipe_sampler_state
**rstates
= (struct si_pipe_sampler_state
**)states
;
2853 uint32_t *border_color_table
= NULL
;
2859 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
2861 si_pm4_sh_data_begin(pm4
);
2862 for (i
= 0; i
< count
; i
++) {
2864 G_008F3C_BORDER_COLOR_TYPE(rstates
[i
]->val
[3]) ==
2865 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2866 if (!sctx
->border_color_table
||
2867 ((sctx
->border_color_offset
+ count
- i
) &
2868 C_008F3C_BORDER_COLOR_PTR
)) {
2869 r600_resource_reference(&sctx
->border_color_table
, NULL
);
2870 sctx
->border_color_offset
= 0;
2872 sctx
->border_color_table
=
2873 si_resource_create_custom(&sctx
->screen
->b
.b
,
2878 if (!border_color_table
) {
2879 border_color_table
=
2880 sctx
->b
.ws
->buffer_map(sctx
->border_color_table
->cs_buf
,
2881 sctx
->b
.rings
.gfx
.cs
,
2882 PIPE_TRANSFER_WRITE
|
2883 PIPE_TRANSFER_UNSYNCHRONIZED
);
2886 for (j
= 0; j
< 4; j
++) {
2887 border_color_table
[4 * sctx
->border_color_offset
+ j
] =
2888 util_le32_to_cpu(rstates
[i
]->border_color
[j
]);
2891 rstates
[i
]->val
[3] &= C_008F3C_BORDER_COLOR_PTR
;
2892 rstates
[i
]->val
[3] |= S_008F3C_BORDER_COLOR_PTR(sctx
->border_color_offset
++);
2895 for (j
= 0; j
< Elements(rstates
[i
]->val
); ++j
) {
2896 si_pm4_sh_data_add(pm4
, rstates
[i
] ? rstates
[i
]->val
[j
] : 0);
2899 si_pm4_sh_data_end(pm4
, user_data_reg
, SI_SGPR_SAMPLER
);
2901 if (border_color_table
) {
2902 uint64_t va_offset
=
2903 r600_resource_va(&sctx
->screen
->b
.b
,
2904 (void*)sctx
->border_color_table
);
2906 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, va_offset
>> 8);
2907 if (sctx
->b
.chip_class
>= CIK
)
2908 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, va_offset
>> 40);
2909 sctx
->b
.ws
->buffer_unmap(sctx
->border_color_table
->cs_buf
);
2910 si_pm4_add_bo(pm4
, sctx
->border_color_table
, RADEON_USAGE_READ
);
2913 memcpy(samplers
->samplers
, states
, sizeof(void*) * count
);
2916 samplers
->n_samplers
= count
;
2919 static void si_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
2921 struct si_context
*sctx
= (struct si_context
*)ctx
;
2922 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2924 si_set_sampler_states(sctx
, pm4
, count
, states
,
2925 &sctx
->samplers
[PIPE_SHADER_VERTEX
],
2926 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2927 #if HAVE_LLVM >= 0x0305
2928 si_set_sampler_states(sctx
, pm4
, count
, states
,
2929 &sctx
->samplers
[PIPE_SHADER_VERTEX
],
2930 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2932 si_pm4_set_state(sctx
, vs_sampler
, pm4
);
2935 static void si_bind_gs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
2937 struct si_context
*sctx
= (struct si_context
*)ctx
;
2938 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2940 si_set_sampler_states(sctx
, pm4
, count
, states
,
2941 &sctx
->samplers
[PIPE_SHADER_GEOMETRY
],
2942 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2943 si_pm4_set_state(sctx
, gs_sampler
, pm4
);
2946 static void si_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
2948 struct si_context
*sctx
= (struct si_context
*)ctx
;
2949 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2951 si_set_sampler_states(sctx
, pm4
, count
, states
,
2952 &sctx
->samplers
[PIPE_SHADER_FRAGMENT
],
2953 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2954 si_pm4_set_state(sctx
, ps_sampler
, pm4
);
2958 static void si_bind_sampler_states(struct pipe_context
*ctx
, unsigned shader
,
2959 unsigned start
, unsigned count
,
2965 case PIPE_SHADER_VERTEX
:
2966 si_bind_vs_sampler_states(ctx
, count
, states
);
2968 case PIPE_SHADER_GEOMETRY
:
2969 si_bind_gs_sampler_states(ctx
, count
, states
);
2971 case PIPE_SHADER_FRAGMENT
:
2972 si_bind_ps_sampler_states(ctx
, count
, states
);
2981 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2983 struct si_context
*sctx
= (struct si_context
*)ctx
;
2984 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2985 uint16_t mask
= sample_mask
;
2990 si_pm4_set_reg(pm4
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, mask
| (mask
<< 16));
2991 si_pm4_set_reg(pm4
, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, mask
| (mask
<< 16));
2993 si_pm4_set_state(sctx
, sample_mask
, pm4
);
2996 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
3002 * Vertex elements & buffers
3005 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
3007 const struct pipe_vertex_element
*elements
)
3009 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
3012 assert(count
< PIPE_MAX_ATTRIBS
);
3017 for (i
= 0; i
< count
; ++i
) {
3018 const struct util_format_description
*desc
;
3019 unsigned data_format
, num_format
;
3022 desc
= util_format_description(elements
[i
].src_format
);
3023 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
3024 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
3025 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
3027 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3028 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3029 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3030 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3031 S_008F0C_NUM_FORMAT(num_format
) |
3032 S_008F0C_DATA_FORMAT(data_format
);
3034 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
3039 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
3041 struct si_context
*sctx
= (struct si_context
*)ctx
;
3042 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
3044 sctx
->vertex_elements
= v
;
3047 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
3049 struct si_context
*sctx
= (struct si_context
*)ctx
;
3051 if (sctx
->vertex_elements
== state
)
3052 sctx
->vertex_elements
= NULL
;
3056 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
3057 const struct pipe_vertex_buffer
*buffers
)
3059 struct si_context
*sctx
= (struct si_context
*)ctx
;
3061 util_set_vertex_buffers_count(sctx
->vertex_buffer
, &sctx
->nr_vertex_buffers
, buffers
, start_slot
, count
);
3064 static void si_set_index_buffer(struct pipe_context
*ctx
,
3065 const struct pipe_index_buffer
*ib
)
3067 struct si_context
*sctx
= (struct si_context
*)ctx
;
3070 pipe_resource_reference(&sctx
->index_buffer
.buffer
, ib
->buffer
);
3071 memcpy(&sctx
->index_buffer
, ib
, sizeof(*ib
));
3073 pipe_resource_reference(&sctx
->index_buffer
.buffer
, NULL
);
3080 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
3081 const struct pipe_poly_stipple
*state
)
3085 static void si_texture_barrier(struct pipe_context
*ctx
)
3087 struct si_context
*sctx
= (struct si_context
*)ctx
;
3089 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
3090 R600_CONTEXT_FLUSH_AND_INV_CB
;
3093 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
3095 struct pipe_blend_state blend
;
3097 memset(&blend
, 0, sizeof(blend
));
3098 blend
.independent_blend_enable
= true;
3099 blend
.rt
[0].colormask
= 0xf;
3100 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
3103 static boolean
si_dma_copy(struct pipe_context
*ctx
,
3104 struct pipe_resource
*dst
,
3106 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
3107 struct pipe_resource
*src
,
3109 const struct pipe_box
*src_box
)
3111 /* XXX implement this or share evergreen_dma_blit with r600g */
3115 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
3117 /* XXX Turn this into a proper state. Right now the queries are
3118 * enabled in draw_vbo, which snoops r600_common_context to see
3119 * if any occlusion queries are active. */
3122 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3123 bool include_draw_vbo
)
3125 si_need_cs_space((struct si_context
*)ctx
, num_dw
, include_draw_vbo
);
3128 void si_init_state_functions(struct si_context
*sctx
)
3132 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
3133 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
3134 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
3135 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
3137 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
3138 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
3139 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
3141 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
3142 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
3143 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
3145 for (i
= 0; i
< 8; i
++) {
3146 sctx
->custom_dsa_flush_depth_stencil
[i
] = si_create_db_flush_dsa(sctx
, true, true, i
);
3147 sctx
->custom_dsa_flush_depth
[i
] = si_create_db_flush_dsa(sctx
, true, false, i
);
3148 sctx
->custom_dsa_flush_stencil
[i
] = si_create_db_flush_dsa(sctx
, false, true, i
);
3150 sctx
->custom_dsa_flush_inplace
= si_create_db_flush_dsa(sctx
, false, false, 0);
3151 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
3152 sctx
->custom_blend_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
3154 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
3155 sctx
->b
.b
.set_scissor_states
= si_set_scissor_states
;
3156 sctx
->b
.b
.set_viewport_states
= si_set_viewport_states
;
3157 sctx
->b
.b
.set_stencil_ref
= si_set_pipe_stencil_ref
;
3159 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3160 sctx
->b
.b
.get_sample_position
= si_get_sample_position
;
3162 sctx
->b
.b
.create_vs_state
= si_create_vs_state
;
3163 sctx
->b
.b
.create_fs_state
= si_create_fs_state
;
3164 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3165 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3166 sctx
->b
.b
.delete_vs_state
= si_delete_vs_shader
;
3167 sctx
->b
.b
.delete_fs_state
= si_delete_ps_shader
;
3168 #if HAVE_LLVM >= 0x0305
3169 sctx
->b
.b
.create_gs_state
= si_create_gs_state
;
3170 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3171 sctx
->b
.b
.delete_gs_state
= si_delete_gs_shader
;
3174 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3175 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
3176 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3178 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3179 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
3180 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3182 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3184 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3185 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3186 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3187 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3188 sctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3190 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3191 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
3192 sctx
->b
.dma_copy
= si_dma_copy
;
3193 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
3194 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
3196 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3199 void si_init_config(struct si_context
*sctx
)
3201 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
3206 si_cmd_context_control(pm4
);
3208 si_pm4_set_reg(pm4
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0);
3210 si_pm4_set_reg(pm4
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0);
3211 si_pm4_set_reg(pm4
, R_028A14_VGT_HOS_CNTL
, 0x0);
3212 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0);
3213 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0);
3214 si_pm4_set_reg(pm4
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0);
3215 si_pm4_set_reg(pm4
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0);
3216 si_pm4_set_reg(pm4
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0);
3217 si_pm4_set_reg(pm4
, R_028A2C_VGT_GROUP_DECR
, 0x0);
3218 si_pm4_set_reg(pm4
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0);
3219 si_pm4_set_reg(pm4
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0);
3220 si_pm4_set_reg(pm4
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0);
3221 si_pm4_set_reg(pm4
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0);
3223 /* FIXME calculate these values somehow ??? */
3224 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, 0x80);
3225 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
3226 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
3228 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0x0);
3229 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
3230 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0);
3231 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3233 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, 0);
3234 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, 0);
3235 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, 0);
3236 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
, 0);
3238 si_pm4_set_reg(pm4
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0);
3239 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
3240 if (sctx
->b
.chip_class
== SI
) {
3241 si_pm4_set_reg(pm4
, R_028AA8_IA_MULTI_VGT_PARAM
,
3242 S_028AA8_SWITCH_ON_EOP(1) |
3243 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3244 S_028AA8_PRIMGROUP_SIZE(63));
3246 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
, 0x00000000);
3247 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
3248 if (sctx
->b
.chip_class
< CIK
)
3249 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
3250 S_008A14_CLIP_VTX_REORDER_ENA(1));
3252 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
3253 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
3255 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
3257 if (sctx
->b
.chip_class
>= CIK
) {
3258 switch (sctx
->screen
->b
.family
) {
3260 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x16000012);
3261 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x00000000);
3264 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x3a00161a);
3265 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x0000002e);
3272 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3273 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x00000000);
3277 switch (sctx
->screen
->b
.family
) {
3280 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x2a00126a);
3283 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x0000124a);
3286 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000082);
3289 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3292 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3297 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
3298 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
3299 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
3300 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3301 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
3302 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
3303 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3305 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3306 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3307 si_pm4_set_reg(pm4
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000);
3308 si_pm4_set_reg(pm4
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000);
3309 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
3310 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000);
3311 si_pm4_set_reg(pm4
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000);
3312 si_pm4_set_reg(pm4
, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000);
3313 si_pm4_set_reg(pm4
, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000);
3314 si_pm4_set_reg(pm4
, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000);
3315 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, 0x00000000);
3316 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, 0x00000000);
3317 si_pm4_set_reg(pm4
, R_028028_DB_STENCIL_CLEAR
, 0x00000000);
3318 si_pm4_set_reg(pm4
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000);
3319 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
3320 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
3321 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
3322 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
3323 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3324 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
3325 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
3326 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
3328 if (sctx
->b
.chip_class
>= CIK
) {
3329 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
3330 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(0));
3331 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
3334 si_pm4_set_state(sctx
, init
, pm4
);