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radeonsi: implement EXPCLEAR optimization for depth
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_helpers.h"
38 #include "util/u_memory.h"
39
40 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
41 void (*emit)(struct si_context *ctx, struct r600_atom *state),
42 unsigned num_dw)
43 {
44 atom->emit = (void*)emit;
45 atom->num_dw = num_dw;
46 atom->dirty = false;
47 *list_elem = atom;
48 }
49
50 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
51 {
52 if (sscreen->b.chip_class == CIK &&
53 sscreen->b.info.cik_macrotile_mode_array_valid) {
54 unsigned index, tileb;
55
56 tileb = 8 * 8 * tex->surface.bpe;
57 tileb = MIN2(tex->surface.tile_split, tileb);
58
59 for (index = 0; tileb > 64; index++) {
60 tileb >>= 1;
61 }
62 assert(index < 16);
63
64 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
65 }
66
67 if (sscreen->b.chip_class == SI &&
68 sscreen->b.info.si_tile_mode_array_valid) {
69 /* Don't use stencil_tiling_index, because num_banks is always
70 * read from the depth mode. */
71 unsigned tile_mode_index = tex->surface.tiling_index[0];
72 assert(tile_mode_index < 32);
73
74 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
75 }
76
77 /* The old way. */
78 switch (sscreen->b.tiling_info.num_banks) {
79 case 2:
80 return V_02803C_ADDR_SURF_2_BANK;
81 case 4:
82 return V_02803C_ADDR_SURF_4_BANK;
83 case 8:
84 default:
85 return V_02803C_ADDR_SURF_8_BANK;
86 case 16:
87 return V_02803C_ADDR_SURF_16_BANK;
88 }
89 }
90
91 unsigned cik_tile_split(unsigned tile_split)
92 {
93 switch (tile_split) {
94 case 64:
95 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
96 break;
97 case 128:
98 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
99 break;
100 case 256:
101 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
102 break;
103 case 512:
104 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
105 break;
106 default:
107 case 1024:
108 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
109 break;
110 case 2048:
111 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
112 break;
113 case 4096:
114 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
115 break;
116 }
117 return tile_split;
118 }
119
120 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
121 {
122 switch (macro_tile_aspect) {
123 default:
124 case 1:
125 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
126 break;
127 case 2:
128 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
129 break;
130 case 4:
131 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
132 break;
133 case 8:
134 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
135 break;
136 }
137 return macro_tile_aspect;
138 }
139
140 unsigned cik_bank_wh(unsigned bankwh)
141 {
142 switch (bankwh) {
143 default:
144 case 1:
145 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
146 break;
147 case 2:
148 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
149 break;
150 case 4:
151 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
152 break;
153 case 8:
154 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
155 break;
156 }
157 return bankwh;
158 }
159
160 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
161 {
162 if (sscreen->b.info.si_tile_mode_array_valid) {
163 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
164
165 return G_009910_PIPE_CONFIG(gb_tile_mode);
166 }
167
168 /* This is probably broken for a lot of chips, but it's only used
169 * if the kernel cannot return the tile mode array for CIK. */
170 switch (sscreen->b.info.r600_num_tile_pipes) {
171 case 16:
172 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
173 case 8:
174 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
175 case 4:
176 default:
177 if (sscreen->b.info.r600_num_backends == 4)
178 return V_02803C_X_ADDR_SURF_P4_16X16;
179 else
180 return V_02803C_X_ADDR_SURF_P4_8X16;
181 case 2:
182 return V_02803C_ADDR_SURF_P2;
183 }
184 }
185
186 static unsigned si_map_swizzle(unsigned swizzle)
187 {
188 switch (swizzle) {
189 case UTIL_FORMAT_SWIZZLE_Y:
190 return V_008F0C_SQ_SEL_Y;
191 case UTIL_FORMAT_SWIZZLE_Z:
192 return V_008F0C_SQ_SEL_Z;
193 case UTIL_FORMAT_SWIZZLE_W:
194 return V_008F0C_SQ_SEL_W;
195 case UTIL_FORMAT_SWIZZLE_0:
196 return V_008F0C_SQ_SEL_0;
197 case UTIL_FORMAT_SWIZZLE_1:
198 return V_008F0C_SQ_SEL_1;
199 default: /* UTIL_FORMAT_SWIZZLE_X */
200 return V_008F0C_SQ_SEL_X;
201 }
202 }
203
204 static uint32_t S_FIXED(float value, uint32_t frac_bits)
205 {
206 return value * (1 << frac_bits);
207 }
208
209 /* 12.4 fixed-point */
210 static unsigned si_pack_float_12p4(float x)
211 {
212 return x <= 0 ? 0 :
213 x >= 4096 ? 0xffff : x * 16;
214 }
215
216 /*
217 * inferred framebuffer and blender state
218 */
219 static void si_update_fb_blend_state(struct si_context *sctx)
220 {
221 struct si_pm4_state *pm4;
222 struct si_state_blend *blend = sctx->queued.named.blend;
223 uint32_t mask;
224
225 if (blend == NULL)
226 return;
227
228 pm4 = si_pm4_alloc_state(sctx);
229 if (pm4 == NULL)
230 return;
231
232 mask = (1ULL << ((unsigned)sctx->framebuffer.state.nr_cbufs * 4)) - 1;
233 mask &= blend->cb_target_mask;
234 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
235
236 si_pm4_set_state(sctx, fb_blend, pm4);
237 }
238
239 /*
240 * Blender functions
241 */
242
243 static uint32_t si_translate_blend_function(int blend_func)
244 {
245 switch (blend_func) {
246 case PIPE_BLEND_ADD:
247 return V_028780_COMB_DST_PLUS_SRC;
248 case PIPE_BLEND_SUBTRACT:
249 return V_028780_COMB_SRC_MINUS_DST;
250 case PIPE_BLEND_REVERSE_SUBTRACT:
251 return V_028780_COMB_DST_MINUS_SRC;
252 case PIPE_BLEND_MIN:
253 return V_028780_COMB_MIN_DST_SRC;
254 case PIPE_BLEND_MAX:
255 return V_028780_COMB_MAX_DST_SRC;
256 default:
257 R600_ERR("Unknown blend function %d\n", blend_func);
258 assert(0);
259 break;
260 }
261 return 0;
262 }
263
264 static uint32_t si_translate_blend_factor(int blend_fact)
265 {
266 switch (blend_fact) {
267 case PIPE_BLENDFACTOR_ONE:
268 return V_028780_BLEND_ONE;
269 case PIPE_BLENDFACTOR_SRC_COLOR:
270 return V_028780_BLEND_SRC_COLOR;
271 case PIPE_BLENDFACTOR_SRC_ALPHA:
272 return V_028780_BLEND_SRC_ALPHA;
273 case PIPE_BLENDFACTOR_DST_ALPHA:
274 return V_028780_BLEND_DST_ALPHA;
275 case PIPE_BLENDFACTOR_DST_COLOR:
276 return V_028780_BLEND_DST_COLOR;
277 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
278 return V_028780_BLEND_SRC_ALPHA_SATURATE;
279 case PIPE_BLENDFACTOR_CONST_COLOR:
280 return V_028780_BLEND_CONSTANT_COLOR;
281 case PIPE_BLENDFACTOR_CONST_ALPHA:
282 return V_028780_BLEND_CONSTANT_ALPHA;
283 case PIPE_BLENDFACTOR_ZERO:
284 return V_028780_BLEND_ZERO;
285 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
286 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
287 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
288 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
289 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
290 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
291 case PIPE_BLENDFACTOR_INV_DST_COLOR:
292 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
293 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
294 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
295 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
296 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
297 case PIPE_BLENDFACTOR_SRC1_COLOR:
298 return V_028780_BLEND_SRC1_COLOR;
299 case PIPE_BLENDFACTOR_SRC1_ALPHA:
300 return V_028780_BLEND_SRC1_ALPHA;
301 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
302 return V_028780_BLEND_INV_SRC1_COLOR;
303 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
304 return V_028780_BLEND_INV_SRC1_ALPHA;
305 default:
306 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
307 assert(0);
308 break;
309 }
310 return 0;
311 }
312
313 static void *si_create_blend_state_mode(struct pipe_context *ctx,
314 const struct pipe_blend_state *state,
315 unsigned mode)
316 {
317 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
318 struct si_pm4_state *pm4 = &blend->pm4;
319
320 uint32_t color_control = 0;
321
322 if (blend == NULL)
323 return NULL;
324
325 blend->alpha_to_one = state->alpha_to_one;
326
327 if (state->logicop_enable) {
328 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
329 } else {
330 color_control |= S_028808_ROP3(0xcc);
331 }
332
333 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
334 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
335 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
336 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
337 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
338 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
339
340 blend->cb_target_mask = 0;
341 for (int i = 0; i < 8; i++) {
342 /* state->rt entries > 0 only written if independent blending */
343 const int j = state->independent_blend_enable ? i : 0;
344
345 unsigned eqRGB = state->rt[j].rgb_func;
346 unsigned srcRGB = state->rt[j].rgb_src_factor;
347 unsigned dstRGB = state->rt[j].rgb_dst_factor;
348 unsigned eqA = state->rt[j].alpha_func;
349 unsigned srcA = state->rt[j].alpha_src_factor;
350 unsigned dstA = state->rt[j].alpha_dst_factor;
351
352 unsigned blend_cntl = 0;
353
354 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
355 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
356
357 if (!state->rt[j].blend_enable) {
358 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
359 continue;
360 }
361
362 blend_cntl |= S_028780_ENABLE(1);
363 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
364 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
365 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
366
367 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
368 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
369 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
370 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
371 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
372 }
373 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
374 }
375
376 if (blend->cb_target_mask) {
377 color_control |= S_028808_MODE(mode);
378 } else {
379 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
380 }
381 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
382
383 return blend;
384 }
385
386 static void *si_create_blend_state(struct pipe_context *ctx,
387 const struct pipe_blend_state *state)
388 {
389 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
390 }
391
392 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
393 {
394 struct si_context *sctx = (struct si_context *)ctx;
395 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
396 si_update_fb_blend_state(sctx);
397 }
398
399 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
400 {
401 struct si_context *sctx = (struct si_context *)ctx;
402 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
403 }
404
405 static void si_set_blend_color(struct pipe_context *ctx,
406 const struct pipe_blend_color *state)
407 {
408 struct si_context *sctx = (struct si_context *)ctx;
409 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
410
411 if (pm4 == NULL)
412 return;
413
414 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
415 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
416 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
417 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
418
419 si_pm4_set_state(sctx, blend_color, pm4);
420 }
421
422 /*
423 * Clipping, scissors and viewport
424 */
425
426 static void si_set_clip_state(struct pipe_context *ctx,
427 const struct pipe_clip_state *state)
428 {
429 struct si_context *sctx = (struct si_context *)ctx;
430 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
431 struct pipe_constant_buffer cb;
432
433 if (pm4 == NULL)
434 return;
435
436 for (int i = 0; i < 6; i++) {
437 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
438 fui(state->ucp[i][0]));
439 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
440 fui(state->ucp[i][1]));
441 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
442 fui(state->ucp[i][2]));
443 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
444 fui(state->ucp[i][3]));
445 }
446
447 cb.buffer = NULL;
448 cb.user_buffer = state->ucp;
449 cb.buffer_offset = 0;
450 cb.buffer_size = 4*4*8;
451 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
452 pipe_resource_reference(&cb.buffer, NULL);
453
454 si_pm4_set_state(sctx, clip, pm4);
455 }
456
457 static void si_set_scissor_states(struct pipe_context *ctx,
458 unsigned start_slot,
459 unsigned num_scissors,
460 const struct pipe_scissor_state *state)
461 {
462 struct si_context *sctx = (struct si_context *)ctx;
463 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
464 struct si_pm4_state *pm4 = &scissor->pm4;
465
466 if (scissor == NULL)
467 return;
468
469 scissor->scissor = *state;
470 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
471 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
472 S_028250_WINDOW_OFFSET_DISABLE(1));
473 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
474 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
475
476 si_pm4_set_state(sctx, scissor, scissor);
477 }
478
479 static void si_set_viewport_states(struct pipe_context *ctx,
480 unsigned start_slot,
481 unsigned num_viewports,
482 const struct pipe_viewport_state *state)
483 {
484 struct si_context *sctx = (struct si_context *)ctx;
485 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
486 struct si_pm4_state *pm4 = &viewport->pm4;
487
488 if (viewport == NULL)
489 return;
490
491 viewport->viewport = *state;
492 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
493 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
494 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
495 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
496 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
497 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
498
499 si_pm4_set_state(sctx, viewport, viewport);
500 }
501
502 /*
503 * inferred state between framebuffer and rasterizer
504 */
505 static void si_update_fb_rs_state(struct si_context *sctx)
506 {
507 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
508 struct si_pm4_state *pm4;
509 float offset_units;
510
511 if (!rs || !sctx->framebuffer.state.zsbuf)
512 return;
513
514 offset_units = sctx->queued.named.rasterizer->offset_units;
515 switch (sctx->framebuffer.state.zsbuf->texture->format) {
516 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
517 case PIPE_FORMAT_X8Z24_UNORM:
518 case PIPE_FORMAT_Z24X8_UNORM:
519 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
520 offset_units *= 2.0f;
521 break;
522 case PIPE_FORMAT_Z32_FLOAT:
523 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
524 offset_units *= 1.0f;
525 break;
526 case PIPE_FORMAT_Z16_UNORM:
527 offset_units *= 4.0f;
528 break;
529 default:
530 return;
531 }
532
533 pm4 = si_pm4_alloc_state(sctx);
534
535 if (pm4 == NULL)
536 return;
537
538 /* FIXME some of those reg can be computed with cso */
539 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
540 fui(sctx->queued.named.rasterizer->offset_scale));
541 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
542 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
543 fui(sctx->queued.named.rasterizer->offset_scale));
544 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
545
546 si_pm4_set_state(sctx, fb_rs, pm4);
547 }
548
549 /*
550 * Rasterizer
551 */
552
553 static uint32_t si_translate_fill(uint32_t func)
554 {
555 switch(func) {
556 case PIPE_POLYGON_MODE_FILL:
557 return V_028814_X_DRAW_TRIANGLES;
558 case PIPE_POLYGON_MODE_LINE:
559 return V_028814_X_DRAW_LINES;
560 case PIPE_POLYGON_MODE_POINT:
561 return V_028814_X_DRAW_POINTS;
562 default:
563 assert(0);
564 return V_028814_X_DRAW_POINTS;
565 }
566 }
567
568 static void *si_create_rs_state(struct pipe_context *ctx,
569 const struct pipe_rasterizer_state *state)
570 {
571 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
572 struct si_pm4_state *pm4 = &rs->pm4;
573 unsigned tmp;
574 unsigned prov_vtx = 1, polygon_dual_mode;
575 float psize_min, psize_max;
576
577 if (rs == NULL) {
578 return NULL;
579 }
580
581 rs->two_side = state->light_twoside;
582 rs->multisample_enable = state->multisample;
583 rs->clip_plane_enable = state->clip_plane_enable;
584 rs->line_stipple_enable = state->line_stipple_enable;
585
586 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
587 state->fill_back != PIPE_POLYGON_MODE_FILL);
588
589 if (state->flatshade_first)
590 prov_vtx = 0;
591
592 rs->flatshade = state->flatshade;
593 rs->sprite_coord_enable = state->sprite_coord_enable;
594 rs->pa_sc_line_stipple = state->line_stipple_enable ?
595 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
596 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
597 rs->pa_su_sc_mode_cntl =
598 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
599 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
600 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
601 S_028814_FACE(!state->front_ccw) |
602 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
603 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
604 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
605 S_028814_POLY_MODE(polygon_dual_mode) |
606 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
607 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
608 rs->pa_cl_clip_cntl =
609 S_028810_PS_UCP_MODE(3) |
610 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
611 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
612 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
613 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
614
615 /* offset */
616 rs->offset_units = state->offset_units;
617 rs->offset_scale = state->offset_scale * 12.0f;
618
619 tmp = S_0286D4_FLAT_SHADE_ENA(1);
620 if (state->sprite_coord_enable) {
621 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
622 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
623 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
624 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
625 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
626 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
627 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
628 }
629 }
630 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
631
632 /* point size 12.4 fixed point */
633 tmp = (unsigned)(state->point_size * 8.0);
634 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
635
636 if (state->point_size_per_vertex) {
637 psize_min = util_get_min_point_size(state);
638 psize_max = 8192;
639 } else {
640 /* Force the point size to be as if the vertex output was disabled. */
641 psize_min = state->point_size;
642 psize_max = state->point_size;
643 }
644 /* Divide by two, because 0.5 = 1 pixel. */
645 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
646 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
647 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
648
649 tmp = (unsigned)state->line_width * 8;
650 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
651 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
652 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
653 S_028A48_MSAA_ENABLE(state->multisample) |
654 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
655
656 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
657 S_028BE4_PIX_CENTER(state->half_pixel_center) |
658 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
659
660 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
661
662 return rs;
663 }
664
665 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
666 {
667 struct si_context *sctx = (struct si_context *)ctx;
668 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
669
670 if (state == NULL)
671 return;
672
673 // TODO
674 sctx->sprite_coord_enable = rs->sprite_coord_enable;
675 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
676 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
677
678 si_pm4_bind_state(sctx, rasterizer, rs);
679 si_update_fb_rs_state(sctx);
680 }
681
682 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
683 {
684 struct si_context *sctx = (struct si_context *)ctx;
685 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
686 }
687
688 /*
689 * infeered state between dsa and stencil ref
690 */
691 static void si_update_dsa_stencil_ref(struct si_context *sctx)
692 {
693 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
694 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
695 struct si_state_dsa *dsa = sctx->queued.named.dsa;
696
697 if (pm4 == NULL)
698 return;
699
700 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
701 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
702 S_028430_STENCILMASK(dsa->valuemask[0]) |
703 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
704 S_028430_STENCILOPVAL(1));
705 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
706 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
707 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
708 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
709 S_028434_STENCILOPVAL_BF(1));
710
711 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
712 }
713
714 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
715 const struct pipe_stencil_ref *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718 sctx->stencil_ref = *state;
719 si_update_dsa_stencil_ref(sctx);
720 }
721
722
723 /*
724 * DSA
725 */
726
727 static uint32_t si_translate_stencil_op(int s_op)
728 {
729 switch (s_op) {
730 case PIPE_STENCIL_OP_KEEP:
731 return V_02842C_STENCIL_KEEP;
732 case PIPE_STENCIL_OP_ZERO:
733 return V_02842C_STENCIL_ZERO;
734 case PIPE_STENCIL_OP_REPLACE:
735 return V_02842C_STENCIL_REPLACE_TEST;
736 case PIPE_STENCIL_OP_INCR:
737 return V_02842C_STENCIL_ADD_CLAMP;
738 case PIPE_STENCIL_OP_DECR:
739 return V_02842C_STENCIL_SUB_CLAMP;
740 case PIPE_STENCIL_OP_INCR_WRAP:
741 return V_02842C_STENCIL_ADD_WRAP;
742 case PIPE_STENCIL_OP_DECR_WRAP:
743 return V_02842C_STENCIL_SUB_WRAP;
744 case PIPE_STENCIL_OP_INVERT:
745 return V_02842C_STENCIL_INVERT;
746 default:
747 R600_ERR("Unknown stencil op %d", s_op);
748 assert(0);
749 break;
750 }
751 return 0;
752 }
753
754 static void *si_create_dsa_state(struct pipe_context *ctx,
755 const struct pipe_depth_stencil_alpha_state *state)
756 {
757 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
758 struct si_pm4_state *pm4 = &dsa->pm4;
759 unsigned db_depth_control;
760 uint32_t db_stencil_control = 0;
761
762 if (dsa == NULL) {
763 return NULL;
764 }
765
766 dsa->valuemask[0] = state->stencil[0].valuemask;
767 dsa->valuemask[1] = state->stencil[1].valuemask;
768 dsa->writemask[0] = state->stencil[0].writemask;
769 dsa->writemask[1] = state->stencil[1].writemask;
770
771 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
772 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
773 S_028800_ZFUNC(state->depth.func);
774
775 /* stencil */
776 if (state->stencil[0].enabled) {
777 db_depth_control |= S_028800_STENCIL_ENABLE(1);
778 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
779 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
780 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
781 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
782
783 if (state->stencil[1].enabled) {
784 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
785 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
786 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
787 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
788 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
789 }
790 }
791
792 /* alpha */
793 if (state->alpha.enabled) {
794 dsa->alpha_func = state->alpha.func;
795 dsa->alpha_ref = state->alpha.ref_value;
796
797 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
798 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
799 } else {
800 dsa->alpha_func = PIPE_FUNC_ALWAYS;
801 }
802
803 /* misc */
804 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
805 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
806
807 return dsa;
808 }
809
810 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
811 {
812 struct si_context *sctx = (struct si_context *)ctx;
813 struct si_state_dsa *dsa = state;
814
815 if (state == NULL)
816 return;
817
818 si_pm4_bind_state(sctx, dsa, dsa);
819 si_update_dsa_stencil_ref(sctx);
820 }
821
822 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
823 {
824 struct si_context *sctx = (struct si_context *)ctx;
825 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
826 }
827
828 static void *si_create_db_flush_dsa(struct si_context *sctx)
829 {
830 struct pipe_depth_stencil_alpha_state dsa = {};
831
832 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
833 }
834
835 /*
836 * format translation
837 */
838 static uint32_t si_translate_colorformat(enum pipe_format format)
839 {
840 const struct util_format_description *desc = util_format_description(format);
841
842 #define HAS_SIZE(x,y,z,w) \
843 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
844 desc->channel[2].size == (z) && desc->channel[3].size == (w))
845
846 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
847 return V_028C70_COLOR_10_11_11;
848
849 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
850 return V_028C70_COLOR_INVALID;
851
852 switch (desc->nr_channels) {
853 case 1:
854 switch (desc->channel[0].size) {
855 case 8:
856 return V_028C70_COLOR_8;
857 case 16:
858 return V_028C70_COLOR_16;
859 case 32:
860 return V_028C70_COLOR_32;
861 }
862 break;
863 case 2:
864 if (desc->channel[0].size == desc->channel[1].size) {
865 switch (desc->channel[0].size) {
866 case 8:
867 return V_028C70_COLOR_8_8;
868 case 16:
869 return V_028C70_COLOR_16_16;
870 case 32:
871 return V_028C70_COLOR_32_32;
872 }
873 } else if (HAS_SIZE(8,24,0,0)) {
874 return V_028C70_COLOR_24_8;
875 } else if (HAS_SIZE(24,8,0,0)) {
876 return V_028C70_COLOR_8_24;
877 }
878 break;
879 case 3:
880 if (HAS_SIZE(5,6,5,0)) {
881 return V_028C70_COLOR_5_6_5;
882 } else if (HAS_SIZE(32,8,24,0)) {
883 return V_028C70_COLOR_X24_8_32_FLOAT;
884 }
885 break;
886 case 4:
887 if (desc->channel[0].size == desc->channel[1].size &&
888 desc->channel[0].size == desc->channel[2].size &&
889 desc->channel[0].size == desc->channel[3].size) {
890 switch (desc->channel[0].size) {
891 case 4:
892 return V_028C70_COLOR_4_4_4_4;
893 case 8:
894 return V_028C70_COLOR_8_8_8_8;
895 case 16:
896 return V_028C70_COLOR_16_16_16_16;
897 case 32:
898 return V_028C70_COLOR_32_32_32_32;
899 }
900 } else if (HAS_SIZE(5,5,5,1)) {
901 return V_028C70_COLOR_1_5_5_5;
902 } else if (HAS_SIZE(10,10,10,2)) {
903 return V_028C70_COLOR_2_10_10_10;
904 }
905 break;
906 }
907 return V_028C70_COLOR_INVALID;
908 }
909
910 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
911 {
912 if (SI_BIG_ENDIAN) {
913 switch(colorformat) {
914 /* 8-bit buffers. */
915 case V_028C70_COLOR_8:
916 return V_028C70_ENDIAN_NONE;
917
918 /* 16-bit buffers. */
919 case V_028C70_COLOR_5_6_5:
920 case V_028C70_COLOR_1_5_5_5:
921 case V_028C70_COLOR_4_4_4_4:
922 case V_028C70_COLOR_16:
923 case V_028C70_COLOR_8_8:
924 return V_028C70_ENDIAN_8IN16;
925
926 /* 32-bit buffers. */
927 case V_028C70_COLOR_8_8_8_8:
928 case V_028C70_COLOR_2_10_10_10:
929 case V_028C70_COLOR_8_24:
930 case V_028C70_COLOR_24_8:
931 case V_028C70_COLOR_16_16:
932 return V_028C70_ENDIAN_8IN32;
933
934 /* 64-bit buffers. */
935 case V_028C70_COLOR_16_16_16_16:
936 return V_028C70_ENDIAN_8IN16;
937
938 case V_028C70_COLOR_32_32:
939 return V_028C70_ENDIAN_8IN32;
940
941 /* 128-bit buffers. */
942 case V_028C70_COLOR_32_32_32_32:
943 return V_028C70_ENDIAN_8IN32;
944 default:
945 return V_028C70_ENDIAN_NONE; /* Unsupported. */
946 }
947 } else {
948 return V_028C70_ENDIAN_NONE;
949 }
950 }
951
952 /* Returns the size in bits of the widest component of a CB format */
953 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
954 {
955 switch(colorformat) {
956 case V_028C70_COLOR_4_4_4_4:
957 return 4;
958
959 case V_028C70_COLOR_1_5_5_5:
960 case V_028C70_COLOR_5_5_5_1:
961 return 5;
962
963 case V_028C70_COLOR_5_6_5:
964 return 6;
965
966 case V_028C70_COLOR_8:
967 case V_028C70_COLOR_8_8:
968 case V_028C70_COLOR_8_8_8_8:
969 return 8;
970
971 case V_028C70_COLOR_10_10_10_2:
972 case V_028C70_COLOR_2_10_10_10:
973 return 10;
974
975 case V_028C70_COLOR_10_11_11:
976 case V_028C70_COLOR_11_11_10:
977 return 11;
978
979 case V_028C70_COLOR_16:
980 case V_028C70_COLOR_16_16:
981 case V_028C70_COLOR_16_16_16_16:
982 return 16;
983
984 case V_028C70_COLOR_8_24:
985 case V_028C70_COLOR_24_8:
986 return 24;
987
988 case V_028C70_COLOR_32:
989 case V_028C70_COLOR_32_32:
990 case V_028C70_COLOR_32_32_32_32:
991 case V_028C70_COLOR_X24_8_32_FLOAT:
992 return 32;
993 }
994
995 assert(!"Unknown maximum component size");
996 return 0;
997 }
998
999 static uint32_t si_translate_dbformat(enum pipe_format format)
1000 {
1001 switch (format) {
1002 case PIPE_FORMAT_Z16_UNORM:
1003 return V_028040_Z_16;
1004 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1005 case PIPE_FORMAT_X8Z24_UNORM:
1006 case PIPE_FORMAT_Z24X8_UNORM:
1007 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1008 return V_028040_Z_24; /* deprecated on SI */
1009 case PIPE_FORMAT_Z32_FLOAT:
1010 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1011 return V_028040_Z_32_FLOAT;
1012 default:
1013 return V_028040_Z_INVALID;
1014 }
1015 }
1016
1017 /*
1018 * Texture translation
1019 */
1020
1021 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1022 enum pipe_format format,
1023 const struct util_format_description *desc,
1024 int first_non_void)
1025 {
1026 struct si_screen *sscreen = (struct si_screen*)screen;
1027 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1028 boolean uniform = TRUE;
1029 int i;
1030
1031 /* Colorspace (return non-RGB formats directly). */
1032 switch (desc->colorspace) {
1033 /* Depth stencil formats */
1034 case UTIL_FORMAT_COLORSPACE_ZS:
1035 switch (format) {
1036 case PIPE_FORMAT_Z16_UNORM:
1037 return V_008F14_IMG_DATA_FORMAT_16;
1038 case PIPE_FORMAT_X24S8_UINT:
1039 case PIPE_FORMAT_Z24X8_UNORM:
1040 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1041 return V_008F14_IMG_DATA_FORMAT_8_24;
1042 case PIPE_FORMAT_X8Z24_UNORM:
1043 case PIPE_FORMAT_S8X24_UINT:
1044 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1045 return V_008F14_IMG_DATA_FORMAT_24_8;
1046 case PIPE_FORMAT_S8_UINT:
1047 return V_008F14_IMG_DATA_FORMAT_8;
1048 case PIPE_FORMAT_Z32_FLOAT:
1049 return V_008F14_IMG_DATA_FORMAT_32;
1050 case PIPE_FORMAT_X32_S8X24_UINT:
1051 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1052 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1053 default:
1054 goto out_unknown;
1055 }
1056
1057 case UTIL_FORMAT_COLORSPACE_YUV:
1058 goto out_unknown; /* TODO */
1059
1060 case UTIL_FORMAT_COLORSPACE_SRGB:
1061 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1062 goto out_unknown;
1063 break;
1064
1065 default:
1066 break;
1067 }
1068
1069 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1070 if (!enable_s3tc)
1071 goto out_unknown;
1072
1073 switch (format) {
1074 case PIPE_FORMAT_RGTC1_SNORM:
1075 case PIPE_FORMAT_LATC1_SNORM:
1076 case PIPE_FORMAT_RGTC1_UNORM:
1077 case PIPE_FORMAT_LATC1_UNORM:
1078 return V_008F14_IMG_DATA_FORMAT_BC4;
1079 case PIPE_FORMAT_RGTC2_SNORM:
1080 case PIPE_FORMAT_LATC2_SNORM:
1081 case PIPE_FORMAT_RGTC2_UNORM:
1082 case PIPE_FORMAT_LATC2_UNORM:
1083 return V_008F14_IMG_DATA_FORMAT_BC5;
1084 default:
1085 goto out_unknown;
1086 }
1087 }
1088
1089 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1090 if (!enable_s3tc)
1091 goto out_unknown;
1092
1093 switch (format) {
1094 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1095 case PIPE_FORMAT_BPTC_SRGBA:
1096 return V_008F14_IMG_DATA_FORMAT_BC7;
1097 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1098 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1099 return V_008F14_IMG_DATA_FORMAT_BC6;
1100 default:
1101 goto out_unknown;
1102 }
1103 }
1104
1105 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1106 switch (format) {
1107 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1108 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1109 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1110 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1111 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1112 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1113 default:
1114 goto out_unknown;
1115 }
1116 }
1117
1118 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1119
1120 if (!enable_s3tc)
1121 goto out_unknown;
1122
1123 if (!util_format_s3tc_enabled) {
1124 goto out_unknown;
1125 }
1126
1127 switch (format) {
1128 case PIPE_FORMAT_DXT1_RGB:
1129 case PIPE_FORMAT_DXT1_RGBA:
1130 case PIPE_FORMAT_DXT1_SRGB:
1131 case PIPE_FORMAT_DXT1_SRGBA:
1132 return V_008F14_IMG_DATA_FORMAT_BC1;
1133 case PIPE_FORMAT_DXT3_RGBA:
1134 case PIPE_FORMAT_DXT3_SRGBA:
1135 return V_008F14_IMG_DATA_FORMAT_BC2;
1136 case PIPE_FORMAT_DXT5_RGBA:
1137 case PIPE_FORMAT_DXT5_SRGBA:
1138 return V_008F14_IMG_DATA_FORMAT_BC3;
1139 default:
1140 goto out_unknown;
1141 }
1142 }
1143
1144 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1145 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1146 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1147 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1148 }
1149
1150 /* R8G8Bx_SNORM - TODO CxV8U8 */
1151
1152 /* See whether the components are of the same size. */
1153 for (i = 1; i < desc->nr_channels; i++) {
1154 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1155 }
1156
1157 /* Non-uniform formats. */
1158 if (!uniform) {
1159 switch(desc->nr_channels) {
1160 case 3:
1161 if (desc->channel[0].size == 5 &&
1162 desc->channel[1].size == 6 &&
1163 desc->channel[2].size == 5) {
1164 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1165 }
1166 goto out_unknown;
1167 case 4:
1168 if (desc->channel[0].size == 5 &&
1169 desc->channel[1].size == 5 &&
1170 desc->channel[2].size == 5 &&
1171 desc->channel[3].size == 1) {
1172 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1173 }
1174 if (desc->channel[0].size == 10 &&
1175 desc->channel[1].size == 10 &&
1176 desc->channel[2].size == 10 &&
1177 desc->channel[3].size == 2) {
1178 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1179 }
1180 goto out_unknown;
1181 }
1182 goto out_unknown;
1183 }
1184
1185 if (first_non_void < 0 || first_non_void > 3)
1186 goto out_unknown;
1187
1188 /* uniform formats */
1189 switch (desc->channel[first_non_void].size) {
1190 case 4:
1191 switch (desc->nr_channels) {
1192 #if 0 /* Not supported for render targets */
1193 case 2:
1194 return V_008F14_IMG_DATA_FORMAT_4_4;
1195 #endif
1196 case 4:
1197 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1198 }
1199 break;
1200 case 8:
1201 switch (desc->nr_channels) {
1202 case 1:
1203 return V_008F14_IMG_DATA_FORMAT_8;
1204 case 2:
1205 return V_008F14_IMG_DATA_FORMAT_8_8;
1206 case 4:
1207 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1208 }
1209 break;
1210 case 16:
1211 switch (desc->nr_channels) {
1212 case 1:
1213 return V_008F14_IMG_DATA_FORMAT_16;
1214 case 2:
1215 return V_008F14_IMG_DATA_FORMAT_16_16;
1216 case 4:
1217 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1218 }
1219 break;
1220 case 32:
1221 switch (desc->nr_channels) {
1222 case 1:
1223 return V_008F14_IMG_DATA_FORMAT_32;
1224 case 2:
1225 return V_008F14_IMG_DATA_FORMAT_32_32;
1226 #if 0 /* Not supported for render targets */
1227 case 3:
1228 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1229 #endif
1230 case 4:
1231 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1232 }
1233 }
1234
1235 out_unknown:
1236 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1237 return ~0;
1238 }
1239
1240 static unsigned si_tex_wrap(unsigned wrap)
1241 {
1242 switch (wrap) {
1243 default:
1244 case PIPE_TEX_WRAP_REPEAT:
1245 return V_008F30_SQ_TEX_WRAP;
1246 case PIPE_TEX_WRAP_CLAMP:
1247 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1248 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1249 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1250 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1251 return V_008F30_SQ_TEX_CLAMP_BORDER;
1252 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1253 return V_008F30_SQ_TEX_MIRROR;
1254 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1255 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1256 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1257 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1258 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1259 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1260 }
1261 }
1262
1263 static unsigned si_tex_filter(unsigned filter)
1264 {
1265 switch (filter) {
1266 default:
1267 case PIPE_TEX_FILTER_NEAREST:
1268 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1269 case PIPE_TEX_FILTER_LINEAR:
1270 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1271 }
1272 }
1273
1274 static unsigned si_tex_mipfilter(unsigned filter)
1275 {
1276 switch (filter) {
1277 case PIPE_TEX_MIPFILTER_NEAREST:
1278 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1279 case PIPE_TEX_MIPFILTER_LINEAR:
1280 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1281 default:
1282 case PIPE_TEX_MIPFILTER_NONE:
1283 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1284 }
1285 }
1286
1287 static unsigned si_tex_compare(unsigned compare)
1288 {
1289 switch (compare) {
1290 default:
1291 case PIPE_FUNC_NEVER:
1292 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1293 case PIPE_FUNC_LESS:
1294 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1295 case PIPE_FUNC_EQUAL:
1296 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1297 case PIPE_FUNC_LEQUAL:
1298 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1299 case PIPE_FUNC_GREATER:
1300 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1301 case PIPE_FUNC_NOTEQUAL:
1302 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1303 case PIPE_FUNC_GEQUAL:
1304 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1305 case PIPE_FUNC_ALWAYS:
1306 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1307 }
1308 }
1309
1310 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1311 {
1312 switch (dim) {
1313 default:
1314 case PIPE_TEXTURE_1D:
1315 return V_008F1C_SQ_RSRC_IMG_1D;
1316 case PIPE_TEXTURE_1D_ARRAY:
1317 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1318 case PIPE_TEXTURE_2D:
1319 case PIPE_TEXTURE_RECT:
1320 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1321 V_008F1C_SQ_RSRC_IMG_2D;
1322 case PIPE_TEXTURE_2D_ARRAY:
1323 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1324 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1325 case PIPE_TEXTURE_3D:
1326 return V_008F1C_SQ_RSRC_IMG_3D;
1327 case PIPE_TEXTURE_CUBE:
1328 case PIPE_TEXTURE_CUBE_ARRAY:
1329 return V_008F1C_SQ_RSRC_IMG_CUBE;
1330 }
1331 }
1332
1333 /*
1334 * Format support testing
1335 */
1336
1337 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1338 {
1339 return si_translate_texformat(screen, format, util_format_description(format),
1340 util_format_get_first_non_void_channel(format)) != ~0U;
1341 }
1342
1343 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1344 const struct util_format_description *desc,
1345 int first_non_void)
1346 {
1347 unsigned type = desc->channel[first_non_void].type;
1348 int i;
1349
1350 if (type == UTIL_FORMAT_TYPE_FIXED)
1351 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1352
1353 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1354 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1355
1356 if (desc->nr_channels == 4 &&
1357 desc->channel[0].size == 10 &&
1358 desc->channel[1].size == 10 &&
1359 desc->channel[2].size == 10 &&
1360 desc->channel[3].size == 2)
1361 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1362
1363 /* See whether the components are of the same size. */
1364 for (i = 0; i < desc->nr_channels; i++) {
1365 if (desc->channel[first_non_void].size != desc->channel[i].size)
1366 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1367 }
1368
1369 switch (desc->channel[first_non_void].size) {
1370 case 8:
1371 switch (desc->nr_channels) {
1372 case 1:
1373 return V_008F0C_BUF_DATA_FORMAT_8;
1374 case 2:
1375 return V_008F0C_BUF_DATA_FORMAT_8_8;
1376 case 3:
1377 case 4:
1378 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1379 }
1380 break;
1381 case 16:
1382 switch (desc->nr_channels) {
1383 case 1:
1384 return V_008F0C_BUF_DATA_FORMAT_16;
1385 case 2:
1386 return V_008F0C_BUF_DATA_FORMAT_16_16;
1387 case 3:
1388 case 4:
1389 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1390 }
1391 break;
1392 case 32:
1393 /* From the Southern Islands ISA documentation about MTBUF:
1394 * 'Memory reads of data in memory that is 32 or 64 bits do not
1395 * undergo any format conversion.'
1396 */
1397 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1398 !desc->channel[first_non_void].pure_integer)
1399 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1400
1401 switch (desc->nr_channels) {
1402 case 1:
1403 return V_008F0C_BUF_DATA_FORMAT_32;
1404 case 2:
1405 return V_008F0C_BUF_DATA_FORMAT_32_32;
1406 case 3:
1407 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1408 case 4:
1409 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1410 }
1411 break;
1412 }
1413
1414 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1415 }
1416
1417 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1418 const struct util_format_description *desc,
1419 int first_non_void)
1420 {
1421 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1422 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1423
1424 switch (desc->channel[first_non_void].type) {
1425 case UTIL_FORMAT_TYPE_SIGNED:
1426 if (desc->channel[first_non_void].normalized)
1427 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1428 else if (desc->channel[first_non_void].pure_integer)
1429 return V_008F0C_BUF_NUM_FORMAT_SINT;
1430 else
1431 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1432 break;
1433 case UTIL_FORMAT_TYPE_UNSIGNED:
1434 if (desc->channel[first_non_void].normalized)
1435 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1436 else if (desc->channel[first_non_void].pure_integer)
1437 return V_008F0C_BUF_NUM_FORMAT_UINT;
1438 else
1439 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1440 break;
1441 case UTIL_FORMAT_TYPE_FLOAT:
1442 default:
1443 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1444 }
1445 }
1446
1447 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1448 {
1449 const struct util_format_description *desc;
1450 int first_non_void;
1451 unsigned data_format;
1452
1453 desc = util_format_description(format);
1454 first_non_void = util_format_get_first_non_void_channel(format);
1455 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1456 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1457 }
1458
1459 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1460 {
1461 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1462 r600_translate_colorswap(format) != ~0U;
1463 }
1464
1465 static bool si_is_zs_format_supported(enum pipe_format format)
1466 {
1467 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1468 }
1469
1470 boolean si_is_format_supported(struct pipe_screen *screen,
1471 enum pipe_format format,
1472 enum pipe_texture_target target,
1473 unsigned sample_count,
1474 unsigned usage)
1475 {
1476 struct si_screen *sscreen = (struct si_screen *)screen;
1477 unsigned retval = 0;
1478
1479 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1480 R600_ERR("r600: unsupported texture type %d\n", target);
1481 return FALSE;
1482 }
1483
1484 if (!util_format_is_supported(format, usage))
1485 return FALSE;
1486
1487 if (sample_count > 1) {
1488 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1489 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1490 return FALSE;
1491
1492 switch (sample_count) {
1493 case 2:
1494 case 4:
1495 case 8:
1496 break;
1497 default:
1498 return FALSE;
1499 }
1500 }
1501
1502 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1503 if (target == PIPE_BUFFER) {
1504 if (si_is_vertex_format_supported(screen, format))
1505 retval |= PIPE_BIND_SAMPLER_VIEW;
1506 } else {
1507 if (si_is_sampler_format_supported(screen, format))
1508 retval |= PIPE_BIND_SAMPLER_VIEW;
1509 }
1510 }
1511
1512 if ((usage & (PIPE_BIND_RENDER_TARGET |
1513 PIPE_BIND_DISPLAY_TARGET |
1514 PIPE_BIND_SCANOUT |
1515 PIPE_BIND_SHARED |
1516 PIPE_BIND_BLENDABLE)) &&
1517 si_is_colorbuffer_format_supported(format)) {
1518 retval |= usage &
1519 (PIPE_BIND_RENDER_TARGET |
1520 PIPE_BIND_DISPLAY_TARGET |
1521 PIPE_BIND_SCANOUT |
1522 PIPE_BIND_SHARED);
1523 if (!util_format_is_pure_integer(format) &&
1524 !util_format_is_depth_or_stencil(format))
1525 retval |= usage & PIPE_BIND_BLENDABLE;
1526 }
1527
1528 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1529 si_is_zs_format_supported(format)) {
1530 retval |= PIPE_BIND_DEPTH_STENCIL;
1531 }
1532
1533 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1534 si_is_vertex_format_supported(screen, format)) {
1535 retval |= PIPE_BIND_VERTEX_BUFFER;
1536 }
1537
1538 if (usage & PIPE_BIND_TRANSFER_READ)
1539 retval |= PIPE_BIND_TRANSFER_READ;
1540 if (usage & PIPE_BIND_TRANSFER_WRITE)
1541 retval |= PIPE_BIND_TRANSFER_WRITE;
1542
1543 return retval == usage;
1544 }
1545
1546 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1547 {
1548 unsigned tile_mode_index = 0;
1549
1550 if (stencil) {
1551 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1552 } else {
1553 tile_mode_index = rtex->surface.tiling_index[level];
1554 }
1555 return tile_mode_index;
1556 }
1557
1558 /*
1559 * framebuffer handling
1560 */
1561
1562 static void si_initialize_color_surface(struct si_context *sctx,
1563 struct r600_surface *surf)
1564 {
1565 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1566 unsigned level = surf->base.u.tex.level;
1567 uint64_t offset = rtex->surface.level[level].offset;
1568 unsigned pitch, slice;
1569 unsigned color_info, color_attrib, color_pitch, color_view;
1570 unsigned tile_mode_index;
1571 unsigned format, swap, ntype, endian;
1572 const struct util_format_description *desc;
1573 int i;
1574 unsigned blend_clamp = 0, blend_bypass = 0;
1575 unsigned max_comp_size;
1576
1577 /* Layered rendering doesn't work with LINEAR_GENERAL.
1578 * (LINEAR_ALIGNED and others work) */
1579 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1580 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1581 offset += rtex->surface.level[level].slice_size *
1582 surf->base.u.tex.first_layer;
1583 color_view = 0;
1584 } else {
1585 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1586 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1587 }
1588
1589 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1590 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1591 if (slice) {
1592 slice = slice - 1;
1593 }
1594
1595 tile_mode_index = si_tile_mode_index(rtex, level, false);
1596
1597 desc = util_format_description(surf->base.format);
1598 for (i = 0; i < 4; i++) {
1599 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1600 break;
1601 }
1602 }
1603 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1604 ntype = V_028C70_NUMBER_FLOAT;
1605 } else {
1606 ntype = V_028C70_NUMBER_UNORM;
1607 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1608 ntype = V_028C70_NUMBER_SRGB;
1609 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1610 if (desc->channel[i].pure_integer) {
1611 ntype = V_028C70_NUMBER_SINT;
1612 } else {
1613 assert(desc->channel[i].normalized);
1614 ntype = V_028C70_NUMBER_SNORM;
1615 }
1616 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1617 if (desc->channel[i].pure_integer) {
1618 ntype = V_028C70_NUMBER_UINT;
1619 } else {
1620 assert(desc->channel[i].normalized);
1621 ntype = V_028C70_NUMBER_UNORM;
1622 }
1623 }
1624 }
1625
1626 format = si_translate_colorformat(surf->base.format);
1627 if (format == V_028C70_COLOR_INVALID) {
1628 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1629 }
1630 assert(format != V_028C70_COLOR_INVALID);
1631 swap = r600_translate_colorswap(surf->base.format);
1632 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1633 endian = V_028C70_ENDIAN_NONE;
1634 } else {
1635 endian = si_colorformat_endian_swap(format);
1636 }
1637
1638 /* blend clamp should be set for all NORM/SRGB types */
1639 if (ntype == V_028C70_NUMBER_UNORM ||
1640 ntype == V_028C70_NUMBER_SNORM ||
1641 ntype == V_028C70_NUMBER_SRGB)
1642 blend_clamp = 1;
1643
1644 /* set blend bypass according to docs if SINT/UINT or
1645 8/24 COLOR variants */
1646 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1647 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1648 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1649 blend_clamp = 0;
1650 blend_bypass = 1;
1651 }
1652
1653 color_info = S_028C70_FORMAT(format) |
1654 S_028C70_COMP_SWAP(swap) |
1655 S_028C70_BLEND_CLAMP(blend_clamp) |
1656 S_028C70_BLEND_BYPASS(blend_bypass) |
1657 S_028C70_NUMBER_TYPE(ntype) |
1658 S_028C70_ENDIAN(endian);
1659
1660 color_pitch = S_028C64_TILE_MAX(pitch);
1661
1662 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1663 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1664
1665 if (rtex->resource.b.b.nr_samples > 1) {
1666 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1667
1668 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1669 S_028C74_NUM_FRAGMENTS(log_samples);
1670
1671 if (rtex->fmask.size) {
1672 color_info |= S_028C70_COMPRESSION(1);
1673 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1674
1675 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1676
1677 if (sctx->b.chip_class == SI) {
1678 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1679 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1680 }
1681 if (sctx->b.chip_class >= CIK) {
1682 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1683 }
1684 }
1685 }
1686
1687 offset += rtex->resource.gpu_address;
1688
1689 surf->cb_color_base = offset >> 8;
1690 surf->cb_color_pitch = color_pitch;
1691 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1692 surf->cb_color_view = color_view;
1693 surf->cb_color_info = color_info;
1694 surf->cb_color_attrib = color_attrib;
1695
1696 if (rtex->fmask.size) {
1697 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1698 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1699 } else {
1700 /* This must be set for fast clear to work without FMASK. */
1701 surf->cb_color_fmask = surf->cb_color_base;
1702 surf->cb_color_fmask_slice = surf->cb_color_slice;
1703 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1704
1705 if (sctx->b.chip_class == SI) {
1706 unsigned bankh = util_logbase2(rtex->surface.bankh);
1707 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1708 }
1709
1710 if (sctx->b.chip_class >= CIK) {
1711 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1712 }
1713 }
1714
1715 /* Determine pixel shader export format */
1716 max_comp_size = si_colorformat_max_comp_size(format);
1717 if (ntype == V_028C70_NUMBER_SRGB ||
1718 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1719 max_comp_size <= 10) ||
1720 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1721 surf->export_16bpc = true;
1722 }
1723
1724 surf->color_initialized = true;
1725 }
1726
1727 static void si_init_depth_surface(struct si_context *sctx,
1728 struct r600_surface *surf)
1729 {
1730 struct si_screen *sscreen = sctx->screen;
1731 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1732 unsigned level = surf->base.u.tex.level;
1733 struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
1734 unsigned format, tile_mode_index, array_mode;
1735 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1736 uint32_t z_info, s_info, db_depth_info;
1737 uint64_t z_offs, s_offs;
1738 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1739
1740 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1741 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1742 case PIPE_FORMAT_X8Z24_UNORM:
1743 case PIPE_FORMAT_Z24X8_UNORM:
1744 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1745 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1746 break;
1747 case PIPE_FORMAT_Z32_FLOAT:
1748 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1749 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1750 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1751 break;
1752 case PIPE_FORMAT_Z16_UNORM:
1753 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1754 break;
1755 default:
1756 assert(0);
1757 }
1758
1759 format = si_translate_dbformat(rtex->resource.b.b.format);
1760
1761 if (format == V_028040_Z_INVALID) {
1762 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1763 }
1764 assert(format != V_028040_Z_INVALID);
1765
1766 s_offs = z_offs = rtex->resource.gpu_address;
1767 z_offs += rtex->surface.level[level].offset;
1768 s_offs += rtex->surface.stencil_level[level].offset;
1769
1770 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1771
1772 z_info = S_028040_FORMAT(format);
1773 if (rtex->resource.b.b.nr_samples > 1) {
1774 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1775 }
1776
1777 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1778 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1779 else
1780 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1781
1782 if (sctx->b.chip_class >= CIK) {
1783 switch (rtex->surface.level[level].mode) {
1784 case RADEON_SURF_MODE_2D:
1785 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1786 break;
1787 case RADEON_SURF_MODE_1D:
1788 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1789 case RADEON_SURF_MODE_LINEAR:
1790 default:
1791 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1792 break;
1793 }
1794 tile_split = rtex->surface.tile_split;
1795 stile_split = rtex->surface.stencil_tile_split;
1796 macro_aspect = rtex->surface.mtilea;
1797 bankw = rtex->surface.bankw;
1798 bankh = rtex->surface.bankh;
1799 tile_split = cik_tile_split(tile_split);
1800 stile_split = cik_tile_split(stile_split);
1801 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1802 bankw = cik_bank_wh(bankw);
1803 bankh = cik_bank_wh(bankh);
1804 nbanks = si_num_banks(sscreen, rtex);
1805 tile_mode_index = si_tile_mode_index(rtex, level, false);
1806 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1807
1808 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1809 S_02803C_PIPE_CONFIG(pipe_config) |
1810 S_02803C_BANK_WIDTH(bankw) |
1811 S_02803C_BANK_HEIGHT(bankh) |
1812 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1813 S_02803C_NUM_BANKS(nbanks);
1814 z_info |= S_028040_TILE_SPLIT(tile_split);
1815 s_info |= S_028044_TILE_SPLIT(stile_split);
1816 } else {
1817 tile_mode_index = si_tile_mode_index(rtex, level, false);
1818 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1819 tile_mode_index = si_tile_mode_index(rtex, level, true);
1820 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1821 }
1822
1823 /* HiZ aka depth buffer htile */
1824 /* use htile only for first level */
1825 if (rtex->htile_buffer && !level) {
1826 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1827 S_028040_ALLOW_EXPCLEAR(1);
1828
1829 /* This is optimal for the clear value of 1.0 and using
1830 * the LESS and LEQUAL test functions. Set this to 0
1831 * for the opposite case. This can only be changed when
1832 * clearing. */
1833 z_info |= S_028040_ZRANGE_PRECISION(1);
1834
1835 /* Use all of the htile_buffer for depth, because we don't
1836 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1837 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1838
1839 uint64_t va = rtex->htile_buffer->gpu_address;
1840 db_htile_data_base = va >> 8;
1841 db_htile_surface = S_028ABC_FULL_CACHE(1);
1842 } else {
1843 db_htile_data_base = 0;
1844 db_htile_surface = 0;
1845 }
1846
1847 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1848
1849 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1850 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1851 surf->db_htile_data_base = db_htile_data_base;
1852 surf->db_depth_info = db_depth_info;
1853 surf->db_z_info = z_info;
1854 surf->db_stencil_info = s_info;
1855 surf->db_depth_base = z_offs >> 8;
1856 surf->db_stencil_base = s_offs >> 8;
1857 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1858 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1859 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1860 levelinfo->nblk_y) / 64 - 1);
1861 surf->db_htile_surface = db_htile_surface;
1862 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1863
1864 surf->depth_initialized = true;
1865 }
1866
1867 static void si_set_framebuffer_state(struct pipe_context *ctx,
1868 const struct pipe_framebuffer_state *state)
1869 {
1870 struct si_context *sctx = (struct si_context *)ctx;
1871 struct pipe_constant_buffer constbuf = {0};
1872 struct r600_surface *surf = NULL;
1873 struct r600_texture *rtex;
1874 int i;
1875
1876 if (sctx->framebuffer.state.nr_cbufs) {
1877 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1878 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1879 }
1880 if (sctx->framebuffer.state.zsbuf) {
1881 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
1882 R600_CONTEXT_FLUSH_AND_INV_DB_META;
1883 }
1884
1885 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
1886
1887 sctx->framebuffer.export_16bpc = 0;
1888 sctx->framebuffer.compressed_cb_mask = 0;
1889 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1890 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
1891 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1892 util_format_is_pure_integer(state->cbufs[0]->format);
1893
1894 for (i = 0; i < state->nr_cbufs; i++) {
1895 if (!state->cbufs[i])
1896 continue;
1897
1898 surf = (struct r600_surface*)state->cbufs[i];
1899 rtex = (struct r600_texture*)surf->base.texture;
1900
1901 if (!surf->color_initialized) {
1902 si_initialize_color_surface(sctx, surf);
1903 }
1904
1905 if (surf->export_16bpc) {
1906 sctx->framebuffer.export_16bpc |= 1 << i;
1907 }
1908
1909 if (rtex->fmask.size && rtex->cmask.size) {
1910 sctx->framebuffer.compressed_cb_mask |= 1 << i;
1911 }
1912 }
1913 /* Set the 16BPC export for possible dual-src blending. */
1914 if (i == 1 && surf && surf->export_16bpc) {
1915 sctx->framebuffer.export_16bpc |= 1 << 1;
1916 }
1917
1918 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
1919
1920 if (state->zsbuf) {
1921 surf = (struct r600_surface*)state->zsbuf;
1922
1923 if (!surf->depth_initialized) {
1924 si_init_depth_surface(sctx, surf);
1925 }
1926 }
1927
1928 si_update_fb_rs_state(sctx);
1929 si_update_fb_blend_state(sctx);
1930
1931 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
1932 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
1933 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
1934 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
1935 sctx->framebuffer.atom.dirty = true;
1936 sctx->msaa_config.dirty = true;
1937
1938 /* Set sample locations as fragment shader constants. */
1939 switch (sctx->framebuffer.nr_samples) {
1940 case 1:
1941 constbuf.user_buffer = sctx->b.sample_locations_1x;
1942 break;
1943 case 2:
1944 constbuf.user_buffer = sctx->b.sample_locations_2x;
1945 break;
1946 case 4:
1947 constbuf.user_buffer = sctx->b.sample_locations_4x;
1948 break;
1949 case 8:
1950 constbuf.user_buffer = sctx->b.sample_locations_8x;
1951 break;
1952 case 16:
1953 constbuf.user_buffer = sctx->b.sample_locations_16x;
1954 break;
1955 default:
1956 assert(0);
1957 }
1958 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
1959 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
1960 SI_DRIVER_STATE_CONST_BUF, &constbuf);
1961 }
1962
1963 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
1964 {
1965 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
1966 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
1967 unsigned i, nr_cbufs = state->nr_cbufs;
1968 struct r600_texture *tex = NULL;
1969 struct r600_surface *cb = NULL;
1970
1971 /* Colorbuffers. */
1972 for (i = 0; i < nr_cbufs; i++) {
1973 cb = (struct r600_surface*)state->cbufs[i];
1974 if (!cb) {
1975 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1976 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1977 continue;
1978 }
1979
1980 tex = (struct r600_texture *)cb->base.texture;
1981 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1982 &tex->resource, RADEON_USAGE_READWRITE,
1983 tex->surface.nsamples > 1 ?
1984 RADEON_PRIO_COLOR_BUFFER_MSAA :
1985 RADEON_PRIO_COLOR_BUFFER);
1986
1987 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1988 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1989 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1990 RADEON_PRIO_COLOR_META);
1991 }
1992
1993 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1994 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1995 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1996 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1997 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1998 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1999 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2000 radeon_emit(cs, 0); /* R_028C78 unused */
2001 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2002 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2003 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2004 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2005 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2006 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2007 }
2008 /* set CB_COLOR1_INFO for possible dual-src blending */
2009 if (i == 1 && state->cbufs[0]) {
2010 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2011 cb->cb_color_info | tex->cb_color_info);
2012 i++;
2013 }
2014 for (; i < 8 ; i++) {
2015 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2016 }
2017
2018 /* ZS buffer. */
2019 if (state->zsbuf) {
2020 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2021 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2022
2023 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2024 &rtex->resource, RADEON_USAGE_READWRITE,
2025 zb->base.texture->nr_samples > 1 ?
2026 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2027 RADEON_PRIO_DEPTH_BUFFER);
2028
2029 if (zb->db_htile_data_base) {
2030 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2031 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2032 RADEON_PRIO_DEPTH_META);
2033 }
2034
2035 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2036 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2037
2038 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2039 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2040 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
2041 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2042 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2043 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2044 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2045 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2046 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2047 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2048
2049 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2050 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2051 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2052 zb->pa_su_poly_offset_db_fmt_cntl);
2053 } else {
2054 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2055 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2056 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2057 }
2058
2059 /* Framebuffer dimensions. */
2060 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2061 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2062 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2063
2064 cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples);
2065 }
2066
2067 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2068 {
2069 struct si_context *sctx = (struct si_context *)rctx;
2070 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2071
2072 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2073 sctx->ps_iter_samples);
2074 }
2075
2076 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2077
2078 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2079 {
2080 struct si_context *sctx = (struct si_context *)ctx;
2081
2082 if (sctx->ps_iter_samples == min_samples)
2083 return;
2084
2085 sctx->ps_iter_samples = min_samples;
2086
2087 if (sctx->framebuffer.nr_samples > 1)
2088 sctx->msaa_config.dirty = true;
2089 }
2090
2091 /*
2092 * shaders
2093 */
2094
2095 /* Compute the key for the hw shader variant */
2096 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2097 struct si_pipe_shader_selector *sel,
2098 union si_shader_key *key)
2099 {
2100 struct si_context *sctx = (struct si_context *)ctx;
2101 memset(key, 0, sizeof(*key));
2102
2103 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
2104 sctx->queued.named.rasterizer) {
2105 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2106 key->vs.ucps_enabled |= 0x2;
2107 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2108 key->vs.ucps_enabled |= 0x1;
2109 }
2110
2111 if (sel->type == PIPE_SHADER_VERTEX) {
2112 unsigned i;
2113 if (!sctx->vertex_elements)
2114 return;
2115
2116 for (i = 0; i < sctx->vertex_elements->count; ++i)
2117 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2118
2119 key->vs.as_es = sctx->gs_shader != NULL;
2120 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2121 if (sel->fs_write_all)
2122 key->ps.nr_cbufs = sctx->framebuffer.state.nr_cbufs;
2123 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
2124
2125 if (sctx->queued.named.rasterizer) {
2126 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2127 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2128 key->ps.interp_at_sample = sctx->framebuffer.nr_samples > 1 &&
2129 sctx->ps_iter_samples == sctx->framebuffer.nr_samples;
2130
2131 if (sctx->queued.named.blend) {
2132 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2133 sctx->queued.named.rasterizer->multisample_enable &&
2134 !sctx->framebuffer.cb0_is_integer;
2135 }
2136 }
2137 if (sctx->queued.named.dsa) {
2138 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2139
2140 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2141 if (sctx->framebuffer.cb0_is_integer)
2142 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2143 } else {
2144 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2145 }
2146 }
2147 }
2148
2149 /* Select the hw shader variant depending on the current state. */
2150 int si_shader_select(struct pipe_context *ctx,
2151 struct si_pipe_shader_selector *sel)
2152 {
2153 union si_shader_key key;
2154 struct si_pipe_shader * shader = NULL;
2155 int r;
2156
2157 si_shader_selector_key(ctx, sel, &key);
2158
2159 /* Check if we don't need to change anything.
2160 * This path is also used for most shaders that don't need multiple
2161 * variants, it will cost just a computation of the key and this
2162 * test. */
2163 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2164 return 0;
2165 }
2166
2167 /* lookup if we have other variants in the list */
2168 if (sel->num_shaders > 1) {
2169 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2170
2171 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2172 p = c;
2173 c = c->next_variant;
2174 }
2175
2176 if (c) {
2177 p->next_variant = c->next_variant;
2178 shader = c;
2179 }
2180 }
2181
2182 if (shader) {
2183 shader->next_variant = sel->current;
2184 sel->current = shader;
2185 } else {
2186 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2187 shader->selector = sel;
2188 shader->key = key;
2189
2190 shader->next_variant = sel->current;
2191 sel->current = shader;
2192 r = si_pipe_shader_create(ctx, shader);
2193 if (unlikely(r)) {
2194 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2195 sel->type, r);
2196 sel->current = NULL;
2197 FREE(shader);
2198 return r;
2199 }
2200 sel->num_shaders++;
2201 }
2202
2203 return 0;
2204 }
2205
2206 static void *si_create_shader_state(struct pipe_context *ctx,
2207 const struct pipe_shader_state *state,
2208 unsigned pipe_shader_type)
2209 {
2210 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2211 int r;
2212
2213 sel->type = pipe_shader_type;
2214 sel->tokens = tgsi_dup_tokens(state->tokens);
2215 sel->so = state->stream_output;
2216
2217 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2218 struct tgsi_shader_info info;
2219
2220 tgsi_scan_shader(state->tokens, &info);
2221 sel->fs_write_all = info.color0_writes_all_cbufs;
2222 }
2223
2224 r = si_shader_select(ctx, sel);
2225 if (r) {
2226 free(sel);
2227 return NULL;
2228 }
2229
2230 return sel;
2231 }
2232
2233 static void *si_create_fs_state(struct pipe_context *ctx,
2234 const struct pipe_shader_state *state)
2235 {
2236 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2237 }
2238
2239 static void *si_create_gs_state(struct pipe_context *ctx,
2240 const struct pipe_shader_state *state)
2241 {
2242 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
2243 }
2244
2245 static void *si_create_vs_state(struct pipe_context *ctx,
2246 const struct pipe_shader_state *state)
2247 {
2248 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2249 }
2250
2251 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2252 {
2253 struct si_context *sctx = (struct si_context *)ctx;
2254 struct si_pipe_shader_selector *sel = state;
2255
2256 if (sctx->vs_shader == sel)
2257 return;
2258
2259 if (!sel || !sel->current)
2260 return;
2261
2262 sctx->vs_shader = sel;
2263 }
2264
2265 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2266 {
2267 struct si_context *sctx = (struct si_context *)ctx;
2268 struct si_pipe_shader_selector *sel = state;
2269
2270 if (sctx->gs_shader == sel)
2271 return;
2272
2273 sctx->gs_shader = sel;
2274 }
2275
2276 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2277 {
2278 struct si_context *sctx = (struct si_context *)ctx;
2279 struct si_pipe_shader_selector *sel = state;
2280
2281 /* skip if supplied shader is one already in use */
2282 if (sctx->ps_shader == sel)
2283 return;
2284
2285 /* use dummy shader if supplied shader is corrupt */
2286 if (!sel || !sel->current)
2287 sel = sctx->dummy_pixel_shader;
2288
2289 sctx->ps_shader = sel;
2290 }
2291
2292 static void si_delete_shader_selector(struct pipe_context *ctx,
2293 struct si_pipe_shader_selector *sel)
2294 {
2295 struct si_context *sctx = (struct si_context *)ctx;
2296 struct si_pipe_shader *p = sel->current, *c;
2297
2298 while (p) {
2299 c = p->next_variant;
2300 if (sel->type == PIPE_SHADER_GEOMETRY)
2301 si_pm4_delete_state(sctx, gs, p->pm4);
2302 else if (sel->type == PIPE_SHADER_FRAGMENT)
2303 si_pm4_delete_state(sctx, ps, p->pm4);
2304 else if (p->key.vs.as_es)
2305 si_pm4_delete_state(sctx, es, p->pm4);
2306 else
2307 si_pm4_delete_state(sctx, vs, p->pm4);
2308 si_pipe_shader_destroy(ctx, p);
2309 free(p);
2310 p = c;
2311 }
2312
2313 free(sel->tokens);
2314 free(sel);
2315 }
2316
2317 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2318 {
2319 struct si_context *sctx = (struct si_context *)ctx;
2320 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2321
2322 if (sctx->vs_shader == sel) {
2323 sctx->vs_shader = NULL;
2324 }
2325
2326 si_delete_shader_selector(ctx, sel);
2327 }
2328
2329 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
2330 {
2331 struct si_context *sctx = (struct si_context *)ctx;
2332 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2333
2334 if (sctx->gs_shader == sel) {
2335 sctx->gs_shader = NULL;
2336 }
2337
2338 si_delete_shader_selector(ctx, sel);
2339 }
2340
2341 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2342 {
2343 struct si_context *sctx = (struct si_context *)ctx;
2344 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2345
2346 if (sctx->ps_shader == sel) {
2347 sctx->ps_shader = NULL;
2348 }
2349
2350 si_delete_shader_selector(ctx, sel);
2351 }
2352
2353 /*
2354 * Samplers
2355 */
2356
2357 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2358 struct pipe_resource *texture,
2359 const struct pipe_sampler_view *state)
2360 {
2361 struct si_context *sctx = (struct si_context*)ctx;
2362 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2363 struct r600_texture *tmp = (struct r600_texture*)texture;
2364 const struct util_format_description *desc;
2365 unsigned format, num_format;
2366 uint32_t pitch = 0;
2367 unsigned char state_swizzle[4], swizzle[4];
2368 unsigned height, depth, width;
2369 enum pipe_format pipe_format = state->format;
2370 struct radeon_surface_level *surflevel;
2371 int first_non_void;
2372 uint64_t va;
2373
2374 if (view == NULL)
2375 return NULL;
2376
2377 /* initialize base object */
2378 view->base = *state;
2379 view->base.texture = NULL;
2380 pipe_resource_reference(&view->base.texture, texture);
2381 view->base.reference.count = 1;
2382 view->base.context = ctx;
2383 view->resource = &tmp->resource;
2384
2385 /* Buffer resource. */
2386 if (texture->target == PIPE_BUFFER) {
2387 unsigned stride;
2388
2389 desc = util_format_description(state->format);
2390 first_non_void = util_format_get_first_non_void_channel(state->format);
2391 stride = desc->block.bits / 8;
2392 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2393 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2394 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2395
2396 view->state[0] = va;
2397 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2398 S_008F04_STRIDE(stride);
2399 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2400 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2401 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2402 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2403 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2404 S_008F0C_NUM_FORMAT(num_format) |
2405 S_008F0C_DATA_FORMAT(format);
2406
2407 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2408 return &view->base;
2409 }
2410
2411 state_swizzle[0] = state->swizzle_r;
2412 state_swizzle[1] = state->swizzle_g;
2413 state_swizzle[2] = state->swizzle_b;
2414 state_swizzle[3] = state->swizzle_a;
2415
2416 surflevel = tmp->surface.level;
2417
2418 /* Texturing with separate depth and stencil. */
2419 if (tmp->is_depth && !tmp->is_flushing_texture) {
2420 switch (pipe_format) {
2421 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2422 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2423 break;
2424 case PIPE_FORMAT_X8Z24_UNORM:
2425 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2426 /* Z24 is always stored like this. */
2427 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2428 break;
2429 case PIPE_FORMAT_X24S8_UINT:
2430 case PIPE_FORMAT_S8X24_UINT:
2431 case PIPE_FORMAT_X32_S8X24_UINT:
2432 pipe_format = PIPE_FORMAT_S8_UINT;
2433 surflevel = tmp->surface.stencil_level;
2434 break;
2435 default:;
2436 }
2437 }
2438
2439 desc = util_format_description(pipe_format);
2440
2441 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2442 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2443 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2444
2445 switch (pipe_format) {
2446 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2447 case PIPE_FORMAT_X24S8_UINT:
2448 case PIPE_FORMAT_X32_S8X24_UINT:
2449 case PIPE_FORMAT_X8Z24_UNORM:
2450 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2451 break;
2452 default:
2453 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2454 }
2455 } else {
2456 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2457 }
2458
2459 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2460
2461 switch (pipe_format) {
2462 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2463 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2464 break;
2465 default:
2466 if (first_non_void < 0) {
2467 if (util_format_is_compressed(pipe_format)) {
2468 switch (pipe_format) {
2469 case PIPE_FORMAT_DXT1_SRGB:
2470 case PIPE_FORMAT_DXT1_SRGBA:
2471 case PIPE_FORMAT_DXT3_SRGBA:
2472 case PIPE_FORMAT_DXT5_SRGBA:
2473 case PIPE_FORMAT_BPTC_SRGBA:
2474 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2475 break;
2476 case PIPE_FORMAT_RGTC1_SNORM:
2477 case PIPE_FORMAT_LATC1_SNORM:
2478 case PIPE_FORMAT_RGTC2_SNORM:
2479 case PIPE_FORMAT_LATC2_SNORM:
2480 /* implies float, so use SNORM/UNORM to determine
2481 whether data is signed or not */
2482 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2483 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2484 break;
2485 default:
2486 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2487 break;
2488 }
2489 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2490 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2491 } else {
2492 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2493 }
2494 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2495 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2496 } else {
2497 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2498
2499 switch (desc->channel[first_non_void].type) {
2500 case UTIL_FORMAT_TYPE_FLOAT:
2501 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2502 break;
2503 case UTIL_FORMAT_TYPE_SIGNED:
2504 if (desc->channel[first_non_void].normalized)
2505 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2506 else if (desc->channel[first_non_void].pure_integer)
2507 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2508 else
2509 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2510 break;
2511 case UTIL_FORMAT_TYPE_UNSIGNED:
2512 if (desc->channel[first_non_void].normalized)
2513 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2514 else if (desc->channel[first_non_void].pure_integer)
2515 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2516 else
2517 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2518 }
2519 }
2520 }
2521
2522 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2523 if (format == ~0) {
2524 format = 0;
2525 }
2526
2527 /* not supported any more */
2528 //endian = si_colorformat_endian_swap(format);
2529
2530 width = surflevel[0].npix_x;
2531 height = surflevel[0].npix_y;
2532 depth = surflevel[0].npix_z;
2533 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2534
2535 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2536 height = 1;
2537 depth = texture->array_size;
2538 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2539 depth = texture->array_size;
2540 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2541 depth = texture->array_size / 6;
2542
2543 va = tmp->resource.gpu_address + surflevel[0].offset;
2544 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2545
2546 view->state[0] = va >> 8;
2547 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2548 S_008F14_DATA_FORMAT(format) |
2549 S_008F14_NUM_FORMAT(num_format));
2550 view->state[2] = (S_008F18_WIDTH(width - 1) |
2551 S_008F18_HEIGHT(height - 1));
2552 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2553 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2554 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2555 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2556 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2557 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2558 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2559 util_logbase2(texture->nr_samples) :
2560 state->u.tex.last_level - tmp->mipmap_shift) |
2561 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2562 S_008F1C_POW2_PAD(texture->last_level > 0) |
2563 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2564 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2565 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2566 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2567 view->state[6] = 0;
2568 view->state[7] = 0;
2569
2570 /* Initialize the sampler view for FMASK. */
2571 if (tmp->fmask.size) {
2572 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2573 uint32_t fmask_format;
2574
2575 switch (texture->nr_samples) {
2576 case 2:
2577 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2578 break;
2579 case 4:
2580 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2581 break;
2582 case 8:
2583 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2584 break;
2585 default:
2586 assert(0);
2587 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2588 }
2589
2590 view->fmask_state[0] = va >> 8;
2591 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2592 S_008F14_DATA_FORMAT(fmask_format) |
2593 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2594 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2595 S_008F18_HEIGHT(height - 1);
2596 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2597 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2598 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2599 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2600 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2601 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2602 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2603 S_008F20_PITCH(tmp->fmask.pitch - 1);
2604 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2605 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2606 view->fmask_state[6] = 0;
2607 view->fmask_state[7] = 0;
2608 }
2609
2610 return &view->base;
2611 }
2612
2613 static void si_sampler_view_destroy(struct pipe_context *ctx,
2614 struct pipe_sampler_view *state)
2615 {
2616 struct si_pipe_sampler_view *view = (struct si_pipe_sampler_view *)state;
2617
2618 if (view->resource->b.b.target == PIPE_BUFFER)
2619 LIST_DELINIT(&view->list);
2620
2621 pipe_resource_reference(&state->texture, NULL);
2622 FREE(view);
2623 }
2624
2625 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2626 {
2627 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2628 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2629 (linear_filter &&
2630 (wrap == PIPE_TEX_WRAP_CLAMP ||
2631 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2632 }
2633
2634 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2635 {
2636 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2637 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2638
2639 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2640 state->border_color.ui[2] || state->border_color.ui[3]) &&
2641 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2642 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2643 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2644 }
2645
2646 static void *si_create_sampler_state(struct pipe_context *ctx,
2647 const struct pipe_sampler_state *state)
2648 {
2649 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2650 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2651 unsigned border_color_type;
2652
2653 if (rstate == NULL) {
2654 return NULL;
2655 }
2656
2657 if (sampler_state_needs_border_color(state))
2658 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2659 else
2660 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2661
2662 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2663 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2664 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2665 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2666 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2667 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2668 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2669 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2670 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2671 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2672 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2673 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2674 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2675 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2676
2677 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2678 memcpy(rstate->border_color, state->border_color.ui,
2679 sizeof(rstate->border_color));
2680 }
2681
2682 return rstate;
2683 }
2684
2685 /* Upload border colors and update the pointers in resource descriptors.
2686 * There can only be 4096 border colors per context.
2687 *
2688 * XXX: This is broken if the buffer gets reallocated.
2689 */
2690 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2691 void **states)
2692 {
2693 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2694 uint32_t *border_color_table = NULL;
2695 int i, j;
2696
2697 for (i = 0; i < count; i++) {
2698 if (rstates[i] &&
2699 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2700 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2701 if (!sctx->border_color_table ||
2702 ((sctx->border_color_offset + count - i) &
2703 C_008F3C_BORDER_COLOR_PTR)) {
2704 r600_resource_reference(&sctx->border_color_table, NULL);
2705 sctx->border_color_offset = 0;
2706
2707 sctx->border_color_table =
2708 si_resource_create_custom(&sctx->screen->b.b,
2709 PIPE_USAGE_DYNAMIC,
2710 4096 * 4 * 4);
2711 }
2712
2713 if (!border_color_table) {
2714 border_color_table =
2715 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2716 sctx->b.rings.gfx.cs,
2717 PIPE_TRANSFER_WRITE |
2718 PIPE_TRANSFER_UNSYNCHRONIZED);
2719 }
2720
2721 for (j = 0; j < 4; j++) {
2722 border_color_table[4 * sctx->border_color_offset + j] =
2723 util_le32_to_cpu(rstates[i]->border_color[j]);
2724 }
2725
2726 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2727 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2728 }
2729 }
2730
2731 if (border_color_table) {
2732 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2733
2734 uint64_t va_offset = sctx->border_color_table->gpu_address;
2735
2736 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2737 if (sctx->b.chip_class >= CIK)
2738 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2739 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2740 RADEON_PRIO_SHADER_DATA);
2741 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2742 }
2743 }
2744
2745 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2746 unsigned start, unsigned count,
2747 void **states)
2748 {
2749 struct si_context *sctx = (struct si_context *)ctx;
2750
2751 if (!count || shader >= SI_NUM_SHADERS)
2752 return;
2753
2754 si_set_border_colors(sctx, count, states);
2755 si_set_sampler_descriptors(sctx, shader, start, count, states);
2756 }
2757
2758 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2759 {
2760 struct si_context *sctx = (struct si_context *)ctx;
2761 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2762 struct si_pm4_state *pm4 = &state->pm4;
2763 uint16_t mask = sample_mask;
2764
2765 if (state == NULL)
2766 return;
2767
2768 state->sample_mask = mask;
2769 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2770 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2771
2772 si_pm4_set_state(sctx, sample_mask, state);
2773 }
2774
2775 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2776 {
2777 free(state);
2778 }
2779
2780 /*
2781 * Vertex elements & buffers
2782 */
2783
2784 static void *si_create_vertex_elements(struct pipe_context *ctx,
2785 unsigned count,
2786 const struct pipe_vertex_element *elements)
2787 {
2788 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2789 int i;
2790
2791 assert(count < PIPE_MAX_ATTRIBS);
2792 if (!v)
2793 return NULL;
2794
2795 v->count = count;
2796 for (i = 0; i < count; ++i) {
2797 const struct util_format_description *desc;
2798 unsigned data_format, num_format;
2799 int first_non_void;
2800
2801 desc = util_format_description(elements[i].src_format);
2802 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2803 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2804 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2805
2806 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2807 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2808 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2809 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2810 S_008F0C_NUM_FORMAT(num_format) |
2811 S_008F0C_DATA_FORMAT(data_format);
2812 v->format_size[i] = desc->block.bits / 8;
2813 }
2814 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2815
2816 return v;
2817 }
2818
2819 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2820 {
2821 struct si_context *sctx = (struct si_context *)ctx;
2822 struct si_vertex_element *v = (struct si_vertex_element*)state;
2823
2824 sctx->vertex_elements = v;
2825 sctx->vertex_buffers_dirty = true;
2826 }
2827
2828 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2829 {
2830 struct si_context *sctx = (struct si_context *)ctx;
2831
2832 if (sctx->vertex_elements == state)
2833 sctx->vertex_elements = NULL;
2834 FREE(state);
2835 }
2836
2837 static void si_set_vertex_buffers(struct pipe_context *ctx,
2838 unsigned start_slot, unsigned count,
2839 const struct pipe_vertex_buffer *buffers)
2840 {
2841 struct si_context *sctx = (struct si_context *)ctx;
2842 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2843 int i;
2844
2845 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2846
2847 if (buffers) {
2848 for (i = 0; i < count; i++) {
2849 const struct pipe_vertex_buffer *src = buffers + i;
2850 struct pipe_vertex_buffer *dsti = dst + i;
2851
2852 pipe_resource_reference(&dsti->buffer, src->buffer);
2853 dsti->buffer_offset = src->buffer_offset;
2854 dsti->stride = src->stride;
2855 }
2856 } else {
2857 for (i = 0; i < count; i++) {
2858 pipe_resource_reference(&dst[i].buffer, NULL);
2859 }
2860 }
2861 sctx->vertex_buffers_dirty = true;
2862 }
2863
2864 static void si_set_index_buffer(struct pipe_context *ctx,
2865 const struct pipe_index_buffer *ib)
2866 {
2867 struct si_context *sctx = (struct si_context *)ctx;
2868
2869 if (ib) {
2870 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2871 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2872 } else {
2873 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2874 }
2875 }
2876
2877 /*
2878 * Misc
2879 */
2880 static void si_set_polygon_stipple(struct pipe_context *ctx,
2881 const struct pipe_poly_stipple *state)
2882 {
2883 }
2884
2885 static void si_texture_barrier(struct pipe_context *ctx)
2886 {
2887 struct si_context *sctx = (struct si_context *)ctx;
2888
2889 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2890 R600_CONTEXT_FLUSH_AND_INV_CB;
2891 }
2892
2893 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2894 {
2895 struct pipe_blend_state blend;
2896
2897 memset(&blend, 0, sizeof(blend));
2898 blend.independent_blend_enable = true;
2899 blend.rt[0].colormask = 0xf;
2900 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2901 }
2902
2903 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2904 {
2905 /* XXX Turn this into a proper state. Right now the queries are
2906 * enabled in draw_vbo, which snoops r600_common_context to see
2907 * if any occlusion queries are active. */
2908 }
2909
2910 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2911 bool include_draw_vbo)
2912 {
2913 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2914 }
2915
2916 void si_init_state_functions(struct si_context *sctx)
2917 {
2918 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2919
2920 sctx->b.b.create_blend_state = si_create_blend_state;
2921 sctx->b.b.bind_blend_state = si_bind_blend_state;
2922 sctx->b.b.delete_blend_state = si_delete_blend_state;
2923 sctx->b.b.set_blend_color = si_set_blend_color;
2924
2925 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2926 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2927 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2928
2929 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2930 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2931 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2932
2933 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
2934 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2935 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2936 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2937
2938 sctx->b.b.set_clip_state = si_set_clip_state;
2939 sctx->b.b.set_scissor_states = si_set_scissor_states;
2940 sctx->b.b.set_viewport_states = si_set_viewport_states;
2941 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2942
2943 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2944 sctx->b.b.get_sample_position = cayman_get_sample_position;
2945
2946 sctx->b.b.create_vs_state = si_create_vs_state;
2947 sctx->b.b.create_fs_state = si_create_fs_state;
2948 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2949 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2950 sctx->b.b.delete_vs_state = si_delete_vs_shader;
2951 sctx->b.b.delete_fs_state = si_delete_ps_shader;
2952
2953 sctx->b.b.create_gs_state = si_create_gs_state;
2954 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2955 sctx->b.b.delete_gs_state = si_delete_gs_shader;
2956
2957 sctx->b.b.create_sampler_state = si_create_sampler_state;
2958 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2959 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2960
2961 sctx->b.b.create_sampler_view = si_create_sampler_view;
2962 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2963
2964 sctx->b.b.set_sample_mask = si_set_sample_mask;
2965
2966 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2967 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
2968 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
2969 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
2970 sctx->b.b.set_index_buffer = si_set_index_buffer;
2971
2972 sctx->b.b.texture_barrier = si_texture_barrier;
2973 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
2974 sctx->b.b.set_min_samples = si_set_min_samples;
2975
2976 sctx->b.dma_copy = si_dma_copy;
2977 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
2978 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
2979
2980 sctx->b.b.draw_vbo = si_draw_vbo;
2981 }
2982
2983 void si_init_config(struct si_context *sctx)
2984 {
2985 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2986
2987 if (pm4 == NULL)
2988 return;
2989
2990 si_cmd_context_control(pm4);
2991
2992 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2993 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2994 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2995 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2996 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2997 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2998 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2999 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3000 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3001 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3002 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3003 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3004
3005 /* FIXME calculate these values somehow ??? */
3006 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3007 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3008 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3009
3010 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3011 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3012 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3013 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3014
3015 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3016 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3017 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3018 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3019
3020 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3021 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3022 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3023 if (sctx->b.chip_class < CIK)
3024 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3025 S_008A14_CLIP_VTX_REORDER_ENA(1));
3026
3027 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3028 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3029
3030 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3031
3032 if (sctx->b.chip_class >= CIK) {
3033 switch (sctx->screen->b.family) {
3034 case CHIP_BONAIRE:
3035 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3036 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3037 break;
3038 case CHIP_HAWAII:
3039 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3040 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3041 break;
3042 case CHIP_KAVERI:
3043 /* XXX todo */
3044 case CHIP_KABINI:
3045 /* XXX todo */
3046 case CHIP_MULLINS:
3047 /* XXX todo */
3048 default:
3049 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3050 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3051 break;
3052 }
3053 } else {
3054 switch (sctx->screen->b.family) {
3055 case CHIP_TAHITI:
3056 case CHIP_PITCAIRN:
3057 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3058 break;
3059 case CHIP_VERDE:
3060 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3061 break;
3062 case CHIP_OLAND:
3063 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3064 break;
3065 case CHIP_HAINAN:
3066 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3067 break;
3068 default:
3069 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3070 break;
3071 }
3072 }
3073
3074 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3075 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3076 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3077 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3078 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3079 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3080 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3081
3082 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3083 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3084 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3085 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3086 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3087 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3088 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3089 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3090 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3091 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3092 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3093 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3094 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3095 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3096 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3097 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3098
3099 /* There is a hang if stencil is used and fast stencil is enabled
3100 * regardless of whether HTILE is depth-only or not.
3101 */
3102 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3103 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3104 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3105 S_02800C_FAST_STENCIL_DISABLE(1));
3106
3107 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3108 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3109 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3110
3111 if (sctx->b.chip_class >= CIK) {
3112 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3113 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3114 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3115 }
3116
3117 si_pm4_set_state(sctx, init, pm4);
3118 }