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radeonsi: use hardware scissors correctly
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "tgsi/tgsi_scan.h"
37 #include "si_pipe.h"
38 #include "si_shader.h"
39 #include "si_state.h"
40 #include "../radeon/r600_cs.h"
41 #include "sid.h"
42
43 static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split)
44 {
45 if (sscreen->b.info.cik_macrotile_mode_array_valid) {
46 unsigned index, tileb;
47
48 tileb = 8 * 8 * bpe;
49 tileb = MIN2(tile_split, tileb);
50
51 for (index = 0; tileb > 64; index++) {
52 tileb >>= 1;
53 }
54
55 assert(index < 16);
56
57 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
58 }
59
60 /* The old way. */
61 switch (sscreen->b.tiling_info.num_banks) {
62 case 2:
63 return V_02803C_ADDR_SURF_2_BANK;
64 case 4:
65 return V_02803C_ADDR_SURF_4_BANK;
66 case 8:
67 default:
68 return V_02803C_ADDR_SURF_8_BANK;
69 case 16:
70 return V_02803C_ADDR_SURF_16_BANK;
71 }
72 }
73
74 static unsigned cik_tile_split(unsigned tile_split)
75 {
76 switch (tile_split) {
77 case 64:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
79 break;
80 case 128:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
82 break;
83 case 256:
84 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
85 break;
86 case 512:
87 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
88 break;
89 default:
90 case 1024:
91 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
92 break;
93 case 2048:
94 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
95 break;
96 case 4096:
97 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
98 break;
99 }
100 return tile_split;
101 }
102
103 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
104 {
105 switch (macro_tile_aspect) {
106 default:
107 case 1:
108 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
109 break;
110 case 2:
111 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
112 break;
113 case 4:
114 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
115 break;
116 case 8:
117 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
118 break;
119 }
120 return macro_tile_aspect;
121 }
122
123 static unsigned cik_bank_wh(unsigned bankwh)
124 {
125 switch (bankwh) {
126 default:
127 case 1:
128 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
129 break;
130 case 2:
131 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
132 break;
133 case 4:
134 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
135 break;
136 case 8:
137 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
138 break;
139 }
140 return bankwh;
141 }
142
143 static unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
144 {
145 if (sscreen->b.info.si_tile_mode_array_valid) {
146 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
147
148 return G_009910_PIPE_CONFIG(gb_tile_mode);
149 }
150
151 /* This is probably broken for a lot of chips, but it's only used
152 * if the kernel cannot return the tile mode array for CIK. */
153 switch (sscreen->b.info.r600_num_tile_pipes) {
154 case 16:
155 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
156 case 8:
157 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
158 case 4:
159 default:
160 if (sscreen->b.info.r600_num_backends == 4)
161 return V_02803C_X_ADDR_SURF_P4_16X16;
162 else
163 return V_02803C_X_ADDR_SURF_P4_8X16;
164 case 2:
165 return V_02803C_ADDR_SURF_P2;
166 }
167 }
168
169 /*
170 * inferred framebuffer and blender state
171 */
172 static void si_update_fb_blend_state(struct si_context *sctx)
173 {
174 struct si_pm4_state *pm4;
175 struct si_state_blend *blend = sctx->queued.named.blend;
176 uint32_t mask;
177
178 if (blend == NULL)
179 return;
180
181 pm4 = si_pm4_alloc_state(sctx);
182 if (pm4 == NULL)
183 return;
184
185 mask = (1ULL << ((unsigned)sctx->framebuffer.nr_cbufs * 4)) - 1;
186 mask &= blend->cb_target_mask;
187 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
188
189 si_pm4_set_state(sctx, fb_blend, pm4);
190 }
191
192 /*
193 * Blender functions
194 */
195
196 static uint32_t si_translate_blend_function(int blend_func)
197 {
198 switch (blend_func) {
199 case PIPE_BLEND_ADD:
200 return V_028780_COMB_DST_PLUS_SRC;
201 case PIPE_BLEND_SUBTRACT:
202 return V_028780_COMB_SRC_MINUS_DST;
203 case PIPE_BLEND_REVERSE_SUBTRACT:
204 return V_028780_COMB_DST_MINUS_SRC;
205 case PIPE_BLEND_MIN:
206 return V_028780_COMB_MIN_DST_SRC;
207 case PIPE_BLEND_MAX:
208 return V_028780_COMB_MAX_DST_SRC;
209 default:
210 R600_ERR("Unknown blend function %d\n", blend_func);
211 assert(0);
212 break;
213 }
214 return 0;
215 }
216
217 static uint32_t si_translate_blend_factor(int blend_fact)
218 {
219 switch (blend_fact) {
220 case PIPE_BLENDFACTOR_ONE:
221 return V_028780_BLEND_ONE;
222 case PIPE_BLENDFACTOR_SRC_COLOR:
223 return V_028780_BLEND_SRC_COLOR;
224 case PIPE_BLENDFACTOR_SRC_ALPHA:
225 return V_028780_BLEND_SRC_ALPHA;
226 case PIPE_BLENDFACTOR_DST_ALPHA:
227 return V_028780_BLEND_DST_ALPHA;
228 case PIPE_BLENDFACTOR_DST_COLOR:
229 return V_028780_BLEND_DST_COLOR;
230 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
231 return V_028780_BLEND_SRC_ALPHA_SATURATE;
232 case PIPE_BLENDFACTOR_CONST_COLOR:
233 return V_028780_BLEND_CONSTANT_COLOR;
234 case PIPE_BLENDFACTOR_CONST_ALPHA:
235 return V_028780_BLEND_CONSTANT_ALPHA;
236 case PIPE_BLENDFACTOR_ZERO:
237 return V_028780_BLEND_ZERO;
238 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
239 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
240 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
241 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
242 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
243 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
244 case PIPE_BLENDFACTOR_INV_DST_COLOR:
245 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
246 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
247 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
248 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
249 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
250 case PIPE_BLENDFACTOR_SRC1_COLOR:
251 return V_028780_BLEND_SRC1_COLOR;
252 case PIPE_BLENDFACTOR_SRC1_ALPHA:
253 return V_028780_BLEND_SRC1_ALPHA;
254 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
255 return V_028780_BLEND_INV_SRC1_COLOR;
256 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
257 return V_028780_BLEND_INV_SRC1_ALPHA;
258 default:
259 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
260 assert(0);
261 break;
262 }
263 return 0;
264 }
265
266 static void *si_create_blend_state_mode(struct pipe_context *ctx,
267 const struct pipe_blend_state *state,
268 unsigned mode)
269 {
270 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
271 struct si_pm4_state *pm4 = &blend->pm4;
272
273 uint32_t color_control = 0;
274
275 if (blend == NULL)
276 return NULL;
277
278 blend->alpha_to_one = state->alpha_to_one;
279
280 if (state->logicop_enable) {
281 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
282 } else {
283 color_control |= S_028808_ROP3(0xcc);
284 }
285
286 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
287 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
288 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
289 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
290 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
291 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
292
293 blend->cb_target_mask = 0;
294 for (int i = 0; i < 8; i++) {
295 /* state->rt entries > 0 only written if independent blending */
296 const int j = state->independent_blend_enable ? i : 0;
297
298 unsigned eqRGB = state->rt[j].rgb_func;
299 unsigned srcRGB = state->rt[j].rgb_src_factor;
300 unsigned dstRGB = state->rt[j].rgb_dst_factor;
301 unsigned eqA = state->rt[j].alpha_func;
302 unsigned srcA = state->rt[j].alpha_src_factor;
303 unsigned dstA = state->rt[j].alpha_dst_factor;
304
305 unsigned blend_cntl = 0;
306
307 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
308 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
309
310 if (!state->rt[j].blend_enable) {
311 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
312 continue;
313 }
314
315 blend_cntl |= S_028780_ENABLE(1);
316 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
317 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
318 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
319
320 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
321 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
322 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
323 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
324 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
325 }
326 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
327 }
328
329 if (blend->cb_target_mask) {
330 color_control |= S_028808_MODE(mode);
331 } else {
332 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
333 }
334 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
335
336 return blend;
337 }
338
339 static void *si_create_blend_state(struct pipe_context *ctx,
340 const struct pipe_blend_state *state)
341 {
342 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
343 }
344
345 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
346 {
347 struct si_context *sctx = (struct si_context *)ctx;
348 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
349 si_update_fb_blend_state(sctx);
350 }
351
352 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
353 {
354 struct si_context *sctx = (struct si_context *)ctx;
355 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
356 }
357
358 static void si_set_blend_color(struct pipe_context *ctx,
359 const struct pipe_blend_color *state)
360 {
361 struct si_context *sctx = (struct si_context *)ctx;
362 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
363
364 if (pm4 == NULL)
365 return;
366
367 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
368 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
369 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
370 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
371
372 si_pm4_set_state(sctx, blend_color, pm4);
373 }
374
375 /*
376 * Clipping, scissors and viewport
377 */
378
379 static void si_set_clip_state(struct pipe_context *ctx,
380 const struct pipe_clip_state *state)
381 {
382 struct si_context *sctx = (struct si_context *)ctx;
383 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
384 struct pipe_constant_buffer cb;
385
386 if (pm4 == NULL)
387 return;
388
389 for (int i = 0; i < 6; i++) {
390 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
391 fui(state->ucp[i][0]));
392 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
393 fui(state->ucp[i][1]));
394 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
395 fui(state->ucp[i][2]));
396 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
397 fui(state->ucp[i][3]));
398 }
399
400 cb.buffer = NULL;
401 cb.user_buffer = state->ucp;
402 cb.buffer_offset = 0;
403 cb.buffer_size = 4*4*8;
404 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
405 pipe_resource_reference(&cb.buffer, NULL);
406
407 si_pm4_set_state(sctx, clip, pm4);
408 }
409
410 static void si_set_scissor_states(struct pipe_context *ctx,
411 unsigned start_slot,
412 unsigned num_scissors,
413 const struct pipe_scissor_state *state)
414 {
415 struct si_context *sctx = (struct si_context *)ctx;
416 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
417
418 if (pm4 == NULL)
419 return;
420
421 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
422 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
423 S_028250_WINDOW_OFFSET_DISABLE(1));
424 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
425 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
426
427 si_pm4_set_state(sctx, scissor, pm4);
428 }
429
430 static void si_set_viewport_states(struct pipe_context *ctx,
431 unsigned start_slot,
432 unsigned num_viewports,
433 const struct pipe_viewport_state *state)
434 {
435 struct si_context *sctx = (struct si_context *)ctx;
436 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
437 struct si_pm4_state *pm4 = &viewport->pm4;
438
439 if (viewport == NULL)
440 return;
441
442 viewport->viewport = *state;
443 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
444 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
445 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
446 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
447 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
448 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
449
450 si_pm4_set_state(sctx, viewport, viewport);
451 }
452
453 /*
454 * inferred state between framebuffer and rasterizer
455 */
456 static void si_update_fb_rs_state(struct si_context *sctx)
457 {
458 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
459 struct si_pm4_state *pm4;
460 unsigned offset_db_fmt_cntl = 0, depth;
461 float offset_units;
462
463 if (!rs || !sctx->framebuffer.zsbuf)
464 return;
465
466 offset_units = sctx->queued.named.rasterizer->offset_units;
467 switch (sctx->framebuffer.zsbuf->texture->format) {
468 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
469 case PIPE_FORMAT_X8Z24_UNORM:
470 case PIPE_FORMAT_Z24X8_UNORM:
471 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
472 depth = -24;
473 offset_units *= 2.0f;
474 break;
475 case PIPE_FORMAT_Z32_FLOAT:
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 depth = -23;
478 offset_units *= 1.0f;
479 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
480 break;
481 case PIPE_FORMAT_Z16_UNORM:
482 depth = -16;
483 offset_units *= 4.0f;
484 break;
485 default:
486 return;
487 }
488
489 pm4 = si_pm4_alloc_state(sctx);
490
491 if (pm4 == NULL)
492 return;
493
494 /* FIXME some of those reg can be computed with cso */
495 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
496 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
497 fui(sctx->queued.named.rasterizer->offset_scale));
498 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
499 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
500 fui(sctx->queued.named.rasterizer->offset_scale));
501 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
502 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
503
504 si_pm4_set_state(sctx, fb_rs, pm4);
505 }
506
507 /*
508 * Rasterizer
509 */
510
511 static uint32_t si_translate_fill(uint32_t func)
512 {
513 switch(func) {
514 case PIPE_POLYGON_MODE_FILL:
515 return V_028814_X_DRAW_TRIANGLES;
516 case PIPE_POLYGON_MODE_LINE:
517 return V_028814_X_DRAW_LINES;
518 case PIPE_POLYGON_MODE_POINT:
519 return V_028814_X_DRAW_POINTS;
520 default:
521 assert(0);
522 return V_028814_X_DRAW_POINTS;
523 }
524 }
525
526 static void *si_create_rs_state(struct pipe_context *ctx,
527 const struct pipe_rasterizer_state *state)
528 {
529 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
530 struct si_pm4_state *pm4 = &rs->pm4;
531 unsigned tmp;
532 unsigned prov_vtx = 1, polygon_dual_mode;
533 float psize_min, psize_max;
534
535 if (rs == NULL) {
536 return NULL;
537 }
538
539 rs->two_side = state->light_twoside;
540 rs->multisample_enable = state->multisample;
541 rs->clip_plane_enable = state->clip_plane_enable;
542 rs->line_stipple_enable = state->line_stipple_enable;
543
544 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
545 state->fill_back != PIPE_POLYGON_MODE_FILL);
546
547 if (state->flatshade_first)
548 prov_vtx = 0;
549
550 rs->flatshade = state->flatshade;
551 rs->sprite_coord_enable = state->sprite_coord_enable;
552 rs->pa_sc_line_stipple = state->line_stipple_enable ?
553 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
554 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
555 rs->pa_su_sc_mode_cntl =
556 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
557 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
558 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
559 S_028814_FACE(!state->front_ccw) |
560 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
561 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
562 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
563 S_028814_POLY_MODE(polygon_dual_mode) |
564 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
565 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
566 rs->pa_cl_clip_cntl =
567 S_028810_PS_UCP_MODE(3) |
568 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
569 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
570 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
571 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
572
573 /* offset */
574 rs->offset_units = state->offset_units;
575 rs->offset_scale = state->offset_scale * 12.0f;
576
577 tmp = S_0286D4_FLAT_SHADE_ENA(1);
578 if (state->sprite_coord_enable) {
579 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
580 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
581 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
582 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
583 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
584 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
585 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
586 }
587 }
588 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
589
590 /* point size 12.4 fixed point */
591 tmp = (unsigned)(state->point_size * 8.0);
592 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
593
594 if (state->point_size_per_vertex) {
595 psize_min = util_get_min_point_size(state);
596 psize_max = 8192;
597 } else {
598 /* Force the point size to be as if the vertex output was disabled. */
599 psize_min = state->point_size;
600 psize_max = state->point_size;
601 }
602 /* Divide by two, because 0.5 = 1 pixel. */
603 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
604 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
605 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
606
607 tmp = (unsigned)state->line_width * 8;
608 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
609 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
610 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
611 S_028A48_MSAA_ENABLE(state->multisample) |
612 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
613
614 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
615 S_028BE4_PIX_CENTER(state->half_pixel_center) |
616 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
617
618 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
619
620 return rs;
621 }
622
623 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
624 {
625 struct si_context *sctx = (struct si_context *)ctx;
626 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
627
628 if (state == NULL)
629 return;
630
631 // TODO
632 sctx->sprite_coord_enable = rs->sprite_coord_enable;
633 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
634 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
635
636 si_pm4_bind_state(sctx, rasterizer, rs);
637 si_update_fb_rs_state(sctx);
638 }
639
640 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
641 {
642 struct si_context *sctx = (struct si_context *)ctx;
643 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
644 }
645
646 /*
647 * infeered state between dsa and stencil ref
648 */
649 static void si_update_dsa_stencil_ref(struct si_context *sctx)
650 {
651 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
652 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
653 struct si_state_dsa *dsa = sctx->queued.named.dsa;
654
655 if (pm4 == NULL)
656 return;
657
658 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
659 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
660 S_028430_STENCILMASK(dsa->valuemask[0]) |
661 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
662 S_028430_STENCILOPVAL(1));
663 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
664 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
665 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
666 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
667 S_028434_STENCILOPVAL_BF(1));
668
669 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
670 }
671
672 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
673 const struct pipe_stencil_ref *state)
674 {
675 struct si_context *sctx = (struct si_context *)ctx;
676 sctx->stencil_ref = *state;
677 si_update_dsa_stencil_ref(sctx);
678 }
679
680
681 /*
682 * DSA
683 */
684
685 static uint32_t si_translate_stencil_op(int s_op)
686 {
687 switch (s_op) {
688 case PIPE_STENCIL_OP_KEEP:
689 return V_02842C_STENCIL_KEEP;
690 case PIPE_STENCIL_OP_ZERO:
691 return V_02842C_STENCIL_ZERO;
692 case PIPE_STENCIL_OP_REPLACE:
693 return V_02842C_STENCIL_REPLACE_TEST;
694 case PIPE_STENCIL_OP_INCR:
695 return V_02842C_STENCIL_ADD_CLAMP;
696 case PIPE_STENCIL_OP_DECR:
697 return V_02842C_STENCIL_SUB_CLAMP;
698 case PIPE_STENCIL_OP_INCR_WRAP:
699 return V_02842C_STENCIL_ADD_WRAP;
700 case PIPE_STENCIL_OP_DECR_WRAP:
701 return V_02842C_STENCIL_SUB_WRAP;
702 case PIPE_STENCIL_OP_INVERT:
703 return V_02842C_STENCIL_INVERT;
704 default:
705 R600_ERR("Unknown stencil op %d", s_op);
706 assert(0);
707 break;
708 }
709 return 0;
710 }
711
712 static void *si_create_dsa_state(struct pipe_context *ctx,
713 const struct pipe_depth_stencil_alpha_state *state)
714 {
715 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
716 struct si_pm4_state *pm4 = &dsa->pm4;
717 unsigned db_depth_control;
718 unsigned db_render_control;
719 uint32_t db_stencil_control = 0;
720
721 if (dsa == NULL) {
722 return NULL;
723 }
724
725 dsa->valuemask[0] = state->stencil[0].valuemask;
726 dsa->valuemask[1] = state->stencil[1].valuemask;
727 dsa->writemask[0] = state->stencil[0].writemask;
728 dsa->writemask[1] = state->stencil[1].writemask;
729
730 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
731 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
732 S_028800_ZFUNC(state->depth.func);
733
734 /* stencil */
735 if (state->stencil[0].enabled) {
736 db_depth_control |= S_028800_STENCIL_ENABLE(1);
737 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
738 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
739 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
740 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
741
742 if (state->stencil[1].enabled) {
743 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
744 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
745 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
746 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
747 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
748 }
749 }
750
751 /* alpha */
752 if (state->alpha.enabled) {
753 dsa->alpha_func = state->alpha.func;
754 dsa->alpha_ref = state->alpha.ref_value;
755
756 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
757 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
758 } else {
759 dsa->alpha_func = PIPE_FUNC_ALWAYS;
760 }
761
762 /* misc */
763 db_render_control = 0;
764 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
765 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
766 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
767
768 return dsa;
769 }
770
771 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
772 {
773 struct si_context *sctx = (struct si_context *)ctx;
774 struct si_state_dsa *dsa = state;
775
776 if (state == NULL)
777 return;
778
779 si_pm4_bind_state(sctx, dsa, dsa);
780 si_update_dsa_stencil_ref(sctx);
781 }
782
783 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
784 {
785 struct si_context *sctx = (struct si_context *)ctx;
786 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
787 }
788
789 static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth,
790 bool copy_stencil, int sample)
791 {
792 struct pipe_depth_stencil_alpha_state dsa;
793 struct si_state_dsa *state;
794
795 memset(&dsa, 0, sizeof(dsa));
796
797 state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
798 if (copy_depth || copy_stencil) {
799 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
800 S_028000_DEPTH_COPY(copy_depth) |
801 S_028000_STENCIL_COPY(copy_stencil) |
802 S_028000_COPY_CENTROID(1) |
803 S_028000_COPY_SAMPLE(sample));
804 } else {
805 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
806 S_028000_DEPTH_COMPRESS_DISABLE(1) |
807 S_028000_STENCIL_COMPRESS_DISABLE(1));
808 }
809
810 return state;
811 }
812
813 /*
814 * format translation
815 */
816 static uint32_t si_translate_colorformat(enum pipe_format format)
817 {
818 const struct util_format_description *desc = util_format_description(format);
819
820 #define HAS_SIZE(x,y,z,w) \
821 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
822 desc->channel[2].size == (z) && desc->channel[3].size == (w))
823
824 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
825 return V_028C70_COLOR_10_11_11;
826
827 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
828 return V_028C70_COLOR_INVALID;
829
830 switch (desc->nr_channels) {
831 case 1:
832 switch (desc->channel[0].size) {
833 case 8:
834 return V_028C70_COLOR_8;
835 case 16:
836 return V_028C70_COLOR_16;
837 case 32:
838 return V_028C70_COLOR_32;
839 }
840 break;
841 case 2:
842 if (desc->channel[0].size == desc->channel[1].size) {
843 switch (desc->channel[0].size) {
844 case 8:
845 return V_028C70_COLOR_8_8;
846 case 16:
847 return V_028C70_COLOR_16_16;
848 case 32:
849 return V_028C70_COLOR_32_32;
850 }
851 } else if (HAS_SIZE(8,24,0,0)) {
852 return V_028C70_COLOR_24_8;
853 } else if (HAS_SIZE(24,8,0,0)) {
854 return V_028C70_COLOR_8_24;
855 }
856 break;
857 case 3:
858 if (HAS_SIZE(5,6,5,0)) {
859 return V_028C70_COLOR_5_6_5;
860 } else if (HAS_SIZE(32,8,24,0)) {
861 return V_028C70_COLOR_X24_8_32_FLOAT;
862 }
863 break;
864 case 4:
865 if (desc->channel[0].size == desc->channel[1].size &&
866 desc->channel[0].size == desc->channel[2].size &&
867 desc->channel[0].size == desc->channel[3].size) {
868 switch (desc->channel[0].size) {
869 case 4:
870 return V_028C70_COLOR_4_4_4_4;
871 case 8:
872 return V_028C70_COLOR_8_8_8_8;
873 case 16:
874 return V_028C70_COLOR_16_16_16_16;
875 case 32:
876 return V_028C70_COLOR_32_32_32_32;
877 }
878 } else if (HAS_SIZE(5,5,5,1)) {
879 return V_028C70_COLOR_1_5_5_5;
880 } else if (HAS_SIZE(10,10,10,2)) {
881 return V_028C70_COLOR_2_10_10_10;
882 }
883 break;
884 }
885 return V_028C70_COLOR_INVALID;
886 }
887
888 static uint32_t si_translate_colorswap(enum pipe_format format)
889 {
890 const struct util_format_description *desc = util_format_description(format);
891
892 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
893
894 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
895 return V_028C70_SWAP_STD;
896
897 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
898 return ~0;
899
900 switch (desc->nr_channels) {
901 case 1:
902 if (HAS_SWIZZLE(0,X))
903 return V_028C70_SWAP_STD; /* X___ */
904 else if (HAS_SWIZZLE(3,X))
905 return V_028C70_SWAP_ALT_REV; /* ___X */
906 break;
907 case 2:
908 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
909 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
910 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
911 return V_028C70_SWAP_STD; /* XY__ */
912 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
913 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
914 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
915 return V_028C70_SWAP_STD_REV; /* YX__ */
916 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
917 return V_028C70_SWAP_ALT; /* X__Y */
918 break;
919 case 3:
920 if (HAS_SWIZZLE(0,X))
921 return V_028C70_SWAP_STD; /* XYZ */
922 else if (HAS_SWIZZLE(0,Z))
923 return V_028C70_SWAP_STD_REV; /* ZYX */
924 break;
925 case 4:
926 /* check the middle channels, the 1st and 4th channel can be NONE */
927 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
928 return V_028C70_SWAP_STD; /* XYZW */
929 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
930 return V_028C70_SWAP_STD_REV; /* WZYX */
931 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
932 return V_028C70_SWAP_ALT; /* ZYXW */
933 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
934 return V_028C70_SWAP_ALT_REV; /* WXYZ */
935 break;
936 }
937 return ~0U;
938 }
939
940 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
941 {
942 if (SI_BIG_ENDIAN) {
943 switch(colorformat) {
944 /* 8-bit buffers. */
945 case V_028C70_COLOR_8:
946 return V_028C70_ENDIAN_NONE;
947
948 /* 16-bit buffers. */
949 case V_028C70_COLOR_5_6_5:
950 case V_028C70_COLOR_1_5_5_5:
951 case V_028C70_COLOR_4_4_4_4:
952 case V_028C70_COLOR_16:
953 case V_028C70_COLOR_8_8:
954 return V_028C70_ENDIAN_8IN16;
955
956 /* 32-bit buffers. */
957 case V_028C70_COLOR_8_8_8_8:
958 case V_028C70_COLOR_2_10_10_10:
959 case V_028C70_COLOR_8_24:
960 case V_028C70_COLOR_24_8:
961 case V_028C70_COLOR_16_16:
962 return V_028C70_ENDIAN_8IN32;
963
964 /* 64-bit buffers. */
965 case V_028C70_COLOR_16_16_16_16:
966 return V_028C70_ENDIAN_8IN16;
967
968 case V_028C70_COLOR_32_32:
969 return V_028C70_ENDIAN_8IN32;
970
971 /* 128-bit buffers. */
972 case V_028C70_COLOR_32_32_32_32:
973 return V_028C70_ENDIAN_8IN32;
974 default:
975 return V_028C70_ENDIAN_NONE; /* Unsupported. */
976 }
977 } else {
978 return V_028C70_ENDIAN_NONE;
979 }
980 }
981
982 /* Returns the size in bits of the widest component of a CB format */
983 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
984 {
985 switch(colorformat) {
986 case V_028C70_COLOR_4_4_4_4:
987 return 4;
988
989 case V_028C70_COLOR_1_5_5_5:
990 case V_028C70_COLOR_5_5_5_1:
991 return 5;
992
993 case V_028C70_COLOR_5_6_5:
994 return 6;
995
996 case V_028C70_COLOR_8:
997 case V_028C70_COLOR_8_8:
998 case V_028C70_COLOR_8_8_8_8:
999 return 8;
1000
1001 case V_028C70_COLOR_10_10_10_2:
1002 case V_028C70_COLOR_2_10_10_10:
1003 return 10;
1004
1005 case V_028C70_COLOR_10_11_11:
1006 case V_028C70_COLOR_11_11_10:
1007 return 11;
1008
1009 case V_028C70_COLOR_16:
1010 case V_028C70_COLOR_16_16:
1011 case V_028C70_COLOR_16_16_16_16:
1012 return 16;
1013
1014 case V_028C70_COLOR_8_24:
1015 case V_028C70_COLOR_24_8:
1016 return 24;
1017
1018 case V_028C70_COLOR_32:
1019 case V_028C70_COLOR_32_32:
1020 case V_028C70_COLOR_32_32_32_32:
1021 case V_028C70_COLOR_X24_8_32_FLOAT:
1022 return 32;
1023 }
1024
1025 assert(!"Unknown maximum component size");
1026 return 0;
1027 }
1028
1029 static uint32_t si_translate_dbformat(enum pipe_format format)
1030 {
1031 switch (format) {
1032 case PIPE_FORMAT_Z16_UNORM:
1033 return V_028040_Z_16;
1034 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1035 case PIPE_FORMAT_X8Z24_UNORM:
1036 case PIPE_FORMAT_Z24X8_UNORM:
1037 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1038 return V_028040_Z_24; /* deprecated on SI */
1039 case PIPE_FORMAT_Z32_FLOAT:
1040 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1041 return V_028040_Z_32_FLOAT;
1042 default:
1043 return V_028040_Z_INVALID;
1044 }
1045 }
1046
1047 /*
1048 * Texture translation
1049 */
1050
1051 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1052 enum pipe_format format,
1053 const struct util_format_description *desc,
1054 int first_non_void)
1055 {
1056 struct si_screen *sscreen = (struct si_screen*)screen;
1057 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1058 boolean uniform = TRUE;
1059 int i;
1060
1061 /* Colorspace (return non-RGB formats directly). */
1062 switch (desc->colorspace) {
1063 /* Depth stencil formats */
1064 case UTIL_FORMAT_COLORSPACE_ZS:
1065 switch (format) {
1066 case PIPE_FORMAT_Z16_UNORM:
1067 return V_008F14_IMG_DATA_FORMAT_16;
1068 case PIPE_FORMAT_X24S8_UINT:
1069 case PIPE_FORMAT_Z24X8_UNORM:
1070 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1071 return V_008F14_IMG_DATA_FORMAT_8_24;
1072 case PIPE_FORMAT_X8Z24_UNORM:
1073 case PIPE_FORMAT_S8X24_UINT:
1074 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1075 return V_008F14_IMG_DATA_FORMAT_24_8;
1076 case PIPE_FORMAT_S8_UINT:
1077 return V_008F14_IMG_DATA_FORMAT_8;
1078 case PIPE_FORMAT_Z32_FLOAT:
1079 return V_008F14_IMG_DATA_FORMAT_32;
1080 case PIPE_FORMAT_X32_S8X24_UINT:
1081 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1082 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1083 default:
1084 goto out_unknown;
1085 }
1086
1087 case UTIL_FORMAT_COLORSPACE_YUV:
1088 goto out_unknown; /* TODO */
1089
1090 case UTIL_FORMAT_COLORSPACE_SRGB:
1091 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1092 goto out_unknown;
1093 break;
1094
1095 default:
1096 break;
1097 }
1098
1099 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1100 if (!enable_s3tc)
1101 goto out_unknown;
1102
1103 switch (format) {
1104 case PIPE_FORMAT_RGTC1_SNORM:
1105 case PIPE_FORMAT_LATC1_SNORM:
1106 case PIPE_FORMAT_RGTC1_UNORM:
1107 case PIPE_FORMAT_LATC1_UNORM:
1108 return V_008F14_IMG_DATA_FORMAT_BC4;
1109 case PIPE_FORMAT_RGTC2_SNORM:
1110 case PIPE_FORMAT_LATC2_SNORM:
1111 case PIPE_FORMAT_RGTC2_UNORM:
1112 case PIPE_FORMAT_LATC2_UNORM:
1113 return V_008F14_IMG_DATA_FORMAT_BC5;
1114 default:
1115 goto out_unknown;
1116 }
1117 }
1118
1119 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1120
1121 if (!enable_s3tc)
1122 goto out_unknown;
1123
1124 if (!util_format_s3tc_enabled) {
1125 goto out_unknown;
1126 }
1127
1128 switch (format) {
1129 case PIPE_FORMAT_DXT1_RGB:
1130 case PIPE_FORMAT_DXT1_RGBA:
1131 case PIPE_FORMAT_DXT1_SRGB:
1132 case PIPE_FORMAT_DXT1_SRGBA:
1133 return V_008F14_IMG_DATA_FORMAT_BC1;
1134 case PIPE_FORMAT_DXT3_RGBA:
1135 case PIPE_FORMAT_DXT3_SRGBA:
1136 return V_008F14_IMG_DATA_FORMAT_BC2;
1137 case PIPE_FORMAT_DXT5_RGBA:
1138 case PIPE_FORMAT_DXT5_SRGBA:
1139 return V_008F14_IMG_DATA_FORMAT_BC3;
1140 default:
1141 goto out_unknown;
1142 }
1143 }
1144
1145 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1146 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1147 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1148 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1149 }
1150
1151 /* R8G8Bx_SNORM - TODO CxV8U8 */
1152
1153 /* See whether the components are of the same size. */
1154 for (i = 1; i < desc->nr_channels; i++) {
1155 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1156 }
1157
1158 /* Non-uniform formats. */
1159 if (!uniform) {
1160 switch(desc->nr_channels) {
1161 case 3:
1162 if (desc->channel[0].size == 5 &&
1163 desc->channel[1].size == 6 &&
1164 desc->channel[2].size == 5) {
1165 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1166 }
1167 goto out_unknown;
1168 case 4:
1169 if (desc->channel[0].size == 5 &&
1170 desc->channel[1].size == 5 &&
1171 desc->channel[2].size == 5 &&
1172 desc->channel[3].size == 1) {
1173 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1174 }
1175 if (desc->channel[0].size == 10 &&
1176 desc->channel[1].size == 10 &&
1177 desc->channel[2].size == 10 &&
1178 desc->channel[3].size == 2) {
1179 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1180 }
1181 goto out_unknown;
1182 }
1183 goto out_unknown;
1184 }
1185
1186 if (first_non_void < 0 || first_non_void > 3)
1187 goto out_unknown;
1188
1189 /* uniform formats */
1190 switch (desc->channel[first_non_void].size) {
1191 case 4:
1192 switch (desc->nr_channels) {
1193 #if 0 /* Not supported for render targets */
1194 case 2:
1195 return V_008F14_IMG_DATA_FORMAT_4_4;
1196 #endif
1197 case 4:
1198 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1199 }
1200 break;
1201 case 8:
1202 switch (desc->nr_channels) {
1203 case 1:
1204 return V_008F14_IMG_DATA_FORMAT_8;
1205 case 2:
1206 return V_008F14_IMG_DATA_FORMAT_8_8;
1207 case 4:
1208 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1209 }
1210 break;
1211 case 16:
1212 switch (desc->nr_channels) {
1213 case 1:
1214 return V_008F14_IMG_DATA_FORMAT_16;
1215 case 2:
1216 return V_008F14_IMG_DATA_FORMAT_16_16;
1217 case 4:
1218 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1219 }
1220 break;
1221 case 32:
1222 switch (desc->nr_channels) {
1223 case 1:
1224 return V_008F14_IMG_DATA_FORMAT_32;
1225 case 2:
1226 return V_008F14_IMG_DATA_FORMAT_32_32;
1227 #if 0 /* Not supported for render targets */
1228 case 3:
1229 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1230 #endif
1231 case 4:
1232 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1233 }
1234 }
1235
1236 out_unknown:
1237 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1238 return ~0;
1239 }
1240
1241 static unsigned si_tex_wrap(unsigned wrap)
1242 {
1243 switch (wrap) {
1244 default:
1245 case PIPE_TEX_WRAP_REPEAT:
1246 return V_008F30_SQ_TEX_WRAP;
1247 case PIPE_TEX_WRAP_CLAMP:
1248 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1249 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1250 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1251 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1252 return V_008F30_SQ_TEX_CLAMP_BORDER;
1253 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1254 return V_008F30_SQ_TEX_MIRROR;
1255 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1256 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1257 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1258 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1259 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1260 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1261 }
1262 }
1263
1264 static unsigned si_tex_filter(unsigned filter)
1265 {
1266 switch (filter) {
1267 default:
1268 case PIPE_TEX_FILTER_NEAREST:
1269 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1270 case PIPE_TEX_FILTER_LINEAR:
1271 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1272 }
1273 }
1274
1275 static unsigned si_tex_mipfilter(unsigned filter)
1276 {
1277 switch (filter) {
1278 case PIPE_TEX_MIPFILTER_NEAREST:
1279 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1280 case PIPE_TEX_MIPFILTER_LINEAR:
1281 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1282 default:
1283 case PIPE_TEX_MIPFILTER_NONE:
1284 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1285 }
1286 }
1287
1288 static unsigned si_tex_compare(unsigned compare)
1289 {
1290 switch (compare) {
1291 default:
1292 case PIPE_FUNC_NEVER:
1293 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1294 case PIPE_FUNC_LESS:
1295 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1296 case PIPE_FUNC_EQUAL:
1297 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1298 case PIPE_FUNC_LEQUAL:
1299 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1300 case PIPE_FUNC_GREATER:
1301 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1302 case PIPE_FUNC_NOTEQUAL:
1303 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1304 case PIPE_FUNC_GEQUAL:
1305 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1306 case PIPE_FUNC_ALWAYS:
1307 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1308 }
1309 }
1310
1311 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1312 {
1313 switch (dim) {
1314 default:
1315 case PIPE_TEXTURE_1D:
1316 return V_008F1C_SQ_RSRC_IMG_1D;
1317 case PIPE_TEXTURE_1D_ARRAY:
1318 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1319 case PIPE_TEXTURE_2D:
1320 case PIPE_TEXTURE_RECT:
1321 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1322 V_008F1C_SQ_RSRC_IMG_2D;
1323 case PIPE_TEXTURE_2D_ARRAY:
1324 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1325 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1326 case PIPE_TEXTURE_3D:
1327 return V_008F1C_SQ_RSRC_IMG_3D;
1328 case PIPE_TEXTURE_CUBE:
1329 return V_008F1C_SQ_RSRC_IMG_CUBE;
1330 }
1331 }
1332
1333 /*
1334 * Format support testing
1335 */
1336
1337 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1338 {
1339 return si_translate_texformat(screen, format, util_format_description(format),
1340 util_format_get_first_non_void_channel(format)) != ~0U;
1341 }
1342
1343 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1344 const struct util_format_description *desc,
1345 int first_non_void)
1346 {
1347 unsigned type = desc->channel[first_non_void].type;
1348 int i;
1349
1350 if (type == UTIL_FORMAT_TYPE_FIXED)
1351 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1352
1353 if (desc->nr_channels == 4 &&
1354 desc->channel[0].size == 10 &&
1355 desc->channel[1].size == 10 &&
1356 desc->channel[2].size == 10 &&
1357 desc->channel[3].size == 2)
1358 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1359
1360 /* See whether the components are of the same size. */
1361 for (i = 0; i < desc->nr_channels; i++) {
1362 if (desc->channel[first_non_void].size != desc->channel[i].size)
1363 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1364 }
1365
1366 switch (desc->channel[first_non_void].size) {
1367 case 8:
1368 switch (desc->nr_channels) {
1369 case 1:
1370 return V_008F0C_BUF_DATA_FORMAT_8;
1371 case 2:
1372 return V_008F0C_BUF_DATA_FORMAT_8_8;
1373 case 3:
1374 case 4:
1375 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1376 }
1377 break;
1378 case 16:
1379 switch (desc->nr_channels) {
1380 case 1:
1381 return V_008F0C_BUF_DATA_FORMAT_16;
1382 case 2:
1383 return V_008F0C_BUF_DATA_FORMAT_16_16;
1384 case 3:
1385 case 4:
1386 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1387 }
1388 break;
1389 case 32:
1390 /* From the Southern Islands ISA documentation about MTBUF:
1391 * 'Memory reads of data in memory that is 32 or 64 bits do not
1392 * undergo any format conversion.'
1393 */
1394 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1395 !desc->channel[first_non_void].pure_integer)
1396 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1397
1398 switch (desc->nr_channels) {
1399 case 1:
1400 return V_008F0C_BUF_DATA_FORMAT_32;
1401 case 2:
1402 return V_008F0C_BUF_DATA_FORMAT_32_32;
1403 case 3:
1404 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1405 case 4:
1406 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1407 }
1408 break;
1409 }
1410
1411 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1412 }
1413
1414 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1415 const struct util_format_description *desc,
1416 int first_non_void)
1417 {
1418 switch (desc->channel[first_non_void].type) {
1419 case UTIL_FORMAT_TYPE_SIGNED:
1420 if (desc->channel[first_non_void].normalized)
1421 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1422 else if (desc->channel[first_non_void].pure_integer)
1423 return V_008F0C_BUF_NUM_FORMAT_SINT;
1424 else
1425 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1426 break;
1427 case UTIL_FORMAT_TYPE_UNSIGNED:
1428 if (desc->channel[first_non_void].normalized)
1429 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1430 else if (desc->channel[first_non_void].pure_integer)
1431 return V_008F0C_BUF_NUM_FORMAT_UINT;
1432 else
1433 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1434 break;
1435 case UTIL_FORMAT_TYPE_FLOAT:
1436 default:
1437 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1438 }
1439 }
1440
1441 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1442 {
1443 const struct util_format_description *desc;
1444 int first_non_void;
1445 unsigned data_format;
1446
1447 desc = util_format_description(format);
1448 first_non_void = util_format_get_first_non_void_channel(format);
1449 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1450 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1451 }
1452
1453 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1454 {
1455 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1456 si_translate_colorswap(format) != ~0U;
1457 }
1458
1459 static bool si_is_zs_format_supported(enum pipe_format format)
1460 {
1461 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1462 }
1463
1464 boolean si_is_format_supported(struct pipe_screen *screen,
1465 enum pipe_format format,
1466 enum pipe_texture_target target,
1467 unsigned sample_count,
1468 unsigned usage)
1469 {
1470 struct si_screen *sscreen = (struct si_screen *)screen;
1471 unsigned retval = 0;
1472
1473 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1474 R600_ERR("r600: unsupported texture type %d\n", target);
1475 return FALSE;
1476 }
1477
1478 if (!util_format_is_supported(format, usage))
1479 return FALSE;
1480
1481 if (sample_count > 1) {
1482 if (HAVE_LLVM < 0x0304)
1483 return FALSE;
1484
1485 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1486 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1487 return FALSE;
1488
1489 switch (sample_count) {
1490 case 2:
1491 case 4:
1492 case 8:
1493 break;
1494 default:
1495 return FALSE;
1496 }
1497 }
1498
1499 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1500 if (target == PIPE_BUFFER) {
1501 if (si_is_vertex_format_supported(screen, format))
1502 retval |= PIPE_BIND_SAMPLER_VIEW;
1503 } else {
1504 if (si_is_sampler_format_supported(screen, format))
1505 retval |= PIPE_BIND_SAMPLER_VIEW;
1506 }
1507 }
1508
1509 if ((usage & (PIPE_BIND_RENDER_TARGET |
1510 PIPE_BIND_DISPLAY_TARGET |
1511 PIPE_BIND_SCANOUT |
1512 PIPE_BIND_SHARED)) &&
1513 si_is_colorbuffer_format_supported(format)) {
1514 retval |= usage &
1515 (PIPE_BIND_RENDER_TARGET |
1516 PIPE_BIND_DISPLAY_TARGET |
1517 PIPE_BIND_SCANOUT |
1518 PIPE_BIND_SHARED);
1519 }
1520
1521 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1522 si_is_zs_format_supported(format)) {
1523 retval |= PIPE_BIND_DEPTH_STENCIL;
1524 }
1525
1526 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1527 si_is_vertex_format_supported(screen, format)) {
1528 retval |= PIPE_BIND_VERTEX_BUFFER;
1529 }
1530
1531 if (usage & PIPE_BIND_TRANSFER_READ)
1532 retval |= PIPE_BIND_TRANSFER_READ;
1533 if (usage & PIPE_BIND_TRANSFER_WRITE)
1534 retval |= PIPE_BIND_TRANSFER_WRITE;
1535
1536 return retval == usage;
1537 }
1538
1539 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1540 {
1541 unsigned tile_mode_index = 0;
1542
1543 if (stencil) {
1544 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1545 } else {
1546 tile_mode_index = rtex->surface.tiling_index[level];
1547 }
1548 return tile_mode_index;
1549 }
1550
1551 /*
1552 * framebuffer handling
1553 */
1554
1555 static void si_cb(struct si_context *sctx, struct si_pm4_state *pm4,
1556 const struct pipe_framebuffer_state *state, int cb)
1557 {
1558 struct r600_texture *rtex;
1559 struct si_surface *surf;
1560 unsigned level = state->cbufs[cb]->u.tex.level;
1561 unsigned pitch, slice;
1562 unsigned color_info, color_attrib, color_pitch, color_view;
1563 unsigned tile_mode_index;
1564 unsigned format, swap, ntype, endian;
1565 uint64_t offset;
1566 const struct util_format_description *desc;
1567 int i;
1568 unsigned blend_clamp = 0, blend_bypass = 0;
1569 unsigned max_comp_size;
1570
1571 surf = (struct si_surface *)state->cbufs[cb];
1572 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1573
1574 offset = rtex->surface.level[level].offset;
1575
1576 /* Layered rendering doesn't work with LINEAR_GENERAL.
1577 * (LINEAR_ALIGNED and others work) */
1578 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1579 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer);
1580 offset += rtex->surface.level[level].slice_size *
1581 state->cbufs[cb]->u.tex.first_layer;
1582 color_view = 0;
1583 } else {
1584 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1585 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
1586 }
1587
1588 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1589 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1590 if (slice) {
1591 slice = slice - 1;
1592 }
1593
1594 tile_mode_index = si_tile_mode_index(rtex, level, false);
1595
1596 desc = util_format_description(surf->base.format);
1597 for (i = 0; i < 4; i++) {
1598 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1599 break;
1600 }
1601 }
1602 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1603 ntype = V_028C70_NUMBER_FLOAT;
1604 } else {
1605 ntype = V_028C70_NUMBER_UNORM;
1606 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1607 ntype = V_028C70_NUMBER_SRGB;
1608 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1609 if (desc->channel[i].pure_integer) {
1610 ntype = V_028C70_NUMBER_SINT;
1611 } else {
1612 assert(desc->channel[i].normalized);
1613 ntype = V_028C70_NUMBER_SNORM;
1614 }
1615 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1616 if (desc->channel[i].pure_integer) {
1617 ntype = V_028C70_NUMBER_UINT;
1618 } else {
1619 assert(desc->channel[i].normalized);
1620 ntype = V_028C70_NUMBER_UNORM;
1621 }
1622 }
1623 }
1624
1625 format = si_translate_colorformat(surf->base.format);
1626 if (format == V_028C70_COLOR_INVALID) {
1627 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1628 }
1629 assert(format != V_028C70_COLOR_INVALID);
1630 swap = si_translate_colorswap(surf->base.format);
1631 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1632 endian = V_028C70_ENDIAN_NONE;
1633 } else {
1634 endian = si_colorformat_endian_swap(format);
1635 }
1636
1637 /* blend clamp should be set for all NORM/SRGB types */
1638 if (ntype == V_028C70_NUMBER_UNORM ||
1639 ntype == V_028C70_NUMBER_SNORM ||
1640 ntype == V_028C70_NUMBER_SRGB)
1641 blend_clamp = 1;
1642
1643 /* set blend bypass according to docs if SINT/UINT or
1644 8/24 COLOR variants */
1645 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1646 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1647 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1648 blend_clamp = 0;
1649 blend_bypass = 1;
1650 }
1651
1652 color_info = S_028C70_FORMAT(format) |
1653 S_028C70_COMP_SWAP(swap) |
1654 S_028C70_BLEND_CLAMP(blend_clamp) |
1655 S_028C70_BLEND_BYPASS(blend_bypass) |
1656 S_028C70_NUMBER_TYPE(ntype) |
1657 S_028C70_ENDIAN(endian);
1658
1659 color_pitch = S_028C64_TILE_MAX(pitch);
1660
1661 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1662 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1663
1664 if (rtex->resource.b.b.nr_samples > 1) {
1665 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1666
1667 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1668 S_028C74_NUM_FRAGMENTS(log_samples);
1669
1670 if (rtex->fmask.size) {
1671 color_info |= S_028C70_COMPRESSION(1);
1672 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1673
1674 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1675
1676 if (sctx->b.chip_class == SI) {
1677 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1678 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1679 }
1680 if (sctx->b.chip_class >= CIK) {
1681 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1682 }
1683 }
1684 }
1685
1686 if (rtex->cmask.size) {
1687 color_info |= S_028C70_FAST_CLEAR(1);
1688 }
1689
1690 offset += r600_resource_va(sctx->b.b.screen, state->cbufs[cb]->texture);
1691 offset >>= 8;
1692
1693 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1694 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1695 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1696 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1697 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
1698 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1699 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1700
1701 if (rtex->cmask.size) {
1702 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1703 offset + (rtex->cmask.offset >> 8));
1704 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1705 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1706 }
1707 if (rtex->fmask.size) {
1708 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1709 offset + (rtex->fmask.offset >> 8));
1710 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1711 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1712 }
1713
1714 /* set CB_COLOR1_INFO for possible dual-src blending */
1715 if (state->nr_cbufs == 1) {
1716 assert(cb == 0);
1717 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1718 }
1719
1720 /* Determine pixel shader export format */
1721 max_comp_size = si_colorformat_max_comp_size(format);
1722 if (ntype == V_028C70_NUMBER_SRGB ||
1723 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1724 max_comp_size <= 10) ||
1725 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1726 sctx->export_16bpc |= 1 << cb;
1727 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1728 if (state->nr_cbufs == 1)
1729 sctx->export_16bpc |= 1 << 1;
1730 }
1731 }
1732
1733 static void si_db(struct si_context *sctx, struct si_pm4_state *pm4,
1734 const struct pipe_framebuffer_state *state)
1735 {
1736 struct si_screen *sscreen = sctx->screen;
1737 struct r600_texture *rtex;
1738 struct si_surface *surf;
1739 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1740 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1741 uint32_t z_info, s_info, db_depth_info;
1742 uint64_t z_offs, s_offs;
1743 uint32_t db_htile_data_base, db_htile_surface;
1744
1745 if (state->zsbuf == NULL) {
1746 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1747 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1748 return;
1749 }
1750
1751 surf = (struct si_surface *)state->zsbuf;
1752 level = surf->base.u.tex.level;
1753 rtex = (struct r600_texture*)surf->base.texture;
1754
1755 format = si_translate_dbformat(rtex->resource.b.b.format);
1756
1757 if (format == V_028040_Z_INVALID) {
1758 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1759 }
1760 assert(format != V_028040_Z_INVALID);
1761
1762 s_offs = z_offs = r600_resource_va(sctx->b.b.screen, surf->base.texture);
1763 z_offs += rtex->surface.level[level].offset;
1764 s_offs += rtex->surface.stencil_level[level].offset;
1765
1766 z_offs >>= 8;
1767 s_offs >>= 8;
1768
1769 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1770 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1771 if (slice) {
1772 slice = slice - 1;
1773 }
1774
1775 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1776
1777 z_info = S_028040_FORMAT(format);
1778 if (rtex->resource.b.b.nr_samples > 1) {
1779 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1780 }
1781
1782 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1783 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1784 else
1785 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1786
1787 if (sctx->b.chip_class >= CIK) {
1788 switch (rtex->surface.level[level].mode) {
1789 case RADEON_SURF_MODE_2D:
1790 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1791 break;
1792 case RADEON_SURF_MODE_1D:
1793 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1794 case RADEON_SURF_MODE_LINEAR:
1795 default:
1796 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1797 break;
1798 }
1799 tile_split = rtex->surface.tile_split;
1800 stile_split = rtex->surface.stencil_tile_split;
1801 macro_aspect = rtex->surface.mtilea;
1802 bankw = rtex->surface.bankw;
1803 bankh = rtex->surface.bankh;
1804 tile_split = cik_tile_split(tile_split);
1805 stile_split = cik_tile_split(stile_split);
1806 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1807 bankw = cik_bank_wh(bankw);
1808 bankh = cik_bank_wh(bankh);
1809 nbanks = cik_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split);
1810 tile_mode_index = si_tile_mode_index(rtex, level, false);
1811 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1812
1813 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1814 S_02803C_PIPE_CONFIG(pipe_config) |
1815 S_02803C_BANK_WIDTH(bankw) |
1816 S_02803C_BANK_HEIGHT(bankh) |
1817 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1818 S_02803C_NUM_BANKS(nbanks);
1819 z_info |= S_028040_TILE_SPLIT(tile_split);
1820 s_info |= S_028044_TILE_SPLIT(stile_split);
1821 } else {
1822 tile_mode_index = si_tile_mode_index(rtex, level, false);
1823 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1824 tile_mode_index = si_tile_mode_index(rtex, level, true);
1825 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1826 }
1827
1828 /* HiZ aka depth buffer htile */
1829 /* use htile only for first level */
1830 if (rtex->htile_buffer && !level) {
1831 const struct util_format_description *fmt_desc;
1832
1833 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1834
1835 /* This is optimal for the clear value of 1.0 and using
1836 * the LESS and LEQUAL test functions. Set this to 0
1837 * for the opposite case. This can only be changed when
1838 * clearing. */
1839 z_info |= S_028040_ZRANGE_PRECISION(1);
1840
1841 fmt_desc = util_format_description(rtex->resource.b.b.format);
1842 if (!util_format_has_stencil(fmt_desc)) {
1843 /* Use all of the htile_buffer for depth */
1844 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1845 }
1846
1847 uint64_t va = r600_resource_va(&sctx->screen->b.b, &rtex->htile_buffer->b.b);
1848 db_htile_data_base = va >> 8;
1849 db_htile_surface = S_028ABC_FULL_CACHE(1);
1850
1851 si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE);
1852 } else {
1853 db_htile_data_base = 0;
1854 db_htile_surface = 0;
1855 }
1856
1857 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1858 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1859 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1860 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
1861
1862 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1863 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1864 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1865
1866 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1867 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1868 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1869 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1870 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1871
1872 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1873 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1874
1875 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
1876 }
1877
1878 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1879 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1880 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1881 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1882 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1883
1884 /* 2xMSAA
1885 * There are two locations (-4, 4), (4, -4). */
1886 static uint32_t sample_locs_2x[] = {
1887 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1888 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1889 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1890 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1891 };
1892 static unsigned max_dist_2x = 4;
1893 /* 4xMSAA
1894 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1895 static uint32_t sample_locs_4x[] = {
1896 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1897 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1898 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1899 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1900 };
1901 static unsigned max_dist_4x = 6;
1902 /* Cayman/SI 8xMSAA */
1903 static uint32_t cm_sample_locs_8x[] = {
1904 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1905 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1906 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1907 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1908 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1909 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1910 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1911 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1912 };
1913 static unsigned cm_max_dist_8x = 8;
1914 /* Cayman/SI 16xMSAA */
1915 static uint32_t cm_sample_locs_16x[] = {
1916 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1917 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1918 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1919 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1920 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1921 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1922 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1923 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1924 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1925 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1926 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1927 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1928 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1929 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1930 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1931 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1932 };
1933 static unsigned cm_max_dist_16x = 8;
1934
1935 static void si_get_sample_position(struct pipe_context *ctx,
1936 unsigned sample_count,
1937 unsigned sample_index,
1938 float *out_value)
1939 {
1940 int offset, index;
1941 struct {
1942 int idx:4;
1943 } val;
1944 switch (sample_count) {
1945 case 1:
1946 default:
1947 out_value[0] = out_value[1] = 0.5;
1948 break;
1949 case 2:
1950 offset = 4 * (sample_index * 2);
1951 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1952 out_value[0] = (float)(val.idx + 8) / 16.0f;
1953 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1954 out_value[1] = (float)(val.idx + 8) / 16.0f;
1955 break;
1956 case 4:
1957 offset = 4 * (sample_index * 2);
1958 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1959 out_value[0] = (float)(val.idx + 8) / 16.0f;
1960 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1961 out_value[1] = (float)(val.idx + 8) / 16.0f;
1962 break;
1963 case 8:
1964 offset = 4 * (sample_index % 4 * 2);
1965 index = (sample_index / 4) * 4;
1966 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1967 out_value[0] = (float)(val.idx + 8) / 16.0f;
1968 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1969 out_value[1] = (float)(val.idx + 8) / 16.0f;
1970 break;
1971 case 16:
1972 offset = 4 * (sample_index % 4 * 2);
1973 index = (sample_index / 4) * 4;
1974 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1975 out_value[0] = (float)(val.idx + 8) / 16.0f;
1976 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1977 out_value[1] = (float)(val.idx + 8) / 16.0f;
1978 break;
1979 }
1980 }
1981
1982 static void si_set_msaa_state(struct si_context *sctx, struct si_pm4_state *pm4, int nr_samples)
1983 {
1984 unsigned max_dist = 0;
1985
1986 switch (nr_samples) {
1987 default:
1988 nr_samples = 0;
1989 break;
1990 case 2:
1991 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1992 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1993 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1994 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1995 max_dist = max_dist_2x;
1996 break;
1997 case 4:
1998 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1999 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2000 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2001 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2002 max_dist = max_dist_4x;
2003 break;
2004 case 8:
2005 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2006 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2007 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2008 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2009 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2010 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2011 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2012 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2013 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2014 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2015 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2016 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2017 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2018 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2019 max_dist = cm_max_dist_8x;
2020 break;
2021 case 16:
2022 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2023 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2024 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2025 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2026 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2027 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2028 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2029 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2030 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2031 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2032 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2033 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2034 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2035 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2036 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2037 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2038 max_dist = cm_max_dist_16x;
2039 break;
2040 }
2041
2042 if (nr_samples > 1) {
2043 unsigned log_samples = util_logbase2(nr_samples);
2044
2045 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2046 S_028BDC_LAST_PIXEL(1) |
2047 S_028BDC_EXPAND_LINE_WIDTH(1));
2048 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2049 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2050 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2051 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2052
2053 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2054 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2055 S_028804_PS_ITER_SAMPLES(log_samples) |
2056 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2057 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2058 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2059 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2060 } else {
2061 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2062 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2063
2064 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2065 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2066 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2067 }
2068 }
2069
2070 static void si_set_framebuffer_state(struct pipe_context *ctx,
2071 const struct pipe_framebuffer_state *state)
2072 {
2073 struct si_context *sctx = (struct si_context *)ctx;
2074 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2075 int nr_samples, i;
2076
2077 if (pm4 == NULL)
2078 return;
2079
2080 if (sctx->framebuffer.nr_cbufs) {
2081 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2082 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2083 }
2084 if (sctx->framebuffer.zsbuf) {
2085 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
2086 R600_CONTEXT_FLUSH_AND_INV_DB_META;
2087 }
2088
2089 util_copy_framebuffer_state(&sctx->framebuffer, state);
2090
2091 /* build states */
2092 sctx->export_16bpc = 0;
2093 sctx->fb_compressed_cb_mask = 0;
2094 for (i = 0; i < state->nr_cbufs; i++) {
2095 struct r600_texture *rtex;
2096
2097 if (!state->cbufs[i]) {
2098 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2099 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2100 continue;
2101 }
2102
2103 rtex = (struct r600_texture*)state->cbufs[i]->texture;
2104
2105 si_cb(sctx, pm4, state, i);
2106
2107 if (rtex->fmask.size || rtex->cmask.size) {
2108 sctx->fb_compressed_cb_mask |= 1 << i;
2109 }
2110 }
2111 for (; i < 8; i++) {
2112 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2113 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2114 }
2115
2116 assert(!(sctx->export_16bpc & ~0xff));
2117 si_db(sctx, pm4, state);
2118
2119 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2120 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2121 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2122
2123 nr_samples = util_framebuffer_get_num_samples(state);
2124
2125 si_set_msaa_state(sctx, pm4, nr_samples);
2126 sctx->fb_log_samples = util_logbase2(nr_samples);
2127 sctx->fb_cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2128 util_format_is_pure_integer(state->cbufs[0]->format);
2129
2130 si_pm4_set_state(sctx, framebuffer, pm4);
2131 si_update_fb_rs_state(sctx);
2132 si_update_fb_blend_state(sctx);
2133 }
2134
2135 /*
2136 * shaders
2137 */
2138
2139 /* Compute the key for the hw shader variant */
2140 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2141 struct si_pipe_shader_selector *sel,
2142 union si_shader_key *key)
2143 {
2144 struct si_context *sctx = (struct si_context *)ctx;
2145 memset(key, 0, sizeof(*key));
2146
2147 if (sel->type == PIPE_SHADER_VERTEX) {
2148 unsigned i;
2149 if (!sctx->vertex_elements)
2150 return;
2151
2152 for (i = 0; i < sctx->vertex_elements->count; ++i)
2153 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2154
2155 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2156 key->vs.ucps_enabled |= 0x2;
2157 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2158 key->vs.ucps_enabled |= 0x1;
2159 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2160 if (sel->fs_write_all)
2161 key->ps.nr_cbufs = sctx->framebuffer.nr_cbufs;
2162 key->ps.export_16bpc = sctx->export_16bpc;
2163
2164 if (sctx->queued.named.rasterizer) {
2165 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2166 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2167
2168 if (sctx->queued.named.blend) {
2169 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2170 sctx->queued.named.rasterizer->multisample_enable &&
2171 !sctx->fb_cb0_is_integer;
2172 }
2173 }
2174 if (sctx->queued.named.dsa) {
2175 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2176
2177 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2178 if (sctx->framebuffer.nr_cbufs &&
2179 sctx->framebuffer.cbufs[0] &&
2180 util_format_is_pure_integer(sctx->framebuffer.cbufs[0]->texture->format))
2181 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2182 } else {
2183 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2184 }
2185 }
2186 }
2187
2188 /* Select the hw shader variant depending on the current state.
2189 * (*dirty) is set to 1 if current variant was changed */
2190 int si_shader_select(struct pipe_context *ctx,
2191 struct si_pipe_shader_selector *sel,
2192 unsigned *dirty)
2193 {
2194 union si_shader_key key;
2195 struct si_pipe_shader * shader = NULL;
2196 int r;
2197
2198 si_shader_selector_key(ctx, sel, &key);
2199
2200 /* Check if we don't need to change anything.
2201 * This path is also used for most shaders that don't need multiple
2202 * variants, it will cost just a computation of the key and this
2203 * test. */
2204 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2205 return 0;
2206 }
2207
2208 /* lookup if we have other variants in the list */
2209 if (sel->num_shaders > 1) {
2210 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2211
2212 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2213 p = c;
2214 c = c->next_variant;
2215 }
2216
2217 if (c) {
2218 p->next_variant = c->next_variant;
2219 shader = c;
2220 }
2221 }
2222
2223 if (unlikely(!shader)) {
2224 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2225 shader->selector = sel;
2226 shader->key = key;
2227
2228 r = si_pipe_shader_create(ctx, shader);
2229 if (unlikely(r)) {
2230 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2231 sel->type, r);
2232 sel->current = NULL;
2233 FREE(shader);
2234 return r;
2235 }
2236 sel->num_shaders++;
2237 }
2238
2239 if (dirty)
2240 *dirty = 1;
2241
2242 shader->next_variant = sel->current;
2243 sel->current = shader;
2244
2245 return 0;
2246 }
2247
2248 static void *si_create_shader_state(struct pipe_context *ctx,
2249 const struct pipe_shader_state *state,
2250 unsigned pipe_shader_type)
2251 {
2252 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2253 int r;
2254
2255 sel->type = pipe_shader_type;
2256 sel->tokens = tgsi_dup_tokens(state->tokens);
2257 sel->so = state->stream_output;
2258
2259 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2260 struct tgsi_shader_info info;
2261
2262 tgsi_scan_shader(state->tokens, &info);
2263 sel->fs_write_all = info.color0_writes_all_cbufs;
2264 }
2265
2266 r = si_shader_select(ctx, sel, NULL);
2267 if (r) {
2268 free(sel);
2269 return NULL;
2270 }
2271
2272 return sel;
2273 }
2274
2275 static void *si_create_fs_state(struct pipe_context *ctx,
2276 const struct pipe_shader_state *state)
2277 {
2278 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2279 }
2280
2281 static void *si_create_vs_state(struct pipe_context *ctx,
2282 const struct pipe_shader_state *state)
2283 {
2284 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2285 }
2286
2287 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2288 {
2289 struct si_context *sctx = (struct si_context *)ctx;
2290 struct si_pipe_shader_selector *sel = state;
2291
2292 if (sctx->vs_shader == sel)
2293 return;
2294
2295 if (!sel || !sel->current)
2296 return;
2297
2298 sctx->vs_shader = sel;
2299 si_pm4_bind_state(sctx, vs, sel->current->pm4);
2300 sctx->b.streamout.stride_in_dw = sel->so.stride;
2301 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2302 }
2303
2304 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2305 {
2306 struct si_context *sctx = (struct si_context *)ctx;
2307 struct si_pipe_shader_selector *sel = state;
2308
2309 if (sctx->ps_shader == sel)
2310 return;
2311
2312 if (!sel || !sel->current)
2313 sel = sctx->dummy_pixel_shader;
2314
2315 sctx->ps_shader = sel;
2316 si_pm4_bind_state(sctx, ps, sel->current->pm4);
2317 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2318 }
2319
2320 static void si_delete_shader_selector(struct pipe_context *ctx,
2321 struct si_pipe_shader_selector *sel)
2322 {
2323 struct si_context *sctx = (struct si_context *)ctx;
2324 struct si_pipe_shader *p = sel->current, *c;
2325
2326 while (p) {
2327 c = p->next_variant;
2328 si_pm4_delete_state(sctx, vs, p->pm4);
2329 si_pipe_shader_destroy(ctx, p);
2330 free(p);
2331 p = c;
2332 }
2333
2334 free(sel->tokens);
2335 free(sel);
2336 }
2337
2338 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2339 {
2340 struct si_context *sctx = (struct si_context *)ctx;
2341 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2342
2343 if (sctx->vs_shader == sel) {
2344 sctx->vs_shader = NULL;
2345 }
2346
2347 si_delete_shader_selector(ctx, sel);
2348 }
2349
2350 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2351 {
2352 struct si_context *sctx = (struct si_context *)ctx;
2353 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2354
2355 if (sctx->ps_shader == sel) {
2356 sctx->ps_shader = NULL;
2357 }
2358
2359 si_delete_shader_selector(ctx, sel);
2360 }
2361
2362 /*
2363 * Samplers
2364 */
2365
2366 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2367 struct pipe_resource *texture,
2368 const struct pipe_sampler_view *state)
2369 {
2370 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2371 struct r600_texture *tmp = (struct r600_texture*)texture;
2372 const struct util_format_description *desc;
2373 unsigned format, num_format;
2374 uint32_t pitch = 0;
2375 unsigned char state_swizzle[4], swizzle[4];
2376 unsigned height, depth, width;
2377 enum pipe_format pipe_format = state->format;
2378 struct radeon_surface_level *surflevel;
2379 int first_non_void;
2380 uint64_t va;
2381
2382 if (view == NULL)
2383 return NULL;
2384
2385 /* initialize base object */
2386 view->base = *state;
2387 view->base.texture = NULL;
2388 pipe_resource_reference(&view->base.texture, texture);
2389 view->base.reference.count = 1;
2390 view->base.context = ctx;
2391 view->resource = &tmp->resource;
2392
2393 /* Buffer resource. */
2394 if (texture->target == PIPE_BUFFER) {
2395 unsigned stride;
2396
2397 desc = util_format_description(state->format);
2398 first_non_void = util_format_get_first_non_void_channel(state->format);
2399 stride = desc->block.bits / 8;
2400 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2401 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2402 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2403
2404 view->state[0] = va;
2405 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2406 S_008F04_STRIDE(stride);
2407 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2408 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2409 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2410 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2411 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2412 S_008F0C_NUM_FORMAT(num_format) |
2413 S_008F0C_DATA_FORMAT(format);
2414 return &view->base;
2415 }
2416
2417 state_swizzle[0] = state->swizzle_r;
2418 state_swizzle[1] = state->swizzle_g;
2419 state_swizzle[2] = state->swizzle_b;
2420 state_swizzle[3] = state->swizzle_a;
2421
2422 surflevel = tmp->surface.level;
2423
2424 /* Texturing with separate depth and stencil. */
2425 if (tmp->is_depth && !tmp->is_flushing_texture) {
2426 switch (pipe_format) {
2427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2428 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2429 break;
2430 case PIPE_FORMAT_X8Z24_UNORM:
2431 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2432 /* Z24 is always stored like this. */
2433 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2434 break;
2435 case PIPE_FORMAT_X24S8_UINT:
2436 case PIPE_FORMAT_S8X24_UINT:
2437 case PIPE_FORMAT_X32_S8X24_UINT:
2438 pipe_format = PIPE_FORMAT_S8_UINT;
2439 surflevel = tmp->surface.stencil_level;
2440 break;
2441 default:;
2442 }
2443 }
2444
2445 desc = util_format_description(pipe_format);
2446
2447 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2448 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2449 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2450
2451 switch (pipe_format) {
2452 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2453 case PIPE_FORMAT_X24S8_UINT:
2454 case PIPE_FORMAT_X32_S8X24_UINT:
2455 case PIPE_FORMAT_X8Z24_UNORM:
2456 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2457 break;
2458 default:
2459 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2460 }
2461 } else {
2462 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2463 }
2464
2465 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2466
2467 switch (pipe_format) {
2468 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2469 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2470 break;
2471 default:
2472 if (first_non_void < 0) {
2473 if (util_format_is_compressed(pipe_format)) {
2474 switch (pipe_format) {
2475 case PIPE_FORMAT_DXT1_SRGB:
2476 case PIPE_FORMAT_DXT1_SRGBA:
2477 case PIPE_FORMAT_DXT3_SRGBA:
2478 case PIPE_FORMAT_DXT5_SRGBA:
2479 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2480 break;
2481 case PIPE_FORMAT_RGTC1_SNORM:
2482 case PIPE_FORMAT_LATC1_SNORM:
2483 case PIPE_FORMAT_RGTC2_SNORM:
2484 case PIPE_FORMAT_LATC2_SNORM:
2485 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2486 break;
2487 default:
2488 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2489 break;
2490 }
2491 } else {
2492 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2493 }
2494 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2495 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2496 } else {
2497 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2498
2499 switch (desc->channel[first_non_void].type) {
2500 case UTIL_FORMAT_TYPE_FLOAT:
2501 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2502 break;
2503 case UTIL_FORMAT_TYPE_SIGNED:
2504 if (desc->channel[first_non_void].normalized)
2505 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2506 else if (desc->channel[first_non_void].pure_integer)
2507 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2508 else
2509 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2510 break;
2511 case UTIL_FORMAT_TYPE_UNSIGNED:
2512 if (desc->channel[first_non_void].normalized)
2513 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2514 else if (desc->channel[first_non_void].pure_integer)
2515 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2516 else
2517 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2518 }
2519 }
2520 }
2521
2522 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2523 if (format == ~0) {
2524 format = 0;
2525 }
2526
2527 /* not supported any more */
2528 //endian = si_colorformat_endian_swap(format);
2529
2530 width = surflevel[0].npix_x;
2531 height = surflevel[0].npix_y;
2532 depth = surflevel[0].npix_z;
2533 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2534
2535 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2536 height = 1;
2537 depth = texture->array_size;
2538 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2539 depth = texture->array_size;
2540 }
2541
2542 va = r600_resource_va(ctx->screen, texture);
2543 va += surflevel[0].offset;
2544 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2545 view->state[0] = va >> 8;
2546 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2547 S_008F14_DATA_FORMAT(format) |
2548 S_008F14_NUM_FORMAT(num_format));
2549 view->state[2] = (S_008F18_WIDTH(width - 1) |
2550 S_008F18_HEIGHT(height - 1));
2551 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2552 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2553 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2554 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2555 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2556 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2557 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2558 util_logbase2(texture->nr_samples) :
2559 state->u.tex.last_level - tmp->mipmap_shift) |
2560 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2561 S_008F1C_POW2_PAD(texture->last_level > 0) |
2562 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2563 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2564 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2565 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2566 view->state[6] = 0;
2567 view->state[7] = 0;
2568
2569 /* Initialize the sampler view for FMASK. */
2570 if (tmp->fmask.size) {
2571 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2572 uint32_t fmask_format;
2573
2574 switch (texture->nr_samples) {
2575 case 2:
2576 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2577 break;
2578 case 4:
2579 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2580 break;
2581 case 8:
2582 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2583 break;
2584 default:
2585 assert(0);
2586 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2587 }
2588
2589 view->fmask_state[0] = va >> 8;
2590 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2591 S_008F14_DATA_FORMAT(fmask_format) |
2592 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2593 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2594 S_008F18_HEIGHT(height - 1);
2595 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2596 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2597 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2598 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2599 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2600 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2601 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2602 S_008F20_PITCH(tmp->fmask.pitch - 1);
2603 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2604 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2605 view->fmask_state[6] = 0;
2606 view->fmask_state[7] = 0;
2607 }
2608
2609 return &view->base;
2610 }
2611
2612 static void si_sampler_view_destroy(struct pipe_context *ctx,
2613 struct pipe_sampler_view *state)
2614 {
2615 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2616
2617 pipe_resource_reference(&state->texture, NULL);
2618 FREE(resource);
2619 }
2620
2621 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2622 {
2623 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2624 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2625 (linear_filter &&
2626 (wrap == PIPE_TEX_WRAP_CLAMP ||
2627 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2628 }
2629
2630 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2631 {
2632 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2633 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2634
2635 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2636 state->border_color.ui[2] || state->border_color.ui[3]) &&
2637 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2638 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2639 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2640 }
2641
2642 static void *si_create_sampler_state(struct pipe_context *ctx,
2643 const struct pipe_sampler_state *state)
2644 {
2645 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2646 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2647 unsigned border_color_type;
2648
2649 if (rstate == NULL) {
2650 return NULL;
2651 }
2652
2653 if (sampler_state_needs_border_color(state))
2654 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2655 else
2656 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2657
2658 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2659 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2660 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2661 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2662 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2663 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2664 aniso_flag_offset << 16 | /* XXX */
2665 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2666 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2667 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2668 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2669 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2670 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2671 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2672 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2673
2674 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2675 memcpy(rstate->border_color, state->border_color.ui,
2676 sizeof(rstate->border_color));
2677 }
2678
2679 return rstate;
2680 }
2681
2682 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2683 * the si_set_sampler_view calls. LTO might help too. */
2684 static void si_set_sampler_views(struct pipe_context *ctx,
2685 unsigned shader, unsigned start,
2686 unsigned count,
2687 struct pipe_sampler_view **views)
2688 {
2689 struct si_context *sctx = (struct si_context *)ctx;
2690 struct si_textures_info *samplers = &sctx->samplers[shader];
2691 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2692 int i;
2693
2694 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2695 return;
2696
2697 assert(start == 0);
2698
2699 for (i = 0; i < count; i++) {
2700 if (!views[i]) {
2701 samplers->depth_texture_mask &= ~(1 << i);
2702 samplers->compressed_colortex_mask &= ~(1 << i);
2703 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2704 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2705 NULL, NULL);
2706 continue;
2707 }
2708
2709 si_set_sampler_view(sctx, shader, i, views[i], rviews[i]->state);
2710
2711 if (views[i]->texture->target != PIPE_BUFFER) {
2712 struct r600_texture *rtex =
2713 (struct r600_texture*)views[i]->texture;
2714
2715 if (rtex->is_depth && !rtex->is_flushing_texture) {
2716 samplers->depth_texture_mask |= 1 << i;
2717 } else {
2718 samplers->depth_texture_mask &= ~(1 << i);
2719 }
2720 if (rtex->cmask.size || rtex->fmask.size) {
2721 samplers->compressed_colortex_mask |= 1 << i;
2722 } else {
2723 samplers->compressed_colortex_mask &= ~(1 << i);
2724 }
2725
2726 if (rtex->fmask.size) {
2727 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2728 views[i], rviews[i]->fmask_state);
2729 } else {
2730 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2731 NULL, NULL);
2732 }
2733 }
2734 }
2735 for (; i < samplers->n_views; i++) {
2736 samplers->depth_texture_mask &= ~(1 << i);
2737 samplers->compressed_colortex_mask &= ~(1 << i);
2738 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2739 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2740 NULL, NULL);
2741 }
2742
2743 samplers->n_views = count;
2744 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2745 }
2746
2747 static struct si_pm4_state *si_set_sampler_states(struct si_context *sctx, unsigned count,
2748 void **states,
2749 struct si_textures_info *samplers,
2750 unsigned user_data_reg)
2751 {
2752 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2753 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2754 uint32_t *border_color_table = NULL;
2755 int i, j;
2756
2757 if (!count)
2758 goto out;
2759
2760 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2761
2762 si_pm4_sh_data_begin(pm4);
2763 for (i = 0; i < count; i++) {
2764 if (rstates[i] &&
2765 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2766 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2767 if (!sctx->border_color_table ||
2768 ((sctx->border_color_offset + count - i) &
2769 C_008F3C_BORDER_COLOR_PTR)) {
2770 r600_resource_reference(&sctx->border_color_table, NULL);
2771 sctx->border_color_offset = 0;
2772
2773 sctx->border_color_table =
2774 si_resource_create_custom(&sctx->screen->b.b,
2775 PIPE_USAGE_STAGING,
2776 4096 * 4 * 4);
2777 }
2778
2779 if (!border_color_table) {
2780 border_color_table =
2781 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2782 sctx->b.rings.gfx.cs,
2783 PIPE_TRANSFER_WRITE |
2784 PIPE_TRANSFER_UNSYNCHRONIZED);
2785 }
2786
2787 for (j = 0; j < 4; j++) {
2788 border_color_table[4 * sctx->border_color_offset + j] =
2789 util_le32_to_cpu(rstates[i]->border_color[j]);
2790 }
2791
2792 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2793 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2794 }
2795
2796 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2797 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2798 }
2799 }
2800 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2801
2802 if (border_color_table) {
2803 uint64_t va_offset =
2804 r600_resource_va(&sctx->screen->b.b,
2805 (void*)sctx->border_color_table);
2806
2807 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2808 if (sctx->b.chip_class >= CIK)
2809 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2810 sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf);
2811 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ);
2812 }
2813
2814 memcpy(samplers->samplers, states, sizeof(void*) * count);
2815
2816 out:
2817 samplers->n_samplers = count;
2818 return pm4;
2819 }
2820
2821 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2822 {
2823 struct si_context *sctx = (struct si_context *)ctx;
2824 struct si_pm4_state *pm4;
2825
2826 pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_VERTEX],
2827 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2828 si_pm4_set_state(sctx, vs_sampler, pm4);
2829 }
2830
2831 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2832 {
2833 struct si_context *sctx = (struct si_context *)ctx;
2834 struct si_pm4_state *pm4;
2835
2836 pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_FRAGMENT],
2837 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2838 si_pm4_set_state(sctx, ps_sampler, pm4);
2839 }
2840
2841
2842 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2843 unsigned start, unsigned count,
2844 void **states)
2845 {
2846 assert(start == 0);
2847
2848 switch (shader) {
2849 case PIPE_SHADER_VERTEX:
2850 si_bind_vs_sampler_states(ctx, count, states);
2851 break;
2852 case PIPE_SHADER_FRAGMENT:
2853 si_bind_ps_sampler_states(ctx, count, states);
2854 break;
2855 default:
2856 ;
2857 }
2858 }
2859
2860
2861
2862 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2863 {
2864 struct si_context *sctx = (struct si_context *)ctx;
2865 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2866 uint16_t mask = sample_mask;
2867
2868 if (pm4 == NULL)
2869 return;
2870
2871 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2872 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2873
2874 si_pm4_set_state(sctx, sample_mask, pm4);
2875 }
2876
2877 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2878 {
2879 free(state);
2880 }
2881
2882 /*
2883 * Vertex elements & buffers
2884 */
2885
2886 static void *si_create_vertex_elements(struct pipe_context *ctx,
2887 unsigned count,
2888 const struct pipe_vertex_element *elements)
2889 {
2890 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2891 int i;
2892
2893 assert(count < PIPE_MAX_ATTRIBS);
2894 if (!v)
2895 return NULL;
2896
2897 v->count = count;
2898 for (i = 0; i < count; ++i) {
2899 const struct util_format_description *desc;
2900 unsigned data_format, num_format;
2901 int first_non_void;
2902
2903 desc = util_format_description(elements[i].src_format);
2904 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2905 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2906 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2907
2908 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2909 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2910 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2911 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2912 S_008F0C_NUM_FORMAT(num_format) |
2913 S_008F0C_DATA_FORMAT(data_format);
2914 }
2915 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2916
2917 return v;
2918 }
2919
2920 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2921 {
2922 struct si_context *sctx = (struct si_context *)ctx;
2923 struct si_vertex_element *v = (struct si_vertex_element*)state;
2924
2925 sctx->vertex_elements = v;
2926 }
2927
2928 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2929 {
2930 struct si_context *sctx = (struct si_context *)ctx;
2931
2932 if (sctx->vertex_elements == state)
2933 sctx->vertex_elements = NULL;
2934 FREE(state);
2935 }
2936
2937 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2938 const struct pipe_vertex_buffer *buffers)
2939 {
2940 struct si_context *sctx = (struct si_context *)ctx;
2941
2942 util_set_vertex_buffers_count(sctx->vertex_buffer, &sctx->nr_vertex_buffers, buffers, start_slot, count);
2943 }
2944
2945 static void si_set_index_buffer(struct pipe_context *ctx,
2946 const struct pipe_index_buffer *ib)
2947 {
2948 struct si_context *sctx = (struct si_context *)ctx;
2949
2950 if (ib) {
2951 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2952 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2953 } else {
2954 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2955 }
2956 }
2957
2958 /*
2959 * Misc
2960 */
2961 static void si_set_polygon_stipple(struct pipe_context *ctx,
2962 const struct pipe_poly_stipple *state)
2963 {
2964 }
2965
2966 static void si_texture_barrier(struct pipe_context *ctx)
2967 {
2968 struct si_context *sctx = (struct si_context *)ctx;
2969
2970 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2971 R600_CONTEXT_FLUSH_AND_INV_CB;
2972 }
2973
2974 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2975 {
2976 struct pipe_blend_state blend;
2977
2978 memset(&blend, 0, sizeof(blend));
2979 blend.independent_blend_enable = true;
2980 blend.rt[0].colormask = 0xf;
2981 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2982 }
2983
2984 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2985 struct pipe_resource *texture,
2986 const struct pipe_surface *surf_tmpl)
2987 {
2988 struct r600_texture *rtex = (struct r600_texture*)texture;
2989 struct si_surface *surface = CALLOC_STRUCT(si_surface);
2990 unsigned level = surf_tmpl->u.tex.level;
2991
2992 if (surface == NULL)
2993 return NULL;
2994
2995 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2996 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2997
2998 pipe_reference_init(&surface->base.reference, 1);
2999 pipe_resource_reference(&surface->base.texture, texture);
3000 surface->base.context = pipe;
3001 surface->base.format = surf_tmpl->format;
3002 surface->base.width = rtex->surface.level[level].npix_x;
3003 surface->base.height = rtex->surface.level[level].npix_y;
3004 surface->base.texture = texture;
3005 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
3006 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
3007 surface->base.u.tex.level = level;
3008
3009 return &surface->base;
3010 }
3011
3012 static void r600_surface_destroy(struct pipe_context *pipe,
3013 struct pipe_surface *surface)
3014 {
3015 pipe_resource_reference(&surface->texture, NULL);
3016 FREE(surface);
3017 }
3018
3019 static boolean si_dma_copy(struct pipe_context *ctx,
3020 struct pipe_resource *dst,
3021 unsigned dst_level,
3022 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3023 struct pipe_resource *src,
3024 unsigned src_level,
3025 const struct pipe_box *src_box)
3026 {
3027 /* XXX implement this or share evergreen_dma_blit with r600g */
3028 return FALSE;
3029 }
3030
3031 void si_init_state_functions(struct si_context *sctx)
3032 {
3033 int i;
3034
3035 sctx->b.b.create_blend_state = si_create_blend_state;
3036 sctx->b.b.bind_blend_state = si_bind_blend_state;
3037 sctx->b.b.delete_blend_state = si_delete_blend_state;
3038 sctx->b.b.set_blend_color = si_set_blend_color;
3039
3040 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3041 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3042 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3043
3044 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3045 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3046 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3047
3048 for (i = 0; i < 8; i++) {
3049 sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i);
3050 sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i);
3051 sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i);
3052 }
3053 sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0);
3054 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3055 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3056
3057 sctx->b.b.set_clip_state = si_set_clip_state;
3058 sctx->b.b.set_scissor_states = si_set_scissor_states;
3059 sctx->b.b.set_viewport_states = si_set_viewport_states;
3060 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3061
3062 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3063 sctx->b.b.get_sample_position = si_get_sample_position;
3064
3065 sctx->b.b.create_vs_state = si_create_vs_state;
3066 sctx->b.b.create_fs_state = si_create_fs_state;
3067 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3068 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3069 sctx->b.b.delete_vs_state = si_delete_vs_shader;
3070 sctx->b.b.delete_fs_state = si_delete_ps_shader;
3071
3072 sctx->b.b.create_sampler_state = si_create_sampler_state;
3073 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3074 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3075
3076 sctx->b.b.create_sampler_view = si_create_sampler_view;
3077 sctx->b.b.set_sampler_views = si_set_sampler_views;
3078 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3079
3080 sctx->b.b.set_sample_mask = si_set_sample_mask;
3081
3082 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3083 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3084 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3085 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3086 sctx->b.b.set_index_buffer = si_set_index_buffer;
3087
3088 sctx->b.b.texture_barrier = si_texture_barrier;
3089 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3090 sctx->b.b.create_surface = r600_create_surface;
3091 sctx->b.b.surface_destroy = r600_surface_destroy;
3092 sctx->b.dma_copy = si_dma_copy;
3093
3094 sctx->b.b.draw_vbo = si_draw_vbo;
3095 }
3096
3097 void si_init_config(struct si_context *sctx)
3098 {
3099 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
3100
3101 if (pm4 == NULL)
3102 return;
3103
3104 si_cmd_context_control(pm4);
3105
3106 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3107
3108 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3109 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3110 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3111 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3112 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3113 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3114 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3115 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3116 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3117 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3118 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3119 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3120 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3121 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3122 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3123 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3124 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3125 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3126 if (sctx->b.chip_class == SI) {
3127 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3128 S_028AA8_SWITCH_ON_EOP(1) |
3129 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3130 S_028AA8_PRIMGROUP_SIZE(63));
3131 }
3132 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3133 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3134 if (sctx->b.chip_class < CIK)
3135 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3136 S_008A14_CLIP_VTX_REORDER_ENA(1));
3137
3138 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3139 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3140 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3141
3142 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3143
3144 if (sctx->b.chip_class >= CIK) {
3145 switch (sctx->screen->b.family) {
3146 case CHIP_BONAIRE:
3147 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3148 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3149 break;
3150 case CHIP_HAWAII:
3151 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3152 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3153 break;
3154 case CHIP_KAVERI:
3155 /* XXX todo */
3156 case CHIP_KABINI:
3157 /* XXX todo */
3158 default:
3159 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3160 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3161 break;
3162 }
3163 } else {
3164 switch (sctx->screen->b.family) {
3165 case CHIP_TAHITI:
3166 case CHIP_PITCAIRN:
3167 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3168 break;
3169 case CHIP_VERDE:
3170 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3171 break;
3172 case CHIP_OLAND:
3173 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3174 break;
3175 case CHIP_HAINAN:
3176 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3177 break;
3178 default:
3179 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3180 break;
3181 }
3182 }
3183
3184 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3185 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3186 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3187 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3188 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3189 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3190 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3191
3192 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3193 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3194 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3195 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3196 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3197 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3198 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3199 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3200 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3201 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3202 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3203 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3204 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3205 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3206 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3207 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3208 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3209 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3210 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3211 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3212 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3213 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3214
3215 if (sctx->b.chip_class >= CIK) {
3216 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3217 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3218 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3219 }
3220
3221 si_pm4_set_state(sctx, init, pm4);
3222 }