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radeonsi/gfx10: set more registers and fields
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
86 unsigned i;
87
88 if (blend)
89 cb_target_mask &= blend->cb_target_mask;
90
91 /* Avoid a hang that happens when dual source blending is enabled
92 * but there is not enough color outputs. This is undefined behavior,
93 * so disable color writes completely.
94 *
95 * Reproducible with Unigine Heaven 4.0 and drirc missing.
96 */
97 if (blend && blend->dual_src_blend &&
98 sctx->ps_shader.cso &&
99 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
100 cb_target_mask = 0;
101
102 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
103 * I think we don't have to do anything between IBs.
104 */
105 if (sctx->screen->dfsm_allowed &&
106 sctx->last_cb_target_mask != cb_target_mask) {
107 sctx->last_cb_target_mask = cb_target_mask;
108
109 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
110 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
111 }
112
113 unsigned initial_cdw = cs->current.cdw;
114 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
115 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
116
117 if (sctx->chip_class >= GFX8) {
118 /* DCC MSAA workaround for blending.
119 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
120 * COMBINER_DISABLE, but that would be more complicated.
121 */
122 bool oc_disable = blend &&
123 blend->blend_enable_4bit & cb_target_mask &&
124 sctx->framebuffer.nr_samples >= 2;
125 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
126
127 radeon_opt_set_context_reg(
128 sctx, R_028424_CB_DCC_CONTROL,
129 SI_TRACKED_CB_DCC_CONTROL,
130 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
131 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
132 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
133 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
134 }
135
136 /* RB+ register settings. */
137 if (sctx->screen->rbplus_allowed) {
138 unsigned spi_shader_col_format =
139 sctx->ps_shader.cso ?
140 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
141 unsigned sx_ps_downconvert = 0;
142 unsigned sx_blend_opt_epsilon = 0;
143 unsigned sx_blend_opt_control = 0;
144
145 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
146 struct si_surface *surf =
147 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
148 unsigned format, swap, spi_format, colormask;
149 bool has_alpha, has_rgb;
150
151 if (!surf) {
152 /* If the color buffer is not set, the driver sets 32_R
153 * as the SPI color format, because the hw doesn't allow
154 * holes between color outputs, so also set this to
155 * enable RB+.
156 */
157 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
158 continue;
159 }
160
161 format = G_028C70_FORMAT(surf->cb_color_info);
162 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
163 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
164 colormask = (cb_target_mask >> (i * 4)) & 0xf;
165
166 /* Set if RGB and A are present. */
167 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
168
169 if (format == V_028C70_COLOR_8 ||
170 format == V_028C70_COLOR_16 ||
171 format == V_028C70_COLOR_32)
172 has_rgb = !has_alpha;
173 else
174 has_rgb = true;
175
176 /* Check the colormask and export format. */
177 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
178 has_rgb = false;
179 if (!(colormask & PIPE_MASK_A))
180 has_alpha = false;
181
182 if (spi_format == V_028714_SPI_SHADER_ZERO) {
183 has_rgb = false;
184 has_alpha = false;
185 }
186
187 /* Disable value checking for disabled channels. */
188 if (!has_rgb)
189 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
190 if (!has_alpha)
191 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
192
193 /* Enable down-conversion for 32bpp and smaller formats. */
194 switch (format) {
195 case V_028C70_COLOR_8:
196 case V_028C70_COLOR_8_8:
197 case V_028C70_COLOR_8_8_8_8:
198 /* For 1 and 2-channel formats, use the superset thereof. */
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
200 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
201 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
202 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
203 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
204 }
205 break;
206
207 case V_028C70_COLOR_5_6_5:
208 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
210 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
211 }
212 break;
213
214 case V_028C70_COLOR_1_5_5_5:
215 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
216 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
217 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
218 }
219 break;
220
221 case V_028C70_COLOR_4_4_4_4:
222 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
224 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
225 }
226 break;
227
228 case V_028C70_COLOR_32:
229 if (swap == V_028C70_SWAP_STD &&
230 spi_format == V_028714_SPI_SHADER_32_R)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
232 else if (swap == V_028C70_SWAP_ALT_REV &&
233 spi_format == V_028714_SPI_SHADER_32_AR)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
235 break;
236
237 case V_028C70_COLOR_16:
238 case V_028C70_COLOR_16_16:
239 /* For 1-channel formats, use the superset thereof. */
240 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
241 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
242 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
243 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
244 if (swap == V_028C70_SWAP_STD ||
245 swap == V_028C70_SWAP_STD_REV)
246 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
247 else
248 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
249 }
250 break;
251
252 case V_028C70_COLOR_10_11_11:
253 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
254 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
255 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
256 }
257 break;
258
259 case V_028C70_COLOR_2_10_10_10:
260 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
261 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
262 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
263 }
264 break;
265 }
266 }
267
268 /* If there are no color outputs, the first color export is
269 * always enabled as 32_R, so also set this to enable RB+.
270 */
271 if (!sx_ps_downconvert)
272 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
273
274 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
275 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
276 SI_TRACKED_SX_PS_DOWNCONVERT,
277 sx_ps_downconvert, sx_blend_opt_epsilon,
278 sx_blend_opt_control);
279 }
280 if (initial_cdw != cs->current.cdw)
281 sctx->context_roll = true;
282 }
283
284 /*
285 * Blender functions
286 */
287
288 static uint32_t si_translate_blend_function(int blend_func)
289 {
290 switch (blend_func) {
291 case PIPE_BLEND_ADD:
292 return V_028780_COMB_DST_PLUS_SRC;
293 case PIPE_BLEND_SUBTRACT:
294 return V_028780_COMB_SRC_MINUS_DST;
295 case PIPE_BLEND_REVERSE_SUBTRACT:
296 return V_028780_COMB_DST_MINUS_SRC;
297 case PIPE_BLEND_MIN:
298 return V_028780_COMB_MIN_DST_SRC;
299 case PIPE_BLEND_MAX:
300 return V_028780_COMB_MAX_DST_SRC;
301 default:
302 PRINT_ERR("Unknown blend function %d\n", blend_func);
303 assert(0);
304 break;
305 }
306 return 0;
307 }
308
309 static uint32_t si_translate_blend_factor(int blend_fact)
310 {
311 switch (blend_fact) {
312 case PIPE_BLENDFACTOR_ONE:
313 return V_028780_BLEND_ONE;
314 case PIPE_BLENDFACTOR_SRC_COLOR:
315 return V_028780_BLEND_SRC_COLOR;
316 case PIPE_BLENDFACTOR_SRC_ALPHA:
317 return V_028780_BLEND_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_DST_ALPHA:
319 return V_028780_BLEND_DST_ALPHA;
320 case PIPE_BLENDFACTOR_DST_COLOR:
321 return V_028780_BLEND_DST_COLOR;
322 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
323 return V_028780_BLEND_SRC_ALPHA_SATURATE;
324 case PIPE_BLENDFACTOR_CONST_COLOR:
325 return V_028780_BLEND_CONSTANT_COLOR;
326 case PIPE_BLENDFACTOR_CONST_ALPHA:
327 return V_028780_BLEND_CONSTANT_ALPHA;
328 case PIPE_BLENDFACTOR_ZERO:
329 return V_028780_BLEND_ZERO;
330 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
331 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
334 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
335 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
336 case PIPE_BLENDFACTOR_INV_DST_COLOR:
337 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
338 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
339 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
340 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
341 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
342 case PIPE_BLENDFACTOR_SRC1_COLOR:
343 return V_028780_BLEND_SRC1_COLOR;
344 case PIPE_BLENDFACTOR_SRC1_ALPHA:
345 return V_028780_BLEND_SRC1_ALPHA;
346 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
347 return V_028780_BLEND_INV_SRC1_COLOR;
348 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
349 return V_028780_BLEND_INV_SRC1_ALPHA;
350 default:
351 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
352 assert(0);
353 break;
354 }
355 return 0;
356 }
357
358 static uint32_t si_translate_blend_opt_function(int blend_func)
359 {
360 switch (blend_func) {
361 case PIPE_BLEND_ADD:
362 return V_028760_OPT_COMB_ADD;
363 case PIPE_BLEND_SUBTRACT:
364 return V_028760_OPT_COMB_SUBTRACT;
365 case PIPE_BLEND_REVERSE_SUBTRACT:
366 return V_028760_OPT_COMB_REVSUBTRACT;
367 case PIPE_BLEND_MIN:
368 return V_028760_OPT_COMB_MIN;
369 case PIPE_BLEND_MAX:
370 return V_028760_OPT_COMB_MAX;
371 default:
372 return V_028760_OPT_COMB_BLEND_DISABLED;
373 }
374 }
375
376 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
377 {
378 switch (blend_fact) {
379 case PIPE_BLENDFACTOR_ZERO:
380 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
381 case PIPE_BLENDFACTOR_ONE:
382 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
383 case PIPE_BLENDFACTOR_SRC_COLOR:
384 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
385 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
386 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
387 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
388 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
389 case PIPE_BLENDFACTOR_SRC_ALPHA:
390 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
391 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
392 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
393 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
394 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
395 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
396 default:
397 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
398 }
399 }
400
401 static void si_blend_check_commutativity(struct si_screen *sscreen,
402 struct si_state_blend *blend,
403 enum pipe_blend_func func,
404 enum pipe_blendfactor src,
405 enum pipe_blendfactor dst,
406 unsigned chanmask)
407 {
408 /* Src factor is allowed when it does not depend on Dst */
409 static const uint32_t src_allowed =
410 (1u << PIPE_BLENDFACTOR_ONE) |
411 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
412 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
413 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
414 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
415 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
417 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
418 (1u << PIPE_BLENDFACTOR_ZERO) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
420 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
421 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
422 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
423 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
424 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
425
426 if (dst == PIPE_BLENDFACTOR_ONE &&
427 (src_allowed & (1u << src))) {
428 /* Addition is commutative, but floating point addition isn't
429 * associative: subtle changes can be introduced via different
430 * rounding.
431 *
432 * Out-of-order is also non-deterministic, which means that
433 * this breaks OpenGL invariance requirements. So only enable
434 * out-of-order additive blending if explicitly allowed by a
435 * setting.
436 */
437 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
438 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
439 blend->commutative_4bit |= chanmask;
440 }
441 }
442
443 /**
444 * Get rid of DST in the blend factors by commuting the operands:
445 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
446 */
447 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
448 unsigned *dst_factor, unsigned expected_dst,
449 unsigned replacement_src)
450 {
451 if (*src_factor == expected_dst &&
452 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
453 *src_factor = PIPE_BLENDFACTOR_ZERO;
454 *dst_factor = replacement_src;
455
456 /* Commuting the operands requires reversing subtractions. */
457 if (*func == PIPE_BLEND_SUBTRACT)
458 *func = PIPE_BLEND_REVERSE_SUBTRACT;
459 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
460 *func = PIPE_BLEND_SUBTRACT;
461 }
462 }
463
464 static bool si_blend_factor_uses_dst(unsigned factor)
465 {
466 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
467 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
468 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
469 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
470 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
471 }
472
473 static void *si_create_blend_state_mode(struct pipe_context *ctx,
474 const struct pipe_blend_state *state,
475 unsigned mode)
476 {
477 struct si_context *sctx = (struct si_context*)ctx;
478 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
479 struct si_pm4_state *pm4 = &blend->pm4;
480 uint32_t sx_mrt_blend_opt[8] = {0};
481 uint32_t color_control = 0;
482
483 if (!blend)
484 return NULL;
485
486 blend->alpha_to_coverage = state->alpha_to_coverage;
487 blend->alpha_to_one = state->alpha_to_one;
488 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
489 blend->logicop_enable = state->logicop_enable;
490
491 if (state->logicop_enable) {
492 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
493 } else {
494 color_control |= S_028808_ROP3(0xcc);
495 }
496
497 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
498 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
499 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
500 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
501 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
502 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
503 S_028B70_OFFSET_ROUND(1));
504
505 if (state->alpha_to_coverage)
506 blend->need_src_alpha_4bit |= 0xf;
507
508 blend->cb_target_mask = 0;
509 blend->cb_target_enabled_4bit = 0;
510
511 for (int i = 0; i < 8; i++) {
512 /* state->rt entries > 0 only written if independent blending */
513 const int j = state->independent_blend_enable ? i : 0;
514
515 unsigned eqRGB = state->rt[j].rgb_func;
516 unsigned srcRGB = state->rt[j].rgb_src_factor;
517 unsigned dstRGB = state->rt[j].rgb_dst_factor;
518 unsigned eqA = state->rt[j].alpha_func;
519 unsigned srcA = state->rt[j].alpha_src_factor;
520 unsigned dstA = state->rt[j].alpha_dst_factor;
521
522 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
523 unsigned blend_cntl = 0;
524
525 sx_mrt_blend_opt[i] =
526 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
527 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
528
529 /* Only set dual source blending for MRT0 to avoid a hang. */
530 if (i >= 1 && blend->dual_src_blend) {
531 /* Vulkan does this for dual source blending. */
532 if (i == 1)
533 blend_cntl |= S_028780_ENABLE(1);
534
535 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
536 continue;
537 }
538
539 /* Only addition and subtraction equations are supported with
540 * dual source blending.
541 */
542 if (blend->dual_src_blend &&
543 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
544 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
545 assert(!"Unsupported equation for dual source blending");
546 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
547 continue;
548 }
549
550 /* cb_render_state will disable unused ones */
551 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
552 if (state->rt[j].colormask)
553 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
554
555 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
556 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
557 continue;
558 }
559
560 si_blend_check_commutativity(sctx->screen, blend,
561 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
562 si_blend_check_commutativity(sctx->screen, blend,
563 eqA, srcA, dstA, 0x8 << (4 * i));
564
565 /* Blending optimizations for RB+.
566 * These transformations don't change the behavior.
567 *
568 * First, get rid of DST in the blend factors:
569 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
570 */
571 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
572 PIPE_BLENDFACTOR_DST_COLOR,
573 PIPE_BLENDFACTOR_SRC_COLOR);
574 si_blend_remove_dst(&eqA, &srcA, &dstA,
575 PIPE_BLENDFACTOR_DST_COLOR,
576 PIPE_BLENDFACTOR_SRC_COLOR);
577 si_blend_remove_dst(&eqA, &srcA, &dstA,
578 PIPE_BLENDFACTOR_DST_ALPHA,
579 PIPE_BLENDFACTOR_SRC_ALPHA);
580
581 /* Look up the ideal settings from tables. */
582 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
583 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
584 srcA_opt = si_translate_blend_opt_factor(srcA, true);
585 dstA_opt = si_translate_blend_opt_factor(dstA, true);
586
587 /* Handle interdependencies. */
588 if (si_blend_factor_uses_dst(srcRGB))
589 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
590 if (si_blend_factor_uses_dst(srcA))
591 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
592
593 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
594 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
595 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
596 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
597 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
598
599 /* Set the final value. */
600 sx_mrt_blend_opt[i] =
601 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
602 S_028760_COLOR_DST_OPT(dstRGB_opt) |
603 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
604 S_028760_ALPHA_SRC_OPT(srcA_opt) |
605 S_028760_ALPHA_DST_OPT(dstA_opt) |
606 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
607
608 /* Set blend state. */
609 blend_cntl |= S_028780_ENABLE(1);
610 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
611 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
612 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
613
614 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
615 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
616 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
617 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
618 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
619 }
620 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
621
622 blend->blend_enable_4bit |= 0xfu << (i * 4);
623
624 /* This is only important for formats without alpha. */
625 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
626 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
627 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
628 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
629 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
630 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
631 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
632 }
633
634 if (blend->cb_target_mask) {
635 color_control |= S_028808_MODE(mode);
636 } else {
637 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
638 }
639
640 if (sctx->screen->rbplus_allowed) {
641 /* Disable RB+ blend optimizations for dual source blending.
642 * Vulkan does this.
643 */
644 if (blend->dual_src_blend) {
645 for (int i = 0; i < 8; i++) {
646 sx_mrt_blend_opt[i] =
647 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
648 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
649 }
650 }
651
652 for (int i = 0; i < 8; i++)
653 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
654 sx_mrt_blend_opt[i]);
655
656 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
657 if (blend->dual_src_blend || state->logicop_enable ||
658 mode == V_028808_CB_RESOLVE)
659 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
660 }
661
662 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
663 return blend;
664 }
665
666 static void *si_create_blend_state(struct pipe_context *ctx,
667 const struct pipe_blend_state *state)
668 {
669 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
670 }
671
672 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
673 {
674 struct si_context *sctx = (struct si_context *)ctx;
675 struct si_state_blend *old_blend = sctx->queued.named.blend;
676 struct si_state_blend *blend = (struct si_state_blend *)state;
677
678 if (!state)
679 return;
680
681 si_pm4_bind_state(sctx, blend, state);
682
683 if (!old_blend ||
684 old_blend->cb_target_mask != blend->cb_target_mask ||
685 old_blend->dual_src_blend != blend->dual_src_blend ||
686 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
687 sctx->framebuffer.nr_samples >= 2 &&
688 sctx->screen->dcc_msaa_allowed))
689 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
690
691 if (!old_blend ||
692 old_blend->cb_target_mask != blend->cb_target_mask ||
693 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
694 old_blend->alpha_to_one != blend->alpha_to_one ||
695 old_blend->dual_src_blend != blend->dual_src_blend ||
696 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
697 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
698 sctx->do_update_shaders = true;
699
700 if (sctx->screen->dpbb_allowed &&
701 (!old_blend ||
702 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
703 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
704 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
705 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
706
707 if (sctx->screen->has_out_of_order_rast &&
708 (!old_blend ||
709 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
710 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
711 old_blend->commutative_4bit != blend->commutative_4bit ||
712 old_blend->logicop_enable != blend->logicop_enable)))
713 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
714 }
715
716 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
717 {
718 struct si_context *sctx = (struct si_context *)ctx;
719 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
720 }
721
722 static void si_set_blend_color(struct pipe_context *ctx,
723 const struct pipe_blend_color *state)
724 {
725 struct si_context *sctx = (struct si_context *)ctx;
726 static const struct pipe_blend_color zeros;
727
728 sctx->blend_color.state = *state;
729 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
730 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
731 }
732
733 static void si_emit_blend_color(struct si_context *sctx)
734 {
735 struct radeon_cmdbuf *cs = sctx->gfx_cs;
736
737 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
738 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
739 }
740
741 /*
742 * Clipping
743 */
744
745 static void si_set_clip_state(struct pipe_context *ctx,
746 const struct pipe_clip_state *state)
747 {
748 struct si_context *sctx = (struct si_context *)ctx;
749 struct pipe_constant_buffer cb;
750 static const struct pipe_clip_state zeros;
751
752 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
753 return;
754
755 sctx->clip_state.state = *state;
756 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
757 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
758
759 cb.buffer = NULL;
760 cb.user_buffer = state->ucp;
761 cb.buffer_offset = 0;
762 cb.buffer_size = 4*4*8;
763 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
764 pipe_resource_reference(&cb.buffer, NULL);
765 }
766
767 static void si_emit_clip_state(struct si_context *sctx)
768 {
769 struct radeon_cmdbuf *cs = sctx->gfx_cs;
770
771 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
772 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
773 }
774
775 static void si_emit_clip_regs(struct si_context *sctx)
776 {
777 struct si_shader *vs = si_get_vs_state(sctx);
778 struct si_shader_selector *vs_sel = vs->selector;
779 struct tgsi_shader_info *info = &vs_sel->info;
780 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
781 unsigned window_space =
782 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
783 unsigned clipdist_mask = vs_sel->clipdist_mask;
784 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
785 unsigned culldist_mask = vs_sel->culldist_mask;
786 unsigned total_mask;
787
788 if (vs->key.opt.clip_disable) {
789 assert(!info->culldist_writemask);
790 clipdist_mask = 0;
791 culldist_mask = 0;
792 }
793 total_mask = clipdist_mask | culldist_mask;
794
795 /* Clip distances on points have no effect, so need to be implemented
796 * as cull distances. This applies for the clipvertex case as well.
797 *
798 * Setting this for primitives other than points should have no adverse
799 * effects.
800 */
801 clipdist_mask &= rs->clip_plane_enable;
802 culldist_mask |= clipdist_mask;
803
804 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
805 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
806 SI_TRACKED_PA_CL_VS_OUT_CNTL,
807 vs_sel->pa_cl_vs_out_cntl |
808 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
809 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
810 clipdist_mask | (culldist_mask << 8));
811 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
812 SI_TRACKED_PA_CL_CLIP_CNTL,
813 rs->pa_cl_clip_cntl |
814 ucp_mask |
815 S_028810_CLIP_DISABLE(window_space));
816
817 if (initial_cdw != sctx->gfx_cs->current.cdw)
818 sctx->context_roll = true;
819 }
820
821 /*
822 * inferred state between framebuffer and rasterizer
823 */
824 static void si_update_poly_offset_state(struct si_context *sctx)
825 {
826 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
827
828 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
829 si_pm4_bind_state(sctx, poly_offset, NULL);
830 return;
831 }
832
833 /* Use the user format, not db_render_format, so that the polygon
834 * offset behaves as expected by applications.
835 */
836 switch (sctx->framebuffer.state.zsbuf->texture->format) {
837 case PIPE_FORMAT_Z16_UNORM:
838 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
839 break;
840 default: /* 24-bit */
841 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
842 break;
843 case PIPE_FORMAT_Z32_FLOAT:
844 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
845 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
846 break;
847 }
848 }
849
850 /*
851 * Rasterizer
852 */
853
854 static uint32_t si_translate_fill(uint32_t func)
855 {
856 switch(func) {
857 case PIPE_POLYGON_MODE_FILL:
858 return V_028814_X_DRAW_TRIANGLES;
859 case PIPE_POLYGON_MODE_LINE:
860 return V_028814_X_DRAW_LINES;
861 case PIPE_POLYGON_MODE_POINT:
862 return V_028814_X_DRAW_POINTS;
863 default:
864 assert(0);
865 return V_028814_X_DRAW_POINTS;
866 }
867 }
868
869 static void *si_create_rs_state(struct pipe_context *ctx,
870 const struct pipe_rasterizer_state *state)
871 {
872 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
873 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
874 struct si_pm4_state *pm4 = &rs->pm4;
875 unsigned tmp, i;
876 float psize_min, psize_max;
877
878 if (!rs) {
879 return NULL;
880 }
881
882 if (!state->front_ccw) {
883 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
884 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
885 } else {
886 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
887 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
888 }
889 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
890 rs->provoking_vertex_first = state->flatshade_first;
891 rs->scissor_enable = state->scissor;
892 rs->clip_halfz = state->clip_halfz;
893 rs->two_side = state->light_twoside;
894 rs->multisample_enable = state->multisample;
895 rs->force_persample_interp = state->force_persample_interp;
896 rs->clip_plane_enable = state->clip_plane_enable;
897 rs->half_pixel_center = state->half_pixel_center;
898 rs->line_stipple_enable = state->line_stipple_enable;
899 rs->poly_stipple_enable = state->poly_stipple_enable;
900 rs->line_smooth = state->line_smooth;
901 rs->line_width = state->line_width;
902 rs->poly_smooth = state->poly_smooth;
903 rs->uses_poly_offset = state->offset_point || state->offset_line ||
904 state->offset_tri;
905 rs->clamp_fragment_color = state->clamp_fragment_color;
906 rs->clamp_vertex_color = state->clamp_vertex_color;
907 rs->flatshade = state->flatshade;
908 rs->flatshade_first = state->flatshade_first;
909 rs->sprite_coord_enable = state->sprite_coord_enable;
910 rs->rasterizer_discard = state->rasterizer_discard;
911 rs->pa_sc_line_stipple = state->line_stipple_enable ?
912 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
913 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
914 rs->pa_cl_clip_cntl =
915 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
916 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
917 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
918 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
919 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
920
921 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
922 S_0286D4_FLAT_SHADE_ENA(1) |
923 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
924 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
925 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
926 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
927 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
928 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
929
930 /* point size 12.4 fixed point */
931 tmp = (unsigned)(state->point_size * 8.0);
932 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
933
934 if (state->point_size_per_vertex) {
935 psize_min = util_get_min_point_size(state);
936 psize_max = SI_MAX_POINT_SIZE;
937 } else {
938 /* Force the point size to be as if the vertex output was disabled. */
939 psize_min = state->point_size;
940 psize_max = state->point_size;
941 }
942 rs->max_point_size = psize_max;
943
944 /* Divide by two, because 0.5 = 1 pixel. */
945 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
946 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
947 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
948
949 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
950 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
951 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
952 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
953 S_028A48_MSAA_ENABLE(state->multisample ||
954 state->poly_smooth ||
955 state->line_smooth) |
956 S_028A48_VPORT_SCISSOR_ENABLE(1) |
957 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
958
959 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
960 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
961 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
962 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
963 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
964 S_028814_FACE(!state->front_ccw) |
965 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
966 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
967 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
968 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
969 state->fill_back != PIPE_POLYGON_MODE_FILL) |
970 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
971 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
972
973 if (!rs->uses_poly_offset)
974 return rs;
975
976 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
977 if (!rs->pm4_poly_offset) {
978 FREE(rs);
979 return NULL;
980 }
981
982 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
983 for (i = 0; i < 3; i++) {
984 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
985 float offset_units = state->offset_units;
986 float offset_scale = state->offset_scale * 16.0f;
987 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
988
989 if (!state->offset_units_unscaled) {
990 switch (i) {
991 case 0: /* 16-bit zbuffer */
992 offset_units *= 4.0f;
993 pa_su_poly_offset_db_fmt_cntl =
994 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
995 break;
996 case 1: /* 24-bit zbuffer */
997 offset_units *= 2.0f;
998 pa_su_poly_offset_db_fmt_cntl =
999 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1000 break;
1001 case 2: /* 32-bit zbuffer */
1002 offset_units *= 1.0f;
1003 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1004 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1005 break;
1006 }
1007 }
1008
1009 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1010 fui(offset_scale));
1011 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1012 fui(offset_units));
1013 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1014 fui(offset_scale));
1015 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1016 fui(offset_units));
1017 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1018 pa_su_poly_offset_db_fmt_cntl);
1019 }
1020
1021 return rs;
1022 }
1023
1024 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1025 {
1026 struct si_context *sctx = (struct si_context *)ctx;
1027 struct si_state_rasterizer *old_rs =
1028 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1029 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1030
1031 if (!state)
1032 return;
1033
1034 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1035 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1036
1037 /* Update the small primitive filter workaround if necessary. */
1038 if (sctx->screen->has_msaa_sample_loc_bug &&
1039 sctx->framebuffer.nr_samples > 1)
1040 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1041 }
1042
1043 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1044 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1045
1046 si_pm4_bind_state(sctx, rasterizer, rs);
1047 si_update_poly_offset_state(sctx);
1048
1049 if (!old_rs ||
1050 old_rs->scissor_enable != rs->scissor_enable)
1051 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1052
1053 if (!old_rs ||
1054 old_rs->line_width != rs->line_width ||
1055 old_rs->max_point_size != rs->max_point_size ||
1056 old_rs->half_pixel_center != rs->half_pixel_center)
1057 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1058
1059 if (!old_rs ||
1060 old_rs->clip_halfz != rs->clip_halfz)
1061 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1062
1063 if (!old_rs ||
1064 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1065 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1066 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1067
1068 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1069 rs->line_stipple_enable;
1070
1071 if (!old_rs ||
1072 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1073 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1074 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1075 old_rs->flatshade != rs->flatshade ||
1076 old_rs->two_side != rs->two_side ||
1077 old_rs->multisample_enable != rs->multisample_enable ||
1078 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1079 old_rs->poly_smooth != rs->poly_smooth ||
1080 old_rs->line_smooth != rs->line_smooth ||
1081 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1082 old_rs->force_persample_interp != rs->force_persample_interp)
1083 sctx->do_update_shaders = true;
1084 }
1085
1086 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1087 {
1088 struct si_context *sctx = (struct si_context *)ctx;
1089 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1090
1091 if (sctx->queued.named.rasterizer == state)
1092 si_pm4_bind_state(sctx, poly_offset, NULL);
1093
1094 FREE(rs->pm4_poly_offset);
1095 si_pm4_delete_state(sctx, rasterizer, rs);
1096 }
1097
1098 /*
1099 * infeered state between dsa and stencil ref
1100 */
1101 static void si_emit_stencil_ref(struct si_context *sctx)
1102 {
1103 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1104 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1105 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1106
1107 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1108 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1109 S_028430_STENCILMASK(dsa->valuemask[0]) |
1110 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1111 S_028430_STENCILOPVAL(1));
1112 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1113 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1114 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1115 S_028434_STENCILOPVAL_BF(1));
1116 }
1117
1118 static void si_set_stencil_ref(struct pipe_context *ctx,
1119 const struct pipe_stencil_ref *state)
1120 {
1121 struct si_context *sctx = (struct si_context *)ctx;
1122
1123 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1124 return;
1125
1126 sctx->stencil_ref.state = *state;
1127 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1128 }
1129
1130
1131 /*
1132 * DSA
1133 */
1134
1135 static uint32_t si_translate_stencil_op(int s_op)
1136 {
1137 switch (s_op) {
1138 case PIPE_STENCIL_OP_KEEP:
1139 return V_02842C_STENCIL_KEEP;
1140 case PIPE_STENCIL_OP_ZERO:
1141 return V_02842C_STENCIL_ZERO;
1142 case PIPE_STENCIL_OP_REPLACE:
1143 return V_02842C_STENCIL_REPLACE_TEST;
1144 case PIPE_STENCIL_OP_INCR:
1145 return V_02842C_STENCIL_ADD_CLAMP;
1146 case PIPE_STENCIL_OP_DECR:
1147 return V_02842C_STENCIL_SUB_CLAMP;
1148 case PIPE_STENCIL_OP_INCR_WRAP:
1149 return V_02842C_STENCIL_ADD_WRAP;
1150 case PIPE_STENCIL_OP_DECR_WRAP:
1151 return V_02842C_STENCIL_SUB_WRAP;
1152 case PIPE_STENCIL_OP_INVERT:
1153 return V_02842C_STENCIL_INVERT;
1154 default:
1155 PRINT_ERR("Unknown stencil op %d", s_op);
1156 assert(0);
1157 break;
1158 }
1159 return 0;
1160 }
1161
1162 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1163 {
1164 return s->enabled && s->writemask &&
1165 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1166 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1167 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1168 }
1169
1170 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1171 {
1172 /* REPLACE is normally order invariant, except when the stencil
1173 * reference value is written by the fragment shader. Tracking this
1174 * interaction does not seem worth the effort, so be conservative. */
1175 return op != PIPE_STENCIL_OP_INCR &&
1176 op != PIPE_STENCIL_OP_DECR &&
1177 op != PIPE_STENCIL_OP_REPLACE;
1178 }
1179
1180 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1181 * invariant in the sense that the set of passing fragments as well as the
1182 * final stencil buffer result does not depend on the order of fragments. */
1183 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1184 {
1185 return !state->enabled || !state->writemask ||
1186 /* The following assumes that Z writes are disabled. */
1187 (state->func == PIPE_FUNC_ALWAYS &&
1188 si_order_invariant_stencil_op(state->zpass_op) &&
1189 si_order_invariant_stencil_op(state->zfail_op)) ||
1190 (state->func == PIPE_FUNC_NEVER &&
1191 si_order_invariant_stencil_op(state->fail_op));
1192 }
1193
1194 static void *si_create_dsa_state(struct pipe_context *ctx,
1195 const struct pipe_depth_stencil_alpha_state *state)
1196 {
1197 struct si_context *sctx = (struct si_context *)ctx;
1198 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1199 struct si_pm4_state *pm4 = &dsa->pm4;
1200 unsigned db_depth_control;
1201 uint32_t db_stencil_control = 0;
1202
1203 if (!dsa) {
1204 return NULL;
1205 }
1206
1207 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1208 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1209 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1210 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1211
1212 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1213 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1214 S_028800_ZFUNC(state->depth.func) |
1215 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1216
1217 /* stencil */
1218 if (state->stencil[0].enabled) {
1219 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1220 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1221 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1222 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1223 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1224
1225 if (state->stencil[1].enabled) {
1226 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1227 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1228 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1229 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1230 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1231 }
1232 }
1233
1234 /* alpha */
1235 if (state->alpha.enabled) {
1236 dsa->alpha_func = state->alpha.func;
1237
1238 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1239 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1240 } else {
1241 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1242 }
1243
1244 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1245 if (state->stencil[0].enabled)
1246 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1247 if (state->depth.bounds_test) {
1248 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1249 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1250 }
1251
1252 dsa->depth_enabled = state->depth.enabled;
1253 dsa->depth_write_enabled = state->depth.enabled &&
1254 state->depth.writemask;
1255 dsa->stencil_enabled = state->stencil[0].enabled;
1256 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1257 (si_dsa_writes_stencil(&state->stencil[0]) ||
1258 si_dsa_writes_stencil(&state->stencil[1]));
1259 dsa->db_can_write = dsa->depth_write_enabled ||
1260 dsa->stencil_write_enabled;
1261
1262 bool zfunc_is_ordered =
1263 state->depth.func == PIPE_FUNC_NEVER ||
1264 state->depth.func == PIPE_FUNC_LESS ||
1265 state->depth.func == PIPE_FUNC_LEQUAL ||
1266 state->depth.func == PIPE_FUNC_GREATER ||
1267 state->depth.func == PIPE_FUNC_GEQUAL;
1268
1269 bool nozwrite_and_order_invariant_stencil =
1270 !dsa->db_can_write ||
1271 (!dsa->depth_write_enabled &&
1272 si_order_invariant_stencil_state(&state->stencil[0]) &&
1273 si_order_invariant_stencil_state(&state->stencil[1]));
1274
1275 dsa->order_invariance[1].zs =
1276 nozwrite_and_order_invariant_stencil ||
1277 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1278 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1279
1280 dsa->order_invariance[1].pass_set =
1281 nozwrite_and_order_invariant_stencil ||
1282 (!dsa->stencil_write_enabled &&
1283 (state->depth.func == PIPE_FUNC_ALWAYS ||
1284 state->depth.func == PIPE_FUNC_NEVER));
1285 dsa->order_invariance[0].pass_set =
1286 !dsa->depth_write_enabled ||
1287 (state->depth.func == PIPE_FUNC_ALWAYS ||
1288 state->depth.func == PIPE_FUNC_NEVER);
1289
1290 dsa->order_invariance[1].pass_last =
1291 sctx->screen->assume_no_z_fights &&
1292 !dsa->stencil_write_enabled &&
1293 dsa->depth_write_enabled && zfunc_is_ordered;
1294 dsa->order_invariance[0].pass_last =
1295 sctx->screen->assume_no_z_fights &&
1296 dsa->depth_write_enabled && zfunc_is_ordered;
1297
1298 return dsa;
1299 }
1300
1301 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1302 {
1303 struct si_context *sctx = (struct si_context *)ctx;
1304 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1305 struct si_state_dsa *dsa = state;
1306
1307 if (!state)
1308 return;
1309
1310 si_pm4_bind_state(sctx, dsa, dsa);
1311
1312 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1313 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1314 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1315 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1316 }
1317
1318 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1319 sctx->do_update_shaders = true;
1320
1321 if (sctx->screen->dpbb_allowed &&
1322 (!old_dsa ||
1323 (old_dsa->depth_enabled != dsa->depth_enabled ||
1324 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1325 old_dsa->db_can_write != dsa->db_can_write)))
1326 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1327
1328 if (sctx->screen->has_out_of_order_rast &&
1329 (!old_dsa ||
1330 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1331 sizeof(old_dsa->order_invariance))))
1332 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1333 }
1334
1335 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1336 {
1337 struct si_context *sctx = (struct si_context *)ctx;
1338 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1339 }
1340
1341 static void *si_create_db_flush_dsa(struct si_context *sctx)
1342 {
1343 struct pipe_depth_stencil_alpha_state dsa = {};
1344
1345 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1346 }
1347
1348 /* DB RENDER STATE */
1349
1350 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1351 {
1352 struct si_context *sctx = (struct si_context*)ctx;
1353
1354 /* Pipeline stat & streamout queries. */
1355 if (enable) {
1356 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1357 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1358 } else {
1359 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1360 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1361 }
1362
1363 /* Occlusion queries. */
1364 if (sctx->occlusion_queries_disabled != !enable) {
1365 sctx->occlusion_queries_disabled = !enable;
1366 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1367 }
1368 }
1369
1370 void si_set_occlusion_query_state(struct si_context *sctx,
1371 bool old_perfect_enable)
1372 {
1373 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1374
1375 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1376
1377 if (perfect_enable != old_perfect_enable)
1378 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1379 }
1380
1381 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1382 {
1383 st->saved_compute = sctx->cs_shader_state.program;
1384
1385 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1386 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1387
1388 st->saved_ssbo_writable_mask = 0;
1389
1390 for (unsigned i = 0; i < 3; i++) {
1391 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1392 (1u << si_get_shaderbuf_slot(i)))
1393 st->saved_ssbo_writable_mask |= 1 << i;
1394 }
1395 }
1396
1397 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1398 {
1399 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1400
1401 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1402 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1403
1404 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1405 st->saved_ssbo_writable_mask);
1406 for (unsigned i = 0; i < 3; ++i)
1407 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1408 }
1409
1410 static void si_emit_db_render_state(struct si_context *sctx)
1411 {
1412 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1413 unsigned db_shader_control, db_render_control, db_count_control;
1414 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1415
1416 /* DB_RENDER_CONTROL */
1417 if (sctx->dbcb_depth_copy_enabled ||
1418 sctx->dbcb_stencil_copy_enabled) {
1419 db_render_control =
1420 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1421 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1422 S_028000_COPY_CENTROID(1) |
1423 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1424 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1425 db_render_control =
1426 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1427 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1428 } else {
1429 db_render_control =
1430 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1431 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1432 }
1433
1434 /* DB_COUNT_CONTROL (occlusion queries) */
1435 if (sctx->num_occlusion_queries > 0 &&
1436 !sctx->occlusion_queries_disabled) {
1437 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1438 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1439
1440 if (sctx->chip_class >= GFX7) {
1441 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1442
1443 /* Stoney doesn't increment occlusion query counters
1444 * if the sample rate is 16x. Use 8x sample rate instead.
1445 */
1446 if (sctx->family == CHIP_STONEY)
1447 log_sample_rate = MIN2(log_sample_rate, 3);
1448
1449 db_count_control =
1450 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1451 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1452 S_028004_SAMPLE_RATE(log_sample_rate) |
1453 S_028004_ZPASS_ENABLE(1) |
1454 S_028004_SLICE_EVEN_ENABLE(1) |
1455 S_028004_SLICE_ODD_ENABLE(1);
1456 } else {
1457 db_count_control =
1458 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1459 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1460 }
1461 } else {
1462 /* Disable occlusion queries. */
1463 if (sctx->chip_class >= GFX7) {
1464 db_count_control = 0;
1465 } else {
1466 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1467 }
1468 }
1469
1470 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1471 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1472 db_count_control);
1473
1474 /* DB_RENDER_OVERRIDE2 */
1475 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1476 SI_TRACKED_DB_RENDER_OVERRIDE2,
1477 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1478 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1479 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1480
1481 db_shader_control = sctx->ps_db_shader_control;
1482
1483 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1484 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1485 db_shader_control &= C_02880C_Z_ORDER;
1486 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1487 }
1488
1489 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1490 if (!rs->multisample_enable)
1491 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1492
1493 if (sctx->screen->has_rbplus &&
1494 !sctx->screen->rbplus_allowed)
1495 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1496
1497 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1498 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1499
1500 if (initial_cdw != sctx->gfx_cs->current.cdw)
1501 sctx->context_roll = true;
1502 }
1503
1504 /*
1505 * format translation
1506 */
1507 static uint32_t si_translate_colorformat(enum pipe_format format)
1508 {
1509 const struct util_format_description *desc = util_format_description(format);
1510 if (!desc)
1511 return V_028C70_COLOR_INVALID;
1512
1513 #define HAS_SIZE(x,y,z,w) \
1514 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1515 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1516
1517 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1518 return V_028C70_COLOR_10_11_11;
1519
1520 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1521 return V_028C70_COLOR_INVALID;
1522
1523 /* hw cannot support mixed formats (except depth/stencil, since
1524 * stencil is not written to). */
1525 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1526 return V_028C70_COLOR_INVALID;
1527
1528 switch (desc->nr_channels) {
1529 case 1:
1530 switch (desc->channel[0].size) {
1531 case 8:
1532 return V_028C70_COLOR_8;
1533 case 16:
1534 return V_028C70_COLOR_16;
1535 case 32:
1536 return V_028C70_COLOR_32;
1537 }
1538 break;
1539 case 2:
1540 if (desc->channel[0].size == desc->channel[1].size) {
1541 switch (desc->channel[0].size) {
1542 case 8:
1543 return V_028C70_COLOR_8_8;
1544 case 16:
1545 return V_028C70_COLOR_16_16;
1546 case 32:
1547 return V_028C70_COLOR_32_32;
1548 }
1549 } else if (HAS_SIZE(8,24,0,0)) {
1550 return V_028C70_COLOR_24_8;
1551 } else if (HAS_SIZE(24,8,0,0)) {
1552 return V_028C70_COLOR_8_24;
1553 }
1554 break;
1555 case 3:
1556 if (HAS_SIZE(5,6,5,0)) {
1557 return V_028C70_COLOR_5_6_5;
1558 } else if (HAS_SIZE(32,8,24,0)) {
1559 return V_028C70_COLOR_X24_8_32_FLOAT;
1560 }
1561 break;
1562 case 4:
1563 if (desc->channel[0].size == desc->channel[1].size &&
1564 desc->channel[0].size == desc->channel[2].size &&
1565 desc->channel[0].size == desc->channel[3].size) {
1566 switch (desc->channel[0].size) {
1567 case 4:
1568 return V_028C70_COLOR_4_4_4_4;
1569 case 8:
1570 return V_028C70_COLOR_8_8_8_8;
1571 case 16:
1572 return V_028C70_COLOR_16_16_16_16;
1573 case 32:
1574 return V_028C70_COLOR_32_32_32_32;
1575 }
1576 } else if (HAS_SIZE(5,5,5,1)) {
1577 return V_028C70_COLOR_1_5_5_5;
1578 } else if (HAS_SIZE(1,5,5,5)) {
1579 return V_028C70_COLOR_5_5_5_1;
1580 } else if (HAS_SIZE(10,10,10,2)) {
1581 return V_028C70_COLOR_2_10_10_10;
1582 }
1583 break;
1584 }
1585 return V_028C70_COLOR_INVALID;
1586 }
1587
1588 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1589 {
1590 if (SI_BIG_ENDIAN) {
1591 switch(colorformat) {
1592 /* 8-bit buffers. */
1593 case V_028C70_COLOR_8:
1594 return V_028C70_ENDIAN_NONE;
1595
1596 /* 16-bit buffers. */
1597 case V_028C70_COLOR_5_6_5:
1598 case V_028C70_COLOR_1_5_5_5:
1599 case V_028C70_COLOR_4_4_4_4:
1600 case V_028C70_COLOR_16:
1601 case V_028C70_COLOR_8_8:
1602 return V_028C70_ENDIAN_8IN16;
1603
1604 /* 32-bit buffers. */
1605 case V_028C70_COLOR_8_8_8_8:
1606 case V_028C70_COLOR_2_10_10_10:
1607 case V_028C70_COLOR_8_24:
1608 case V_028C70_COLOR_24_8:
1609 case V_028C70_COLOR_16_16:
1610 return V_028C70_ENDIAN_8IN32;
1611
1612 /* 64-bit buffers. */
1613 case V_028C70_COLOR_16_16_16_16:
1614 return V_028C70_ENDIAN_8IN16;
1615
1616 case V_028C70_COLOR_32_32:
1617 return V_028C70_ENDIAN_8IN32;
1618
1619 /* 128-bit buffers. */
1620 case V_028C70_COLOR_32_32_32_32:
1621 return V_028C70_ENDIAN_8IN32;
1622 default:
1623 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1624 }
1625 } else {
1626 return V_028C70_ENDIAN_NONE;
1627 }
1628 }
1629
1630 static uint32_t si_translate_dbformat(enum pipe_format format)
1631 {
1632 switch (format) {
1633 case PIPE_FORMAT_Z16_UNORM:
1634 return V_028040_Z_16;
1635 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1636 case PIPE_FORMAT_X8Z24_UNORM:
1637 case PIPE_FORMAT_Z24X8_UNORM:
1638 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1639 return V_028040_Z_24; /* deprecated on AMD GCN */
1640 case PIPE_FORMAT_Z32_FLOAT:
1641 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1642 return V_028040_Z_32_FLOAT;
1643 default:
1644 return V_028040_Z_INVALID;
1645 }
1646 }
1647
1648 /*
1649 * Texture translation
1650 */
1651
1652 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1653 enum pipe_format format,
1654 const struct util_format_description *desc,
1655 int first_non_void)
1656 {
1657 struct si_screen *sscreen = (struct si_screen*)screen;
1658 bool uniform = true;
1659 int i;
1660
1661 assert(sscreen->info.chip_class <= GFX9);
1662
1663 /* Colorspace (return non-RGB formats directly). */
1664 switch (desc->colorspace) {
1665 /* Depth stencil formats */
1666 case UTIL_FORMAT_COLORSPACE_ZS:
1667 switch (format) {
1668 case PIPE_FORMAT_Z16_UNORM:
1669 return V_008F14_IMG_DATA_FORMAT_16;
1670 case PIPE_FORMAT_X24S8_UINT:
1671 case PIPE_FORMAT_S8X24_UINT:
1672 /*
1673 * Implemented as an 8_8_8_8 data format to fix texture
1674 * gathers in stencil sampling. This affects at least
1675 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1676 */
1677 if (sscreen->info.chip_class <= GFX8)
1678 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1679
1680 if (format == PIPE_FORMAT_X24S8_UINT)
1681 return V_008F14_IMG_DATA_FORMAT_8_24;
1682 else
1683 return V_008F14_IMG_DATA_FORMAT_24_8;
1684 case PIPE_FORMAT_Z24X8_UNORM:
1685 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1686 return V_008F14_IMG_DATA_FORMAT_8_24;
1687 case PIPE_FORMAT_X8Z24_UNORM:
1688 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1689 return V_008F14_IMG_DATA_FORMAT_24_8;
1690 case PIPE_FORMAT_S8_UINT:
1691 return V_008F14_IMG_DATA_FORMAT_8;
1692 case PIPE_FORMAT_Z32_FLOAT:
1693 return V_008F14_IMG_DATA_FORMAT_32;
1694 case PIPE_FORMAT_X32_S8X24_UINT:
1695 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1696 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1697 default:
1698 goto out_unknown;
1699 }
1700
1701 case UTIL_FORMAT_COLORSPACE_YUV:
1702 goto out_unknown; /* TODO */
1703
1704 case UTIL_FORMAT_COLORSPACE_SRGB:
1705 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1706 goto out_unknown;
1707 break;
1708
1709 default:
1710 break;
1711 }
1712
1713 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1714 if (!sscreen->info.has_format_bc1_through_bc7)
1715 goto out_unknown;
1716
1717 switch (format) {
1718 case PIPE_FORMAT_RGTC1_SNORM:
1719 case PIPE_FORMAT_LATC1_SNORM:
1720 case PIPE_FORMAT_RGTC1_UNORM:
1721 case PIPE_FORMAT_LATC1_UNORM:
1722 return V_008F14_IMG_DATA_FORMAT_BC4;
1723 case PIPE_FORMAT_RGTC2_SNORM:
1724 case PIPE_FORMAT_LATC2_SNORM:
1725 case PIPE_FORMAT_RGTC2_UNORM:
1726 case PIPE_FORMAT_LATC2_UNORM:
1727 return V_008F14_IMG_DATA_FORMAT_BC5;
1728 default:
1729 goto out_unknown;
1730 }
1731 }
1732
1733 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1734 (sscreen->info.family == CHIP_STONEY ||
1735 sscreen->info.family == CHIP_VEGA10 ||
1736 sscreen->info.family == CHIP_RAVEN)) {
1737 switch (format) {
1738 case PIPE_FORMAT_ETC1_RGB8:
1739 case PIPE_FORMAT_ETC2_RGB8:
1740 case PIPE_FORMAT_ETC2_SRGB8:
1741 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1742 case PIPE_FORMAT_ETC2_RGB8A1:
1743 case PIPE_FORMAT_ETC2_SRGB8A1:
1744 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1745 case PIPE_FORMAT_ETC2_RGBA8:
1746 case PIPE_FORMAT_ETC2_SRGBA8:
1747 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1748 case PIPE_FORMAT_ETC2_R11_UNORM:
1749 case PIPE_FORMAT_ETC2_R11_SNORM:
1750 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1751 case PIPE_FORMAT_ETC2_RG11_UNORM:
1752 case PIPE_FORMAT_ETC2_RG11_SNORM:
1753 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1754 default:
1755 goto out_unknown;
1756 }
1757 }
1758
1759 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1760 if (!sscreen->info.has_format_bc1_through_bc7)
1761 goto out_unknown;
1762
1763 switch (format) {
1764 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1765 case PIPE_FORMAT_BPTC_SRGBA:
1766 return V_008F14_IMG_DATA_FORMAT_BC7;
1767 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1768 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1769 return V_008F14_IMG_DATA_FORMAT_BC6;
1770 default:
1771 goto out_unknown;
1772 }
1773 }
1774
1775 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1776 switch (format) {
1777 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1778 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1779 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1780 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1781 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1782 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1783 default:
1784 goto out_unknown;
1785 }
1786 }
1787
1788 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1789 if (!sscreen->info.has_format_bc1_through_bc7)
1790 goto out_unknown;
1791
1792 switch (format) {
1793 case PIPE_FORMAT_DXT1_RGB:
1794 case PIPE_FORMAT_DXT1_RGBA:
1795 case PIPE_FORMAT_DXT1_SRGB:
1796 case PIPE_FORMAT_DXT1_SRGBA:
1797 return V_008F14_IMG_DATA_FORMAT_BC1;
1798 case PIPE_FORMAT_DXT3_RGBA:
1799 case PIPE_FORMAT_DXT3_SRGBA:
1800 return V_008F14_IMG_DATA_FORMAT_BC2;
1801 case PIPE_FORMAT_DXT5_RGBA:
1802 case PIPE_FORMAT_DXT5_SRGBA:
1803 return V_008F14_IMG_DATA_FORMAT_BC3;
1804 default:
1805 goto out_unknown;
1806 }
1807 }
1808
1809 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1810 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1811 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1812 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1813 }
1814
1815 /* R8G8Bx_SNORM - TODO CxV8U8 */
1816
1817 /* hw cannot support mixed formats (except depth/stencil, since only
1818 * depth is read).*/
1819 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1820 goto out_unknown;
1821
1822 /* See whether the components are of the same size. */
1823 for (i = 1; i < desc->nr_channels; i++) {
1824 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1825 }
1826
1827 /* Non-uniform formats. */
1828 if (!uniform) {
1829 switch(desc->nr_channels) {
1830 case 3:
1831 if (desc->channel[0].size == 5 &&
1832 desc->channel[1].size == 6 &&
1833 desc->channel[2].size == 5) {
1834 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1835 }
1836 goto out_unknown;
1837 case 4:
1838 if (desc->channel[0].size == 5 &&
1839 desc->channel[1].size == 5 &&
1840 desc->channel[2].size == 5 &&
1841 desc->channel[3].size == 1) {
1842 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1843 }
1844 if (desc->channel[0].size == 1 &&
1845 desc->channel[1].size == 5 &&
1846 desc->channel[2].size == 5 &&
1847 desc->channel[3].size == 5) {
1848 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1849 }
1850 if (desc->channel[0].size == 10 &&
1851 desc->channel[1].size == 10 &&
1852 desc->channel[2].size == 10 &&
1853 desc->channel[3].size == 2) {
1854 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1855 }
1856 goto out_unknown;
1857 }
1858 goto out_unknown;
1859 }
1860
1861 if (first_non_void < 0 || first_non_void > 3)
1862 goto out_unknown;
1863
1864 /* uniform formats */
1865 switch (desc->channel[first_non_void].size) {
1866 case 4:
1867 switch (desc->nr_channels) {
1868 #if 0 /* Not supported for render targets */
1869 case 2:
1870 return V_008F14_IMG_DATA_FORMAT_4_4;
1871 #endif
1872 case 4:
1873 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1874 }
1875 break;
1876 case 8:
1877 switch (desc->nr_channels) {
1878 case 1:
1879 return V_008F14_IMG_DATA_FORMAT_8;
1880 case 2:
1881 return V_008F14_IMG_DATA_FORMAT_8_8;
1882 case 4:
1883 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1884 }
1885 break;
1886 case 16:
1887 switch (desc->nr_channels) {
1888 case 1:
1889 return V_008F14_IMG_DATA_FORMAT_16;
1890 case 2:
1891 return V_008F14_IMG_DATA_FORMAT_16_16;
1892 case 4:
1893 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1894 }
1895 break;
1896 case 32:
1897 switch (desc->nr_channels) {
1898 case 1:
1899 return V_008F14_IMG_DATA_FORMAT_32;
1900 case 2:
1901 return V_008F14_IMG_DATA_FORMAT_32_32;
1902 #if 0 /* Not supported for render targets */
1903 case 3:
1904 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1905 #endif
1906 case 4:
1907 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1908 }
1909 }
1910
1911 out_unknown:
1912 return ~0;
1913 }
1914
1915 static unsigned si_tex_wrap(unsigned wrap)
1916 {
1917 switch (wrap) {
1918 default:
1919 case PIPE_TEX_WRAP_REPEAT:
1920 return V_008F30_SQ_TEX_WRAP;
1921 case PIPE_TEX_WRAP_CLAMP:
1922 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1923 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1924 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1925 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1926 return V_008F30_SQ_TEX_CLAMP_BORDER;
1927 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1928 return V_008F30_SQ_TEX_MIRROR;
1929 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1930 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1931 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1932 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1933 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1934 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1935 }
1936 }
1937
1938 static unsigned si_tex_mipfilter(unsigned filter)
1939 {
1940 switch (filter) {
1941 case PIPE_TEX_MIPFILTER_NEAREST:
1942 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1943 case PIPE_TEX_MIPFILTER_LINEAR:
1944 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1945 default:
1946 case PIPE_TEX_MIPFILTER_NONE:
1947 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1948 }
1949 }
1950
1951 static unsigned si_tex_compare(unsigned compare)
1952 {
1953 switch (compare) {
1954 default:
1955 case PIPE_FUNC_NEVER:
1956 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1957 case PIPE_FUNC_LESS:
1958 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1959 case PIPE_FUNC_EQUAL:
1960 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1961 case PIPE_FUNC_LEQUAL:
1962 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1963 case PIPE_FUNC_GREATER:
1964 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1965 case PIPE_FUNC_NOTEQUAL:
1966 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1967 case PIPE_FUNC_GEQUAL:
1968 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1969 case PIPE_FUNC_ALWAYS:
1970 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1971 }
1972 }
1973
1974 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1975 unsigned view_target, unsigned nr_samples)
1976 {
1977 unsigned res_target = tex->buffer.b.b.target;
1978
1979 if (view_target == PIPE_TEXTURE_CUBE ||
1980 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1981 res_target = view_target;
1982 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1983 else if (res_target == PIPE_TEXTURE_CUBE ||
1984 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1985 res_target = PIPE_TEXTURE_2D_ARRAY;
1986
1987 /* GFX9 allocates 1D textures as 2D. */
1988 if ((res_target == PIPE_TEXTURE_1D ||
1989 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1990 sscreen->info.chip_class == GFX9 &&
1991 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1992 if (res_target == PIPE_TEXTURE_1D)
1993 res_target = PIPE_TEXTURE_2D;
1994 else
1995 res_target = PIPE_TEXTURE_2D_ARRAY;
1996 }
1997
1998 switch (res_target) {
1999 default:
2000 case PIPE_TEXTURE_1D:
2001 return V_008F1C_SQ_RSRC_IMG_1D;
2002 case PIPE_TEXTURE_1D_ARRAY:
2003 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2004 case PIPE_TEXTURE_2D:
2005 case PIPE_TEXTURE_RECT:
2006 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
2007 V_008F1C_SQ_RSRC_IMG_2D;
2008 case PIPE_TEXTURE_2D_ARRAY:
2009 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
2010 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2011 case PIPE_TEXTURE_3D:
2012 return V_008F1C_SQ_RSRC_IMG_3D;
2013 case PIPE_TEXTURE_CUBE:
2014 case PIPE_TEXTURE_CUBE_ARRAY:
2015 return V_008F1C_SQ_RSRC_IMG_CUBE;
2016 }
2017 }
2018
2019 /*
2020 * Format support testing
2021 */
2022
2023 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2024 {
2025 struct si_screen *sscreen = (struct si_screen *)screen;
2026
2027 if (sscreen->info.chip_class >= GFX10) {
2028 const struct gfx10_format *fmt = &gfx10_format_table[format];
2029 if (!fmt->img_format || fmt->buffers_only)
2030 return false;
2031 return true;
2032 }
2033
2034 const struct util_format_description *desc = util_format_description(format);
2035 if (!desc)
2036 return false;
2037
2038 return si_translate_texformat(screen, format, desc,
2039 util_format_get_first_non_void_channel(format)) != ~0U;
2040 }
2041
2042 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2043 const struct util_format_description *desc,
2044 int first_non_void)
2045 {
2046 int i;
2047
2048 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2049
2050 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2051 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2052
2053 assert(first_non_void >= 0);
2054
2055 if (desc->nr_channels == 4 &&
2056 desc->channel[0].size == 10 &&
2057 desc->channel[1].size == 10 &&
2058 desc->channel[2].size == 10 &&
2059 desc->channel[3].size == 2)
2060 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2061
2062 /* See whether the components are of the same size. */
2063 for (i = 0; i < desc->nr_channels; i++) {
2064 if (desc->channel[first_non_void].size != desc->channel[i].size)
2065 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2066 }
2067
2068 switch (desc->channel[first_non_void].size) {
2069 case 8:
2070 switch (desc->nr_channels) {
2071 case 1:
2072 case 3: /* 3 loads */
2073 return V_008F0C_BUF_DATA_FORMAT_8;
2074 case 2:
2075 return V_008F0C_BUF_DATA_FORMAT_8_8;
2076 case 4:
2077 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2078 }
2079 break;
2080 case 16:
2081 switch (desc->nr_channels) {
2082 case 1:
2083 case 3: /* 3 loads */
2084 return V_008F0C_BUF_DATA_FORMAT_16;
2085 case 2:
2086 return V_008F0C_BUF_DATA_FORMAT_16_16;
2087 case 4:
2088 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2089 }
2090 break;
2091 case 32:
2092 switch (desc->nr_channels) {
2093 case 1:
2094 return V_008F0C_BUF_DATA_FORMAT_32;
2095 case 2:
2096 return V_008F0C_BUF_DATA_FORMAT_32_32;
2097 case 3:
2098 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2099 case 4:
2100 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2101 }
2102 break;
2103 case 64:
2104 /* Legacy double formats. */
2105 switch (desc->nr_channels) {
2106 case 1: /* 1 load */
2107 return V_008F0C_BUF_DATA_FORMAT_32_32;
2108 case 2: /* 1 load */
2109 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2110 case 3: /* 3 loads */
2111 return V_008F0C_BUF_DATA_FORMAT_32_32;
2112 case 4: /* 2 loads */
2113 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2114 }
2115 break;
2116 }
2117
2118 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2119 }
2120
2121 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2122 const struct util_format_description *desc,
2123 int first_non_void)
2124 {
2125 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2126
2127 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2128 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2129
2130 assert(first_non_void >= 0);
2131
2132 switch (desc->channel[first_non_void].type) {
2133 case UTIL_FORMAT_TYPE_SIGNED:
2134 case UTIL_FORMAT_TYPE_FIXED:
2135 if (desc->channel[first_non_void].size >= 32 ||
2136 desc->channel[first_non_void].pure_integer)
2137 return V_008F0C_BUF_NUM_FORMAT_SINT;
2138 else if (desc->channel[first_non_void].normalized)
2139 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2140 else
2141 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2142 break;
2143 case UTIL_FORMAT_TYPE_UNSIGNED:
2144 if (desc->channel[first_non_void].size >= 32 ||
2145 desc->channel[first_non_void].pure_integer)
2146 return V_008F0C_BUF_NUM_FORMAT_UINT;
2147 else if (desc->channel[first_non_void].normalized)
2148 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2149 else
2150 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2151 break;
2152 case UTIL_FORMAT_TYPE_FLOAT:
2153 default:
2154 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2155 }
2156 }
2157
2158 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2159 enum pipe_format format,
2160 unsigned usage)
2161 {
2162 struct si_screen *sscreen = (struct si_screen *)screen;
2163 const struct util_format_description *desc;
2164 int first_non_void;
2165 unsigned data_format;
2166
2167 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2168 PIPE_BIND_SAMPLER_VIEW |
2169 PIPE_BIND_VERTEX_BUFFER)) == 0);
2170
2171 desc = util_format_description(format);
2172 if (!desc)
2173 return 0;
2174
2175 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2176 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2177 * for read-only access (with caveats surrounding bounds checks), but
2178 * obviously fails for write access which we have to implement for
2179 * shader images. Luckily, OpenGL doesn't expect this to be supported
2180 * anyway, and so the only impact is on PBO uploads / downloads, which
2181 * shouldn't be expected to be fast for GL_RGB anyway.
2182 */
2183 if (desc->block.bits == 3 * 8 ||
2184 desc->block.bits == 3 * 16) {
2185 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2186 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2187 if (!usage)
2188 return 0;
2189 }
2190 }
2191
2192 if (sscreen->info.chip_class >= GFX10) {
2193 const struct gfx10_format *fmt = &gfx10_format_table[format];
2194 if (!fmt->img_format || fmt->img_format >= 128)
2195 return 0;
2196 return usage;
2197 }
2198
2199 first_non_void = util_format_get_first_non_void_channel(format);
2200 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2201 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2202 return 0;
2203
2204 return usage;
2205 }
2206
2207 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2208 {
2209 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2210 si_translate_colorswap(format, false) != ~0U;
2211 }
2212
2213 static bool si_is_zs_format_supported(enum pipe_format format)
2214 {
2215 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2216 }
2217
2218 static boolean si_is_format_supported(struct pipe_screen *screen,
2219 enum pipe_format format,
2220 enum pipe_texture_target target,
2221 unsigned sample_count,
2222 unsigned storage_sample_count,
2223 unsigned usage)
2224 {
2225 struct si_screen *sscreen = (struct si_screen *)screen;
2226 unsigned retval = 0;
2227
2228 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2229 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2230 return false;
2231 }
2232
2233 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2234 return false;
2235
2236 if (sample_count > 1) {
2237 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2238 return false;
2239
2240 if (usage & PIPE_BIND_SHADER_IMAGE)
2241 return false;
2242
2243 /* Only power-of-two sample counts are supported. */
2244 if (!util_is_power_of_two_or_zero(sample_count) ||
2245 !util_is_power_of_two_or_zero(storage_sample_count))
2246 return false;
2247
2248 /* MSAA support without framebuffer attachments. */
2249 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2250 return true;
2251
2252 if (!sscreen->info.has_eqaa_surface_allocator ||
2253 util_format_is_depth_or_stencil(format)) {
2254 /* Color without EQAA or depth/stencil. */
2255 if (sample_count > 8 ||
2256 sample_count != storage_sample_count)
2257 return false;
2258 } else {
2259 /* Color with EQAA. */
2260 if (sample_count > 16 ||
2261 storage_sample_count > 8)
2262 return false;
2263 }
2264 }
2265
2266 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2267 PIPE_BIND_SHADER_IMAGE)) {
2268 if (target == PIPE_BUFFER) {
2269 retval |= si_is_vertex_format_supported(
2270 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2271 PIPE_BIND_SHADER_IMAGE));
2272 } else {
2273 if (si_is_sampler_format_supported(screen, format))
2274 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2275 PIPE_BIND_SHADER_IMAGE);
2276 }
2277 }
2278
2279 if ((usage & (PIPE_BIND_RENDER_TARGET |
2280 PIPE_BIND_DISPLAY_TARGET |
2281 PIPE_BIND_SCANOUT |
2282 PIPE_BIND_SHARED |
2283 PIPE_BIND_BLENDABLE)) &&
2284 si_is_colorbuffer_format_supported(format)) {
2285 retval |= usage &
2286 (PIPE_BIND_RENDER_TARGET |
2287 PIPE_BIND_DISPLAY_TARGET |
2288 PIPE_BIND_SCANOUT |
2289 PIPE_BIND_SHARED);
2290 if (!util_format_is_pure_integer(format) &&
2291 !util_format_is_depth_or_stencil(format))
2292 retval |= usage & PIPE_BIND_BLENDABLE;
2293 }
2294
2295 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2296 si_is_zs_format_supported(format)) {
2297 retval |= PIPE_BIND_DEPTH_STENCIL;
2298 }
2299
2300 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2301 retval |= si_is_vertex_format_supported(screen, format,
2302 PIPE_BIND_VERTEX_BUFFER);
2303 }
2304
2305 if ((usage & PIPE_BIND_LINEAR) &&
2306 !util_format_is_compressed(format) &&
2307 !(usage & PIPE_BIND_DEPTH_STENCIL))
2308 retval |= PIPE_BIND_LINEAR;
2309
2310 return retval == usage;
2311 }
2312
2313 /*
2314 * framebuffer handling
2315 */
2316
2317 static void si_choose_spi_color_formats(struct si_surface *surf,
2318 unsigned format, unsigned swap,
2319 unsigned ntype, bool is_depth)
2320 {
2321 /* Alpha is needed for alpha-to-coverage.
2322 * Blending may be with or without alpha.
2323 */
2324 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2325 unsigned alpha = 0; /* exports alpha, but may not support blending */
2326 unsigned blend = 0; /* supports blending, but may not export alpha */
2327 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2328
2329 /* Choose the SPI color formats. These are required values for RB+.
2330 * Other chips have multiple choices, though they are not necessarily better.
2331 */
2332 switch (format) {
2333 case V_028C70_COLOR_5_6_5:
2334 case V_028C70_COLOR_1_5_5_5:
2335 case V_028C70_COLOR_5_5_5_1:
2336 case V_028C70_COLOR_4_4_4_4:
2337 case V_028C70_COLOR_10_11_11:
2338 case V_028C70_COLOR_11_11_10:
2339 case V_028C70_COLOR_8:
2340 case V_028C70_COLOR_8_8:
2341 case V_028C70_COLOR_8_8_8_8:
2342 case V_028C70_COLOR_10_10_10_2:
2343 case V_028C70_COLOR_2_10_10_10:
2344 if (ntype == V_028C70_NUMBER_UINT)
2345 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2346 else if (ntype == V_028C70_NUMBER_SINT)
2347 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2348 else
2349 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2350 break;
2351
2352 case V_028C70_COLOR_16:
2353 case V_028C70_COLOR_16_16:
2354 case V_028C70_COLOR_16_16_16_16:
2355 if (ntype == V_028C70_NUMBER_UNORM ||
2356 ntype == V_028C70_NUMBER_SNORM) {
2357 /* UNORM16 and SNORM16 don't support blending */
2358 if (ntype == V_028C70_NUMBER_UNORM)
2359 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2360 else
2361 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2362
2363 /* Use 32 bits per channel for blending. */
2364 if (format == V_028C70_COLOR_16) {
2365 if (swap == V_028C70_SWAP_STD) { /* R */
2366 blend = V_028714_SPI_SHADER_32_R;
2367 blend_alpha = V_028714_SPI_SHADER_32_AR;
2368 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2369 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2370 else
2371 assert(0);
2372 } else if (format == V_028C70_COLOR_16_16) {
2373 if (swap == V_028C70_SWAP_STD) { /* RG */
2374 blend = V_028714_SPI_SHADER_32_GR;
2375 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2376 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2377 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2378 else
2379 assert(0);
2380 } else /* 16_16_16_16 */
2381 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2382 } else if (ntype == V_028C70_NUMBER_UINT)
2383 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2384 else if (ntype == V_028C70_NUMBER_SINT)
2385 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2386 else if (ntype == V_028C70_NUMBER_FLOAT)
2387 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2388 else
2389 assert(0);
2390 break;
2391
2392 case V_028C70_COLOR_32:
2393 if (swap == V_028C70_SWAP_STD) { /* R */
2394 blend = normal = V_028714_SPI_SHADER_32_R;
2395 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2396 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2397 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2398 else
2399 assert(0);
2400 break;
2401
2402 case V_028C70_COLOR_32_32:
2403 if (swap == V_028C70_SWAP_STD) { /* RG */
2404 blend = normal = V_028714_SPI_SHADER_32_GR;
2405 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2406 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2407 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2408 else
2409 assert(0);
2410 break;
2411
2412 case V_028C70_COLOR_32_32_32_32:
2413 case V_028C70_COLOR_8_24:
2414 case V_028C70_COLOR_24_8:
2415 case V_028C70_COLOR_X24_8_32_FLOAT:
2416 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2417 break;
2418
2419 default:
2420 assert(0);
2421 return;
2422 }
2423
2424 /* The DB->CB copy needs 32_ABGR. */
2425 if (is_depth)
2426 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2427
2428 surf->spi_shader_col_format = normal;
2429 surf->spi_shader_col_format_alpha = alpha;
2430 surf->spi_shader_col_format_blend = blend;
2431 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2432 }
2433
2434 static void si_initialize_color_surface(struct si_context *sctx,
2435 struct si_surface *surf)
2436 {
2437 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2438 unsigned color_info, color_attrib;
2439 unsigned format, swap, ntype, endian;
2440 const struct util_format_description *desc;
2441 int firstchan;
2442 unsigned blend_clamp = 0, blend_bypass = 0;
2443
2444 desc = util_format_description(surf->base.format);
2445 for (firstchan = 0; firstchan < 4; firstchan++) {
2446 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2447 break;
2448 }
2449 }
2450 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2451 ntype = V_028C70_NUMBER_FLOAT;
2452 } else {
2453 ntype = V_028C70_NUMBER_UNORM;
2454 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2455 ntype = V_028C70_NUMBER_SRGB;
2456 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2457 if (desc->channel[firstchan].pure_integer) {
2458 ntype = V_028C70_NUMBER_SINT;
2459 } else {
2460 assert(desc->channel[firstchan].normalized);
2461 ntype = V_028C70_NUMBER_SNORM;
2462 }
2463 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2464 if (desc->channel[firstchan].pure_integer) {
2465 ntype = V_028C70_NUMBER_UINT;
2466 } else {
2467 assert(desc->channel[firstchan].normalized);
2468 ntype = V_028C70_NUMBER_UNORM;
2469 }
2470 }
2471 }
2472
2473 format = si_translate_colorformat(surf->base.format);
2474 if (format == V_028C70_COLOR_INVALID) {
2475 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2476 }
2477 assert(format != V_028C70_COLOR_INVALID);
2478 swap = si_translate_colorswap(surf->base.format, false);
2479 endian = si_colorformat_endian_swap(format);
2480
2481 /* blend clamp should be set for all NORM/SRGB types */
2482 if (ntype == V_028C70_NUMBER_UNORM ||
2483 ntype == V_028C70_NUMBER_SNORM ||
2484 ntype == V_028C70_NUMBER_SRGB)
2485 blend_clamp = 1;
2486
2487 /* set blend bypass according to docs if SINT/UINT or
2488 8/24 COLOR variants */
2489 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2490 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2491 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2492 blend_clamp = 0;
2493 blend_bypass = 1;
2494 }
2495
2496 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2497 if (format == V_028C70_COLOR_8 ||
2498 format == V_028C70_COLOR_8_8 ||
2499 format == V_028C70_COLOR_8_8_8_8)
2500 surf->color_is_int8 = true;
2501 else if (format == V_028C70_COLOR_10_10_10_2 ||
2502 format == V_028C70_COLOR_2_10_10_10)
2503 surf->color_is_int10 = true;
2504 }
2505
2506 color_info = S_028C70_FORMAT(format) |
2507 S_028C70_COMP_SWAP(swap) |
2508 S_028C70_BLEND_CLAMP(blend_clamp) |
2509 S_028C70_BLEND_BYPASS(blend_bypass) |
2510 S_028C70_SIMPLE_FLOAT(1) |
2511 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2512 ntype != V_028C70_NUMBER_SNORM &&
2513 ntype != V_028C70_NUMBER_SRGB &&
2514 format != V_028C70_COLOR_8_24 &&
2515 format != V_028C70_COLOR_24_8) |
2516 S_028C70_NUMBER_TYPE(ntype) |
2517 S_028C70_ENDIAN(endian);
2518
2519 /* Intensity is implemented as Red, so treat it that way. */
2520 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2521 util_format_is_intensity(surf->base.format));
2522
2523 if (tex->buffer.b.b.nr_samples > 1) {
2524 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2525 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2526
2527 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2528 S_028C74_NUM_FRAGMENTS(log_fragments);
2529
2530 if (tex->fmask_offset) {
2531 color_info |= S_028C70_COMPRESSION(1);
2532 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2533
2534 if (sctx->chip_class == GFX6) {
2535 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2536 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2537 }
2538 }
2539 }
2540
2541 if (sctx->chip_class >= GFX10) {
2542 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2543
2544 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2545 64 for APU because all of our APUs to date use DIMMs which have
2546 a request granularity size of 64B while all other chips have a
2547 32B request size */
2548 if (!sctx->screen->info.has_dedicated_vram)
2549 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2550
2551 surf->cb_dcc_control =
2552 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2553 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
2554 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2555 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2556 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2557 } else if (sctx->chip_class >= GFX8) {
2558 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2559 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2560
2561 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2562 64 for APU because all of our APUs to date use DIMMs which have
2563 a request granularity size of 64B while all other chips have a
2564 32B request size */
2565 if (!sctx->screen->info.has_dedicated_vram)
2566 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2567
2568 if (tex->buffer.b.b.nr_storage_samples > 1) {
2569 if (tex->surface.bpe == 1)
2570 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2571 else if (tex->surface.bpe == 2)
2572 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2573 }
2574
2575 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2576 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2577 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2578 }
2579
2580 /* This must be set for fast clear to work without FMASK. */
2581 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2582 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2583 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2584 }
2585
2586 /* GFX10 field has the same base shift as the GFX6 field */
2587 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2588 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2589 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2590
2591 if (sctx->chip_class >= GFX10) {
2592 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2593
2594 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2595 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2596 S_028EE0_RESOURCE_LEVEL(1);
2597 } else if (sctx->chip_class == GFX9) {
2598 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2599 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2600 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2601 }
2602
2603 if (sctx->chip_class >= GFX9) {
2604 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2605 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2606 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2607 }
2608
2609 surf->cb_color_view = color_view;
2610 surf->cb_color_info = color_info;
2611 surf->cb_color_attrib = color_attrib;
2612
2613 /* Determine pixel shader export format */
2614 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2615
2616 surf->color_initialized = true;
2617 }
2618
2619 static void si_init_depth_surface(struct si_context *sctx,
2620 struct si_surface *surf)
2621 {
2622 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2623 unsigned level = surf->base.u.tex.level;
2624 unsigned format, stencil_format;
2625 uint32_t z_info, s_info;
2626
2627 format = si_translate_dbformat(tex->db_render_format);
2628 stencil_format = tex->surface.has_stencil ?
2629 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2630
2631 assert(format != V_028040_Z_INVALID);
2632 if (format == V_028040_Z_INVALID)
2633 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2634
2635 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2636 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2637 surf->db_htile_data_base = 0;
2638 surf->db_htile_surface = 0;
2639
2640 if (sctx->chip_class >= GFX10) {
2641 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2642 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2643 }
2644
2645 if (sctx->chip_class >= GFX9) {
2646 assert(tex->surface.u.gfx9.surf_offset == 0);
2647 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2648 surf->db_stencil_base = (tex->buffer.gpu_address +
2649 tex->surface.u.gfx9.stencil_offset) >> 8;
2650 z_info = S_028038_FORMAT(format) |
2651 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2652 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2653 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2654 s_info = S_02803C_FORMAT(stencil_format) |
2655 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2656
2657 if (sctx->chip_class == GFX9) {
2658 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2659 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2660 }
2661 surf->db_depth_view |= S_028008_MIPID(level);
2662 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2663 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2664
2665 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2666 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2667 S_028038_ALLOW_EXPCLEAR(1);
2668
2669 if (tex->tc_compatible_htile) {
2670 unsigned max_zplanes = 4;
2671
2672 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2673 tex->buffer.b.b.nr_samples > 1)
2674 max_zplanes = 2;
2675
2676 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
2677
2678 if (sctx->chip_class >= GFX10) {
2679 z_info |= S_028040_ITERATE_FLUSH(1);
2680 s_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled);
2681 } else {
2682 z_info |= S_028038_ITERATE_FLUSH(1);
2683 s_info |= S_02803C_ITERATE_FLUSH(1);
2684 }
2685 }
2686
2687 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2688 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2689 * See that for explanation.
2690 */
2691 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2692 } else {
2693 /* Use all HTILE for depth if there's no stencil. */
2694 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2695 }
2696
2697 surf->db_htile_data_base = (tex->buffer.gpu_address +
2698 tex->htile_offset) >> 8;
2699 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2700 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
2701 if (sctx->chip_class == GFX9) {
2702 surf->db_htile_surface |=
2703 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2704 }
2705 }
2706 } else {
2707 /* GFX6-GFX8 */
2708 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2709
2710 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2711
2712 surf->db_depth_base = (tex->buffer.gpu_address +
2713 tex->surface.u.legacy.level[level].offset) >> 8;
2714 surf->db_stencil_base = (tex->buffer.gpu_address +
2715 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2716
2717 z_info = S_028040_FORMAT(format) |
2718 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2719 s_info = S_028044_FORMAT(stencil_format);
2720 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2721
2722 if (sctx->chip_class >= GFX7) {
2723 struct radeon_info *info = &sctx->screen->info;
2724 unsigned index = tex->surface.u.legacy.tiling_index[level];
2725 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2726 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2727 unsigned tile_mode = info->si_tile_mode_array[index];
2728 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2729 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2730
2731 surf->db_depth_info |=
2732 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2733 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2734 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2735 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2736 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2737 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2738 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2739 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2740 } else {
2741 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2742 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2743 tile_mode_index = si_tile_mode_index(tex, level, true);
2744 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2745 }
2746
2747 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2748 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2749 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2750 levelinfo->nblk_y) / 64 - 1);
2751
2752 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2753 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2754 S_028040_ALLOW_EXPCLEAR(1);
2755
2756 if (tex->surface.has_stencil) {
2757 /* Workaround: For a not yet understood reason, the
2758 * combination of MSAA, fast stencil clear and stencil
2759 * decompress messes with subsequent stencil buffer
2760 * uses. Problem was reproduced on Verde, Bonaire,
2761 * Tonga, and Carrizo.
2762 *
2763 * Disabling EXPCLEAR works around the problem.
2764 *
2765 * Check piglit's arb_texture_multisample-stencil-clear
2766 * test if you want to try changing this.
2767 */
2768 if (tex->buffer.b.b.nr_samples <= 1)
2769 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2770 } else if (!tex->tc_compatible_htile) {
2771 /* Use all of the htile_buffer for depth if there's no stencil.
2772 * This must not be set when TC-compatible HTILE is enabled
2773 * due to a hw bug.
2774 */
2775 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2776 }
2777
2778 surf->db_htile_data_base = (tex->buffer.gpu_address +
2779 tex->htile_offset) >> 8;
2780 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2781
2782 if (tex->tc_compatible_htile) {
2783 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2784
2785 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2786 if (tex->buffer.b.b.nr_samples <= 1)
2787 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2788 else if (tex->buffer.b.b.nr_samples <= 4)
2789 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2790 else
2791 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2792 }
2793 }
2794 }
2795
2796 surf->db_z_info = z_info;
2797 surf->db_stencil_info = s_info;
2798
2799 surf->depth_initialized = true;
2800 }
2801
2802 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2803 {
2804 if (sctx->decompression_enabled)
2805 return;
2806
2807 if (sctx->framebuffer.state.zsbuf) {
2808 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2809 struct si_texture *tex = (struct si_texture *)surf->texture;
2810
2811 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2812
2813 if (tex->surface.has_stencil)
2814 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2815 }
2816
2817 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2818 while (compressed_cb_mask) {
2819 unsigned i = u_bit_scan(&compressed_cb_mask);
2820 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2821 struct si_texture *tex = (struct si_texture*)surf->texture;
2822
2823 if (tex->fmask_offset)
2824 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2825 if (tex->dcc_gather_statistics)
2826 tex->separate_dcc_dirty = true;
2827 }
2828 }
2829
2830 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2831 {
2832 for (int i = 0; i < state->nr_cbufs; ++i) {
2833 struct si_surface *surf = NULL;
2834 struct si_texture *tex;
2835
2836 if (!state->cbufs[i])
2837 continue;
2838 surf = (struct si_surface*)state->cbufs[i];
2839 tex = (struct si_texture*)surf->base.texture;
2840
2841 p_atomic_dec(&tex->framebuffers_bound);
2842 }
2843 }
2844
2845 static void si_set_framebuffer_state(struct pipe_context *ctx,
2846 const struct pipe_framebuffer_state *state)
2847 {
2848 struct si_context *sctx = (struct si_context *)ctx;
2849 struct si_surface *surf = NULL;
2850 struct si_texture *tex;
2851 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2852 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2853 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2854 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2855 bool old_has_stencil =
2856 old_has_zsbuf &&
2857 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2858 bool unbound = false;
2859 int i;
2860
2861 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2862 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2863 * We could implement the full workaround here, but it's a useless case.
2864 */
2865 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2866 unreachable("the framebuffer shouldn't have zero area");
2867 return;
2868 }
2869
2870 si_update_fb_dirtiness_after_rendering(sctx);
2871
2872 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2873 if (!sctx->framebuffer.state.cbufs[i])
2874 continue;
2875
2876 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2877 if (tex->dcc_gather_statistics)
2878 vi_separate_dcc_stop_query(sctx, tex);
2879 }
2880
2881 /* Disable DCC if the formats are incompatible. */
2882 for (i = 0; i < state->nr_cbufs; i++) {
2883 if (!state->cbufs[i])
2884 continue;
2885
2886 surf = (struct si_surface*)state->cbufs[i];
2887 tex = (struct si_texture*)surf->base.texture;
2888
2889 if (!surf->dcc_incompatible)
2890 continue;
2891
2892 /* Since the DCC decompression calls back into set_framebuffer-
2893 * _state, we need to unbind the framebuffer, so that
2894 * vi_separate_dcc_stop_query isn't called twice with the same
2895 * color buffer.
2896 */
2897 if (!unbound) {
2898 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2899 unbound = true;
2900 }
2901
2902 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2903 if (!si_texture_disable_dcc(sctx, tex))
2904 si_decompress_dcc(sctx, tex);
2905
2906 surf->dcc_incompatible = false;
2907 }
2908
2909 /* Only flush TC when changing the framebuffer state, because
2910 * the only client not using TC that can change textures is
2911 * the framebuffer.
2912 *
2913 * Wait for compute shaders because of possible transitions:
2914 * - FB write -> shader read
2915 * - shader write -> FB read
2916 *
2917 * DB caches are flushed on demand (using si_decompress_textures).
2918 *
2919 * When MSAA is enabled, CB and TC caches are flushed on demand
2920 * (after FMASK decompression). Shader write -> FB read transitions
2921 * cannot happen for MSAA textures, because MSAA shader images are
2922 * not supported.
2923 *
2924 * Only flush and wait for CB if there is actually a bound color buffer.
2925 */
2926 if (sctx->framebuffer.uncompressed_cb_mask) {
2927 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2928 sctx->framebuffer.CB_has_shader_readable_metadata,
2929 sctx->framebuffer.all_DCC_pipe_aligned);
2930 }
2931
2932 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2933
2934 /* u_blitter doesn't invoke depth decompression when it does multiple
2935 * blits in a row, but the only case when it matters for DB is when
2936 * doing generate_mipmap. So here we flush DB manually between
2937 * individual generate_mipmap blits.
2938 * Note that lower mipmap levels aren't compressed.
2939 */
2940 if (sctx->generate_mipmap_for_depth) {
2941 si_make_DB_shader_coherent(sctx, 1, false,
2942 sctx->framebuffer.DB_has_shader_readable_metadata);
2943 } else if (sctx->chip_class == GFX9) {
2944 /* It appears that DB metadata "leaks" in a sequence of:
2945 * - depth clear
2946 * - DCC decompress for shader image writes (with DB disabled)
2947 * - render with DEPTH_BEFORE_SHADER=1
2948 * Flushing DB metadata works around the problem.
2949 */
2950 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2951 }
2952
2953 /* Take the maximum of the old and new count. If the new count is lower,
2954 * dirtying is needed to disable the unbound colorbuffers.
2955 */
2956 sctx->framebuffer.dirty_cbufs |=
2957 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2958 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2959
2960 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2961 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2962
2963 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2964 sctx->framebuffer.spi_shader_col_format = 0;
2965 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2966 sctx->framebuffer.spi_shader_col_format_blend = 0;
2967 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2968 sctx->framebuffer.color_is_int8 = 0;
2969 sctx->framebuffer.color_is_int10 = 0;
2970
2971 sctx->framebuffer.compressed_cb_mask = 0;
2972 sctx->framebuffer.uncompressed_cb_mask = 0;
2973 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2974 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2975 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2976 sctx->framebuffer.any_dst_linear = false;
2977 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2978 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2979 sctx->framebuffer.all_DCC_pipe_aligned = true;
2980
2981 for (i = 0; i < state->nr_cbufs; i++) {
2982 if (!state->cbufs[i])
2983 continue;
2984
2985 surf = (struct si_surface*)state->cbufs[i];
2986 tex = (struct si_texture*)surf->base.texture;
2987
2988 if (!surf->color_initialized) {
2989 si_initialize_color_surface(sctx, surf);
2990 }
2991
2992 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2993 sctx->framebuffer.spi_shader_col_format |=
2994 surf->spi_shader_col_format << (i * 4);
2995 sctx->framebuffer.spi_shader_col_format_alpha |=
2996 surf->spi_shader_col_format_alpha << (i * 4);
2997 sctx->framebuffer.spi_shader_col_format_blend |=
2998 surf->spi_shader_col_format_blend << (i * 4);
2999 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
3000 surf->spi_shader_col_format_blend_alpha << (i * 4);
3001
3002 if (surf->color_is_int8)
3003 sctx->framebuffer.color_is_int8 |= 1 << i;
3004 if (surf->color_is_int10)
3005 sctx->framebuffer.color_is_int10 |= 1 << i;
3006
3007 if (tex->fmask_offset)
3008 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3009 else
3010 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
3011
3012 /* Don't update nr_color_samples for non-AA buffers.
3013 * (e.g. destination of MSAA resolve)
3014 */
3015 if (tex->buffer.b.b.nr_samples >= 2 &&
3016 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3017 sctx->framebuffer.nr_color_samples =
3018 MIN2(sctx->framebuffer.nr_color_samples,
3019 tex->buffer.b.b.nr_storage_samples);
3020 sctx->framebuffer.nr_color_samples =
3021 MAX2(1, sctx->framebuffer.nr_color_samples);
3022 }
3023
3024 if (tex->surface.is_linear)
3025 sctx->framebuffer.any_dst_linear = true;
3026
3027 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3028 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3029
3030 if (sctx->chip_class >= GFX9 &&
3031 !tex->surface.u.gfx9.dcc.pipe_aligned)
3032 sctx->framebuffer.all_DCC_pipe_aligned = false;
3033 }
3034
3035 si_context_add_resource_size(sctx, surf->base.texture);
3036
3037 p_atomic_inc(&tex->framebuffers_bound);
3038
3039 if (tex->dcc_gather_statistics) {
3040 /* Dirty tracking must be enabled for DCC usage analysis. */
3041 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3042 vi_separate_dcc_start_query(sctx, tex);
3043 }
3044 }
3045
3046 /* For optimal DCC performance. */
3047 if (sctx->chip_class >= GFX10)
3048 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
3049 else
3050 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
3051
3052 struct si_texture *zstex = NULL;
3053
3054 if (state->zsbuf) {
3055 surf = (struct si_surface*)state->zsbuf;
3056 zstex = (struct si_texture*)surf->base.texture;
3057
3058 if (!surf->depth_initialized) {
3059 si_init_depth_surface(sctx, surf);
3060 }
3061
3062 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level,
3063 PIPE_MASK_ZS))
3064 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3065
3066 si_context_add_resource_size(sctx, surf->base.texture);
3067 }
3068
3069 si_update_ps_colorbuf0_slot(sctx);
3070 si_update_poly_offset_state(sctx);
3071 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3072 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3073
3074 if (sctx->screen->dpbb_allowed)
3075 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3076
3077 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3078 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3079
3080 if (sctx->screen->has_out_of_order_rast &&
3081 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3082 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3083 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3084 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3085
3086 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3087 struct pipe_constant_buffer constbuf = {0};
3088
3089 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3090 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3091
3092 constbuf.buffer = sctx->sample_pos_buffer;
3093
3094 /* Set sample locations as fragment shader constants. */
3095 switch (sctx->framebuffer.nr_samples) {
3096 case 1:
3097 constbuf.buffer_offset = 0;
3098 break;
3099 case 2:
3100 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3101 (ubyte*)sctx->sample_positions.x1;
3102 break;
3103 case 4:
3104 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3105 (ubyte*)sctx->sample_positions.x1;
3106 break;
3107 case 8:
3108 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3109 (ubyte*)sctx->sample_positions.x1;
3110 break;
3111 case 16:
3112 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3113 (ubyte*)sctx->sample_positions.x1;
3114 break;
3115 default:
3116 PRINT_ERR("Requested an invalid number of samples %i.\n",
3117 sctx->framebuffer.nr_samples);
3118 assert(0);
3119 }
3120 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3121 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3122
3123 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3124 }
3125
3126 sctx->do_update_shaders = true;
3127
3128 if (!sctx->decompression_enabled) {
3129 /* Prevent textures decompression when the framebuffer state
3130 * changes come from the decompression passes themselves.
3131 */
3132 sctx->need_check_render_feedback = true;
3133 }
3134 }
3135
3136 static void si_emit_framebuffer_state(struct si_context *sctx)
3137 {
3138 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3139 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3140 unsigned i, nr_cbufs = state->nr_cbufs;
3141 struct si_texture *tex = NULL;
3142 struct si_surface *cb = NULL;
3143 unsigned cb_color_info = 0;
3144
3145 /* Colorbuffers. */
3146 for (i = 0; i < nr_cbufs; i++) {
3147 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3148 unsigned cb_color_attrib;
3149
3150 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3151 continue;
3152
3153 cb = (struct si_surface*)state->cbufs[i];
3154 if (!cb) {
3155 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3156 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3157 continue;
3158 }
3159
3160 tex = (struct si_texture *)cb->base.texture;
3161 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3162 &tex->buffer, RADEON_USAGE_READWRITE,
3163 tex->buffer.b.b.nr_samples > 1 ?
3164 RADEON_PRIO_COLOR_BUFFER_MSAA :
3165 RADEON_PRIO_COLOR_BUFFER);
3166
3167 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3168 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3169 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3170 RADEON_PRIO_SEPARATE_META);
3171 }
3172
3173 if (tex->dcc_separate_buffer)
3174 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3175 tex->dcc_separate_buffer,
3176 RADEON_USAGE_READWRITE,
3177 RADEON_PRIO_SEPARATE_META);
3178
3179 /* Compute mutable surface parameters. */
3180 cb_color_base = tex->buffer.gpu_address >> 8;
3181 cb_color_fmask = 0;
3182 cb_color_cmask = tex->cmask_base_address_reg;
3183 cb_dcc_base = 0;
3184 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3185 cb_color_attrib = cb->cb_color_attrib;
3186
3187 if (cb->base.u.tex.level > 0)
3188 cb_color_info &= C_028C70_FAST_CLEAR;
3189
3190 if (tex->fmask_offset) {
3191 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3192 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3193 }
3194
3195 /* Set up DCC. */
3196 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3197 bool is_msaa_resolve_dst = state->cbufs[0] &&
3198 state->cbufs[0]->texture->nr_samples > 1 &&
3199 state->cbufs[1] == &cb->base &&
3200 state->cbufs[1]->texture->nr_samples <= 1;
3201
3202 if (!is_msaa_resolve_dst)
3203 cb_color_info |= S_028C70_DCC_ENABLE(1);
3204
3205 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3206 tex->dcc_offset) >> 8;
3207
3208 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3209 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
3210 cb_dcc_base |= dcc_tile_swizzle;
3211 }
3212
3213 if (sctx->chip_class >= GFX10) {
3214 unsigned cb_color_attrib3;
3215
3216 /* Set mutable surface parameters. */
3217 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3218 cb_color_base |= tex->surface.tile_swizzle;
3219 if (!tex->fmask_offset)
3220 cb_color_fmask = cb_color_base;
3221 if (cb->base.u.tex.level > 0)
3222 cb_color_cmask = cb_color_base;
3223
3224 cb_color_attrib3 = cb->cb_color_attrib3 |
3225 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3226 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3227 S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3228 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
3229
3230 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3231 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3232 radeon_emit(cs, 0); /* hole */
3233 radeon_emit(cs, 0); /* hole */
3234 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3235 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3236 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3237 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3238 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3239 radeon_emit(cs, 0); /* hole */
3240 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3241 radeon_emit(cs, 0); /* hole */
3242 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3243 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3244 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3245
3246 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4,
3247 cb_color_base >> 32);
3248 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3249 cb_color_cmask >> 32);
3250 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3251 cb_color_fmask >> 32);
3252 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4,
3253 cb_dcc_base >> 32);
3254 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4,
3255 cb->cb_color_attrib2);
3256 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4,
3257 cb_color_attrib3);
3258 } else if (sctx->chip_class == GFX9) {
3259 struct gfx9_surf_meta_flags meta;
3260
3261 if (tex->dcc_offset)
3262 meta = tex->surface.u.gfx9.dcc;
3263 else
3264 meta = tex->surface.u.gfx9.cmask;
3265
3266 /* Set mutable surface parameters. */
3267 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3268 cb_color_base |= tex->surface.tile_swizzle;
3269 if (!tex->fmask_offset)
3270 cb_color_fmask = cb_color_base;
3271 if (cb->base.u.tex.level > 0)
3272 cb_color_cmask = cb_color_base;
3273 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3274 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3275 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3276 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3277
3278 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3279 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3280 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3281 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3282 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3283 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3284 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3285 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3286 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3287 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3288 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3289 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3290 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3291 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3292 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3293 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3294
3295 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3296 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3297 } else {
3298 /* Compute mutable surface parameters (GFX6-GFX8). */
3299 const struct legacy_surf_level *level_info =
3300 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3301 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3302 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3303
3304 cb_color_base += level_info->offset >> 8;
3305 /* Only macrotiled modes can set tile swizzle. */
3306 if (level_info->mode == RADEON_SURF_MODE_2D)
3307 cb_color_base |= tex->surface.tile_swizzle;
3308
3309 if (!tex->fmask_offset)
3310 cb_color_fmask = cb_color_base;
3311 if (cb->base.u.tex.level > 0)
3312 cb_color_cmask = cb_color_base;
3313 if (cb_dcc_base)
3314 cb_dcc_base += level_info->dcc_offset >> 8;
3315
3316 pitch_tile_max = level_info->nblk_x / 8 - 1;
3317 slice_tile_max = level_info->nblk_x *
3318 level_info->nblk_y / 64 - 1;
3319 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3320
3321 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3322 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3323 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3324
3325 if (tex->fmask_offset) {
3326 if (sctx->chip_class >= GFX7)
3327 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3328 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3329 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3330 } else {
3331 /* This must be set for fast clear to work without FMASK. */
3332 if (sctx->chip_class >= GFX7)
3333 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3334 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3335 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3336 }
3337
3338 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3339 sctx->chip_class >= GFX8 ? 14 : 13);
3340 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3341 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3342 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3343 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3344 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3345 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3346 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3347 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3348 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3349 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3350 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3351 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3352 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3353
3354 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3355 radeon_emit(cs, cb_dcc_base);
3356 }
3357 }
3358 for (; i < 8 ; i++)
3359 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3360 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3361
3362 /* ZS buffer. */
3363 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3364 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3365 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3366
3367 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3368 &tex->buffer, RADEON_USAGE_READWRITE,
3369 zb->base.texture->nr_samples > 1 ?
3370 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3371 RADEON_PRIO_DEPTH_BUFFER);
3372
3373 if (sctx->chip_class >= GFX10) {
3374 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3375 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3376
3377 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3378 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3379 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3380 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3381 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3382 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3383 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3384 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3385 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3386
3387 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
3388 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3389 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3390 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3391 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3392 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3393 } else if (sctx->chip_class == GFX9) {
3394 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3395 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3396 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3397 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3398
3399 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3400 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3401 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3402 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3403 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3404 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3405 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3406 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3407 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3408 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3409 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3410 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3411
3412 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3413 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3414 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3415 } else {
3416 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3417
3418 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3419 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3420 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3421 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3422 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3423 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3424 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3425 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3426 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3427 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3428 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3429 }
3430
3431 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3432 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3433 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3434
3435 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3436 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3437 } else if (sctx->framebuffer.dirty_zsbuf) {
3438 if (sctx->chip_class == GFX9)
3439 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3440 else
3441 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3442
3443 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3444 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3445 }
3446
3447 /* Framebuffer dimensions. */
3448 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3449 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3450 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3451
3452 if (sctx->screen->dfsm_allowed) {
3453 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3454 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3455 }
3456
3457 sctx->framebuffer.dirty_cbufs = 0;
3458 sctx->framebuffer.dirty_zsbuf = false;
3459 }
3460
3461 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3462 {
3463 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3464 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3465 unsigned nr_samples = sctx->framebuffer.nr_samples;
3466 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3467
3468 /* Smoothing (only possible with nr_samples == 1) uses the same
3469 * sample locations as the MSAA it simulates.
3470 */
3471 if (nr_samples <= 1 && sctx->smoothing_enabled)
3472 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3473
3474 /* On Polaris, the small primitive filter uses the sample locations
3475 * even when MSAA is off, so we need to make sure they're set to 0.
3476 *
3477 * GFX10 uses sample locations unconditionally, so they always need
3478 * to be set up.
3479 */
3480 if ((nr_samples >= 2 || has_msaa_sample_loc_bug ||
3481 sctx->chip_class >= GFX10) &&
3482 nr_samples != sctx->sample_locs_num_samples) {
3483 sctx->sample_locs_num_samples = nr_samples;
3484 si_emit_sample_locations(cs, nr_samples);
3485 }
3486
3487 if (sctx->family >= CHIP_POLARIS10) {
3488 unsigned small_prim_filter_cntl =
3489 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3490 /* line bug */
3491 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3492
3493 /* The alternative of setting sample locations to 0 would
3494 * require a DB flush to avoid Z errors, see
3495 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3496 */
3497 if (has_msaa_sample_loc_bug &&
3498 sctx->framebuffer.nr_samples > 1 &&
3499 !rs->multisample_enable)
3500 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3501
3502 radeon_opt_set_context_reg(sctx,
3503 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3504 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3505 small_prim_filter_cntl);
3506 }
3507
3508 /* The exclusion bits can be set to improve rasterization efficiency
3509 * if no sample lies on the pixel boundary (-8 sample offset).
3510 */
3511 bool exclusion = sctx->chip_class >= GFX7 &&
3512 (!rs->multisample_enable || nr_samples != 16);
3513 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3514 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3515 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3516 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3517 }
3518
3519 static bool si_out_of_order_rasterization(struct si_context *sctx)
3520 {
3521 struct si_state_blend *blend = sctx->queued.named.blend;
3522 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3523
3524 if (!sctx->screen->has_out_of_order_rast)
3525 return false;
3526
3527 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3528
3529 if (blend) {
3530 colormask &= blend->cb_target_enabled_4bit;
3531 } else {
3532 colormask = 0;
3533 }
3534
3535 /* Conservative: No logic op. */
3536 if (colormask && blend->logicop_enable)
3537 return false;
3538
3539 struct si_dsa_order_invariance dsa_order_invariant = {
3540 .zs = true, .pass_set = true, .pass_last = false
3541 };
3542
3543 if (sctx->framebuffer.state.zsbuf) {
3544 struct si_texture *zstex =
3545 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3546 bool has_stencil = zstex->surface.has_stencil;
3547 dsa_order_invariant = dsa->order_invariance[has_stencil];
3548 if (!dsa_order_invariant.zs)
3549 return false;
3550
3551 /* The set of PS invocations is always order invariant,
3552 * except when early Z/S tests are requested. */
3553 if (sctx->ps_shader.cso &&
3554 sctx->ps_shader.cso->info.writes_memory &&
3555 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3556 !dsa_order_invariant.pass_set)
3557 return false;
3558
3559 if (sctx->num_perfect_occlusion_queries != 0 &&
3560 !dsa_order_invariant.pass_set)
3561 return false;
3562 }
3563
3564 if (!colormask)
3565 return true;
3566
3567 unsigned blendmask = colormask & blend->blend_enable_4bit;
3568
3569 if (blendmask) {
3570 /* Only commutative blending. */
3571 if (blendmask & ~blend->commutative_4bit)
3572 return false;
3573
3574 if (!dsa_order_invariant.pass_set)
3575 return false;
3576 }
3577
3578 if (colormask & ~blendmask) {
3579 if (!dsa_order_invariant.pass_last)
3580 return false;
3581 }
3582
3583 return true;
3584 }
3585
3586 static void si_emit_msaa_config(struct si_context *sctx)
3587 {
3588 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3589 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3590 /* 33% faster rendering to linear color buffers */
3591 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3592 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3593 unsigned sc_mode_cntl_1 =
3594 S_028A4C_WALK_SIZE(dst_is_linear) |
3595 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3596 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3597 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3598 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3599 /* always 1: */
3600 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3601 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3602 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3603 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3604 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3605 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3606 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3607 S_028804_INCOHERENT_EQAA_READS(1) |
3608 S_028804_INTERPOLATE_COMP_Z(1) |
3609 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3610 unsigned coverage_samples, color_samples, z_samples;
3611 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3612
3613 /* S: Coverage samples (up to 16x):
3614 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3615 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3616 *
3617 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3618 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3619 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3620 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3621 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3622 * # Z samples).
3623 *
3624 * F: Color samples (up to 8x, must be <= coverage samples):
3625 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3626 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3627 *
3628 * Can be anything between coverage and color samples:
3629 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3630 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3631 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3632 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3633 * # All are currently set the same as coverage samples.
3634 *
3635 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3636 * flag for undefined color samples. A shader-based resolve must handle unknowns
3637 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3638 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3639 * useful. The CB resolve always drops unknowns.
3640 *
3641 * Sensible AA configurations:
3642 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3643 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3644 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3645 * EQAA 8s 8z 8f = 8x MSAA
3646 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3647 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3648 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3649 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3650 * EQAA 4s 4z 4f = 4x MSAA
3651 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3652 * EQAA 2s 2z 2f = 2x MSAA
3653 */
3654 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3655 coverage_samples = sctx->framebuffer.nr_samples;
3656 color_samples = sctx->framebuffer.nr_color_samples;
3657
3658 if (sctx->framebuffer.state.zsbuf) {
3659 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3660 z_samples = MAX2(1, z_samples);
3661 } else {
3662 z_samples = coverage_samples;
3663 }
3664 } else if (sctx->smoothing_enabled) {
3665 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3666 } else {
3667 coverage_samples = color_samples = z_samples = 1;
3668 }
3669
3670 /* Required by OpenGL line rasterization.
3671 *
3672 * TODO: We should also enable perpendicular endcaps for AA lines,
3673 * but that requires implementing line stippling in the pixel
3674 * shader. SC can only do line stippling with axis-aligned
3675 * endcaps.
3676 */
3677 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3678 unsigned sc_aa_config = 0;
3679
3680 if (coverage_samples > 1) {
3681 /* distance from the pixel center, indexed by log2(nr_samples) */
3682 static unsigned max_dist[] = {
3683 0, /* unused */
3684 4, /* 2x MSAA */
3685 6, /* 4x MSAA */
3686 7, /* 8x MSAA */
3687 8, /* 16x MSAA */
3688 };
3689 unsigned log_samples = util_logbase2(coverage_samples);
3690 unsigned log_z_samples = util_logbase2(z_samples);
3691 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3692 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3693
3694 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3695 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3696 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3697 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3698
3699 if (sctx->framebuffer.nr_samples > 1) {
3700 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3701 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3702 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3703 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3704 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3705 } else if (sctx->smoothing_enabled) {
3706 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3707 }
3708 }
3709
3710 unsigned initial_cdw = cs->current.cdw;
3711
3712 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3713 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3714 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3715 sc_aa_config);
3716 /* R_028804_DB_EQAA */
3717 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3718 db_eqaa);
3719 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3720 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3721 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3722
3723 if (initial_cdw != cs->current.cdw) {
3724 sctx->context_roll = true;
3725
3726 /* GFX9: Flush DFSM when the AA mode changes. */
3727 if (sctx->screen->dfsm_allowed) {
3728 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3729 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3730 }
3731 }
3732 }
3733
3734 void si_update_ps_iter_samples(struct si_context *sctx)
3735 {
3736 if (sctx->framebuffer.nr_samples > 1)
3737 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3738 if (sctx->screen->dpbb_allowed)
3739 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3740 }
3741
3742 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3743 {
3744 struct si_context *sctx = (struct si_context *)ctx;
3745
3746 /* The hardware can only do sample shading with 2^n samples. */
3747 min_samples = util_next_power_of_two(min_samples);
3748
3749 if (sctx->ps_iter_samples == min_samples)
3750 return;
3751
3752 sctx->ps_iter_samples = min_samples;
3753 sctx->do_update_shaders = true;
3754
3755 si_update_ps_iter_samples(sctx);
3756 }
3757
3758 /*
3759 * Samplers
3760 */
3761
3762 /**
3763 * Build the sampler view descriptor for a buffer texture.
3764 * @param state 256-bit descriptor; only the high 128 bits are filled in
3765 */
3766 void
3767 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3768 enum pipe_format format,
3769 unsigned offset, unsigned size,
3770 uint32_t *state)
3771 {
3772 const struct util_format_description *desc;
3773 unsigned stride;
3774 unsigned num_records;
3775
3776 desc = util_format_description(format);
3777 stride = desc->block.bits / 8;
3778
3779 num_records = size / stride;
3780 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3781
3782 /* The NUM_RECORDS field has a different meaning depending on the chip,
3783 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3784 *
3785 * GFX6-7,10:
3786 * - If STRIDE == 0, it's in byte units.
3787 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3788 *
3789 * GFX8:
3790 * - For SMEM and STRIDE == 0, it's in byte units.
3791 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3792 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3793 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3794 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3795 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3796 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3797 * That way the same descriptor can be used by both SMEM and VMEM.
3798 *
3799 * GFX9:
3800 * - For SMEM and STRIDE == 0, it's in byte units.
3801 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3802 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3803 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3804 */
3805 if (screen->info.chip_class == GFX9 && HAVE_LLVM < 0x0800)
3806 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3807 * from STRIDE to bytes. This works around it by setting
3808 * NUM_RECORDS to at least the size of one element, so that
3809 * the first element is readable when IDXEN == 0.
3810 */
3811 num_records = num_records ? MAX2(num_records, stride) : 0;
3812 else if (screen->info.chip_class == GFX8)
3813 num_records *= stride;
3814
3815 state[4] = 0;
3816 state[5] = S_008F04_STRIDE(stride);
3817 state[6] = num_records;
3818 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3819 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3820 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3821 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3822
3823 if (screen->info.chip_class >= GFX10) {
3824 const struct gfx10_format *fmt = &gfx10_format_table[format];
3825
3826 /* OOB_SELECT chooses the out-of-bounds check:
3827 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3828 * - 1: index >= NUM_RECORDS
3829 * - 2: NUM_RECORDS == 0
3830 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3831 * else: swizzle_address >= NUM_RECORDS
3832 */
3833 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3834 S_008F0C_OOB_SELECT(0) |
3835 S_008F0C_RESOURCE_LEVEL(1);
3836 } else {
3837 int first_non_void;
3838 unsigned num_format, data_format;
3839
3840 first_non_void = util_format_get_first_non_void_channel(format);
3841 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3842 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3843
3844 state[7] |= S_008F0C_NUM_FORMAT(num_format) |
3845 S_008F0C_DATA_FORMAT(data_format);
3846 }
3847 }
3848
3849 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3850 {
3851 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3852
3853 if (swizzle[3] == PIPE_SWIZZLE_X) {
3854 /* For the pre-defined border color values (white, opaque
3855 * black, transparent black), the only thing that matters is
3856 * that the alpha channel winds up in the correct place
3857 * (because the RGB channels are all the same) so either of
3858 * these enumerations will work.
3859 */
3860 if (swizzle[2] == PIPE_SWIZZLE_Y)
3861 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3862 else
3863 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3864 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3865 if (swizzle[1] == PIPE_SWIZZLE_Y)
3866 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3867 else
3868 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3869 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3870 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3871 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3872 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3873 }
3874
3875 return bc_swizzle;
3876 }
3877
3878 /**
3879 * Build the sampler view descriptor for a texture.
3880 */
3881 static void
3882 gfx10_make_texture_descriptor(struct si_screen *screen,
3883 struct si_texture *tex,
3884 bool sampler,
3885 enum pipe_texture_target target,
3886 enum pipe_format pipe_format,
3887 const unsigned char state_swizzle[4],
3888 unsigned first_level, unsigned last_level,
3889 unsigned first_layer, unsigned last_layer,
3890 unsigned width, unsigned height, unsigned depth,
3891 uint32_t *state,
3892 uint32_t *fmask_state)
3893 {
3894 struct pipe_resource *res = &tex->buffer.b.b;
3895 const struct util_format_description *desc;
3896 unsigned img_format;
3897 unsigned char swizzle[4];
3898 unsigned type;
3899 uint64_t va;
3900
3901 desc = util_format_description(pipe_format);
3902 img_format = gfx10_format_table[pipe_format].img_format;
3903
3904 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3905 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3906 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3907 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3908 bool is_stencil = false;
3909
3910 switch (pipe_format) {
3911 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3912 case PIPE_FORMAT_X32_S8X24_UINT:
3913 case PIPE_FORMAT_X8Z24_UNORM:
3914 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3915 is_stencil = true;
3916 break;
3917 case PIPE_FORMAT_X24S8_UINT:
3918 /*
3919 * X24S8 is implemented as an 8_8_8_8 data format, to
3920 * fix texture gathers. This affects at least
3921 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3922 */
3923 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3924 is_stencil = true;
3925 break;
3926 default:
3927 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3928 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3929 }
3930
3931 if (tex->upgraded_depth && !is_stencil) {
3932 assert(img_format == V_008F0C_IMG_FORMAT_32_FLOAT);
3933 img_format = V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP;
3934 }
3935 } else {
3936 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3937 }
3938
3939 if (!sampler &&
3940 (res->target == PIPE_TEXTURE_CUBE ||
3941 res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3942 /* For the purpose of shader images, treat cube maps as 2D
3943 * arrays.
3944 */
3945 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3946 } else {
3947 type = si_tex_dim(screen, tex, target, res->nr_samples);
3948 }
3949
3950 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3951 height = 1;
3952 depth = res->array_size;
3953 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3954 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3955 if (sampler || res->target != PIPE_TEXTURE_3D)
3956 depth = res->array_size;
3957 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3958 depth = res->array_size / 6;
3959
3960 state[0] = 0;
3961 state[1] = S_00A004_FORMAT(img_format) |
3962 S_00A004_WIDTH_LO(width - 1);
3963 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
3964 S_00A008_HEIGHT(height - 1) |
3965 S_00A008_RESOURCE_LEVEL(1);
3966 state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3967 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3968 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3969 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3970 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ?
3971 0 : first_level) |
3972 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ?
3973 util_logbase2(res->nr_samples) :
3974 last_level) |
3975 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) |
3976 S_00A00C_TYPE(type);
3977 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3978 * to know the total number of layers.
3979 */
3980 state[4] = S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler)
3981 ? depth - 1 : last_layer) |
3982 S_00A010_BASE_ARRAY(first_layer);
3983 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
3984 S_00A014_MAX_MIP(res->nr_samples > 1 ?
3985 util_logbase2(res->nr_samples) :
3986 tex->buffer.b.b.last_level) |
3987 S_00A014_PERF_MOD(4);
3988 state[6] = 0;
3989 state[7] = 0;
3990
3991 if (tex->dcc_offset) {
3992 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
3993 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
3994 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
3995 }
3996
3997 /* Initialize the sampler view for FMASK. */
3998 if (tex->fmask_offset) {
3999 uint32_t format;
4000
4001 va = tex->buffer.gpu_address + tex->fmask_offset;
4002
4003 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4004 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4005 case FMASK(2,1):
4006 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F1;
4007 break;
4008 case FMASK(2,2):
4009 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
4010 break;
4011 case FMASK(4,1):
4012 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F1;
4013 break;
4014 case FMASK(4,2):
4015 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F2;
4016 break;
4017 case FMASK(4,4):
4018 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
4019 break;
4020 case FMASK(8,1):
4021 format = V_008F0C_IMG_FORMAT_FMASK8_S8_F1;
4022 break;
4023 case FMASK(8,2):
4024 format = V_008F0C_IMG_FORMAT_FMASK16_S8_F2;
4025 break;
4026 case FMASK(8,4):
4027 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F4;
4028 break;
4029 case FMASK(8,8):
4030 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
4031 break;
4032 case FMASK(16,1):
4033 format = V_008F0C_IMG_FORMAT_FMASK16_S16_F1;
4034 break;
4035 case FMASK(16,2):
4036 format = V_008F0C_IMG_FORMAT_FMASK32_S16_F2;
4037 break;
4038 case FMASK(16,4):
4039 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F4;
4040 break;
4041 case FMASK(16,8):
4042 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F8;
4043 break;
4044 default:
4045 unreachable("invalid nr_samples");
4046 }
4047 #undef FMASK
4048 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4049 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
4050 S_00A004_FORMAT(format) |
4051 S_00A004_WIDTH_LO(width - 1);
4052 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
4053 S_00A008_HEIGHT(height - 1) |
4054 S_00A008_RESOURCE_LEVEL(1);
4055 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4056 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4057 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4058 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4059 S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
4060 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4061 fmask_state[4] = S_00A010_DEPTH(last_layer) |
4062 S_00A010_BASE_ARRAY(first_layer);
4063 fmask_state[5] = 0;
4064 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
4065 fmask_state[7] = 0;
4066 }
4067 }
4068
4069 /**
4070 * Build the sampler view descriptor for a texture (SI-GFX9).
4071 */
4072 static void
4073 si_make_texture_descriptor(struct si_screen *screen,
4074 struct si_texture *tex,
4075 bool sampler,
4076 enum pipe_texture_target target,
4077 enum pipe_format pipe_format,
4078 const unsigned char state_swizzle[4],
4079 unsigned first_level, unsigned last_level,
4080 unsigned first_layer, unsigned last_layer,
4081 unsigned width, unsigned height, unsigned depth,
4082 uint32_t *state,
4083 uint32_t *fmask_state)
4084 {
4085 struct pipe_resource *res = &tex->buffer.b.b;
4086 const struct util_format_description *desc;
4087 unsigned char swizzle[4];
4088 int first_non_void;
4089 unsigned num_format, data_format, type, num_samples;
4090 uint64_t va;
4091
4092 desc = util_format_description(pipe_format);
4093
4094 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
4095 MAX2(1, res->nr_samples) :
4096 MAX2(1, res->nr_storage_samples);
4097
4098 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4099 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4100 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4101 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4102
4103 switch (pipe_format) {
4104 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4105 case PIPE_FORMAT_X32_S8X24_UINT:
4106 case PIPE_FORMAT_X8Z24_UNORM:
4107 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4108 break;
4109 case PIPE_FORMAT_X24S8_UINT:
4110 /*
4111 * X24S8 is implemented as an 8_8_8_8 data format, to
4112 * fix texture gathers. This affects at least
4113 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4114 */
4115 if (screen->info.chip_class <= GFX8)
4116 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4117 else
4118 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4119 break;
4120 default:
4121 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4122 }
4123 } else {
4124 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4125 }
4126
4127 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4128
4129 switch (pipe_format) {
4130 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4131 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4132 break;
4133 default:
4134 if (first_non_void < 0) {
4135 if (util_format_is_compressed(pipe_format)) {
4136 switch (pipe_format) {
4137 case PIPE_FORMAT_DXT1_SRGB:
4138 case PIPE_FORMAT_DXT1_SRGBA:
4139 case PIPE_FORMAT_DXT3_SRGBA:
4140 case PIPE_FORMAT_DXT5_SRGBA:
4141 case PIPE_FORMAT_BPTC_SRGBA:
4142 case PIPE_FORMAT_ETC2_SRGB8:
4143 case PIPE_FORMAT_ETC2_SRGB8A1:
4144 case PIPE_FORMAT_ETC2_SRGBA8:
4145 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4146 break;
4147 case PIPE_FORMAT_RGTC1_SNORM:
4148 case PIPE_FORMAT_LATC1_SNORM:
4149 case PIPE_FORMAT_RGTC2_SNORM:
4150 case PIPE_FORMAT_LATC2_SNORM:
4151 case PIPE_FORMAT_ETC2_R11_SNORM:
4152 case PIPE_FORMAT_ETC2_RG11_SNORM:
4153 /* implies float, so use SNORM/UNORM to determine
4154 whether data is signed or not */
4155 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4156 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4157 break;
4158 default:
4159 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4160 break;
4161 }
4162 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4163 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4164 } else {
4165 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4166 }
4167 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4168 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4169 } else {
4170 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4171
4172 switch (desc->channel[first_non_void].type) {
4173 case UTIL_FORMAT_TYPE_FLOAT:
4174 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4175 break;
4176 case UTIL_FORMAT_TYPE_SIGNED:
4177 if (desc->channel[first_non_void].normalized)
4178 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4179 else if (desc->channel[first_non_void].pure_integer)
4180 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4181 else
4182 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4183 break;
4184 case UTIL_FORMAT_TYPE_UNSIGNED:
4185 if (desc->channel[first_non_void].normalized)
4186 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4187 else if (desc->channel[first_non_void].pure_integer)
4188 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4189 else
4190 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4191 }
4192 }
4193 }
4194
4195 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4196 if (data_format == ~0) {
4197 data_format = 0;
4198 }
4199
4200 /* S8 with Z32 HTILE needs a special format. */
4201 if (screen->info.chip_class == GFX9 &&
4202 pipe_format == PIPE_FORMAT_S8_UINT &&
4203 tex->tc_compatible_htile)
4204 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4205
4206 if (!sampler &&
4207 (res->target == PIPE_TEXTURE_CUBE ||
4208 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4209 (screen->info.chip_class <= GFX8 &&
4210 res->target == PIPE_TEXTURE_3D))) {
4211 /* For the purpose of shader images, treat cube maps and 3D
4212 * textures as 2D arrays. For 3D textures, the address
4213 * calculations for mipmaps are different, so we rely on the
4214 * caller to effectively disable mipmaps.
4215 */
4216 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4217
4218 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4219 } else {
4220 type = si_tex_dim(screen, tex, target, num_samples);
4221 }
4222
4223 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4224 height = 1;
4225 depth = res->array_size;
4226 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
4227 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4228 if (sampler || res->target != PIPE_TEXTURE_3D)
4229 depth = res->array_size;
4230 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4231 depth = res->array_size / 6;
4232
4233 state[0] = 0;
4234 state[1] = (S_008F14_DATA_FORMAT(data_format) |
4235 S_008F14_NUM_FORMAT(num_format));
4236 state[2] = (S_008F18_WIDTH(width - 1) |
4237 S_008F18_HEIGHT(height - 1) |
4238 S_008F18_PERF_MOD(4));
4239 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4240 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4241 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4242 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4243 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4244 S_008F1C_LAST_LEVEL(num_samples > 1 ?
4245 util_logbase2(num_samples) :
4246 last_level) |
4247 S_008F1C_TYPE(type));
4248 state[4] = 0;
4249 state[5] = S_008F24_BASE_ARRAY(first_layer);
4250 state[6] = 0;
4251 state[7] = 0;
4252
4253 if (screen->info.chip_class == GFX9) {
4254 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4255
4256 /* Depth is the the last accessible layer on Gfx9.
4257 * The hw doesn't need to know the total number of layers.
4258 */
4259 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4260 state[4] |= S_008F20_DEPTH(depth - 1);
4261 else
4262 state[4] |= S_008F20_DEPTH(last_layer);
4263
4264 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4265 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
4266 util_logbase2(num_samples) :
4267 tex->buffer.b.b.last_level);
4268 } else {
4269 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4270 state[4] |= S_008F20_DEPTH(depth - 1);
4271 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4272 }
4273
4274 if (tex->dcc_offset) {
4275 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4276 } else {
4277 /* The last dword is unused by hw. The shader uses it to clear
4278 * bits in the first dword of sampler state.
4279 */
4280 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4281 if (first_level == last_level)
4282 state[7] = C_008F30_MAX_ANISO_RATIO;
4283 else
4284 state[7] = 0xffffffff;
4285 }
4286 }
4287
4288 /* Initialize the sampler view for FMASK. */
4289 if (tex->fmask_offset) {
4290 uint32_t data_format, num_format;
4291
4292 va = tex->buffer.gpu_address + tex->fmask_offset;
4293
4294 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4295 if (screen->info.chip_class == GFX9) {
4296 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4297 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4298 case FMASK(2,1):
4299 num_format = V_008F14_IMG_FMASK_8_2_1;
4300 break;
4301 case FMASK(2,2):
4302 num_format = V_008F14_IMG_FMASK_8_2_2;
4303 break;
4304 case FMASK(4,1):
4305 num_format = V_008F14_IMG_FMASK_8_4_1;
4306 break;
4307 case FMASK(4,2):
4308 num_format = V_008F14_IMG_FMASK_8_4_2;
4309 break;
4310 case FMASK(4,4):
4311 num_format = V_008F14_IMG_FMASK_8_4_4;
4312 break;
4313 case FMASK(8,1):
4314 num_format = V_008F14_IMG_FMASK_8_8_1;
4315 break;
4316 case FMASK(8,2):
4317 num_format = V_008F14_IMG_FMASK_16_8_2;
4318 break;
4319 case FMASK(8,4):
4320 num_format = V_008F14_IMG_FMASK_32_8_4;
4321 break;
4322 case FMASK(8,8):
4323 num_format = V_008F14_IMG_FMASK_32_8_8;
4324 break;
4325 case FMASK(16,1):
4326 num_format = V_008F14_IMG_FMASK_16_16_1;
4327 break;
4328 case FMASK(16,2):
4329 num_format = V_008F14_IMG_FMASK_32_16_2;
4330 break;
4331 case FMASK(16,4):
4332 num_format = V_008F14_IMG_FMASK_64_16_4;
4333 break;
4334 case FMASK(16,8):
4335 num_format = V_008F14_IMG_FMASK_64_16_8;
4336 break;
4337 default:
4338 unreachable("invalid nr_samples");
4339 }
4340 } else {
4341 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4342 case FMASK(2,1):
4343 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4344 break;
4345 case FMASK(2,2):
4346 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4347 break;
4348 case FMASK(4,1):
4349 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4350 break;
4351 case FMASK(4,2):
4352 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4353 break;
4354 case FMASK(4,4):
4355 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4356 break;
4357 case FMASK(8,1):
4358 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4359 break;
4360 case FMASK(8,2):
4361 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4362 break;
4363 case FMASK(8,4):
4364 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4365 break;
4366 case FMASK(8,8):
4367 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4368 break;
4369 case FMASK(16,1):
4370 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4371 break;
4372 case FMASK(16,2):
4373 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4374 break;
4375 case FMASK(16,4):
4376 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4377 break;
4378 case FMASK(16,8):
4379 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4380 break;
4381 default:
4382 unreachable("invalid nr_samples");
4383 }
4384 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4385 }
4386 #undef FMASK
4387
4388 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4389 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4390 S_008F14_DATA_FORMAT(data_format) |
4391 S_008F14_NUM_FORMAT(num_format);
4392 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4393 S_008F18_HEIGHT(height - 1);
4394 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4395 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4396 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4397 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4398 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4399 fmask_state[4] = 0;
4400 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4401 fmask_state[6] = 0;
4402 fmask_state[7] = 0;
4403
4404 if (screen->info.chip_class == GFX9) {
4405 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4406 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4407 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4408 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4409 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4410 } else {
4411 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4412 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4413 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4414 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4415 }
4416 }
4417 }
4418
4419 /**
4420 * Create a sampler view.
4421 *
4422 * @param ctx context
4423 * @param texture texture
4424 * @param state sampler view template
4425 * @param width0 width0 override (for compressed textures as int)
4426 * @param height0 height0 override (for compressed textures as int)
4427 * @param force_level set the base address to the level (for compressed textures)
4428 */
4429 struct pipe_sampler_view *
4430 si_create_sampler_view_custom(struct pipe_context *ctx,
4431 struct pipe_resource *texture,
4432 const struct pipe_sampler_view *state,
4433 unsigned width0, unsigned height0,
4434 unsigned force_level)
4435 {
4436 struct si_context *sctx = (struct si_context*)ctx;
4437 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4438 struct si_texture *tex = (struct si_texture*)texture;
4439 unsigned base_level, first_level, last_level;
4440 unsigned char state_swizzle[4];
4441 unsigned height, depth, width;
4442 unsigned last_layer = state->u.tex.last_layer;
4443 enum pipe_format pipe_format;
4444 const struct legacy_surf_level *surflevel;
4445
4446 if (!view)
4447 return NULL;
4448
4449 /* initialize base object */
4450 view->base = *state;
4451 view->base.texture = NULL;
4452 view->base.reference.count = 1;
4453 view->base.context = ctx;
4454
4455 assert(texture);
4456 pipe_resource_reference(&view->base.texture, texture);
4457
4458 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4459 state->format == PIPE_FORMAT_S8X24_UINT ||
4460 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4461 state->format == PIPE_FORMAT_S8_UINT)
4462 view->is_stencil_sampler = true;
4463
4464 /* Buffer resource. */
4465 if (texture->target == PIPE_BUFFER) {
4466 si_make_buffer_descriptor(sctx->screen,
4467 si_resource(texture),
4468 state->format,
4469 state->u.buf.offset,
4470 state->u.buf.size,
4471 view->state);
4472 return &view->base;
4473 }
4474
4475 state_swizzle[0] = state->swizzle_r;
4476 state_swizzle[1] = state->swizzle_g;
4477 state_swizzle[2] = state->swizzle_b;
4478 state_swizzle[3] = state->swizzle_a;
4479
4480 base_level = 0;
4481 first_level = state->u.tex.first_level;
4482 last_level = state->u.tex.last_level;
4483 width = width0;
4484 height = height0;
4485 depth = texture->depth0;
4486
4487 if (sctx->chip_class <= GFX8 && force_level) {
4488 assert(force_level == first_level &&
4489 force_level == last_level);
4490 base_level = force_level;
4491 first_level = 0;
4492 last_level = 0;
4493 width = u_minify(width, force_level);
4494 height = u_minify(height, force_level);
4495 depth = u_minify(depth, force_level);
4496 }
4497
4498 /* This is not needed if state trackers set last_layer correctly. */
4499 if (state->target == PIPE_TEXTURE_1D ||
4500 state->target == PIPE_TEXTURE_2D ||
4501 state->target == PIPE_TEXTURE_RECT ||
4502 state->target == PIPE_TEXTURE_CUBE)
4503 last_layer = state->u.tex.first_layer;
4504
4505 /* Texturing with separate depth and stencil. */
4506 pipe_format = state->format;
4507
4508 /* Depth/stencil texturing sometimes needs separate texture. */
4509 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4510 if (!tex->flushed_depth_texture &&
4511 !si_init_flushed_depth_texture(ctx, texture)) {
4512 pipe_resource_reference(&view->base.texture, NULL);
4513 FREE(view);
4514 return NULL;
4515 }
4516
4517 assert(tex->flushed_depth_texture);
4518
4519 /* Override format for the case where the flushed texture
4520 * contains only Z or only S.
4521 */
4522 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4523 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4524
4525 tex = tex->flushed_depth_texture;
4526 }
4527
4528 surflevel = tex->surface.u.legacy.level;
4529
4530 if (tex->db_compatible) {
4531 if (!view->is_stencil_sampler)
4532 pipe_format = tex->db_render_format;
4533
4534 switch (pipe_format) {
4535 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4536 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4537 break;
4538 case PIPE_FORMAT_X8Z24_UNORM:
4539 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4540 /* Z24 is always stored like this for DB
4541 * compatibility.
4542 */
4543 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4544 break;
4545 case PIPE_FORMAT_X24S8_UINT:
4546 case PIPE_FORMAT_S8X24_UINT:
4547 case PIPE_FORMAT_X32_S8X24_UINT:
4548 pipe_format = PIPE_FORMAT_S8_UINT;
4549 surflevel = tex->surface.u.legacy.stencil_level;
4550 break;
4551 default:;
4552 }
4553 }
4554
4555 view->dcc_incompatible =
4556 vi_dcc_formats_are_incompatible(texture,
4557 state->u.tex.first_level,
4558 state->format);
4559
4560 sctx->screen->make_texture_descriptor(sctx->screen, tex, true,
4561 state->target, pipe_format, state_swizzle,
4562 first_level, last_level,
4563 state->u.tex.first_layer, last_layer,
4564 width, height, depth,
4565 view->state, view->fmask_state);
4566
4567 const struct util_format_description *desc = util_format_description(pipe_format);
4568 view->is_integer = false;
4569
4570 for (unsigned i = 0; i < desc->nr_channels; ++i) {
4571 if (desc->channel[i].type == UTIL_FORMAT_TYPE_VOID)
4572 continue;
4573
4574 /* Whether the number format is {U,S}{SCALED,INT} */
4575 view->is_integer =
4576 (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
4577 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) &&
4578 (desc->channel[i].pure_integer || !desc->channel[i].normalized);
4579 break;
4580 }
4581
4582 view->base_level_info = &surflevel[base_level];
4583 view->base_level = base_level;
4584 view->block_width = util_format_get_blockwidth(pipe_format);
4585 return &view->base;
4586 }
4587
4588 static struct pipe_sampler_view *
4589 si_create_sampler_view(struct pipe_context *ctx,
4590 struct pipe_resource *texture,
4591 const struct pipe_sampler_view *state)
4592 {
4593 return si_create_sampler_view_custom(ctx, texture, state,
4594 texture ? texture->width0 : 0,
4595 texture ? texture->height0 : 0, 0);
4596 }
4597
4598 static void si_sampler_view_destroy(struct pipe_context *ctx,
4599 struct pipe_sampler_view *state)
4600 {
4601 struct si_sampler_view *view = (struct si_sampler_view *)state;
4602
4603 pipe_resource_reference(&state->texture, NULL);
4604 FREE(view);
4605 }
4606
4607 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4608 {
4609 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4610 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4611 (linear_filter &&
4612 (wrap == PIPE_TEX_WRAP_CLAMP ||
4613 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4614 }
4615
4616 static uint32_t si_translate_border_color(struct si_context *sctx,
4617 const struct pipe_sampler_state *state,
4618 const union pipe_color_union *color,
4619 bool is_integer)
4620 {
4621 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4622 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4623
4624 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4625 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4626 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4627 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4628
4629 #define simple_border_types(elt) \
4630 do { \
4631 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4632 color->elt[2] == 0 && color->elt[3] == 0) \
4633 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4634 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4635 color->elt[2] == 0 && color->elt[3] == 1) \
4636 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4637 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4638 color->elt[2] == 1 && color->elt[3] == 1) \
4639 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4640 } while (false)
4641
4642 if (is_integer)
4643 simple_border_types(ui);
4644 else
4645 simple_border_types(f);
4646
4647 #undef simple_border_types
4648
4649 int i;
4650
4651 /* Check if the border has been uploaded already. */
4652 for (i = 0; i < sctx->border_color_count; i++)
4653 if (memcmp(&sctx->border_color_table[i], color,
4654 sizeof(*color)) == 0)
4655 break;
4656
4657 if (i >= SI_MAX_BORDER_COLORS) {
4658 /* Getting 4096 unique border colors is very unlikely. */
4659 fprintf(stderr, "radeonsi: The border color table is full. "
4660 "Any new border colors will be just black. "
4661 "Please file a bug.\n");
4662 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4663 }
4664
4665 if (i == sctx->border_color_count) {
4666 /* Upload a new border color. */
4667 memcpy(&sctx->border_color_table[i], color,
4668 sizeof(*color));
4669 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4670 color, sizeof(*color));
4671 sctx->border_color_count++;
4672 }
4673
4674 return S_008F3C_BORDER_COLOR_PTR(i) |
4675 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4676 }
4677
4678 static inline int S_FIXED(float value, unsigned frac_bits)
4679 {
4680 return value * (1 << frac_bits);
4681 }
4682
4683 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4684 {
4685 if (filter == PIPE_TEX_FILTER_LINEAR)
4686 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4687 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4688 else
4689 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4690 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4691 }
4692
4693 static inline unsigned si_tex_aniso_filter(unsigned filter)
4694 {
4695 if (filter < 2)
4696 return 0;
4697 if (filter < 4)
4698 return 1;
4699 if (filter < 8)
4700 return 2;
4701 if (filter < 16)
4702 return 3;
4703 return 4;
4704 }
4705
4706 static void *si_create_sampler_state(struct pipe_context *ctx,
4707 const struct pipe_sampler_state *state)
4708 {
4709 struct si_context *sctx = (struct si_context *)ctx;
4710 struct si_screen *sscreen = sctx->screen;
4711 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4712 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4713 : state->max_anisotropy;
4714 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4715 union pipe_color_union clamped_border_color;
4716
4717 if (!rstate) {
4718 return NULL;
4719 }
4720
4721 #ifndef NDEBUG
4722 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4723 #endif
4724 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4725 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4726 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4727 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4728 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4729 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4730 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4731 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4732 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4733 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4734 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4735 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4736 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4737 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4738 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4739 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4740 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4741 S_008F38_MIP_POINT_PRECLAMP(0));
4742 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4743
4744 if (sscreen->info.chip_class >= GFX10) {
4745 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4746 } else {
4747 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4748 S_008F38_FILTER_PREC_FIX(1) |
4749 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8);
4750 }
4751
4752 /* Create sampler resource for integer textures. */
4753 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4754 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4755
4756 /* Create sampler resource for upgraded depth textures. */
4757 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4758
4759 for (unsigned i = 0; i < 4; ++i) {
4760 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4761 * when the border color is 1.0. */
4762 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4763 }
4764
4765 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4766 if (sscreen->info.chip_class <= GFX9)
4767 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4768 } else {
4769 rstate->upgraded_depth_val[3] =
4770 si_translate_border_color(sctx, state, &clamped_border_color, false);
4771 }
4772
4773 return rstate;
4774 }
4775
4776 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4777 {
4778 struct si_context *sctx = (struct si_context *)ctx;
4779
4780 if (sctx->sample_mask == (uint16_t)sample_mask)
4781 return;
4782
4783 sctx->sample_mask = sample_mask;
4784 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4785 }
4786
4787 static void si_emit_sample_mask(struct si_context *sctx)
4788 {
4789 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4790 unsigned mask = sctx->sample_mask;
4791
4792 /* Needed for line and polygon smoothing as well as for the Polaris
4793 * small primitive filter. We expect the state tracker to take care of
4794 * this for us.
4795 */
4796 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4797 (mask & 1 && sctx->blitter->running));
4798
4799 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4800 radeon_emit(cs, mask | (mask << 16));
4801 radeon_emit(cs, mask | (mask << 16));
4802 }
4803
4804 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4805 {
4806 #ifndef NDEBUG
4807 struct si_sampler_state *s = state;
4808
4809 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4810 s->magic = 0;
4811 #endif
4812 free(state);
4813 }
4814
4815 /*
4816 * Vertex elements & buffers
4817 */
4818
4819 struct si_fast_udiv_info32
4820 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4821 {
4822 struct util_fast_udiv_info info =
4823 util_compute_fast_udiv_info(D, num_bits, 32);
4824
4825 struct si_fast_udiv_info32 result = {
4826 info.multiplier,
4827 info.pre_shift,
4828 info.post_shift,
4829 info.increment,
4830 };
4831 return result;
4832 }
4833
4834 static void *si_create_vertex_elements(struct pipe_context *ctx,
4835 unsigned count,
4836 const struct pipe_vertex_element *elements)
4837 {
4838 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4839 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4840 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4841 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4842 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4843 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4844 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4845 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4846 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4847 int i;
4848
4849 assert(count <= SI_MAX_ATTRIBS);
4850 if (!v)
4851 return NULL;
4852
4853 v->count = count;
4854 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4855
4856 for (i = 0; i < count; ++i) {
4857 const struct util_format_description *desc;
4858 const struct util_format_channel_description *channel;
4859 int first_non_void;
4860 unsigned vbo_index = elements[i].vertex_buffer_index;
4861
4862 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4863 FREE(v);
4864 return NULL;
4865 }
4866
4867 unsigned instance_divisor = elements[i].instance_divisor;
4868 if (instance_divisor) {
4869 v->uses_instance_divisors = true;
4870
4871 if (instance_divisor == 1) {
4872 v->instance_divisor_is_one |= 1u << i;
4873 } else {
4874 v->instance_divisor_is_fetched |= 1u << i;
4875 divisor_factors[i] =
4876 si_compute_fast_udiv_info32(instance_divisor, 32);
4877 }
4878 }
4879
4880 if (!used[vbo_index]) {
4881 v->first_vb_use_mask |= 1 << i;
4882 used[vbo_index] = true;
4883 }
4884
4885 desc = util_format_description(elements[i].src_format);
4886 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4887 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4888
4889 v->format_size[i] = desc->block.bits / 8;
4890 v->src_offset[i] = elements[i].src_offset;
4891 v->vertex_buffer_index[i] = vbo_index;
4892
4893 bool always_fix = false;
4894 union si_vs_fix_fetch fix_fetch;
4895 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4896
4897 fix_fetch.bits = 0;
4898 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4899
4900 if (channel) {
4901 switch (channel->type) {
4902 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4903 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4904 case UTIL_FORMAT_TYPE_SIGNED: {
4905 if (channel->pure_integer)
4906 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4907 else if (channel->normalized)
4908 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4909 else
4910 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4911 break;
4912 }
4913 case UTIL_FORMAT_TYPE_UNSIGNED: {
4914 if (channel->pure_integer)
4915 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4916 else if (channel->normalized)
4917 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4918 else
4919 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4920 break;
4921 }
4922 default: unreachable("bad format type");
4923 }
4924 } else {
4925 switch (elements[i].src_format) {
4926 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4927 default: unreachable("bad other format");
4928 }
4929 }
4930
4931 if (desc->channel[0].size == 10) {
4932 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4933 log_hw_load_size = 2;
4934
4935 /* The hardware always treats the 2-bit alpha channel as
4936 * unsigned, so a shader workaround is needed. The affected
4937 * chips are GFX8 and older except Stoney (GFX8.1).
4938 */
4939 always_fix = sscreen->info.chip_class <= GFX8 &&
4940 sscreen->info.family != CHIP_STONEY &&
4941 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4942 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4943 fix_fetch.u.log_size = 3; /* special encoding */
4944 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4945 log_hw_load_size = 2;
4946 } else {
4947 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4948 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4949
4950 /* Always fix up:
4951 * - doubles (multiple loads + truncate to float)
4952 * - 32-bit requiring a conversion
4953 */
4954 always_fix =
4955 (fix_fetch.u.log_size == 3) ||
4956 (fix_fetch.u.log_size == 2 &&
4957 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4958 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4959 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4960
4961 /* Also fixup 8_8_8 and 16_16_16. */
4962 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4963 always_fix = true;
4964 log_hw_load_size = fix_fetch.u.log_size;
4965 }
4966 }
4967
4968 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4969 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4970 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4971 fix_fetch.u.reverse = 1;
4972 }
4973
4974 /* Force the workaround for unaligned access here already if the
4975 * offset relative to the vertex buffer base is unaligned.
4976 *
4977 * There is a theoretical case in which this is too conservative:
4978 * if the vertex buffer's offset is also unaligned in just the
4979 * right way, we end up with an aligned address after all.
4980 * However, this case should be extremely rare in practice (it
4981 * won't happen in well-behaved applications), and taking it
4982 * into account would complicate the fast path (where everything
4983 * is nicely aligned).
4984 */
4985 bool check_alignment =
4986 log_hw_load_size >= 1 &&
4987 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
4988 bool opencode = sscreen->options.vs_fetch_always_opencode;
4989
4990 if (check_alignment &&
4991 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4992 opencode = true;
4993
4994 if (always_fix || check_alignment || opencode)
4995 v->fix_fetch[i] = fix_fetch.bits;
4996
4997 if (opencode)
4998 v->fix_fetch_opencode |= 1 << i;
4999 if (opencode || always_fix)
5000 v->fix_fetch_always |= 1 << i;
5001
5002 if (check_alignment && !opencode) {
5003 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
5004
5005 v->fix_fetch_unaligned |= 1 << i;
5006 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
5007 v->vb_alignment_check_mask |= 1 << vbo_index;
5008 }
5009
5010 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
5011 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
5012 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
5013 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
5014
5015 if (sscreen->info.chip_class >= GFX10) {
5016 const struct gfx10_format *fmt =
5017 &gfx10_format_table[elements[i].src_format];
5018 assert(fmt->img_format != 0 && fmt->img_format < 128);
5019 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
5020 S_008F0C_RESOURCE_LEVEL(1);
5021 } else {
5022 unsigned data_format, num_format;
5023 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
5024 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
5025 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
5026 S_008F0C_DATA_FORMAT(data_format);
5027 }
5028 }
5029
5030 if (v->instance_divisor_is_fetched) {
5031 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
5032
5033 v->instance_divisor_factor_buffer =
5034 (struct si_resource*)
5035 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
5036 num_divisors * sizeof(divisor_factors[0]));
5037 if (!v->instance_divisor_factor_buffer) {
5038 FREE(v);
5039 return NULL;
5040 }
5041 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
5042 NULL, PIPE_TRANSFER_WRITE);
5043 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
5044 }
5045 return v;
5046 }
5047
5048 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5049 {
5050 struct si_context *sctx = (struct si_context *)ctx;
5051 struct si_vertex_elements *old = sctx->vertex_elements;
5052 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5053
5054 sctx->vertex_elements = v;
5055 sctx->vertex_buffers_dirty = true;
5056
5057 if (v &&
5058 (!old ||
5059 old->count != v->count ||
5060 old->uses_instance_divisors != v->uses_instance_divisors ||
5061 /* we don't check which divisors changed */
5062 v->uses_instance_divisors ||
5063 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
5064 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5065 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
5066 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
5067 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5068 * functions of fix_fetch and the src_offset alignment.
5069 * If they change and fix_fetch doesn't, it must be due to different
5070 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5071 old->fix_fetch_opencode != v->fix_fetch_opencode ||
5072 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
5073 sctx->do_update_shaders = true;
5074
5075 if (v && v->instance_divisor_is_fetched) {
5076 struct pipe_constant_buffer cb;
5077
5078 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5079 cb.user_buffer = NULL;
5080 cb.buffer_offset = 0;
5081 cb.buffer_size = 0xffffffff;
5082 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5083 }
5084 }
5085
5086 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5087 {
5088 struct si_context *sctx = (struct si_context *)ctx;
5089 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5090
5091 if (sctx->vertex_elements == state)
5092 sctx->vertex_elements = NULL;
5093 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
5094 FREE(state);
5095 }
5096
5097 static void si_set_vertex_buffers(struct pipe_context *ctx,
5098 unsigned start_slot, unsigned count,
5099 const struct pipe_vertex_buffer *buffers)
5100 {
5101 struct si_context *sctx = (struct si_context *)ctx;
5102 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5103 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5104 uint32_t unaligned = orig_unaligned;
5105 int i;
5106
5107 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
5108
5109 if (buffers) {
5110 for (i = 0; i < count; i++) {
5111 const struct pipe_vertex_buffer *src = buffers + i;
5112 struct pipe_vertex_buffer *dsti = dst + i;
5113 struct pipe_resource *buf = src->buffer.resource;
5114
5115 pipe_resource_reference(&dsti->buffer.resource, buf);
5116 dsti->buffer_offset = src->buffer_offset;
5117 dsti->stride = src->stride;
5118 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5119 unaligned |= 1 << (start_slot + i);
5120 else
5121 unaligned &= ~(1 << (start_slot + i));
5122
5123 si_context_add_resource_size(sctx, buf);
5124 if (buf)
5125 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
5126 }
5127 } else {
5128 for (i = 0; i < count; i++) {
5129 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5130 }
5131 unaligned &= ~u_bit_consecutive(start_slot, count);
5132 }
5133 sctx->vertex_buffers_dirty = true;
5134 sctx->vertex_buffer_unaligned = unaligned;
5135
5136 /* Check whether alignment may have changed in a way that requires
5137 * shader changes. This check is conservative: a vertex buffer can only
5138 * trigger a shader change if the misalignment amount changes (e.g.
5139 * from byte-aligned to short-aligned), but we only keep track of
5140 * whether buffers are at least dword-aligned, since that should always
5141 * be the case in well-behaved applications anyway.
5142 */
5143 if (sctx->vertex_elements &&
5144 (sctx->vertex_elements->vb_alignment_check_mask &
5145 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
5146 sctx->do_update_shaders = true;
5147 }
5148
5149 /*
5150 * Misc
5151 */
5152
5153 static void si_set_tess_state(struct pipe_context *ctx,
5154 const float default_outer_level[4],
5155 const float default_inner_level[2])
5156 {
5157 struct si_context *sctx = (struct si_context *)ctx;
5158 struct pipe_constant_buffer cb;
5159 float array[8];
5160
5161 memcpy(array, default_outer_level, sizeof(float) * 4);
5162 memcpy(array+4, default_inner_level, sizeof(float) * 2);
5163
5164 cb.buffer = NULL;
5165 cb.user_buffer = NULL;
5166 cb.buffer_size = sizeof(array);
5167
5168 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
5169 (void*)array, sizeof(array),
5170 &cb.buffer_offset);
5171
5172 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5173 pipe_resource_reference(&cb.buffer, NULL);
5174 }
5175
5176 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5177 {
5178 struct si_context *sctx = (struct si_context *)ctx;
5179
5180 si_update_fb_dirtiness_after_rendering(sctx);
5181
5182 /* Multisample surfaces are flushed in si_decompress_textures. */
5183 if (sctx->framebuffer.uncompressed_cb_mask) {
5184 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5185 sctx->framebuffer.CB_has_shader_readable_metadata,
5186 sctx->framebuffer.all_DCC_pipe_aligned);
5187 }
5188 }
5189
5190 /* This only ensures coherency for shader image/buffer stores. */
5191 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5192 {
5193 struct si_context *sctx = (struct si_context *)ctx;
5194
5195 if (!(flags & ~PIPE_BARRIER_UPDATE))
5196 return;
5197
5198 /* Subsequent commands must wait for all shader invocations to
5199 * complete. */
5200 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
5201 SI_CONTEXT_CS_PARTIAL_FLUSH;
5202
5203 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5204 sctx->flags |= SI_CONTEXT_INV_SCACHE |
5205 SI_CONTEXT_INV_VCACHE;
5206
5207 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
5208 PIPE_BARRIER_SHADER_BUFFER |
5209 PIPE_BARRIER_TEXTURE |
5210 PIPE_BARRIER_IMAGE |
5211 PIPE_BARRIER_STREAMOUT_BUFFER |
5212 PIPE_BARRIER_GLOBAL_BUFFER)) {
5213 /* As far as I can tell, L1 contents are written back to L2
5214 * automatically at end of shader, but the contents of other
5215 * L1 caches might still be stale. */
5216 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5217 }
5218
5219 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5220 /* Indices are read through TC L2 since GFX8.
5221 * L1 isn't used.
5222 */
5223 if (sctx->screen->info.chip_class <= GFX7)
5224 sctx->flags |= SI_CONTEXT_WB_L2;
5225 }
5226
5227 /* MSAA color, any depth and any stencil are flushed in
5228 * si_decompress_textures when needed.
5229 */
5230 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
5231 sctx->framebuffer.uncompressed_cb_mask) {
5232 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5233
5234 if (sctx->chip_class <= GFX8)
5235 sctx->flags |= SI_CONTEXT_WB_L2;
5236 }
5237
5238 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5239 if (sctx->screen->info.chip_class <= GFX8 &&
5240 flags & PIPE_BARRIER_INDIRECT_BUFFER)
5241 sctx->flags |= SI_CONTEXT_WB_L2;
5242 }
5243
5244 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5245 {
5246 struct pipe_blend_state blend;
5247
5248 memset(&blend, 0, sizeof(blend));
5249 blend.independent_blend_enable = true;
5250 blend.rt[0].colormask = 0xf;
5251 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5252 }
5253
5254 static void si_init_config(struct si_context *sctx);
5255
5256 void si_init_state_compute_functions(struct si_context *sctx)
5257 {
5258 sctx->b.create_sampler_state = si_create_sampler_state;
5259 sctx->b.delete_sampler_state = si_delete_sampler_state;
5260 sctx->b.create_sampler_view = si_create_sampler_view;
5261 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5262 sctx->b.memory_barrier = si_memory_barrier;
5263 }
5264
5265 void si_init_state_functions(struct si_context *sctx)
5266 {
5267 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5268 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5269 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5270 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5271 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5272 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5273 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5274 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5275 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5276 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5277 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5278
5279 sctx->b.create_blend_state = si_create_blend_state;
5280 sctx->b.bind_blend_state = si_bind_blend_state;
5281 sctx->b.delete_blend_state = si_delete_blend_state;
5282 sctx->b.set_blend_color = si_set_blend_color;
5283
5284 sctx->b.create_rasterizer_state = si_create_rs_state;
5285 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5286 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5287
5288 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5289 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5290 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5291
5292 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5293 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5294 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5295 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5296 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5297
5298 sctx->b.set_clip_state = si_set_clip_state;
5299 sctx->b.set_stencil_ref = si_set_stencil_ref;
5300
5301 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5302
5303 sctx->b.set_sample_mask = si_set_sample_mask;
5304
5305 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5306 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5307 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5308 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5309
5310 sctx->b.texture_barrier = si_texture_barrier;
5311 sctx->b.set_min_samples = si_set_min_samples;
5312 sctx->b.set_tess_state = si_set_tess_state;
5313
5314 sctx->b.set_active_query_state = si_set_active_query_state;
5315
5316 si_init_config(sctx);
5317 }
5318
5319 void si_init_screen_state_functions(struct si_screen *sscreen)
5320 {
5321 sscreen->b.is_format_supported = si_is_format_supported;
5322
5323 if (sscreen->info.chip_class >= GFX10) {
5324 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5325 } else {
5326 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5327 }
5328 }
5329
5330 static void si_set_grbm_gfx_index(struct si_context *sctx,
5331 struct si_pm4_state *pm4, unsigned value)
5332 {
5333 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
5334 R_00802C_GRBM_GFX_INDEX;
5335 si_pm4_set_reg(pm4, reg, value);
5336 }
5337
5338 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
5339 struct si_pm4_state *pm4, unsigned se)
5340 {
5341 assert(se == ~0 || se < sctx->screen->info.max_se);
5342 si_set_grbm_gfx_index(sctx, pm4,
5343 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5344 S_030800_SE_INDEX(se)) |
5345 S_030800_SH_BROADCAST_WRITES(1) |
5346 S_030800_INSTANCE_BROADCAST_WRITES(1));
5347 }
5348
5349 static void
5350 si_write_harvested_raster_configs(struct si_context *sctx,
5351 struct si_pm4_state *pm4,
5352 unsigned raster_config,
5353 unsigned raster_config_1)
5354 {
5355 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5356 unsigned raster_config_se[4];
5357 unsigned se;
5358
5359 ac_get_harvested_configs(&sctx->screen->info,
5360 raster_config,
5361 &raster_config_1,
5362 raster_config_se);
5363
5364 for (se = 0; se < num_se; se++) {
5365 si_set_grbm_gfx_index_se(sctx, pm4, se);
5366 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5367 }
5368 si_set_grbm_gfx_index(sctx, pm4, ~0);
5369
5370 if (sctx->chip_class >= GFX7) {
5371 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5372 }
5373 }
5374
5375 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5376 {
5377 struct si_screen *sscreen = sctx->screen;
5378 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
5379 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5380 unsigned raster_config = sscreen->pa_sc_raster_config;
5381 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5382
5383 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5384 /* Always use the default config when all backends are enabled
5385 * (or when we failed to determine the enabled backends).
5386 */
5387 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5388 raster_config);
5389 if (sctx->chip_class >= GFX7)
5390 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5391 raster_config_1);
5392 } else {
5393 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5394 }
5395 }
5396
5397 static void si_init_config(struct si_context *sctx)
5398 {
5399 struct si_screen *sscreen = sctx->screen;
5400 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5401 bool has_clear_state = sscreen->has_clear_state;
5402 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5403
5404 if (!pm4)
5405 return;
5406
5407 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5408 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5409 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5410 si_pm4_cmd_end(pm4, false);
5411
5412 if (has_clear_state) {
5413 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5414 si_pm4_cmd_add(pm4, 0);
5415 si_pm4_cmd_end(pm4, false);
5416 }
5417
5418 if (sctx->chip_class <= GFX8)
5419 si_set_raster_config(sctx, pm4);
5420
5421 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5422 if (!has_clear_state)
5423 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5424
5425 /* FIXME calculate these values somehow ??? */
5426 if (sctx->chip_class <= GFX8) {
5427 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5428 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5429 }
5430
5431 if (!has_clear_state) {
5432 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5433 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5434 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5435 }
5436
5437 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5438 if (!has_clear_state)
5439 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5440 if (sctx->chip_class < GFX7)
5441 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5442 S_008A14_CLIP_VTX_REORDER_ENA(1));
5443
5444 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5445 * I don't know why. Deduced by trial and error.
5446 */
5447 if (sctx->chip_class <= GFX7) {
5448 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5449 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5450 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5451 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5452 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5453 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5454 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5455 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5456 }
5457
5458 if (!has_clear_state) {
5459 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5460 S_028230_ER_TRI(0xA) |
5461 S_028230_ER_POINT(0xA) |
5462 S_028230_ER_RECT(0xA) |
5463 /* Required by DX10_DIAMOND_TEST_ENA: */
5464 S_028230_ER_LINE_LR(0x1A) |
5465 S_028230_ER_LINE_RL(0x26) |
5466 S_028230_ER_LINE_TB(0xA) |
5467 S_028230_ER_LINE_BT(0xA));
5468 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5469 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5470 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5471 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5472 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5473 }
5474
5475 if (sctx->chip_class >= GFX10) {
5476 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
5477 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5478 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5479 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5480 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
5481 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
5482 } else if (sctx->chip_class == GFX9) {
5483 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5484 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5485 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5486 } else {
5487 /* These registers, when written, also overwrite the CLEAR_STATE
5488 * context, so we can't rely on CLEAR_STATE setting them.
5489 * It would be an issue if there was another UMD changing them.
5490 */
5491 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5492 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5493 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5494 }
5495
5496 if (sctx->chip_class >= GFX7) {
5497 if (sctx->chip_class >= GFX10) {
5498 /* Logical CUs 16 - 31 */
5499 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
5500 S_00B404_CU_EN(0xffff));
5501 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
5502 S_00B104_CU_EN(0xffff));
5503 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
5504 S_00B004_CU_EN(0xffff));
5505 }
5506
5507 if (sctx->chip_class >= GFX9) {
5508 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5509 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5510 } else {
5511 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5512 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5513 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5514 S_00B41C_WAVE_LIMIT(0x3F));
5515 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5516 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5517
5518 /* If this is 0, Bonaire can hang even if GS isn't being used.
5519 * Other chips are unaffected. These are suboptimal values,
5520 * but we don't use on-chip GS.
5521 */
5522 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5523 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5524 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5525 }
5526
5527 /* Compute LATE_ALLOC_VS.LIMIT. */
5528 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5529 unsigned late_alloc_limit; /* The limit is per SH. */
5530
5531 if (sctx->family == CHIP_KABINI) {
5532 late_alloc_limit = 0; /* Potential hang on Kabini. */
5533 } else if (num_cu_per_sh <= 4) {
5534 /* Too few available compute units per SH. Disallowing
5535 * VS to run on one CU could hurt us more than late VS
5536 * allocation would help.
5537 *
5538 * 2 is the highest safe number that allows us to keep
5539 * all CUs enabled.
5540 */
5541 late_alloc_limit = 2;
5542 } else {
5543 /* This is a good initial value, allowing 1 late_alloc
5544 * wave per SIMD on num_cu - 2.
5545 */
5546 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5547 }
5548
5549 unsigned cu_mask_vs = 0xffff;
5550 unsigned cu_mask_gs = 0xffff;
5551
5552 if (late_alloc_limit > 2) {
5553 if (sctx->chip_class >= GFX10) {
5554 /* CU2 & CU3 disabled because of the dual CU design */
5555 cu_mask_vs = 0xfff3;
5556 cu_mask_gs = 0xfff3; /* NGG only */
5557 } else {
5558 cu_mask_vs = 0xfffe; /* 1 CU disabled */
5559 }
5560 }
5561
5562 /* VS can't execute on one CU if the limit is > 2. */
5563 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5564 S_00B118_CU_EN(cu_mask_vs) |
5565 S_00B118_WAVE_LIMIT(0x3F));
5566 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5567 S_00B11C_LIMIT(late_alloc_limit));
5568
5569 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5570 S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
5571
5572 if (sctx->chip_class >= GFX10) {
5573 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
5574 S_00B204_CU_EN(0xffff) |
5575 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit));
5576 }
5577
5578 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5579 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5580 }
5581
5582 if (sctx->chip_class >= GFX10) {
5583 /* Break up a pixel wave if it contains deallocs for more than
5584 * half the parameter cache.
5585 *
5586 * To avoid a deadlock where pixel waves aren't launched
5587 * because they're waiting for more pixels while the frontend
5588 * is stuck waiting for PC space, the maximum allowed value is
5589 * the size of the PC minus the largest possible allocation for
5590 * a single primitive shader subgroup.
5591 */
5592 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5593 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5594 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5595 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5596 sscreen->info.pa_sc_tile_steering_override);
5597
5598 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5599 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5600 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5601 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5602 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5603 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5604 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5605 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
5606
5607 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5608 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5609 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5610 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5611 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5612 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5613 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5614 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
5615 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
5616 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
5617
5618 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
5619 S_00B0C0_SOFT_GROUPING_EN(1) |
5620 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5621 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
5622
5623 }
5624
5625 if (sctx->chip_class >= GFX8) {
5626 unsigned vgt_tess_distribution;
5627
5628 vgt_tess_distribution =
5629 S_028B50_ACCUM_ISOLINE(32) |
5630 S_028B50_ACCUM_TRI(11) |
5631 S_028B50_ACCUM_QUAD(11) |
5632 S_028B50_DONUT_SPLIT(16);
5633
5634 /* Testing with Unigine Heaven extreme tesselation yielded best results
5635 * with TRAP_SPLIT = 3.
5636 */
5637 if (sctx->family == CHIP_FIJI ||
5638 sctx->family >= CHIP_POLARIS10)
5639 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5640
5641 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5642 } else if (!has_clear_state) {
5643 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5644 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5645 }
5646
5647 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5648 if (sctx->chip_class >= GFX7) {
5649 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5650 S_028084_ADDRESS(border_color_va >> 40));
5651 }
5652 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5653 RADEON_PRIO_BORDER_COLORS);
5654
5655 if (sctx->chip_class >= GFX9) {
5656 unsigned num_se = sscreen->info.max_se;
5657 unsigned pc_lines = 0;
5658 unsigned max_alloc_count = 0;
5659
5660 switch (sctx->family) {
5661 case CHIP_VEGA10:
5662 case CHIP_VEGA12:
5663 case CHIP_VEGA20:
5664 pc_lines = 2048;
5665 break;
5666 case CHIP_RAVEN:
5667 case CHIP_RAVEN2:
5668 case CHIP_NAVI10:
5669 case CHIP_NAVI12:
5670 pc_lines = 1024;
5671 break;
5672 case CHIP_NAVI14:
5673 pc_lines = 512;
5674 break;
5675 default:
5676 assert(0);
5677 }
5678
5679 if (sctx->chip_class >= GFX10) {
5680 max_alloc_count = pc_lines / 3;
5681 } else {
5682 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
5683 }
5684
5685 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5686 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
5687 S_028C48_MAX_PRIM_PER_BATCH(1023));
5688 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5689 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5690 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5691 }
5692
5693 si_pm4_upload_indirect_buffer(sctx, pm4);
5694 sctx->init_config = pm4;
5695 }