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r600g,radeonsi: set priorities for relocations
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "../radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_helpers.h"
38 #include "util/u_memory.h"
39
40 static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split)
41 {
42 if (sscreen->b.info.cik_macrotile_mode_array_valid) {
43 unsigned index, tileb;
44
45 tileb = 8 * 8 * bpe;
46 tileb = MIN2(tile_split, tileb);
47
48 for (index = 0; tileb > 64; index++) {
49 tileb >>= 1;
50 }
51
52 assert(index < 16);
53
54 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
55 }
56
57 /* The old way. */
58 switch (sscreen->b.tiling_info.num_banks) {
59 case 2:
60 return V_02803C_ADDR_SURF_2_BANK;
61 case 4:
62 return V_02803C_ADDR_SURF_4_BANK;
63 case 8:
64 default:
65 return V_02803C_ADDR_SURF_8_BANK;
66 case 16:
67 return V_02803C_ADDR_SURF_16_BANK;
68 }
69 }
70
71 static unsigned cik_tile_split(unsigned tile_split)
72 {
73 switch (tile_split) {
74 case 64:
75 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
76 break;
77 case 128:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
79 break;
80 case 256:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
82 break;
83 case 512:
84 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
85 break;
86 default:
87 case 1024:
88 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
89 break;
90 case 2048:
91 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
92 break;
93 case 4096:
94 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
95 break;
96 }
97 return tile_split;
98 }
99
100 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
101 {
102 switch (macro_tile_aspect) {
103 default:
104 case 1:
105 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
106 break;
107 case 2:
108 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
109 break;
110 case 4:
111 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
112 break;
113 case 8:
114 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
115 break;
116 }
117 return macro_tile_aspect;
118 }
119
120 static unsigned cik_bank_wh(unsigned bankwh)
121 {
122 switch (bankwh) {
123 default:
124 case 1:
125 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
126 break;
127 case 2:
128 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
129 break;
130 case 4:
131 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
132 break;
133 case 8:
134 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
135 break;
136 }
137 return bankwh;
138 }
139
140 static unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
141 {
142 if (sscreen->b.info.si_tile_mode_array_valid) {
143 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
144
145 return G_009910_PIPE_CONFIG(gb_tile_mode);
146 }
147
148 /* This is probably broken for a lot of chips, but it's only used
149 * if the kernel cannot return the tile mode array for CIK. */
150 switch (sscreen->b.info.r600_num_tile_pipes) {
151 case 16:
152 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
153 case 8:
154 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
155 case 4:
156 default:
157 if (sscreen->b.info.r600_num_backends == 4)
158 return V_02803C_X_ADDR_SURF_P4_16X16;
159 else
160 return V_02803C_X_ADDR_SURF_P4_8X16;
161 case 2:
162 return V_02803C_ADDR_SURF_P2;
163 }
164 }
165
166 static unsigned si_map_swizzle(unsigned swizzle)
167 {
168 switch (swizzle) {
169 case UTIL_FORMAT_SWIZZLE_Y:
170 return V_008F0C_SQ_SEL_Y;
171 case UTIL_FORMAT_SWIZZLE_Z:
172 return V_008F0C_SQ_SEL_Z;
173 case UTIL_FORMAT_SWIZZLE_W:
174 return V_008F0C_SQ_SEL_W;
175 case UTIL_FORMAT_SWIZZLE_0:
176 return V_008F0C_SQ_SEL_0;
177 case UTIL_FORMAT_SWIZZLE_1:
178 return V_008F0C_SQ_SEL_1;
179 default: /* UTIL_FORMAT_SWIZZLE_X */
180 return V_008F0C_SQ_SEL_X;
181 }
182 }
183
184 static uint32_t S_FIXED(float value, uint32_t frac_bits)
185 {
186 return value * (1 << frac_bits);
187 }
188
189 /* 12.4 fixed-point */
190 static unsigned si_pack_float_12p4(float x)
191 {
192 return x <= 0 ? 0 :
193 x >= 4096 ? 0xffff : x * 16;
194 }
195
196 /*
197 * inferred framebuffer and blender state
198 */
199 static void si_update_fb_blend_state(struct si_context *sctx)
200 {
201 struct si_pm4_state *pm4;
202 struct si_state_blend *blend = sctx->queued.named.blend;
203 uint32_t mask;
204
205 if (blend == NULL)
206 return;
207
208 pm4 = si_pm4_alloc_state(sctx);
209 if (pm4 == NULL)
210 return;
211
212 mask = (1ULL << ((unsigned)sctx->framebuffer.nr_cbufs * 4)) - 1;
213 mask &= blend->cb_target_mask;
214 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
215
216 si_pm4_set_state(sctx, fb_blend, pm4);
217 }
218
219 /*
220 * Blender functions
221 */
222
223 static uint32_t si_translate_blend_function(int blend_func)
224 {
225 switch (blend_func) {
226 case PIPE_BLEND_ADD:
227 return V_028780_COMB_DST_PLUS_SRC;
228 case PIPE_BLEND_SUBTRACT:
229 return V_028780_COMB_SRC_MINUS_DST;
230 case PIPE_BLEND_REVERSE_SUBTRACT:
231 return V_028780_COMB_DST_MINUS_SRC;
232 case PIPE_BLEND_MIN:
233 return V_028780_COMB_MIN_DST_SRC;
234 case PIPE_BLEND_MAX:
235 return V_028780_COMB_MAX_DST_SRC;
236 default:
237 R600_ERR("Unknown blend function %d\n", blend_func);
238 assert(0);
239 break;
240 }
241 return 0;
242 }
243
244 static uint32_t si_translate_blend_factor(int blend_fact)
245 {
246 switch (blend_fact) {
247 case PIPE_BLENDFACTOR_ONE:
248 return V_028780_BLEND_ONE;
249 case PIPE_BLENDFACTOR_SRC_COLOR:
250 return V_028780_BLEND_SRC_COLOR;
251 case PIPE_BLENDFACTOR_SRC_ALPHA:
252 return V_028780_BLEND_SRC_ALPHA;
253 case PIPE_BLENDFACTOR_DST_ALPHA:
254 return V_028780_BLEND_DST_ALPHA;
255 case PIPE_BLENDFACTOR_DST_COLOR:
256 return V_028780_BLEND_DST_COLOR;
257 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
258 return V_028780_BLEND_SRC_ALPHA_SATURATE;
259 case PIPE_BLENDFACTOR_CONST_COLOR:
260 return V_028780_BLEND_CONSTANT_COLOR;
261 case PIPE_BLENDFACTOR_CONST_ALPHA:
262 return V_028780_BLEND_CONSTANT_ALPHA;
263 case PIPE_BLENDFACTOR_ZERO:
264 return V_028780_BLEND_ZERO;
265 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
266 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
267 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
268 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
269 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
270 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
271 case PIPE_BLENDFACTOR_INV_DST_COLOR:
272 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
273 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
274 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
275 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
276 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
277 case PIPE_BLENDFACTOR_SRC1_COLOR:
278 return V_028780_BLEND_SRC1_COLOR;
279 case PIPE_BLENDFACTOR_SRC1_ALPHA:
280 return V_028780_BLEND_SRC1_ALPHA;
281 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
282 return V_028780_BLEND_INV_SRC1_COLOR;
283 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
284 return V_028780_BLEND_INV_SRC1_ALPHA;
285 default:
286 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static void *si_create_blend_state_mode(struct pipe_context *ctx,
294 const struct pipe_blend_state *state,
295 unsigned mode)
296 {
297 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
298 struct si_pm4_state *pm4 = &blend->pm4;
299
300 uint32_t color_control = 0;
301
302 if (blend == NULL)
303 return NULL;
304
305 blend->alpha_to_one = state->alpha_to_one;
306
307 if (state->logicop_enable) {
308 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
309 } else {
310 color_control |= S_028808_ROP3(0xcc);
311 }
312
313 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
314 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
315 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
316 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
317 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
318 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
319
320 blend->cb_target_mask = 0;
321 for (int i = 0; i < 8; i++) {
322 /* state->rt entries > 0 only written if independent blending */
323 const int j = state->independent_blend_enable ? i : 0;
324
325 unsigned eqRGB = state->rt[j].rgb_func;
326 unsigned srcRGB = state->rt[j].rgb_src_factor;
327 unsigned dstRGB = state->rt[j].rgb_dst_factor;
328 unsigned eqA = state->rt[j].alpha_func;
329 unsigned srcA = state->rt[j].alpha_src_factor;
330 unsigned dstA = state->rt[j].alpha_dst_factor;
331
332 unsigned blend_cntl = 0;
333
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
336
337 if (!state->rt[j].blend_enable) {
338 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
339 continue;
340 }
341
342 blend_cntl |= S_028780_ENABLE(1);
343 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
344 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
345 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
346
347 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
348 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
349 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
350 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
351 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
352 }
353 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
354 }
355
356 if (blend->cb_target_mask) {
357 color_control |= S_028808_MODE(mode);
358 } else {
359 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
360 }
361 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
362
363 return blend;
364 }
365
366 static void *si_create_blend_state(struct pipe_context *ctx,
367 const struct pipe_blend_state *state)
368 {
369 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
370 }
371
372 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
373 {
374 struct si_context *sctx = (struct si_context *)ctx;
375 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
376 si_update_fb_blend_state(sctx);
377 }
378
379 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
380 {
381 struct si_context *sctx = (struct si_context *)ctx;
382 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
383 }
384
385 static void si_set_blend_color(struct pipe_context *ctx,
386 const struct pipe_blend_color *state)
387 {
388 struct si_context *sctx = (struct si_context *)ctx;
389 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
390
391 if (pm4 == NULL)
392 return;
393
394 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
395 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
396 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
397 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
398
399 si_pm4_set_state(sctx, blend_color, pm4);
400 }
401
402 /*
403 * Clipping, scissors and viewport
404 */
405
406 static void si_set_clip_state(struct pipe_context *ctx,
407 const struct pipe_clip_state *state)
408 {
409 struct si_context *sctx = (struct si_context *)ctx;
410 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
411 struct pipe_constant_buffer cb;
412
413 if (pm4 == NULL)
414 return;
415
416 for (int i = 0; i < 6; i++) {
417 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
418 fui(state->ucp[i][0]));
419 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
420 fui(state->ucp[i][1]));
421 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
422 fui(state->ucp[i][2]));
423 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
424 fui(state->ucp[i][3]));
425 }
426
427 cb.buffer = NULL;
428 cb.user_buffer = state->ucp;
429 cb.buffer_offset = 0;
430 cb.buffer_size = 4*4*8;
431 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
432 pipe_resource_reference(&cb.buffer, NULL);
433
434 si_pm4_set_state(sctx, clip, pm4);
435 }
436
437 static void si_set_scissor_states(struct pipe_context *ctx,
438 unsigned start_slot,
439 unsigned num_scissors,
440 const struct pipe_scissor_state *state)
441 {
442 struct si_context *sctx = (struct si_context *)ctx;
443 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
444
445 if (pm4 == NULL)
446 return;
447
448 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
449 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
450 S_028250_WINDOW_OFFSET_DISABLE(1));
451 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
452 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
453
454 si_pm4_set_state(sctx, scissor, pm4);
455 }
456
457 static void si_set_viewport_states(struct pipe_context *ctx,
458 unsigned start_slot,
459 unsigned num_viewports,
460 const struct pipe_viewport_state *state)
461 {
462 struct si_context *sctx = (struct si_context *)ctx;
463 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
464 struct si_pm4_state *pm4 = &viewport->pm4;
465
466 if (viewport == NULL)
467 return;
468
469 viewport->viewport = *state;
470 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
471 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
472 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
473 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
474 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
475 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
476
477 si_pm4_set_state(sctx, viewport, viewport);
478 }
479
480 /*
481 * inferred state between framebuffer and rasterizer
482 */
483 static void si_update_fb_rs_state(struct si_context *sctx)
484 {
485 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
486 struct si_pm4_state *pm4;
487 float offset_units;
488
489 if (!rs || !sctx->framebuffer.zsbuf)
490 return;
491
492 offset_units = sctx->queued.named.rasterizer->offset_units;
493 switch (sctx->framebuffer.zsbuf->texture->format) {
494 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
495 case PIPE_FORMAT_X8Z24_UNORM:
496 case PIPE_FORMAT_Z24X8_UNORM:
497 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
498 offset_units *= 2.0f;
499 break;
500 case PIPE_FORMAT_Z32_FLOAT:
501 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
502 offset_units *= 1.0f;
503 break;
504 case PIPE_FORMAT_Z16_UNORM:
505 offset_units *= 4.0f;
506 break;
507 default:
508 return;
509 }
510
511 pm4 = si_pm4_alloc_state(sctx);
512
513 if (pm4 == NULL)
514 return;
515
516 /* FIXME some of those reg can be computed with cso */
517 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
518 fui(sctx->queued.named.rasterizer->offset_scale));
519 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
520 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
521 fui(sctx->queued.named.rasterizer->offset_scale));
522 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
523
524 si_pm4_set_state(sctx, fb_rs, pm4);
525 }
526
527 /*
528 * Rasterizer
529 */
530
531 static uint32_t si_translate_fill(uint32_t func)
532 {
533 switch(func) {
534 case PIPE_POLYGON_MODE_FILL:
535 return V_028814_X_DRAW_TRIANGLES;
536 case PIPE_POLYGON_MODE_LINE:
537 return V_028814_X_DRAW_LINES;
538 case PIPE_POLYGON_MODE_POINT:
539 return V_028814_X_DRAW_POINTS;
540 default:
541 assert(0);
542 return V_028814_X_DRAW_POINTS;
543 }
544 }
545
546 static void *si_create_rs_state(struct pipe_context *ctx,
547 const struct pipe_rasterizer_state *state)
548 {
549 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
550 struct si_pm4_state *pm4 = &rs->pm4;
551 unsigned tmp;
552 unsigned prov_vtx = 1, polygon_dual_mode;
553 float psize_min, psize_max;
554
555 if (rs == NULL) {
556 return NULL;
557 }
558
559 rs->two_side = state->light_twoside;
560 rs->multisample_enable = state->multisample;
561 rs->clip_plane_enable = state->clip_plane_enable;
562 rs->line_stipple_enable = state->line_stipple_enable;
563
564 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
565 state->fill_back != PIPE_POLYGON_MODE_FILL);
566
567 if (state->flatshade_first)
568 prov_vtx = 0;
569
570 rs->flatshade = state->flatshade;
571 rs->sprite_coord_enable = state->sprite_coord_enable;
572 rs->pa_sc_line_stipple = state->line_stipple_enable ?
573 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
574 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
575 rs->pa_su_sc_mode_cntl =
576 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
577 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
578 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
579 S_028814_FACE(!state->front_ccw) |
580 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
581 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
582 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
583 S_028814_POLY_MODE(polygon_dual_mode) |
584 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
585 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
586 rs->pa_cl_clip_cntl =
587 S_028810_PS_UCP_MODE(3) |
588 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
589 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
590 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
591 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
592
593 /* offset */
594 rs->offset_units = state->offset_units;
595 rs->offset_scale = state->offset_scale * 12.0f;
596
597 tmp = S_0286D4_FLAT_SHADE_ENA(1);
598 if (state->sprite_coord_enable) {
599 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
600 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
601 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
602 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
603 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
604 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
605 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
606 }
607 }
608 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
609
610 /* point size 12.4 fixed point */
611 tmp = (unsigned)(state->point_size * 8.0);
612 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
613
614 if (state->point_size_per_vertex) {
615 psize_min = util_get_min_point_size(state);
616 psize_max = 8192;
617 } else {
618 /* Force the point size to be as if the vertex output was disabled. */
619 psize_min = state->point_size;
620 psize_max = state->point_size;
621 }
622 /* Divide by two, because 0.5 = 1 pixel. */
623 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
624 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
625 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
626
627 tmp = (unsigned)state->line_width * 8;
628 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
629 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
630 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
631 S_028A48_MSAA_ENABLE(state->multisample) |
632 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
633
634 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
635 S_028BE4_PIX_CENTER(state->half_pixel_center) |
636 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
637
638 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
639
640 return rs;
641 }
642
643 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
644 {
645 struct si_context *sctx = (struct si_context *)ctx;
646 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
647
648 if (state == NULL)
649 return;
650
651 // TODO
652 sctx->sprite_coord_enable = rs->sprite_coord_enable;
653 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
654 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
655
656 si_pm4_bind_state(sctx, rasterizer, rs);
657 si_update_fb_rs_state(sctx);
658 }
659
660 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
661 {
662 struct si_context *sctx = (struct si_context *)ctx;
663 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
664 }
665
666 /*
667 * infeered state between dsa and stencil ref
668 */
669 static void si_update_dsa_stencil_ref(struct si_context *sctx)
670 {
671 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
672 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
673 struct si_state_dsa *dsa = sctx->queued.named.dsa;
674
675 if (pm4 == NULL)
676 return;
677
678 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
679 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
680 S_028430_STENCILMASK(dsa->valuemask[0]) |
681 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
682 S_028430_STENCILOPVAL(1));
683 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
684 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
685 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
686 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
687 S_028434_STENCILOPVAL_BF(1));
688
689 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
690 }
691
692 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
693 const struct pipe_stencil_ref *state)
694 {
695 struct si_context *sctx = (struct si_context *)ctx;
696 sctx->stencil_ref = *state;
697 si_update_dsa_stencil_ref(sctx);
698 }
699
700
701 /*
702 * DSA
703 */
704
705 static uint32_t si_translate_stencil_op(int s_op)
706 {
707 switch (s_op) {
708 case PIPE_STENCIL_OP_KEEP:
709 return V_02842C_STENCIL_KEEP;
710 case PIPE_STENCIL_OP_ZERO:
711 return V_02842C_STENCIL_ZERO;
712 case PIPE_STENCIL_OP_REPLACE:
713 return V_02842C_STENCIL_REPLACE_TEST;
714 case PIPE_STENCIL_OP_INCR:
715 return V_02842C_STENCIL_ADD_CLAMP;
716 case PIPE_STENCIL_OP_DECR:
717 return V_02842C_STENCIL_SUB_CLAMP;
718 case PIPE_STENCIL_OP_INCR_WRAP:
719 return V_02842C_STENCIL_ADD_WRAP;
720 case PIPE_STENCIL_OP_DECR_WRAP:
721 return V_02842C_STENCIL_SUB_WRAP;
722 case PIPE_STENCIL_OP_INVERT:
723 return V_02842C_STENCIL_INVERT;
724 default:
725 R600_ERR("Unknown stencil op %d", s_op);
726 assert(0);
727 break;
728 }
729 return 0;
730 }
731
732 static void *si_create_dsa_state(struct pipe_context *ctx,
733 const struct pipe_depth_stencil_alpha_state *state)
734 {
735 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
736 struct si_pm4_state *pm4 = &dsa->pm4;
737 unsigned db_depth_control;
738 unsigned db_render_control;
739 uint32_t db_stencil_control = 0;
740
741 if (dsa == NULL) {
742 return NULL;
743 }
744
745 dsa->valuemask[0] = state->stencil[0].valuemask;
746 dsa->valuemask[1] = state->stencil[1].valuemask;
747 dsa->writemask[0] = state->stencil[0].writemask;
748 dsa->writemask[1] = state->stencil[1].writemask;
749
750 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
751 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
752 S_028800_ZFUNC(state->depth.func);
753
754 /* stencil */
755 if (state->stencil[0].enabled) {
756 db_depth_control |= S_028800_STENCIL_ENABLE(1);
757 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
758 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
759 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
760 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
761
762 if (state->stencil[1].enabled) {
763 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
764 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
765 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
766 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
767 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
768 }
769 }
770
771 /* alpha */
772 if (state->alpha.enabled) {
773 dsa->alpha_func = state->alpha.func;
774 dsa->alpha_ref = state->alpha.ref_value;
775
776 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
777 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
778 } else {
779 dsa->alpha_func = PIPE_FUNC_ALWAYS;
780 }
781
782 /* misc */
783 db_render_control = 0;
784 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
785 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
786 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
787
788 return dsa;
789 }
790
791 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
792 {
793 struct si_context *sctx = (struct si_context *)ctx;
794 struct si_state_dsa *dsa = state;
795
796 if (state == NULL)
797 return;
798
799 si_pm4_bind_state(sctx, dsa, dsa);
800 si_update_dsa_stencil_ref(sctx);
801 }
802
803 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
804 {
805 struct si_context *sctx = (struct si_context *)ctx;
806 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
807 }
808
809 static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth,
810 bool copy_stencil, int sample)
811 {
812 struct pipe_depth_stencil_alpha_state dsa;
813 struct si_state_dsa *state;
814
815 memset(&dsa, 0, sizeof(dsa));
816
817 state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
818 if (copy_depth || copy_stencil) {
819 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
820 S_028000_DEPTH_COPY(copy_depth) |
821 S_028000_STENCIL_COPY(copy_stencil) |
822 S_028000_COPY_CENTROID(1) |
823 S_028000_COPY_SAMPLE(sample));
824 } else {
825 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
826 S_028000_DEPTH_COMPRESS_DISABLE(1) |
827 S_028000_STENCIL_COMPRESS_DISABLE(1));
828 }
829
830 return state;
831 }
832
833 /*
834 * format translation
835 */
836 static uint32_t si_translate_colorformat(enum pipe_format format)
837 {
838 const struct util_format_description *desc = util_format_description(format);
839
840 #define HAS_SIZE(x,y,z,w) \
841 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
842 desc->channel[2].size == (z) && desc->channel[3].size == (w))
843
844 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
845 return V_028C70_COLOR_10_11_11;
846
847 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
848 return V_028C70_COLOR_INVALID;
849
850 switch (desc->nr_channels) {
851 case 1:
852 switch (desc->channel[0].size) {
853 case 8:
854 return V_028C70_COLOR_8;
855 case 16:
856 return V_028C70_COLOR_16;
857 case 32:
858 return V_028C70_COLOR_32;
859 }
860 break;
861 case 2:
862 if (desc->channel[0].size == desc->channel[1].size) {
863 switch (desc->channel[0].size) {
864 case 8:
865 return V_028C70_COLOR_8_8;
866 case 16:
867 return V_028C70_COLOR_16_16;
868 case 32:
869 return V_028C70_COLOR_32_32;
870 }
871 } else if (HAS_SIZE(8,24,0,0)) {
872 return V_028C70_COLOR_24_8;
873 } else if (HAS_SIZE(24,8,0,0)) {
874 return V_028C70_COLOR_8_24;
875 }
876 break;
877 case 3:
878 if (HAS_SIZE(5,6,5,0)) {
879 return V_028C70_COLOR_5_6_5;
880 } else if (HAS_SIZE(32,8,24,0)) {
881 return V_028C70_COLOR_X24_8_32_FLOAT;
882 }
883 break;
884 case 4:
885 if (desc->channel[0].size == desc->channel[1].size &&
886 desc->channel[0].size == desc->channel[2].size &&
887 desc->channel[0].size == desc->channel[3].size) {
888 switch (desc->channel[0].size) {
889 case 4:
890 return V_028C70_COLOR_4_4_4_4;
891 case 8:
892 return V_028C70_COLOR_8_8_8_8;
893 case 16:
894 return V_028C70_COLOR_16_16_16_16;
895 case 32:
896 return V_028C70_COLOR_32_32_32_32;
897 }
898 } else if (HAS_SIZE(5,5,5,1)) {
899 return V_028C70_COLOR_1_5_5_5;
900 } else if (HAS_SIZE(10,10,10,2)) {
901 return V_028C70_COLOR_2_10_10_10;
902 }
903 break;
904 }
905 return V_028C70_COLOR_INVALID;
906 }
907
908 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
909 {
910 if (SI_BIG_ENDIAN) {
911 switch(colorformat) {
912 /* 8-bit buffers. */
913 case V_028C70_COLOR_8:
914 return V_028C70_ENDIAN_NONE;
915
916 /* 16-bit buffers. */
917 case V_028C70_COLOR_5_6_5:
918 case V_028C70_COLOR_1_5_5_5:
919 case V_028C70_COLOR_4_4_4_4:
920 case V_028C70_COLOR_16:
921 case V_028C70_COLOR_8_8:
922 return V_028C70_ENDIAN_8IN16;
923
924 /* 32-bit buffers. */
925 case V_028C70_COLOR_8_8_8_8:
926 case V_028C70_COLOR_2_10_10_10:
927 case V_028C70_COLOR_8_24:
928 case V_028C70_COLOR_24_8:
929 case V_028C70_COLOR_16_16:
930 return V_028C70_ENDIAN_8IN32;
931
932 /* 64-bit buffers. */
933 case V_028C70_COLOR_16_16_16_16:
934 return V_028C70_ENDIAN_8IN16;
935
936 case V_028C70_COLOR_32_32:
937 return V_028C70_ENDIAN_8IN32;
938
939 /* 128-bit buffers. */
940 case V_028C70_COLOR_32_32_32_32:
941 return V_028C70_ENDIAN_8IN32;
942 default:
943 return V_028C70_ENDIAN_NONE; /* Unsupported. */
944 }
945 } else {
946 return V_028C70_ENDIAN_NONE;
947 }
948 }
949
950 /* Returns the size in bits of the widest component of a CB format */
951 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
952 {
953 switch(colorformat) {
954 case V_028C70_COLOR_4_4_4_4:
955 return 4;
956
957 case V_028C70_COLOR_1_5_5_5:
958 case V_028C70_COLOR_5_5_5_1:
959 return 5;
960
961 case V_028C70_COLOR_5_6_5:
962 return 6;
963
964 case V_028C70_COLOR_8:
965 case V_028C70_COLOR_8_8:
966 case V_028C70_COLOR_8_8_8_8:
967 return 8;
968
969 case V_028C70_COLOR_10_10_10_2:
970 case V_028C70_COLOR_2_10_10_10:
971 return 10;
972
973 case V_028C70_COLOR_10_11_11:
974 case V_028C70_COLOR_11_11_10:
975 return 11;
976
977 case V_028C70_COLOR_16:
978 case V_028C70_COLOR_16_16:
979 case V_028C70_COLOR_16_16_16_16:
980 return 16;
981
982 case V_028C70_COLOR_8_24:
983 case V_028C70_COLOR_24_8:
984 return 24;
985
986 case V_028C70_COLOR_32:
987 case V_028C70_COLOR_32_32:
988 case V_028C70_COLOR_32_32_32_32:
989 case V_028C70_COLOR_X24_8_32_FLOAT:
990 return 32;
991 }
992
993 assert(!"Unknown maximum component size");
994 return 0;
995 }
996
997 static uint32_t si_translate_dbformat(enum pipe_format format)
998 {
999 switch (format) {
1000 case PIPE_FORMAT_Z16_UNORM:
1001 return V_028040_Z_16;
1002 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1003 case PIPE_FORMAT_X8Z24_UNORM:
1004 case PIPE_FORMAT_Z24X8_UNORM:
1005 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1006 return V_028040_Z_24; /* deprecated on SI */
1007 case PIPE_FORMAT_Z32_FLOAT:
1008 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1009 return V_028040_Z_32_FLOAT;
1010 default:
1011 return V_028040_Z_INVALID;
1012 }
1013 }
1014
1015 /*
1016 * Texture translation
1017 */
1018
1019 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1020 enum pipe_format format,
1021 const struct util_format_description *desc,
1022 int first_non_void)
1023 {
1024 struct si_screen *sscreen = (struct si_screen*)screen;
1025 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1026 boolean uniform = TRUE;
1027 int i;
1028
1029 /* Colorspace (return non-RGB formats directly). */
1030 switch (desc->colorspace) {
1031 /* Depth stencil formats */
1032 case UTIL_FORMAT_COLORSPACE_ZS:
1033 switch (format) {
1034 case PIPE_FORMAT_Z16_UNORM:
1035 return V_008F14_IMG_DATA_FORMAT_16;
1036 case PIPE_FORMAT_X24S8_UINT:
1037 case PIPE_FORMAT_Z24X8_UNORM:
1038 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1039 return V_008F14_IMG_DATA_FORMAT_8_24;
1040 case PIPE_FORMAT_X8Z24_UNORM:
1041 case PIPE_FORMAT_S8X24_UINT:
1042 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1043 return V_008F14_IMG_DATA_FORMAT_24_8;
1044 case PIPE_FORMAT_S8_UINT:
1045 return V_008F14_IMG_DATA_FORMAT_8;
1046 case PIPE_FORMAT_Z32_FLOAT:
1047 return V_008F14_IMG_DATA_FORMAT_32;
1048 case PIPE_FORMAT_X32_S8X24_UINT:
1049 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1050 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1051 default:
1052 goto out_unknown;
1053 }
1054
1055 case UTIL_FORMAT_COLORSPACE_YUV:
1056 goto out_unknown; /* TODO */
1057
1058 case UTIL_FORMAT_COLORSPACE_SRGB:
1059 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1060 goto out_unknown;
1061 break;
1062
1063 default:
1064 break;
1065 }
1066
1067 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1068 if (!enable_s3tc)
1069 goto out_unknown;
1070
1071 switch (format) {
1072 case PIPE_FORMAT_RGTC1_SNORM:
1073 case PIPE_FORMAT_LATC1_SNORM:
1074 case PIPE_FORMAT_RGTC1_UNORM:
1075 case PIPE_FORMAT_LATC1_UNORM:
1076 return V_008F14_IMG_DATA_FORMAT_BC4;
1077 case PIPE_FORMAT_RGTC2_SNORM:
1078 case PIPE_FORMAT_LATC2_SNORM:
1079 case PIPE_FORMAT_RGTC2_UNORM:
1080 case PIPE_FORMAT_LATC2_UNORM:
1081 return V_008F14_IMG_DATA_FORMAT_BC5;
1082 default:
1083 goto out_unknown;
1084 }
1085 }
1086
1087 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1088
1089 if (!enable_s3tc)
1090 goto out_unknown;
1091
1092 if (!util_format_s3tc_enabled) {
1093 goto out_unknown;
1094 }
1095
1096 switch (format) {
1097 case PIPE_FORMAT_DXT1_RGB:
1098 case PIPE_FORMAT_DXT1_RGBA:
1099 case PIPE_FORMAT_DXT1_SRGB:
1100 case PIPE_FORMAT_DXT1_SRGBA:
1101 return V_008F14_IMG_DATA_FORMAT_BC1;
1102 case PIPE_FORMAT_DXT3_RGBA:
1103 case PIPE_FORMAT_DXT3_SRGBA:
1104 return V_008F14_IMG_DATA_FORMAT_BC2;
1105 case PIPE_FORMAT_DXT5_RGBA:
1106 case PIPE_FORMAT_DXT5_SRGBA:
1107 return V_008F14_IMG_DATA_FORMAT_BC3;
1108 default:
1109 goto out_unknown;
1110 }
1111 }
1112
1113 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1114 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1115 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1116 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1117 }
1118
1119 /* R8G8Bx_SNORM - TODO CxV8U8 */
1120
1121 /* See whether the components are of the same size. */
1122 for (i = 1; i < desc->nr_channels; i++) {
1123 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1124 }
1125
1126 /* Non-uniform formats. */
1127 if (!uniform) {
1128 switch(desc->nr_channels) {
1129 case 3:
1130 if (desc->channel[0].size == 5 &&
1131 desc->channel[1].size == 6 &&
1132 desc->channel[2].size == 5) {
1133 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1134 }
1135 goto out_unknown;
1136 case 4:
1137 if (desc->channel[0].size == 5 &&
1138 desc->channel[1].size == 5 &&
1139 desc->channel[2].size == 5 &&
1140 desc->channel[3].size == 1) {
1141 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1142 }
1143 if (desc->channel[0].size == 10 &&
1144 desc->channel[1].size == 10 &&
1145 desc->channel[2].size == 10 &&
1146 desc->channel[3].size == 2) {
1147 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1148 }
1149 goto out_unknown;
1150 }
1151 goto out_unknown;
1152 }
1153
1154 if (first_non_void < 0 || first_non_void > 3)
1155 goto out_unknown;
1156
1157 /* uniform formats */
1158 switch (desc->channel[first_non_void].size) {
1159 case 4:
1160 switch (desc->nr_channels) {
1161 #if 0 /* Not supported for render targets */
1162 case 2:
1163 return V_008F14_IMG_DATA_FORMAT_4_4;
1164 #endif
1165 case 4:
1166 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1167 }
1168 break;
1169 case 8:
1170 switch (desc->nr_channels) {
1171 case 1:
1172 return V_008F14_IMG_DATA_FORMAT_8;
1173 case 2:
1174 return V_008F14_IMG_DATA_FORMAT_8_8;
1175 case 4:
1176 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1177 }
1178 break;
1179 case 16:
1180 switch (desc->nr_channels) {
1181 case 1:
1182 return V_008F14_IMG_DATA_FORMAT_16;
1183 case 2:
1184 return V_008F14_IMG_DATA_FORMAT_16_16;
1185 case 4:
1186 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1187 }
1188 break;
1189 case 32:
1190 switch (desc->nr_channels) {
1191 case 1:
1192 return V_008F14_IMG_DATA_FORMAT_32;
1193 case 2:
1194 return V_008F14_IMG_DATA_FORMAT_32_32;
1195 #if 0 /* Not supported for render targets */
1196 case 3:
1197 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1198 #endif
1199 case 4:
1200 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1201 }
1202 }
1203
1204 out_unknown:
1205 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1206 return ~0;
1207 }
1208
1209 static unsigned si_tex_wrap(unsigned wrap)
1210 {
1211 switch (wrap) {
1212 default:
1213 case PIPE_TEX_WRAP_REPEAT:
1214 return V_008F30_SQ_TEX_WRAP;
1215 case PIPE_TEX_WRAP_CLAMP:
1216 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1217 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1218 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1219 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1220 return V_008F30_SQ_TEX_CLAMP_BORDER;
1221 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1222 return V_008F30_SQ_TEX_MIRROR;
1223 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1224 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1225 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1226 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1227 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1228 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1229 }
1230 }
1231
1232 static unsigned si_tex_filter(unsigned filter)
1233 {
1234 switch (filter) {
1235 default:
1236 case PIPE_TEX_FILTER_NEAREST:
1237 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1238 case PIPE_TEX_FILTER_LINEAR:
1239 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1240 }
1241 }
1242
1243 static unsigned si_tex_mipfilter(unsigned filter)
1244 {
1245 switch (filter) {
1246 case PIPE_TEX_MIPFILTER_NEAREST:
1247 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1248 case PIPE_TEX_MIPFILTER_LINEAR:
1249 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1250 default:
1251 case PIPE_TEX_MIPFILTER_NONE:
1252 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1253 }
1254 }
1255
1256 static unsigned si_tex_compare(unsigned compare)
1257 {
1258 switch (compare) {
1259 default:
1260 case PIPE_FUNC_NEVER:
1261 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1262 case PIPE_FUNC_LESS:
1263 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1264 case PIPE_FUNC_EQUAL:
1265 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1266 case PIPE_FUNC_LEQUAL:
1267 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1268 case PIPE_FUNC_GREATER:
1269 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1270 case PIPE_FUNC_NOTEQUAL:
1271 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1272 case PIPE_FUNC_GEQUAL:
1273 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1274 case PIPE_FUNC_ALWAYS:
1275 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1276 }
1277 }
1278
1279 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1280 {
1281 switch (dim) {
1282 default:
1283 case PIPE_TEXTURE_1D:
1284 return V_008F1C_SQ_RSRC_IMG_1D;
1285 case PIPE_TEXTURE_1D_ARRAY:
1286 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1287 case PIPE_TEXTURE_2D:
1288 case PIPE_TEXTURE_RECT:
1289 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1290 V_008F1C_SQ_RSRC_IMG_2D;
1291 case PIPE_TEXTURE_2D_ARRAY:
1292 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1293 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1294 case PIPE_TEXTURE_3D:
1295 return V_008F1C_SQ_RSRC_IMG_3D;
1296 case PIPE_TEXTURE_CUBE:
1297 return V_008F1C_SQ_RSRC_IMG_CUBE;
1298 }
1299 }
1300
1301 /*
1302 * Format support testing
1303 */
1304
1305 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1306 {
1307 return si_translate_texformat(screen, format, util_format_description(format),
1308 util_format_get_first_non_void_channel(format)) != ~0U;
1309 }
1310
1311 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1312 const struct util_format_description *desc,
1313 int first_non_void)
1314 {
1315 unsigned type = desc->channel[first_non_void].type;
1316 int i;
1317
1318 if (type == UTIL_FORMAT_TYPE_FIXED)
1319 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1320
1321 if (desc->nr_channels == 4 &&
1322 desc->channel[0].size == 10 &&
1323 desc->channel[1].size == 10 &&
1324 desc->channel[2].size == 10 &&
1325 desc->channel[3].size == 2)
1326 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1327
1328 /* See whether the components are of the same size. */
1329 for (i = 0; i < desc->nr_channels; i++) {
1330 if (desc->channel[first_non_void].size != desc->channel[i].size)
1331 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1332 }
1333
1334 switch (desc->channel[first_non_void].size) {
1335 case 8:
1336 switch (desc->nr_channels) {
1337 case 1:
1338 return V_008F0C_BUF_DATA_FORMAT_8;
1339 case 2:
1340 return V_008F0C_BUF_DATA_FORMAT_8_8;
1341 case 3:
1342 case 4:
1343 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1344 }
1345 break;
1346 case 16:
1347 switch (desc->nr_channels) {
1348 case 1:
1349 return V_008F0C_BUF_DATA_FORMAT_16;
1350 case 2:
1351 return V_008F0C_BUF_DATA_FORMAT_16_16;
1352 case 3:
1353 case 4:
1354 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1355 }
1356 break;
1357 case 32:
1358 /* From the Southern Islands ISA documentation about MTBUF:
1359 * 'Memory reads of data in memory that is 32 or 64 bits do not
1360 * undergo any format conversion.'
1361 */
1362 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1363 !desc->channel[first_non_void].pure_integer)
1364 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1365
1366 switch (desc->nr_channels) {
1367 case 1:
1368 return V_008F0C_BUF_DATA_FORMAT_32;
1369 case 2:
1370 return V_008F0C_BUF_DATA_FORMAT_32_32;
1371 case 3:
1372 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1373 case 4:
1374 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1375 }
1376 break;
1377 }
1378
1379 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1380 }
1381
1382 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1383 const struct util_format_description *desc,
1384 int first_non_void)
1385 {
1386 switch (desc->channel[first_non_void].type) {
1387 case UTIL_FORMAT_TYPE_SIGNED:
1388 if (desc->channel[first_non_void].normalized)
1389 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1390 else if (desc->channel[first_non_void].pure_integer)
1391 return V_008F0C_BUF_NUM_FORMAT_SINT;
1392 else
1393 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1394 break;
1395 case UTIL_FORMAT_TYPE_UNSIGNED:
1396 if (desc->channel[first_non_void].normalized)
1397 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1398 else if (desc->channel[first_non_void].pure_integer)
1399 return V_008F0C_BUF_NUM_FORMAT_UINT;
1400 else
1401 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1402 break;
1403 case UTIL_FORMAT_TYPE_FLOAT:
1404 default:
1405 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1406 }
1407 }
1408
1409 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1410 {
1411 const struct util_format_description *desc;
1412 int first_non_void;
1413 unsigned data_format;
1414
1415 desc = util_format_description(format);
1416 first_non_void = util_format_get_first_non_void_channel(format);
1417 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1418 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1419 }
1420
1421 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1422 {
1423 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1424 r600_translate_colorswap(format) != ~0U;
1425 }
1426
1427 static bool si_is_zs_format_supported(enum pipe_format format)
1428 {
1429 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1430 }
1431
1432 boolean si_is_format_supported(struct pipe_screen *screen,
1433 enum pipe_format format,
1434 enum pipe_texture_target target,
1435 unsigned sample_count,
1436 unsigned usage)
1437 {
1438 struct si_screen *sscreen = (struct si_screen *)screen;
1439 unsigned retval = 0;
1440
1441 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1442 R600_ERR("r600: unsupported texture type %d\n", target);
1443 return FALSE;
1444 }
1445
1446 if (!util_format_is_supported(format, usage))
1447 return FALSE;
1448
1449 if (sample_count > 1) {
1450 if (HAVE_LLVM < 0x0304)
1451 return FALSE;
1452
1453 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1454 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1455 return FALSE;
1456
1457 switch (sample_count) {
1458 case 2:
1459 case 4:
1460 case 8:
1461 break;
1462 default:
1463 return FALSE;
1464 }
1465 }
1466
1467 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1468 if (target == PIPE_BUFFER) {
1469 if (si_is_vertex_format_supported(screen, format))
1470 retval |= PIPE_BIND_SAMPLER_VIEW;
1471 } else {
1472 if (si_is_sampler_format_supported(screen, format))
1473 retval |= PIPE_BIND_SAMPLER_VIEW;
1474 }
1475 }
1476
1477 if ((usage & (PIPE_BIND_RENDER_TARGET |
1478 PIPE_BIND_DISPLAY_TARGET |
1479 PIPE_BIND_SCANOUT |
1480 PIPE_BIND_SHARED)) &&
1481 si_is_colorbuffer_format_supported(format)) {
1482 retval |= usage &
1483 (PIPE_BIND_RENDER_TARGET |
1484 PIPE_BIND_DISPLAY_TARGET |
1485 PIPE_BIND_SCANOUT |
1486 PIPE_BIND_SHARED);
1487 }
1488
1489 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1490 si_is_zs_format_supported(format)) {
1491 retval |= PIPE_BIND_DEPTH_STENCIL;
1492 }
1493
1494 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1495 si_is_vertex_format_supported(screen, format)) {
1496 retval |= PIPE_BIND_VERTEX_BUFFER;
1497 }
1498
1499 if (usage & PIPE_BIND_TRANSFER_READ)
1500 retval |= PIPE_BIND_TRANSFER_READ;
1501 if (usage & PIPE_BIND_TRANSFER_WRITE)
1502 retval |= PIPE_BIND_TRANSFER_WRITE;
1503
1504 return retval == usage;
1505 }
1506
1507 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1508 {
1509 unsigned tile_mode_index = 0;
1510
1511 if (stencil) {
1512 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1513 } else {
1514 tile_mode_index = rtex->surface.tiling_index[level];
1515 }
1516 return tile_mode_index;
1517 }
1518
1519 /*
1520 * framebuffer handling
1521 */
1522
1523 static void si_initialize_color_surface(struct si_context *sctx,
1524 struct r600_surface *surf)
1525 {
1526 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1527 unsigned level = surf->base.u.tex.level;
1528 uint64_t offset = rtex->surface.level[level].offset;
1529 unsigned pitch, slice;
1530 unsigned color_info, color_attrib, color_pitch, color_view;
1531 unsigned tile_mode_index;
1532 unsigned format, swap, ntype, endian;
1533 const struct util_format_description *desc;
1534 int i;
1535 unsigned blend_clamp = 0, blend_bypass = 0;
1536 unsigned max_comp_size;
1537
1538 /* Layered rendering doesn't work with LINEAR_GENERAL.
1539 * (LINEAR_ALIGNED and others work) */
1540 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1541 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1542 offset += rtex->surface.level[level].slice_size *
1543 surf->base.u.tex.first_layer;
1544 color_view = 0;
1545 } else {
1546 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1547 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1548 }
1549
1550 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1551 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1552 if (slice) {
1553 slice = slice - 1;
1554 }
1555
1556 tile_mode_index = si_tile_mode_index(rtex, level, false);
1557
1558 desc = util_format_description(surf->base.format);
1559 for (i = 0; i < 4; i++) {
1560 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1561 break;
1562 }
1563 }
1564 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1565 ntype = V_028C70_NUMBER_FLOAT;
1566 } else {
1567 ntype = V_028C70_NUMBER_UNORM;
1568 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1569 ntype = V_028C70_NUMBER_SRGB;
1570 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1571 if (desc->channel[i].pure_integer) {
1572 ntype = V_028C70_NUMBER_SINT;
1573 } else {
1574 assert(desc->channel[i].normalized);
1575 ntype = V_028C70_NUMBER_SNORM;
1576 }
1577 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1578 if (desc->channel[i].pure_integer) {
1579 ntype = V_028C70_NUMBER_UINT;
1580 } else {
1581 assert(desc->channel[i].normalized);
1582 ntype = V_028C70_NUMBER_UNORM;
1583 }
1584 }
1585 }
1586
1587 format = si_translate_colorformat(surf->base.format);
1588 if (format == V_028C70_COLOR_INVALID) {
1589 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1590 }
1591 assert(format != V_028C70_COLOR_INVALID);
1592 swap = r600_translate_colorswap(surf->base.format);
1593 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1594 endian = V_028C70_ENDIAN_NONE;
1595 } else {
1596 endian = si_colorformat_endian_swap(format);
1597 }
1598
1599 /* blend clamp should be set for all NORM/SRGB types */
1600 if (ntype == V_028C70_NUMBER_UNORM ||
1601 ntype == V_028C70_NUMBER_SNORM ||
1602 ntype == V_028C70_NUMBER_SRGB)
1603 blend_clamp = 1;
1604
1605 /* set blend bypass according to docs if SINT/UINT or
1606 8/24 COLOR variants */
1607 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1608 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1609 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1610 blend_clamp = 0;
1611 blend_bypass = 1;
1612 }
1613
1614 color_info = S_028C70_FORMAT(format) |
1615 S_028C70_COMP_SWAP(swap) |
1616 S_028C70_BLEND_CLAMP(blend_clamp) |
1617 S_028C70_BLEND_BYPASS(blend_bypass) |
1618 S_028C70_NUMBER_TYPE(ntype) |
1619 S_028C70_ENDIAN(endian);
1620
1621 color_pitch = S_028C64_TILE_MAX(pitch);
1622
1623 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1624 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1625
1626 if (rtex->resource.b.b.nr_samples > 1) {
1627 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1628
1629 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1630 S_028C74_NUM_FRAGMENTS(log_samples);
1631
1632 if (rtex->fmask.size) {
1633 color_info |= S_028C70_COMPRESSION(1);
1634 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1635
1636 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1637
1638 if (sctx->b.chip_class == SI) {
1639 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1640 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1641 }
1642 if (sctx->b.chip_class >= CIK) {
1643 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1644 }
1645 }
1646 }
1647
1648 if (rtex->cmask.size) {
1649 color_info |= S_028C70_FAST_CLEAR(1);
1650 }
1651
1652 offset += r600_resource_va(sctx->b.b.screen, surf->base.texture);
1653
1654 surf->cb_color_base = offset >> 8;
1655 surf->cb_color_pitch = color_pitch;
1656 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1657 surf->cb_color_view = color_view;
1658 surf->cb_color_info = color_info;
1659 surf->cb_color_attrib = color_attrib;
1660
1661 if (rtex->cmask.size) {
1662 surf->cb_color_cmask = (offset + rtex->cmask.offset) >> 8;
1663 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask.slice_tile_max);
1664 }
1665 if (rtex->fmask.size) {
1666 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1667 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1668 }
1669
1670 /* Determine pixel shader export format */
1671 max_comp_size = si_colorformat_max_comp_size(format);
1672 if (ntype == V_028C70_NUMBER_SRGB ||
1673 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1674 max_comp_size <= 10) ||
1675 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1676 surf->export_16bpc = true;
1677 }
1678
1679 surf->color_initialized = true;
1680 }
1681
1682 static void si_init_depth_surface(struct si_context *sctx,
1683 struct r600_surface *surf)
1684 {
1685 struct si_screen *sscreen = sctx->screen;
1686 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1687 unsigned level = surf->base.u.tex.level;
1688 unsigned pitch, slice, format, tile_mode_index, array_mode;
1689 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1690 uint32_t z_info, s_info, db_depth_info;
1691 uint64_t z_offs, s_offs;
1692 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl;
1693
1694 switch (sctx->framebuffer.zsbuf->texture->format) {
1695 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1696 case PIPE_FORMAT_X8Z24_UNORM:
1697 case PIPE_FORMAT_Z24X8_UNORM:
1698 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1699 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1700 break;
1701 case PIPE_FORMAT_Z32_FLOAT:
1702 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1703 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1704 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1705 break;
1706 case PIPE_FORMAT_Z16_UNORM:
1707 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1708 break;
1709 default:
1710 assert(0);
1711 }
1712
1713 format = si_translate_dbformat(rtex->resource.b.b.format);
1714
1715 if (format == V_028040_Z_INVALID) {
1716 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1717 }
1718 assert(format != V_028040_Z_INVALID);
1719
1720 s_offs = z_offs = r600_resource_va(sctx->b.b.screen, surf->base.texture);
1721 z_offs += rtex->surface.level[level].offset;
1722 s_offs += rtex->surface.stencil_level[level].offset;
1723
1724 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1725 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1726 if (slice) {
1727 slice = slice - 1;
1728 }
1729
1730 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1731
1732 z_info = S_028040_FORMAT(format);
1733 if (rtex->resource.b.b.nr_samples > 1) {
1734 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1735 }
1736
1737 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1738 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1739 else
1740 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1741
1742 if (sctx->b.chip_class >= CIK) {
1743 switch (rtex->surface.level[level].mode) {
1744 case RADEON_SURF_MODE_2D:
1745 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1746 break;
1747 case RADEON_SURF_MODE_1D:
1748 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1749 case RADEON_SURF_MODE_LINEAR:
1750 default:
1751 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1752 break;
1753 }
1754 tile_split = rtex->surface.tile_split;
1755 stile_split = rtex->surface.stencil_tile_split;
1756 macro_aspect = rtex->surface.mtilea;
1757 bankw = rtex->surface.bankw;
1758 bankh = rtex->surface.bankh;
1759 tile_split = cik_tile_split(tile_split);
1760 stile_split = cik_tile_split(stile_split);
1761 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1762 bankw = cik_bank_wh(bankw);
1763 bankh = cik_bank_wh(bankh);
1764 nbanks = cik_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split);
1765 tile_mode_index = si_tile_mode_index(rtex, level, false);
1766 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1767
1768 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1769 S_02803C_PIPE_CONFIG(pipe_config) |
1770 S_02803C_BANK_WIDTH(bankw) |
1771 S_02803C_BANK_HEIGHT(bankh) |
1772 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1773 S_02803C_NUM_BANKS(nbanks);
1774 z_info |= S_028040_TILE_SPLIT(tile_split);
1775 s_info |= S_028044_TILE_SPLIT(stile_split);
1776 } else {
1777 tile_mode_index = si_tile_mode_index(rtex, level, false);
1778 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1779 tile_mode_index = si_tile_mode_index(rtex, level, true);
1780 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1781 }
1782
1783 /* HiZ aka depth buffer htile */
1784 /* use htile only for first level */
1785 if (rtex->htile_buffer && !level) {
1786 const struct util_format_description *fmt_desc;
1787
1788 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1789
1790 /* This is optimal for the clear value of 1.0 and using
1791 * the LESS and LEQUAL test functions. Set this to 0
1792 * for the opposite case. This can only be changed when
1793 * clearing. */
1794 z_info |= S_028040_ZRANGE_PRECISION(1);
1795
1796 fmt_desc = util_format_description(rtex->resource.b.b.format);
1797 if (!util_format_has_stencil(fmt_desc)) {
1798 /* Use all of the htile_buffer for depth */
1799 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1800 }
1801
1802 uint64_t va = r600_resource_va(&sctx->screen->b.b, &rtex->htile_buffer->b.b);
1803 db_htile_data_base = va >> 8;
1804 db_htile_surface = S_028ABC_FULL_CACHE(1);
1805 } else {
1806 db_htile_data_base = 0;
1807 db_htile_surface = 0;
1808 }
1809
1810 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1811 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1812 surf->db_htile_data_base = db_htile_data_base;
1813 surf->db_depth_info = db_depth_info;
1814 surf->db_z_info = z_info;
1815 surf->db_stencil_info = s_info;
1816 surf->db_depth_base = z_offs >> 8;
1817 surf->db_stencil_base = s_offs >> 8;
1818 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1819 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1820 surf->db_htile_surface = db_htile_surface;
1821 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1822
1823 surf->depth_initialized = true;
1824 }
1825
1826 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1827 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1828 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1829 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1830 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1831
1832 /* 2xMSAA
1833 * There are two locations (-4, 4), (4, -4). */
1834 static uint32_t sample_locs_2x[] = {
1835 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1836 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1837 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1838 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1839 };
1840 static unsigned max_dist_2x = 4;
1841 /* 4xMSAA
1842 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1843 static uint32_t sample_locs_4x[] = {
1844 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1845 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1846 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1847 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1848 };
1849 static unsigned max_dist_4x = 6;
1850 /* Cayman/SI 8xMSAA */
1851 static uint32_t cm_sample_locs_8x[] = {
1852 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1853 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1854 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1855 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1856 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1857 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1858 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1859 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1860 };
1861 static unsigned cm_max_dist_8x = 8;
1862 /* Cayman/SI 16xMSAA */
1863 static uint32_t cm_sample_locs_16x[] = {
1864 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1865 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1866 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1867 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1868 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1869 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1870 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1871 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1872 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1873 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1874 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1875 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1876 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1877 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1878 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1879 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1880 };
1881 static unsigned cm_max_dist_16x = 8;
1882
1883 static void si_get_sample_position(struct pipe_context *ctx,
1884 unsigned sample_count,
1885 unsigned sample_index,
1886 float *out_value)
1887 {
1888 int offset, index;
1889 struct {
1890 int idx:4;
1891 } val;
1892 switch (sample_count) {
1893 case 1:
1894 default:
1895 out_value[0] = out_value[1] = 0.5;
1896 break;
1897 case 2:
1898 offset = 4 * (sample_index * 2);
1899 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1900 out_value[0] = (float)(val.idx + 8) / 16.0f;
1901 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1902 out_value[1] = (float)(val.idx + 8) / 16.0f;
1903 break;
1904 case 4:
1905 offset = 4 * (sample_index * 2);
1906 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1907 out_value[0] = (float)(val.idx + 8) / 16.0f;
1908 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1909 out_value[1] = (float)(val.idx + 8) / 16.0f;
1910 break;
1911 case 8:
1912 offset = 4 * (sample_index % 4 * 2);
1913 index = (sample_index / 4) * 4;
1914 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1915 out_value[0] = (float)(val.idx + 8) / 16.0f;
1916 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1917 out_value[1] = (float)(val.idx + 8) / 16.0f;
1918 break;
1919 case 16:
1920 offset = 4 * (sample_index % 4 * 2);
1921 index = (sample_index / 4) * 4;
1922 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1923 out_value[0] = (float)(val.idx + 8) / 16.0f;
1924 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1925 out_value[1] = (float)(val.idx + 8) / 16.0f;
1926 break;
1927 }
1928 }
1929
1930 static void si_set_msaa_state(struct si_context *sctx, struct si_pm4_state *pm4, int nr_samples)
1931 {
1932 unsigned max_dist = 0;
1933
1934 switch (nr_samples) {
1935 default:
1936 nr_samples = 0;
1937 break;
1938 case 2:
1939 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1940 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1941 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1942 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1943 max_dist = max_dist_2x;
1944 break;
1945 case 4:
1946 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1947 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1948 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1949 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1950 max_dist = max_dist_4x;
1951 break;
1952 case 8:
1953 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
1954 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
1955 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
1956 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
1957 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
1958 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
1959 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
1960 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
1961 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
1962 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
1963 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
1964 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
1965 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
1966 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
1967 max_dist = cm_max_dist_8x;
1968 break;
1969 case 16:
1970 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
1971 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
1972 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
1973 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
1974 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
1975 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
1976 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
1977 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
1978 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
1979 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
1980 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
1981 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
1982 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
1983 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
1984 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
1985 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
1986 max_dist = cm_max_dist_16x;
1987 break;
1988 }
1989
1990 if (nr_samples > 1) {
1991 unsigned log_samples = util_logbase2(nr_samples);
1992
1993 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
1994 S_028BDC_LAST_PIXEL(1) |
1995 S_028BDC_EXPAND_LINE_WIDTH(1));
1996 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
1997 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1998 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1999 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2000
2001 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2002 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2003 S_028804_PS_ITER_SAMPLES(log_samples) |
2004 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2005 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2006 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2007 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2008 } else {
2009 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2010 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2011
2012 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2013 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2014 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2015 }
2016 }
2017
2018 static void si_set_framebuffer_state(struct pipe_context *ctx,
2019 const struct pipe_framebuffer_state *state)
2020 {
2021 struct si_context *sctx = (struct si_context *)ctx;
2022 struct r600_surface *surf = NULL;
2023 struct r600_texture *rtex;
2024 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2025 int nr_samples, i;
2026
2027 if (pm4 == NULL)
2028 return;
2029
2030 if (sctx->framebuffer.nr_cbufs) {
2031 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2032 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2033 }
2034 if (sctx->framebuffer.zsbuf) {
2035 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
2036 R600_CONTEXT_FLUSH_AND_INV_DB_META;
2037 }
2038
2039 util_copy_framebuffer_state(&sctx->framebuffer, state);
2040
2041 /* build states */
2042 sctx->export_16bpc = 0;
2043 sctx->fb_compressed_cb_mask = 0;
2044
2045 for (i = 0; i < state->nr_cbufs; i++) {
2046 if (!state->cbufs[i]) {
2047 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2048 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2049 continue;
2050 }
2051
2052 surf = (struct r600_surface*)state->cbufs[i];
2053 rtex = (struct r600_texture*)surf->base.texture;
2054
2055 if (!surf->color_initialized) {
2056 si_initialize_color_surface(sctx, surf);
2057 }
2058
2059 if (surf->export_16bpc) {
2060 sctx->export_16bpc |= 1 << i;
2061 }
2062
2063 if (rtex->fmask.size || rtex->cmask.size) {
2064 sctx->fb_compressed_cb_mask |= 1 << i;
2065 }
2066
2067 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE,
2068 rtex->surface.nsamples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA :
2069 RADEON_PRIO_COLOR_BUFFER);
2070 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + i * 0x3C, surf->cb_color_base);
2071 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + i * 0x3C, surf->cb_color_pitch);
2072 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + i * 0x3C, surf->cb_color_slice);
2073 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + i * 0x3C, surf->cb_color_view);
2074 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C, surf->cb_color_info);
2075 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C, surf->cb_color_attrib);
2076 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + i * 0x3C, surf->cb_color_cmask);
2077 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + i * 0x3C, surf->cb_color_cmask_slice);
2078 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + i * 0x3C, surf->cb_color_fmask);
2079 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + i * 0x3C, surf->cb_color_fmask_slice);
2080 }
2081 /* Set CB_COLOR1_INFO for possible dual-src blending. */
2082 if (i == 1 && surf) {
2083 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, surf->cb_color_info);
2084 /* Also set the 16BPC export. */
2085 if (surf->export_16bpc) {
2086 sctx->export_16bpc |= 1 << 1;
2087 }
2088 i++;
2089 }
2090 for (; i < 8; i++) {
2091 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2092 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2093 }
2094
2095 assert(!(sctx->export_16bpc & ~0xff));
2096
2097 if (state->zsbuf) {
2098 surf = (struct r600_surface*)state->zsbuf;
2099 rtex = (struct r600_texture*)surf->base.texture;
2100
2101 if (!surf->depth_initialized) {
2102 si_init_depth_surface(sctx, surf);
2103 }
2104
2105 if (surf->db_htile_data_base) {
2106 si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE,
2107 RADEON_PRIO_DEPTH_META);
2108 }
2109 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
2110 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, surf->db_htile_data_base);
2111
2112 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, surf->db_depth_info);
2113 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, surf->db_z_info);
2114 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, surf->db_stencil_info);
2115 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE,
2116 rtex->surface.nsamples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA :
2117 RADEON_PRIO_DEPTH_BUFFER);
2118 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, surf->db_depth_base);
2119 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base);
2120 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base);
2121 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base);
2122 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
2123 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
2124
2125 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, surf->db_htile_surface);
2126 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2127 surf->pa_su_poly_offset_db_fmt_cntl);
2128 } else {
2129 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
2130 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
2131 }
2132
2133 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2134 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2135 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2136
2137 nr_samples = util_framebuffer_get_num_samples(state);
2138
2139 si_set_msaa_state(sctx, pm4, nr_samples);
2140 sctx->fb_log_samples = util_logbase2(nr_samples);
2141 sctx->fb_cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2142 util_format_is_pure_integer(state->cbufs[0]->format);
2143
2144 si_pm4_set_state(sctx, framebuffer, pm4);
2145 si_update_fb_rs_state(sctx);
2146 si_update_fb_blend_state(sctx);
2147 }
2148
2149 /*
2150 * shaders
2151 */
2152
2153 /* Compute the key for the hw shader variant */
2154 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2155 struct si_pipe_shader_selector *sel,
2156 union si_shader_key *key)
2157 {
2158 struct si_context *sctx = (struct si_context *)ctx;
2159 memset(key, 0, sizeof(*key));
2160
2161 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
2162 sctx->queued.named.rasterizer) {
2163 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2164 key->vs.ucps_enabled |= 0x2;
2165 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2166 key->vs.ucps_enabled |= 0x1;
2167 }
2168
2169 if (sel->type == PIPE_SHADER_VERTEX) {
2170 unsigned i;
2171 if (!sctx->vertex_elements)
2172 return;
2173
2174 for (i = 0; i < sctx->vertex_elements->count; ++i)
2175 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2176
2177 key->vs.as_es = sctx->gs_shader != NULL;
2178 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2179 if (sel->fs_write_all)
2180 key->ps.nr_cbufs = sctx->framebuffer.nr_cbufs;
2181 key->ps.export_16bpc = sctx->export_16bpc;
2182
2183 if (sctx->queued.named.rasterizer) {
2184 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2185 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2186
2187 if (sctx->queued.named.blend) {
2188 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2189 sctx->queued.named.rasterizer->multisample_enable &&
2190 !sctx->fb_cb0_is_integer;
2191 }
2192 }
2193 if (sctx->queued.named.dsa) {
2194 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2195
2196 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2197 if (sctx->framebuffer.nr_cbufs &&
2198 sctx->framebuffer.cbufs[0] &&
2199 util_format_is_pure_integer(sctx->framebuffer.cbufs[0]->texture->format))
2200 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2201 } else {
2202 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2203 }
2204 }
2205 }
2206
2207 /* Select the hw shader variant depending on the current state. */
2208 int si_shader_select(struct pipe_context *ctx,
2209 struct si_pipe_shader_selector *sel)
2210 {
2211 union si_shader_key key;
2212 struct si_pipe_shader * shader = NULL;
2213 int r;
2214
2215 si_shader_selector_key(ctx, sel, &key);
2216
2217 /* Check if we don't need to change anything.
2218 * This path is also used for most shaders that don't need multiple
2219 * variants, it will cost just a computation of the key and this
2220 * test. */
2221 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2222 return 0;
2223 }
2224
2225 /* lookup if we have other variants in the list */
2226 if (sel->num_shaders > 1) {
2227 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2228
2229 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2230 p = c;
2231 c = c->next_variant;
2232 }
2233
2234 if (c) {
2235 p->next_variant = c->next_variant;
2236 shader = c;
2237 }
2238 }
2239
2240 if (shader) {
2241 shader->next_variant = sel->current;
2242 sel->current = shader;
2243 } else {
2244 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2245 shader->selector = sel;
2246 shader->key = key;
2247
2248 shader->next_variant = sel->current;
2249 sel->current = shader;
2250 r = si_pipe_shader_create(ctx, shader);
2251 if (unlikely(r)) {
2252 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2253 sel->type, r);
2254 sel->current = NULL;
2255 FREE(shader);
2256 return r;
2257 }
2258 sel->num_shaders++;
2259 }
2260
2261 return 0;
2262 }
2263
2264 static void *si_create_shader_state(struct pipe_context *ctx,
2265 const struct pipe_shader_state *state,
2266 unsigned pipe_shader_type)
2267 {
2268 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2269 int r;
2270
2271 sel->type = pipe_shader_type;
2272 sel->tokens = tgsi_dup_tokens(state->tokens);
2273 sel->so = state->stream_output;
2274
2275 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2276 struct tgsi_shader_info info;
2277
2278 tgsi_scan_shader(state->tokens, &info);
2279 sel->fs_write_all = info.color0_writes_all_cbufs;
2280 }
2281
2282 r = si_shader_select(ctx, sel);
2283 if (r) {
2284 free(sel);
2285 return NULL;
2286 }
2287
2288 return sel;
2289 }
2290
2291 static void *si_create_fs_state(struct pipe_context *ctx,
2292 const struct pipe_shader_state *state)
2293 {
2294 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2295 }
2296
2297 #if HAVE_LLVM >= 0x0305
2298
2299 static void *si_create_gs_state(struct pipe_context *ctx,
2300 const struct pipe_shader_state *state)
2301 {
2302 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
2303 }
2304
2305 #endif
2306
2307 static void *si_create_vs_state(struct pipe_context *ctx,
2308 const struct pipe_shader_state *state)
2309 {
2310 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2311 }
2312
2313 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2314 {
2315 struct si_context *sctx = (struct si_context *)ctx;
2316 struct si_pipe_shader_selector *sel = state;
2317
2318 if (sctx->vs_shader == sel)
2319 return;
2320
2321 if (!sel || !sel->current)
2322 return;
2323
2324 sctx->vs_shader = sel;
2325 }
2326
2327 #if HAVE_LLVM >= 0x0305
2328
2329 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2330 {
2331 struct si_context *sctx = (struct si_context *)ctx;
2332 struct si_pipe_shader_selector *sel = state;
2333
2334 if (sctx->gs_shader == sel)
2335 return;
2336
2337 sctx->gs_shader = sel;
2338 }
2339
2340 #endif
2341
2342 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2343 {
2344 struct si_context *sctx = (struct si_context *)ctx;
2345 struct si_pipe_shader_selector *sel = state;
2346
2347 if (sctx->ps_shader == sel)
2348 return;
2349
2350 if (!sel || !sel->current)
2351 sel = sctx->dummy_pixel_shader;
2352
2353 sctx->ps_shader = sel;
2354 }
2355
2356 static void si_delete_shader_selector(struct pipe_context *ctx,
2357 struct si_pipe_shader_selector *sel)
2358 {
2359 struct si_context *sctx = (struct si_context *)ctx;
2360 struct si_pipe_shader *p = sel->current, *c;
2361
2362 while (p) {
2363 c = p->next_variant;
2364 if (sel->type == PIPE_SHADER_GEOMETRY)
2365 si_pm4_delete_state(sctx, gs, p->pm4);
2366 else if (sel->type == PIPE_SHADER_FRAGMENT)
2367 si_pm4_delete_state(sctx, ps, p->pm4);
2368 else if (p->key.vs.as_es)
2369 si_pm4_delete_state(sctx, es, p->pm4);
2370 else
2371 si_pm4_delete_state(sctx, vs, p->pm4);
2372 si_pipe_shader_destroy(ctx, p);
2373 free(p);
2374 p = c;
2375 }
2376
2377 free(sel->tokens);
2378 free(sel);
2379 }
2380
2381 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2382 {
2383 struct si_context *sctx = (struct si_context *)ctx;
2384 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2385
2386 if (sctx->vs_shader == sel) {
2387 sctx->vs_shader = NULL;
2388 }
2389
2390 si_delete_shader_selector(ctx, sel);
2391 }
2392
2393 #if HAVE_LLVM >= 0x0305
2394
2395 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
2396 {
2397 struct si_context *sctx = (struct si_context *)ctx;
2398 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2399
2400 if (sctx->gs_shader == sel) {
2401 sctx->gs_shader = NULL;
2402 }
2403
2404 si_delete_shader_selector(ctx, sel);
2405 }
2406
2407 #endif
2408
2409 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2410 {
2411 struct si_context *sctx = (struct si_context *)ctx;
2412 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2413
2414 if (sctx->ps_shader == sel) {
2415 sctx->ps_shader = NULL;
2416 }
2417
2418 si_delete_shader_selector(ctx, sel);
2419 }
2420
2421 /*
2422 * Samplers
2423 */
2424
2425 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2426 struct pipe_resource *texture,
2427 const struct pipe_sampler_view *state)
2428 {
2429 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2430 struct r600_texture *tmp = (struct r600_texture*)texture;
2431 const struct util_format_description *desc;
2432 unsigned format, num_format;
2433 uint32_t pitch = 0;
2434 unsigned char state_swizzle[4], swizzle[4];
2435 unsigned height, depth, width;
2436 enum pipe_format pipe_format = state->format;
2437 struct radeon_surface_level *surflevel;
2438 int first_non_void;
2439 uint64_t va;
2440
2441 if (view == NULL)
2442 return NULL;
2443
2444 /* initialize base object */
2445 view->base = *state;
2446 view->base.texture = NULL;
2447 pipe_resource_reference(&view->base.texture, texture);
2448 view->base.reference.count = 1;
2449 view->base.context = ctx;
2450 view->resource = &tmp->resource;
2451
2452 /* Buffer resource. */
2453 if (texture->target == PIPE_BUFFER) {
2454 unsigned stride;
2455
2456 desc = util_format_description(state->format);
2457 first_non_void = util_format_get_first_non_void_channel(state->format);
2458 stride = desc->block.bits / 8;
2459 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2460 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2461 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2462
2463 view->state[0] = va;
2464 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2465 S_008F04_STRIDE(stride);
2466 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2467 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2468 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2469 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2470 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2471 S_008F0C_NUM_FORMAT(num_format) |
2472 S_008F0C_DATA_FORMAT(format);
2473 return &view->base;
2474 }
2475
2476 state_swizzle[0] = state->swizzle_r;
2477 state_swizzle[1] = state->swizzle_g;
2478 state_swizzle[2] = state->swizzle_b;
2479 state_swizzle[3] = state->swizzle_a;
2480
2481 surflevel = tmp->surface.level;
2482
2483 /* Texturing with separate depth and stencil. */
2484 if (tmp->is_depth && !tmp->is_flushing_texture) {
2485 switch (pipe_format) {
2486 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2487 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2488 break;
2489 case PIPE_FORMAT_X8Z24_UNORM:
2490 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2491 /* Z24 is always stored like this. */
2492 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2493 break;
2494 case PIPE_FORMAT_X24S8_UINT:
2495 case PIPE_FORMAT_S8X24_UINT:
2496 case PIPE_FORMAT_X32_S8X24_UINT:
2497 pipe_format = PIPE_FORMAT_S8_UINT;
2498 surflevel = tmp->surface.stencil_level;
2499 break;
2500 default:;
2501 }
2502 }
2503
2504 desc = util_format_description(pipe_format);
2505
2506 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2507 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2508 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2509
2510 switch (pipe_format) {
2511 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2512 case PIPE_FORMAT_X24S8_UINT:
2513 case PIPE_FORMAT_X32_S8X24_UINT:
2514 case PIPE_FORMAT_X8Z24_UNORM:
2515 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2516 break;
2517 default:
2518 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2519 }
2520 } else {
2521 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2522 }
2523
2524 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2525
2526 switch (pipe_format) {
2527 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2528 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2529 break;
2530 default:
2531 if (first_non_void < 0) {
2532 if (util_format_is_compressed(pipe_format)) {
2533 switch (pipe_format) {
2534 case PIPE_FORMAT_DXT1_SRGB:
2535 case PIPE_FORMAT_DXT1_SRGBA:
2536 case PIPE_FORMAT_DXT3_SRGBA:
2537 case PIPE_FORMAT_DXT5_SRGBA:
2538 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2539 break;
2540 case PIPE_FORMAT_RGTC1_SNORM:
2541 case PIPE_FORMAT_LATC1_SNORM:
2542 case PIPE_FORMAT_RGTC2_SNORM:
2543 case PIPE_FORMAT_LATC2_SNORM:
2544 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2545 break;
2546 default:
2547 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2548 break;
2549 }
2550 } else {
2551 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2552 }
2553 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2554 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2555 } else {
2556 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2557
2558 switch (desc->channel[first_non_void].type) {
2559 case UTIL_FORMAT_TYPE_FLOAT:
2560 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2561 break;
2562 case UTIL_FORMAT_TYPE_SIGNED:
2563 if (desc->channel[first_non_void].normalized)
2564 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2565 else if (desc->channel[first_non_void].pure_integer)
2566 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2567 else
2568 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2569 break;
2570 case UTIL_FORMAT_TYPE_UNSIGNED:
2571 if (desc->channel[first_non_void].normalized)
2572 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2573 else if (desc->channel[first_non_void].pure_integer)
2574 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2575 else
2576 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2577 }
2578 }
2579 }
2580
2581 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2582 if (format == ~0) {
2583 format = 0;
2584 }
2585
2586 /* not supported any more */
2587 //endian = si_colorformat_endian_swap(format);
2588
2589 width = surflevel[0].npix_x;
2590 height = surflevel[0].npix_y;
2591 depth = surflevel[0].npix_z;
2592 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2593
2594 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2595 height = 1;
2596 depth = texture->array_size;
2597 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2598 depth = texture->array_size;
2599 }
2600
2601 va = r600_resource_va(ctx->screen, texture);
2602 va += surflevel[0].offset;
2603 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2604
2605 view->state[0] = va >> 8;
2606 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2607 S_008F14_DATA_FORMAT(format) |
2608 S_008F14_NUM_FORMAT(num_format));
2609 view->state[2] = (S_008F18_WIDTH(width - 1) |
2610 S_008F18_HEIGHT(height - 1));
2611 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2612 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2613 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2614 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2615 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2616 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2617 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2618 util_logbase2(texture->nr_samples) :
2619 state->u.tex.last_level - tmp->mipmap_shift) |
2620 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2621 S_008F1C_POW2_PAD(texture->last_level > 0) |
2622 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2623 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2624 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2625 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2626 view->state[6] = 0;
2627 view->state[7] = 0;
2628
2629 /* Initialize the sampler view for FMASK. */
2630 if (tmp->fmask.size) {
2631 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2632 uint32_t fmask_format;
2633
2634 switch (texture->nr_samples) {
2635 case 2:
2636 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2637 break;
2638 case 4:
2639 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2640 break;
2641 case 8:
2642 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2643 break;
2644 default:
2645 assert(0);
2646 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2647 }
2648
2649 view->fmask_state[0] = va >> 8;
2650 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2651 S_008F14_DATA_FORMAT(fmask_format) |
2652 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2653 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2654 S_008F18_HEIGHT(height - 1);
2655 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2656 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2657 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2658 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2659 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2660 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2661 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2662 S_008F20_PITCH(tmp->fmask.pitch - 1);
2663 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2664 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2665 view->fmask_state[6] = 0;
2666 view->fmask_state[7] = 0;
2667 }
2668
2669 return &view->base;
2670 }
2671
2672 static void si_sampler_view_destroy(struct pipe_context *ctx,
2673 struct pipe_sampler_view *state)
2674 {
2675 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2676
2677 pipe_resource_reference(&state->texture, NULL);
2678 FREE(resource);
2679 }
2680
2681 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2682 {
2683 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2684 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2685 (linear_filter &&
2686 (wrap == PIPE_TEX_WRAP_CLAMP ||
2687 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2688 }
2689
2690 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2691 {
2692 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2693 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2694
2695 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2696 state->border_color.ui[2] || state->border_color.ui[3]) &&
2697 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2698 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2699 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2700 }
2701
2702 static void *si_create_sampler_state(struct pipe_context *ctx,
2703 const struct pipe_sampler_state *state)
2704 {
2705 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2706 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2707 unsigned border_color_type;
2708
2709 if (rstate == NULL) {
2710 return NULL;
2711 }
2712
2713 if (sampler_state_needs_border_color(state))
2714 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2715 else
2716 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2717
2718 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2719 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2720 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2721 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2722 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2723 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2724 aniso_flag_offset << 16 | /* XXX */
2725 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2726 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2727 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2728 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2729 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2730 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2731 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2732 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2733
2734 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2735 memcpy(rstate->border_color, state->border_color.ui,
2736 sizeof(rstate->border_color));
2737 }
2738
2739 return rstate;
2740 }
2741
2742 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2743 * the si_set_sampler_view calls. LTO might help too. */
2744 static void si_set_sampler_views(struct pipe_context *ctx,
2745 unsigned shader, unsigned start,
2746 unsigned count,
2747 struct pipe_sampler_view **views)
2748 {
2749 struct si_context *sctx = (struct si_context *)ctx;
2750 struct si_textures_info *samplers = &sctx->samplers[shader];
2751 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2752 int i;
2753
2754 if (shader >= SI_NUM_SHADERS)
2755 return;
2756
2757 assert(start == 0);
2758
2759 for (i = 0; i < count; i++) {
2760 if (!views[i]) {
2761 samplers->depth_texture_mask &= ~(1 << i);
2762 samplers->compressed_colortex_mask &= ~(1 << i);
2763 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2764 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2765 NULL, NULL);
2766 continue;
2767 }
2768
2769 si_set_sampler_view(sctx, shader, i, views[i], rviews[i]->state);
2770
2771 if (views[i]->texture->target != PIPE_BUFFER) {
2772 struct r600_texture *rtex =
2773 (struct r600_texture*)views[i]->texture;
2774
2775 if (rtex->is_depth && !rtex->is_flushing_texture) {
2776 samplers->depth_texture_mask |= 1 << i;
2777 } else {
2778 samplers->depth_texture_mask &= ~(1 << i);
2779 }
2780 if (rtex->cmask.size || rtex->fmask.size) {
2781 samplers->compressed_colortex_mask |= 1 << i;
2782 } else {
2783 samplers->compressed_colortex_mask &= ~(1 << i);
2784 }
2785
2786 if (rtex->fmask.size) {
2787 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2788 views[i], rviews[i]->fmask_state);
2789 } else {
2790 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2791 NULL, NULL);
2792 }
2793 }
2794 }
2795 for (; i < samplers->n_views; i++) {
2796 samplers->depth_texture_mask &= ~(1 << i);
2797 samplers->compressed_colortex_mask &= ~(1 << i);
2798 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2799 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2800 NULL, NULL);
2801 }
2802
2803 samplers->n_views = count;
2804 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2805 }
2806
2807 static void si_set_sampler_states(struct si_context *sctx,
2808 struct si_pm4_state *pm4,
2809 unsigned count, void **states,
2810 struct si_textures_info *samplers,
2811 unsigned user_data_reg)
2812 {
2813 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2814 uint32_t *border_color_table = NULL;
2815 int i, j;
2816
2817 if (!count)
2818 goto out;
2819
2820 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2821
2822 si_pm4_sh_data_begin(pm4);
2823 for (i = 0; i < count; i++) {
2824 if (rstates[i] &&
2825 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2826 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2827 if (!sctx->border_color_table ||
2828 ((sctx->border_color_offset + count - i) &
2829 C_008F3C_BORDER_COLOR_PTR)) {
2830 r600_resource_reference(&sctx->border_color_table, NULL);
2831 sctx->border_color_offset = 0;
2832
2833 sctx->border_color_table =
2834 si_resource_create_custom(&sctx->screen->b.b,
2835 PIPE_USAGE_STAGING,
2836 4096 * 4 * 4);
2837 }
2838
2839 if (!border_color_table) {
2840 border_color_table =
2841 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2842 sctx->b.rings.gfx.cs,
2843 PIPE_TRANSFER_WRITE |
2844 PIPE_TRANSFER_UNSYNCHRONIZED);
2845 }
2846
2847 for (j = 0; j < 4; j++) {
2848 border_color_table[4 * sctx->border_color_offset + j] =
2849 util_le32_to_cpu(rstates[i]->border_color[j]);
2850 }
2851
2852 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2853 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2854 }
2855
2856 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2857 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2858 }
2859 }
2860 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2861
2862 if (border_color_table) {
2863 uint64_t va_offset =
2864 r600_resource_va(&sctx->screen->b.b,
2865 (void*)sctx->border_color_table);
2866
2867 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2868 if (sctx->b.chip_class >= CIK)
2869 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2870 sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf);
2871 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2872 RADEON_PRIO_SHADER_DATA);
2873 }
2874
2875 memcpy(samplers->samplers, states, sizeof(void*) * count);
2876
2877 out:
2878 samplers->n_samplers = count;
2879 }
2880
2881 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2882 {
2883 struct si_context *sctx = (struct si_context *)ctx;
2884 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2885
2886 si_set_sampler_states(sctx, pm4, count, states,
2887 &sctx->samplers[PIPE_SHADER_VERTEX],
2888 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2889 #if HAVE_LLVM >= 0x0305
2890 si_set_sampler_states(sctx, pm4, count, states,
2891 &sctx->samplers[PIPE_SHADER_VERTEX],
2892 R_00B330_SPI_SHADER_USER_DATA_ES_0);
2893 #endif
2894 si_pm4_set_state(sctx, vs_sampler, pm4);
2895 }
2896
2897 static void si_bind_gs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2898 {
2899 struct si_context *sctx = (struct si_context *)ctx;
2900 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2901
2902 si_set_sampler_states(sctx, pm4, count, states,
2903 &sctx->samplers[PIPE_SHADER_GEOMETRY],
2904 R_00B230_SPI_SHADER_USER_DATA_GS_0);
2905 si_pm4_set_state(sctx, gs_sampler, pm4);
2906 }
2907
2908 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2909 {
2910 struct si_context *sctx = (struct si_context *)ctx;
2911 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2912
2913 si_set_sampler_states(sctx, pm4, count, states,
2914 &sctx->samplers[PIPE_SHADER_FRAGMENT],
2915 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2916 si_pm4_set_state(sctx, ps_sampler, pm4);
2917 }
2918
2919
2920 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2921 unsigned start, unsigned count,
2922 void **states)
2923 {
2924 assert(start == 0);
2925
2926 switch (shader) {
2927 case PIPE_SHADER_VERTEX:
2928 si_bind_vs_sampler_states(ctx, count, states);
2929 break;
2930 case PIPE_SHADER_GEOMETRY:
2931 si_bind_gs_sampler_states(ctx, count, states);
2932 break;
2933 case PIPE_SHADER_FRAGMENT:
2934 si_bind_ps_sampler_states(ctx, count, states);
2935 break;
2936 default:
2937 ;
2938 }
2939 }
2940
2941
2942
2943 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2944 {
2945 struct si_context *sctx = (struct si_context *)ctx;
2946 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2947 uint16_t mask = sample_mask;
2948
2949 if (pm4 == NULL)
2950 return;
2951
2952 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2953 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2954
2955 si_pm4_set_state(sctx, sample_mask, pm4);
2956 }
2957
2958 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2959 {
2960 free(state);
2961 }
2962
2963 /*
2964 * Vertex elements & buffers
2965 */
2966
2967 static void *si_create_vertex_elements(struct pipe_context *ctx,
2968 unsigned count,
2969 const struct pipe_vertex_element *elements)
2970 {
2971 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2972 int i;
2973
2974 assert(count < PIPE_MAX_ATTRIBS);
2975 if (!v)
2976 return NULL;
2977
2978 v->count = count;
2979 for (i = 0; i < count; ++i) {
2980 const struct util_format_description *desc;
2981 unsigned data_format, num_format;
2982 int first_non_void;
2983
2984 desc = util_format_description(elements[i].src_format);
2985 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2986 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2987 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2988
2989 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2990 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2991 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2992 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2993 S_008F0C_NUM_FORMAT(num_format) |
2994 S_008F0C_DATA_FORMAT(data_format);
2995 }
2996 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2997
2998 return v;
2999 }
3000
3001 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3002 {
3003 struct si_context *sctx = (struct si_context *)ctx;
3004 struct si_vertex_element *v = (struct si_vertex_element*)state;
3005
3006 sctx->vertex_elements = v;
3007 }
3008
3009 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3010 {
3011 struct si_context *sctx = (struct si_context *)ctx;
3012
3013 if (sctx->vertex_elements == state)
3014 sctx->vertex_elements = NULL;
3015 FREE(state);
3016 }
3017
3018 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
3019 const struct pipe_vertex_buffer *buffers)
3020 {
3021 struct si_context *sctx = (struct si_context *)ctx;
3022
3023 util_set_vertex_buffers_count(sctx->vertex_buffer, &sctx->nr_vertex_buffers, buffers, start_slot, count);
3024 }
3025
3026 static void si_set_index_buffer(struct pipe_context *ctx,
3027 const struct pipe_index_buffer *ib)
3028 {
3029 struct si_context *sctx = (struct si_context *)ctx;
3030
3031 if (ib) {
3032 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3033 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3034 } else {
3035 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3036 }
3037 }
3038
3039 /*
3040 * Misc
3041 */
3042 static void si_set_polygon_stipple(struct pipe_context *ctx,
3043 const struct pipe_poly_stipple *state)
3044 {
3045 }
3046
3047 static void si_texture_barrier(struct pipe_context *ctx)
3048 {
3049 struct si_context *sctx = (struct si_context *)ctx;
3050
3051 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
3052 R600_CONTEXT_FLUSH_AND_INV_CB;
3053 }
3054
3055 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3056 {
3057 struct pipe_blend_state blend;
3058
3059 memset(&blend, 0, sizeof(blend));
3060 blend.independent_blend_enable = true;
3061 blend.rt[0].colormask = 0xf;
3062 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3063 }
3064
3065 static boolean si_dma_copy(struct pipe_context *ctx,
3066 struct pipe_resource *dst,
3067 unsigned dst_level,
3068 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3069 struct pipe_resource *src,
3070 unsigned src_level,
3071 const struct pipe_box *src_box)
3072 {
3073 /* XXX implement this or share evergreen_dma_blit with r600g */
3074 return FALSE;
3075 }
3076
3077 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
3078 {
3079 /* XXX Turn this into a proper state. Right now the queries are
3080 * enabled in draw_vbo, which snoops r600_common_context to see
3081 * if any occlusion queries are active. */
3082 }
3083
3084 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3085 bool include_draw_vbo)
3086 {
3087 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
3088 }
3089
3090 void si_init_state_functions(struct si_context *sctx)
3091 {
3092 int i;
3093
3094 sctx->b.b.create_blend_state = si_create_blend_state;
3095 sctx->b.b.bind_blend_state = si_bind_blend_state;
3096 sctx->b.b.delete_blend_state = si_delete_blend_state;
3097 sctx->b.b.set_blend_color = si_set_blend_color;
3098
3099 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3100 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3101 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3102
3103 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3104 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3105 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3106
3107 for (i = 0; i < 8; i++) {
3108 sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i);
3109 sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i);
3110 sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i);
3111 }
3112 sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0);
3113 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3114 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3115
3116 sctx->b.b.set_clip_state = si_set_clip_state;
3117 sctx->b.b.set_scissor_states = si_set_scissor_states;
3118 sctx->b.b.set_viewport_states = si_set_viewport_states;
3119 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3120
3121 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3122 sctx->b.b.get_sample_position = si_get_sample_position;
3123
3124 sctx->b.b.create_vs_state = si_create_vs_state;
3125 sctx->b.b.create_fs_state = si_create_fs_state;
3126 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3127 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3128 sctx->b.b.delete_vs_state = si_delete_vs_shader;
3129 sctx->b.b.delete_fs_state = si_delete_ps_shader;
3130 #if HAVE_LLVM >= 0x0305
3131 sctx->b.b.create_gs_state = si_create_gs_state;
3132 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3133 sctx->b.b.delete_gs_state = si_delete_gs_shader;
3134 #endif
3135
3136 sctx->b.b.create_sampler_state = si_create_sampler_state;
3137 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3138 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3139
3140 sctx->b.b.create_sampler_view = si_create_sampler_view;
3141 sctx->b.b.set_sampler_views = si_set_sampler_views;
3142 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3143
3144 sctx->b.b.set_sample_mask = si_set_sample_mask;
3145
3146 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3147 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3148 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3149 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3150 sctx->b.b.set_index_buffer = si_set_index_buffer;
3151
3152 sctx->b.b.texture_barrier = si_texture_barrier;
3153 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3154 sctx->b.dma_copy = si_dma_copy;
3155 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3156 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3157
3158 sctx->b.b.draw_vbo = si_draw_vbo;
3159 }
3160
3161 void si_init_config(struct si_context *sctx)
3162 {
3163 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
3164
3165 if (pm4 == NULL)
3166 return;
3167
3168 si_cmd_context_control(pm4);
3169
3170 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3171
3172 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3173 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3174 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3175 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3176 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3177 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3178 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3179 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3180 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3181 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3182 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3183 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3184
3185 /* FIXME calculate these values somehow ??? */
3186 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3187 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3188 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3189
3190 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3191 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3192 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3193 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3194
3195 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3196 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3197 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3198 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3199
3200 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3201 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3202 if (sctx->b.chip_class == SI) {
3203 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3204 S_028AA8_SWITCH_ON_EOP(1) |
3205 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3206 S_028AA8_PRIMGROUP_SIZE(63));
3207 }
3208 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3209 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3210 if (sctx->b.chip_class < CIK)
3211 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3212 S_008A14_CLIP_VTX_REORDER_ENA(1));
3213
3214 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3215 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3216
3217 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3218
3219 if (sctx->b.chip_class >= CIK) {
3220 switch (sctx->screen->b.family) {
3221 case CHIP_BONAIRE:
3222 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3223 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3224 break;
3225 case CHIP_HAWAII:
3226 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3227 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3228 break;
3229 case CHIP_KAVERI:
3230 /* XXX todo */
3231 case CHIP_KABINI:
3232 /* XXX todo */
3233 default:
3234 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3235 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3236 break;
3237 }
3238 } else {
3239 switch (sctx->screen->b.family) {
3240 case CHIP_TAHITI:
3241 case CHIP_PITCAIRN:
3242 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3243 break;
3244 case CHIP_VERDE:
3245 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3246 break;
3247 case CHIP_OLAND:
3248 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3249 break;
3250 case CHIP_HAINAN:
3251 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3252 break;
3253 default:
3254 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3255 break;
3256 }
3257 }
3258
3259 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3260 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3261 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3262 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3263 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3264 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3265 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3266
3267 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3268 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3269 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3270 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3271 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3272 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3273 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3274 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3275 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3276 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3277 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3278 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3279 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3280 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3281 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3282 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3283 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3284 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3285 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3286 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3287 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3288 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3289
3290 if (sctx->b.chip_class >= CIK) {
3291 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3292 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3293 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3294 }
3295
3296 si_pm4_set_state(sctx, init, pm4);
3297 }