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r600g,radeonsi: move CMASK register values from r600_surface to r600_texture
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "../radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_helpers.h"
38 #include "util/u_memory.h"
39
40 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
41 void (*emit)(struct si_context *ctx, struct r600_atom *state),
42 unsigned num_dw)
43 {
44 atom->emit = (void*)emit;
45 atom->num_dw = num_dw;
46 atom->dirty = false;
47 *list_elem = atom;
48 }
49
50 static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split)
51 {
52 if (sscreen->b.info.cik_macrotile_mode_array_valid) {
53 unsigned index, tileb;
54
55 tileb = 8 * 8 * bpe;
56 tileb = MIN2(tile_split, tileb);
57
58 for (index = 0; tileb > 64; index++) {
59 tileb >>= 1;
60 }
61
62 assert(index < 16);
63
64 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
65 }
66
67 /* The old way. */
68 switch (sscreen->b.tiling_info.num_banks) {
69 case 2:
70 return V_02803C_ADDR_SURF_2_BANK;
71 case 4:
72 return V_02803C_ADDR_SURF_4_BANK;
73 case 8:
74 default:
75 return V_02803C_ADDR_SURF_8_BANK;
76 case 16:
77 return V_02803C_ADDR_SURF_16_BANK;
78 }
79 }
80
81 static unsigned cik_tile_split(unsigned tile_split)
82 {
83 switch (tile_split) {
84 case 64:
85 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
86 break;
87 case 128:
88 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
89 break;
90 case 256:
91 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
92 break;
93 case 512:
94 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
95 break;
96 default:
97 case 1024:
98 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
99 break;
100 case 2048:
101 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
102 break;
103 case 4096:
104 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
105 break;
106 }
107 return tile_split;
108 }
109
110 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
111 {
112 switch (macro_tile_aspect) {
113 default:
114 case 1:
115 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
116 break;
117 case 2:
118 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
119 break;
120 case 4:
121 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
122 break;
123 case 8:
124 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
125 break;
126 }
127 return macro_tile_aspect;
128 }
129
130 static unsigned cik_bank_wh(unsigned bankwh)
131 {
132 switch (bankwh) {
133 default:
134 case 1:
135 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
136 break;
137 case 2:
138 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
139 break;
140 case 4:
141 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
142 break;
143 case 8:
144 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
145 break;
146 }
147 return bankwh;
148 }
149
150 static unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
151 {
152 if (sscreen->b.info.si_tile_mode_array_valid) {
153 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
154
155 return G_009910_PIPE_CONFIG(gb_tile_mode);
156 }
157
158 /* This is probably broken for a lot of chips, but it's only used
159 * if the kernel cannot return the tile mode array for CIK. */
160 switch (sscreen->b.info.r600_num_tile_pipes) {
161 case 16:
162 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
163 case 8:
164 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
165 case 4:
166 default:
167 if (sscreen->b.info.r600_num_backends == 4)
168 return V_02803C_X_ADDR_SURF_P4_16X16;
169 else
170 return V_02803C_X_ADDR_SURF_P4_8X16;
171 case 2:
172 return V_02803C_ADDR_SURF_P2;
173 }
174 }
175
176 static unsigned si_map_swizzle(unsigned swizzle)
177 {
178 switch (swizzle) {
179 case UTIL_FORMAT_SWIZZLE_Y:
180 return V_008F0C_SQ_SEL_Y;
181 case UTIL_FORMAT_SWIZZLE_Z:
182 return V_008F0C_SQ_SEL_Z;
183 case UTIL_FORMAT_SWIZZLE_W:
184 return V_008F0C_SQ_SEL_W;
185 case UTIL_FORMAT_SWIZZLE_0:
186 return V_008F0C_SQ_SEL_0;
187 case UTIL_FORMAT_SWIZZLE_1:
188 return V_008F0C_SQ_SEL_1;
189 default: /* UTIL_FORMAT_SWIZZLE_X */
190 return V_008F0C_SQ_SEL_X;
191 }
192 }
193
194 static uint32_t S_FIXED(float value, uint32_t frac_bits)
195 {
196 return value * (1 << frac_bits);
197 }
198
199 /* 12.4 fixed-point */
200 static unsigned si_pack_float_12p4(float x)
201 {
202 return x <= 0 ? 0 :
203 x >= 4096 ? 0xffff : x * 16;
204 }
205
206 /*
207 * inferred framebuffer and blender state
208 */
209 static void si_update_fb_blend_state(struct si_context *sctx)
210 {
211 struct si_pm4_state *pm4;
212 struct si_state_blend *blend = sctx->queued.named.blend;
213 uint32_t mask;
214
215 if (blend == NULL)
216 return;
217
218 pm4 = si_pm4_alloc_state(sctx);
219 if (pm4 == NULL)
220 return;
221
222 mask = (1ULL << ((unsigned)sctx->framebuffer.state.nr_cbufs * 4)) - 1;
223 mask &= blend->cb_target_mask;
224 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
225
226 si_pm4_set_state(sctx, fb_blend, pm4);
227 }
228
229 /*
230 * Blender functions
231 */
232
233 static uint32_t si_translate_blend_function(int blend_func)
234 {
235 switch (blend_func) {
236 case PIPE_BLEND_ADD:
237 return V_028780_COMB_DST_PLUS_SRC;
238 case PIPE_BLEND_SUBTRACT:
239 return V_028780_COMB_SRC_MINUS_DST;
240 case PIPE_BLEND_REVERSE_SUBTRACT:
241 return V_028780_COMB_DST_MINUS_SRC;
242 case PIPE_BLEND_MIN:
243 return V_028780_COMB_MIN_DST_SRC;
244 case PIPE_BLEND_MAX:
245 return V_028780_COMB_MAX_DST_SRC;
246 default:
247 R600_ERR("Unknown blend function %d\n", blend_func);
248 assert(0);
249 break;
250 }
251 return 0;
252 }
253
254 static uint32_t si_translate_blend_factor(int blend_fact)
255 {
256 switch (blend_fact) {
257 case PIPE_BLENDFACTOR_ONE:
258 return V_028780_BLEND_ONE;
259 case PIPE_BLENDFACTOR_SRC_COLOR:
260 return V_028780_BLEND_SRC_COLOR;
261 case PIPE_BLENDFACTOR_SRC_ALPHA:
262 return V_028780_BLEND_SRC_ALPHA;
263 case PIPE_BLENDFACTOR_DST_ALPHA:
264 return V_028780_BLEND_DST_ALPHA;
265 case PIPE_BLENDFACTOR_DST_COLOR:
266 return V_028780_BLEND_DST_COLOR;
267 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
268 return V_028780_BLEND_SRC_ALPHA_SATURATE;
269 case PIPE_BLENDFACTOR_CONST_COLOR:
270 return V_028780_BLEND_CONSTANT_COLOR;
271 case PIPE_BLENDFACTOR_CONST_ALPHA:
272 return V_028780_BLEND_CONSTANT_ALPHA;
273 case PIPE_BLENDFACTOR_ZERO:
274 return V_028780_BLEND_ZERO;
275 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
276 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
277 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
278 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
279 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
280 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
281 case PIPE_BLENDFACTOR_INV_DST_COLOR:
282 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
283 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
284 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
285 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
286 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
287 case PIPE_BLENDFACTOR_SRC1_COLOR:
288 return V_028780_BLEND_SRC1_COLOR;
289 case PIPE_BLENDFACTOR_SRC1_ALPHA:
290 return V_028780_BLEND_SRC1_ALPHA;
291 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
292 return V_028780_BLEND_INV_SRC1_COLOR;
293 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
294 return V_028780_BLEND_INV_SRC1_ALPHA;
295 default:
296 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
297 assert(0);
298 break;
299 }
300 return 0;
301 }
302
303 static void *si_create_blend_state_mode(struct pipe_context *ctx,
304 const struct pipe_blend_state *state,
305 unsigned mode)
306 {
307 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
308 struct si_pm4_state *pm4 = &blend->pm4;
309
310 uint32_t color_control = 0;
311
312 if (blend == NULL)
313 return NULL;
314
315 blend->alpha_to_one = state->alpha_to_one;
316
317 if (state->logicop_enable) {
318 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
319 } else {
320 color_control |= S_028808_ROP3(0xcc);
321 }
322
323 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
324 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
325 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
326 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
327 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
328 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
329
330 blend->cb_target_mask = 0;
331 for (int i = 0; i < 8; i++) {
332 /* state->rt entries > 0 only written if independent blending */
333 const int j = state->independent_blend_enable ? i : 0;
334
335 unsigned eqRGB = state->rt[j].rgb_func;
336 unsigned srcRGB = state->rt[j].rgb_src_factor;
337 unsigned dstRGB = state->rt[j].rgb_dst_factor;
338 unsigned eqA = state->rt[j].alpha_func;
339 unsigned srcA = state->rt[j].alpha_src_factor;
340 unsigned dstA = state->rt[j].alpha_dst_factor;
341
342 unsigned blend_cntl = 0;
343
344 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
345 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
346
347 if (!state->rt[j].blend_enable) {
348 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
349 continue;
350 }
351
352 blend_cntl |= S_028780_ENABLE(1);
353 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
354 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
355 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
356
357 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
358 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
359 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
360 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
361 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
362 }
363 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
364 }
365
366 if (blend->cb_target_mask) {
367 color_control |= S_028808_MODE(mode);
368 } else {
369 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
370 }
371 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
372
373 return blend;
374 }
375
376 static void *si_create_blend_state(struct pipe_context *ctx,
377 const struct pipe_blend_state *state)
378 {
379 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
380 }
381
382 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
383 {
384 struct si_context *sctx = (struct si_context *)ctx;
385 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
386 si_update_fb_blend_state(sctx);
387 }
388
389 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
390 {
391 struct si_context *sctx = (struct si_context *)ctx;
392 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
393 }
394
395 static void si_set_blend_color(struct pipe_context *ctx,
396 const struct pipe_blend_color *state)
397 {
398 struct si_context *sctx = (struct si_context *)ctx;
399 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
400
401 if (pm4 == NULL)
402 return;
403
404 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
405 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
406 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
407 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
408
409 si_pm4_set_state(sctx, blend_color, pm4);
410 }
411
412 /*
413 * Clipping, scissors and viewport
414 */
415
416 static void si_set_clip_state(struct pipe_context *ctx,
417 const struct pipe_clip_state *state)
418 {
419 struct si_context *sctx = (struct si_context *)ctx;
420 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
421 struct pipe_constant_buffer cb;
422
423 if (pm4 == NULL)
424 return;
425
426 for (int i = 0; i < 6; i++) {
427 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
428 fui(state->ucp[i][0]));
429 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
430 fui(state->ucp[i][1]));
431 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
432 fui(state->ucp[i][2]));
433 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
434 fui(state->ucp[i][3]));
435 }
436
437 cb.buffer = NULL;
438 cb.user_buffer = state->ucp;
439 cb.buffer_offset = 0;
440 cb.buffer_size = 4*4*8;
441 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
442 pipe_resource_reference(&cb.buffer, NULL);
443
444 si_pm4_set_state(sctx, clip, pm4);
445 }
446
447 static void si_set_scissor_states(struct pipe_context *ctx,
448 unsigned start_slot,
449 unsigned num_scissors,
450 const struct pipe_scissor_state *state)
451 {
452 struct si_context *sctx = (struct si_context *)ctx;
453 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
454
455 if (pm4 == NULL)
456 return;
457
458 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
459 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
460 S_028250_WINDOW_OFFSET_DISABLE(1));
461 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
462 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
463
464 si_pm4_set_state(sctx, scissor, pm4);
465 }
466
467 static void si_set_viewport_states(struct pipe_context *ctx,
468 unsigned start_slot,
469 unsigned num_viewports,
470 const struct pipe_viewport_state *state)
471 {
472 struct si_context *sctx = (struct si_context *)ctx;
473 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
474 struct si_pm4_state *pm4 = &viewport->pm4;
475
476 if (viewport == NULL)
477 return;
478
479 viewport->viewport = *state;
480 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
481 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
482 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
483 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
484 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
485 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
486
487 si_pm4_set_state(sctx, viewport, viewport);
488 }
489
490 /*
491 * inferred state between framebuffer and rasterizer
492 */
493 static void si_update_fb_rs_state(struct si_context *sctx)
494 {
495 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
496 struct si_pm4_state *pm4;
497 float offset_units;
498
499 if (!rs || !sctx->framebuffer.state.zsbuf)
500 return;
501
502 offset_units = sctx->queued.named.rasterizer->offset_units;
503 switch (sctx->framebuffer.state.zsbuf->texture->format) {
504 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
505 case PIPE_FORMAT_X8Z24_UNORM:
506 case PIPE_FORMAT_Z24X8_UNORM:
507 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
508 offset_units *= 2.0f;
509 break;
510 case PIPE_FORMAT_Z32_FLOAT:
511 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
512 offset_units *= 1.0f;
513 break;
514 case PIPE_FORMAT_Z16_UNORM:
515 offset_units *= 4.0f;
516 break;
517 default:
518 return;
519 }
520
521 pm4 = si_pm4_alloc_state(sctx);
522
523 if (pm4 == NULL)
524 return;
525
526 /* FIXME some of those reg can be computed with cso */
527 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
528 fui(sctx->queued.named.rasterizer->offset_scale));
529 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
530 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
531 fui(sctx->queued.named.rasterizer->offset_scale));
532 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
533
534 si_pm4_set_state(sctx, fb_rs, pm4);
535 }
536
537 /*
538 * Rasterizer
539 */
540
541 static uint32_t si_translate_fill(uint32_t func)
542 {
543 switch(func) {
544 case PIPE_POLYGON_MODE_FILL:
545 return V_028814_X_DRAW_TRIANGLES;
546 case PIPE_POLYGON_MODE_LINE:
547 return V_028814_X_DRAW_LINES;
548 case PIPE_POLYGON_MODE_POINT:
549 return V_028814_X_DRAW_POINTS;
550 default:
551 assert(0);
552 return V_028814_X_DRAW_POINTS;
553 }
554 }
555
556 static void *si_create_rs_state(struct pipe_context *ctx,
557 const struct pipe_rasterizer_state *state)
558 {
559 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
560 struct si_pm4_state *pm4 = &rs->pm4;
561 unsigned tmp;
562 unsigned prov_vtx = 1, polygon_dual_mode;
563 float psize_min, psize_max;
564
565 if (rs == NULL) {
566 return NULL;
567 }
568
569 rs->two_side = state->light_twoside;
570 rs->multisample_enable = state->multisample;
571 rs->clip_plane_enable = state->clip_plane_enable;
572 rs->line_stipple_enable = state->line_stipple_enable;
573
574 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
575 state->fill_back != PIPE_POLYGON_MODE_FILL);
576
577 if (state->flatshade_first)
578 prov_vtx = 0;
579
580 rs->flatshade = state->flatshade;
581 rs->sprite_coord_enable = state->sprite_coord_enable;
582 rs->pa_sc_line_stipple = state->line_stipple_enable ?
583 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
584 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
585 rs->pa_su_sc_mode_cntl =
586 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
587 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
588 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
589 S_028814_FACE(!state->front_ccw) |
590 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
591 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
592 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
593 S_028814_POLY_MODE(polygon_dual_mode) |
594 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
595 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
596 rs->pa_cl_clip_cntl =
597 S_028810_PS_UCP_MODE(3) |
598 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
599 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
600 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
601 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
602
603 /* offset */
604 rs->offset_units = state->offset_units;
605 rs->offset_scale = state->offset_scale * 12.0f;
606
607 tmp = S_0286D4_FLAT_SHADE_ENA(1);
608 if (state->sprite_coord_enable) {
609 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
610 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
611 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
612 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
613 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
614 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
615 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
616 }
617 }
618 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
619
620 /* point size 12.4 fixed point */
621 tmp = (unsigned)(state->point_size * 8.0);
622 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
623
624 if (state->point_size_per_vertex) {
625 psize_min = util_get_min_point_size(state);
626 psize_max = 8192;
627 } else {
628 /* Force the point size to be as if the vertex output was disabled. */
629 psize_min = state->point_size;
630 psize_max = state->point_size;
631 }
632 /* Divide by two, because 0.5 = 1 pixel. */
633 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
634 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
635 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
636
637 tmp = (unsigned)state->line_width * 8;
638 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
639 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
640 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
641 S_028A48_MSAA_ENABLE(state->multisample) |
642 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
643
644 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
645 S_028BE4_PIX_CENTER(state->half_pixel_center) |
646 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
647
648 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
649
650 return rs;
651 }
652
653 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
654 {
655 struct si_context *sctx = (struct si_context *)ctx;
656 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
657
658 if (state == NULL)
659 return;
660
661 // TODO
662 sctx->sprite_coord_enable = rs->sprite_coord_enable;
663 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
664 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
665
666 si_pm4_bind_state(sctx, rasterizer, rs);
667 si_update_fb_rs_state(sctx);
668 }
669
670 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
671 {
672 struct si_context *sctx = (struct si_context *)ctx;
673 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
674 }
675
676 /*
677 * infeered state between dsa and stencil ref
678 */
679 static void si_update_dsa_stencil_ref(struct si_context *sctx)
680 {
681 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
682 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
683 struct si_state_dsa *dsa = sctx->queued.named.dsa;
684
685 if (pm4 == NULL)
686 return;
687
688 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
689 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
690 S_028430_STENCILMASK(dsa->valuemask[0]) |
691 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
692 S_028430_STENCILOPVAL(1));
693 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
694 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
695 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
696 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
697 S_028434_STENCILOPVAL_BF(1));
698
699 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
700 }
701
702 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
703 const struct pipe_stencil_ref *state)
704 {
705 struct si_context *sctx = (struct si_context *)ctx;
706 sctx->stencil_ref = *state;
707 si_update_dsa_stencil_ref(sctx);
708 }
709
710
711 /*
712 * DSA
713 */
714
715 static uint32_t si_translate_stencil_op(int s_op)
716 {
717 switch (s_op) {
718 case PIPE_STENCIL_OP_KEEP:
719 return V_02842C_STENCIL_KEEP;
720 case PIPE_STENCIL_OP_ZERO:
721 return V_02842C_STENCIL_ZERO;
722 case PIPE_STENCIL_OP_REPLACE:
723 return V_02842C_STENCIL_REPLACE_TEST;
724 case PIPE_STENCIL_OP_INCR:
725 return V_02842C_STENCIL_ADD_CLAMP;
726 case PIPE_STENCIL_OP_DECR:
727 return V_02842C_STENCIL_SUB_CLAMP;
728 case PIPE_STENCIL_OP_INCR_WRAP:
729 return V_02842C_STENCIL_ADD_WRAP;
730 case PIPE_STENCIL_OP_DECR_WRAP:
731 return V_02842C_STENCIL_SUB_WRAP;
732 case PIPE_STENCIL_OP_INVERT:
733 return V_02842C_STENCIL_INVERT;
734 default:
735 R600_ERR("Unknown stencil op %d", s_op);
736 assert(0);
737 break;
738 }
739 return 0;
740 }
741
742 static void *si_create_dsa_state(struct pipe_context *ctx,
743 const struct pipe_depth_stencil_alpha_state *state)
744 {
745 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
746 struct si_pm4_state *pm4 = &dsa->pm4;
747 unsigned db_depth_control;
748 unsigned db_render_control;
749 uint32_t db_stencil_control = 0;
750
751 if (dsa == NULL) {
752 return NULL;
753 }
754
755 dsa->valuemask[0] = state->stencil[0].valuemask;
756 dsa->valuemask[1] = state->stencil[1].valuemask;
757 dsa->writemask[0] = state->stencil[0].writemask;
758 dsa->writemask[1] = state->stencil[1].writemask;
759
760 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
761 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
762 S_028800_ZFUNC(state->depth.func);
763
764 /* stencil */
765 if (state->stencil[0].enabled) {
766 db_depth_control |= S_028800_STENCIL_ENABLE(1);
767 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
768 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
769 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
770 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
771
772 if (state->stencil[1].enabled) {
773 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
774 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
775 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
776 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
777 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
778 }
779 }
780
781 /* alpha */
782 if (state->alpha.enabled) {
783 dsa->alpha_func = state->alpha.func;
784 dsa->alpha_ref = state->alpha.ref_value;
785
786 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
787 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
788 } else {
789 dsa->alpha_func = PIPE_FUNC_ALWAYS;
790 }
791
792 /* misc */
793 db_render_control = 0;
794 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
795 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
796 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
797
798 return dsa;
799 }
800
801 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
802 {
803 struct si_context *sctx = (struct si_context *)ctx;
804 struct si_state_dsa *dsa = state;
805
806 if (state == NULL)
807 return;
808
809 si_pm4_bind_state(sctx, dsa, dsa);
810 si_update_dsa_stencil_ref(sctx);
811 }
812
813 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
814 {
815 struct si_context *sctx = (struct si_context *)ctx;
816 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
817 }
818
819 static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth,
820 bool copy_stencil, int sample)
821 {
822 struct pipe_depth_stencil_alpha_state dsa;
823 struct si_state_dsa *state;
824
825 memset(&dsa, 0, sizeof(dsa));
826
827 state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
828 if (copy_depth || copy_stencil) {
829 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
830 S_028000_DEPTH_COPY(copy_depth) |
831 S_028000_STENCIL_COPY(copy_stencil) |
832 S_028000_COPY_CENTROID(1) |
833 S_028000_COPY_SAMPLE(sample));
834 } else {
835 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
836 S_028000_DEPTH_COMPRESS_DISABLE(1) |
837 S_028000_STENCIL_COMPRESS_DISABLE(1));
838 }
839
840 return state;
841 }
842
843 /*
844 * format translation
845 */
846 static uint32_t si_translate_colorformat(enum pipe_format format)
847 {
848 const struct util_format_description *desc = util_format_description(format);
849
850 #define HAS_SIZE(x,y,z,w) \
851 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
852 desc->channel[2].size == (z) && desc->channel[3].size == (w))
853
854 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
855 return V_028C70_COLOR_10_11_11;
856
857 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
858 return V_028C70_COLOR_INVALID;
859
860 switch (desc->nr_channels) {
861 case 1:
862 switch (desc->channel[0].size) {
863 case 8:
864 return V_028C70_COLOR_8;
865 case 16:
866 return V_028C70_COLOR_16;
867 case 32:
868 return V_028C70_COLOR_32;
869 }
870 break;
871 case 2:
872 if (desc->channel[0].size == desc->channel[1].size) {
873 switch (desc->channel[0].size) {
874 case 8:
875 return V_028C70_COLOR_8_8;
876 case 16:
877 return V_028C70_COLOR_16_16;
878 case 32:
879 return V_028C70_COLOR_32_32;
880 }
881 } else if (HAS_SIZE(8,24,0,0)) {
882 return V_028C70_COLOR_24_8;
883 } else if (HAS_SIZE(24,8,0,0)) {
884 return V_028C70_COLOR_8_24;
885 }
886 break;
887 case 3:
888 if (HAS_SIZE(5,6,5,0)) {
889 return V_028C70_COLOR_5_6_5;
890 } else if (HAS_SIZE(32,8,24,0)) {
891 return V_028C70_COLOR_X24_8_32_FLOAT;
892 }
893 break;
894 case 4:
895 if (desc->channel[0].size == desc->channel[1].size &&
896 desc->channel[0].size == desc->channel[2].size &&
897 desc->channel[0].size == desc->channel[3].size) {
898 switch (desc->channel[0].size) {
899 case 4:
900 return V_028C70_COLOR_4_4_4_4;
901 case 8:
902 return V_028C70_COLOR_8_8_8_8;
903 case 16:
904 return V_028C70_COLOR_16_16_16_16;
905 case 32:
906 return V_028C70_COLOR_32_32_32_32;
907 }
908 } else if (HAS_SIZE(5,5,5,1)) {
909 return V_028C70_COLOR_1_5_5_5;
910 } else if (HAS_SIZE(10,10,10,2)) {
911 return V_028C70_COLOR_2_10_10_10;
912 }
913 break;
914 }
915 return V_028C70_COLOR_INVALID;
916 }
917
918 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
919 {
920 if (SI_BIG_ENDIAN) {
921 switch(colorformat) {
922 /* 8-bit buffers. */
923 case V_028C70_COLOR_8:
924 return V_028C70_ENDIAN_NONE;
925
926 /* 16-bit buffers. */
927 case V_028C70_COLOR_5_6_5:
928 case V_028C70_COLOR_1_5_5_5:
929 case V_028C70_COLOR_4_4_4_4:
930 case V_028C70_COLOR_16:
931 case V_028C70_COLOR_8_8:
932 return V_028C70_ENDIAN_8IN16;
933
934 /* 32-bit buffers. */
935 case V_028C70_COLOR_8_8_8_8:
936 case V_028C70_COLOR_2_10_10_10:
937 case V_028C70_COLOR_8_24:
938 case V_028C70_COLOR_24_8:
939 case V_028C70_COLOR_16_16:
940 return V_028C70_ENDIAN_8IN32;
941
942 /* 64-bit buffers. */
943 case V_028C70_COLOR_16_16_16_16:
944 return V_028C70_ENDIAN_8IN16;
945
946 case V_028C70_COLOR_32_32:
947 return V_028C70_ENDIAN_8IN32;
948
949 /* 128-bit buffers. */
950 case V_028C70_COLOR_32_32_32_32:
951 return V_028C70_ENDIAN_8IN32;
952 default:
953 return V_028C70_ENDIAN_NONE; /* Unsupported. */
954 }
955 } else {
956 return V_028C70_ENDIAN_NONE;
957 }
958 }
959
960 /* Returns the size in bits of the widest component of a CB format */
961 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
962 {
963 switch(colorformat) {
964 case V_028C70_COLOR_4_4_4_4:
965 return 4;
966
967 case V_028C70_COLOR_1_5_5_5:
968 case V_028C70_COLOR_5_5_5_1:
969 return 5;
970
971 case V_028C70_COLOR_5_6_5:
972 return 6;
973
974 case V_028C70_COLOR_8:
975 case V_028C70_COLOR_8_8:
976 case V_028C70_COLOR_8_8_8_8:
977 return 8;
978
979 case V_028C70_COLOR_10_10_10_2:
980 case V_028C70_COLOR_2_10_10_10:
981 return 10;
982
983 case V_028C70_COLOR_10_11_11:
984 case V_028C70_COLOR_11_11_10:
985 return 11;
986
987 case V_028C70_COLOR_16:
988 case V_028C70_COLOR_16_16:
989 case V_028C70_COLOR_16_16_16_16:
990 return 16;
991
992 case V_028C70_COLOR_8_24:
993 case V_028C70_COLOR_24_8:
994 return 24;
995
996 case V_028C70_COLOR_32:
997 case V_028C70_COLOR_32_32:
998 case V_028C70_COLOR_32_32_32_32:
999 case V_028C70_COLOR_X24_8_32_FLOAT:
1000 return 32;
1001 }
1002
1003 assert(!"Unknown maximum component size");
1004 return 0;
1005 }
1006
1007 static uint32_t si_translate_dbformat(enum pipe_format format)
1008 {
1009 switch (format) {
1010 case PIPE_FORMAT_Z16_UNORM:
1011 return V_028040_Z_16;
1012 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1013 case PIPE_FORMAT_X8Z24_UNORM:
1014 case PIPE_FORMAT_Z24X8_UNORM:
1015 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1016 return V_028040_Z_24; /* deprecated on SI */
1017 case PIPE_FORMAT_Z32_FLOAT:
1018 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1019 return V_028040_Z_32_FLOAT;
1020 default:
1021 return V_028040_Z_INVALID;
1022 }
1023 }
1024
1025 /*
1026 * Texture translation
1027 */
1028
1029 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1030 enum pipe_format format,
1031 const struct util_format_description *desc,
1032 int first_non_void)
1033 {
1034 struct si_screen *sscreen = (struct si_screen*)screen;
1035 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1036 boolean uniform = TRUE;
1037 int i;
1038
1039 /* Colorspace (return non-RGB formats directly). */
1040 switch (desc->colorspace) {
1041 /* Depth stencil formats */
1042 case UTIL_FORMAT_COLORSPACE_ZS:
1043 switch (format) {
1044 case PIPE_FORMAT_Z16_UNORM:
1045 return V_008F14_IMG_DATA_FORMAT_16;
1046 case PIPE_FORMAT_X24S8_UINT:
1047 case PIPE_FORMAT_Z24X8_UNORM:
1048 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1049 return V_008F14_IMG_DATA_FORMAT_8_24;
1050 case PIPE_FORMAT_X8Z24_UNORM:
1051 case PIPE_FORMAT_S8X24_UINT:
1052 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1053 return V_008F14_IMG_DATA_FORMAT_24_8;
1054 case PIPE_FORMAT_S8_UINT:
1055 return V_008F14_IMG_DATA_FORMAT_8;
1056 case PIPE_FORMAT_Z32_FLOAT:
1057 return V_008F14_IMG_DATA_FORMAT_32;
1058 case PIPE_FORMAT_X32_S8X24_UINT:
1059 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1060 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1061 default:
1062 goto out_unknown;
1063 }
1064
1065 case UTIL_FORMAT_COLORSPACE_YUV:
1066 goto out_unknown; /* TODO */
1067
1068 case UTIL_FORMAT_COLORSPACE_SRGB:
1069 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1070 goto out_unknown;
1071 break;
1072
1073 default:
1074 break;
1075 }
1076
1077 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1078 if (!enable_s3tc)
1079 goto out_unknown;
1080
1081 switch (format) {
1082 case PIPE_FORMAT_RGTC1_SNORM:
1083 case PIPE_FORMAT_LATC1_SNORM:
1084 case PIPE_FORMAT_RGTC1_UNORM:
1085 case PIPE_FORMAT_LATC1_UNORM:
1086 return V_008F14_IMG_DATA_FORMAT_BC4;
1087 case PIPE_FORMAT_RGTC2_SNORM:
1088 case PIPE_FORMAT_LATC2_SNORM:
1089 case PIPE_FORMAT_RGTC2_UNORM:
1090 case PIPE_FORMAT_LATC2_UNORM:
1091 return V_008F14_IMG_DATA_FORMAT_BC5;
1092 default:
1093 goto out_unknown;
1094 }
1095 }
1096
1097 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1098
1099 if (!enable_s3tc)
1100 goto out_unknown;
1101
1102 if (!util_format_s3tc_enabled) {
1103 goto out_unknown;
1104 }
1105
1106 switch (format) {
1107 case PIPE_FORMAT_DXT1_RGB:
1108 case PIPE_FORMAT_DXT1_RGBA:
1109 case PIPE_FORMAT_DXT1_SRGB:
1110 case PIPE_FORMAT_DXT1_SRGBA:
1111 return V_008F14_IMG_DATA_FORMAT_BC1;
1112 case PIPE_FORMAT_DXT3_RGBA:
1113 case PIPE_FORMAT_DXT3_SRGBA:
1114 return V_008F14_IMG_DATA_FORMAT_BC2;
1115 case PIPE_FORMAT_DXT5_RGBA:
1116 case PIPE_FORMAT_DXT5_SRGBA:
1117 return V_008F14_IMG_DATA_FORMAT_BC3;
1118 default:
1119 goto out_unknown;
1120 }
1121 }
1122
1123 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1124 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1125 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1126 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1127 }
1128
1129 /* R8G8Bx_SNORM - TODO CxV8U8 */
1130
1131 /* See whether the components are of the same size. */
1132 for (i = 1; i < desc->nr_channels; i++) {
1133 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1134 }
1135
1136 /* Non-uniform formats. */
1137 if (!uniform) {
1138 switch(desc->nr_channels) {
1139 case 3:
1140 if (desc->channel[0].size == 5 &&
1141 desc->channel[1].size == 6 &&
1142 desc->channel[2].size == 5) {
1143 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1144 }
1145 goto out_unknown;
1146 case 4:
1147 if (desc->channel[0].size == 5 &&
1148 desc->channel[1].size == 5 &&
1149 desc->channel[2].size == 5 &&
1150 desc->channel[3].size == 1) {
1151 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1152 }
1153 if (desc->channel[0].size == 10 &&
1154 desc->channel[1].size == 10 &&
1155 desc->channel[2].size == 10 &&
1156 desc->channel[3].size == 2) {
1157 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1158 }
1159 goto out_unknown;
1160 }
1161 goto out_unknown;
1162 }
1163
1164 if (first_non_void < 0 || first_non_void > 3)
1165 goto out_unknown;
1166
1167 /* uniform formats */
1168 switch (desc->channel[first_non_void].size) {
1169 case 4:
1170 switch (desc->nr_channels) {
1171 #if 0 /* Not supported for render targets */
1172 case 2:
1173 return V_008F14_IMG_DATA_FORMAT_4_4;
1174 #endif
1175 case 4:
1176 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1177 }
1178 break;
1179 case 8:
1180 switch (desc->nr_channels) {
1181 case 1:
1182 return V_008F14_IMG_DATA_FORMAT_8;
1183 case 2:
1184 return V_008F14_IMG_DATA_FORMAT_8_8;
1185 case 4:
1186 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1187 }
1188 break;
1189 case 16:
1190 switch (desc->nr_channels) {
1191 case 1:
1192 return V_008F14_IMG_DATA_FORMAT_16;
1193 case 2:
1194 return V_008F14_IMG_DATA_FORMAT_16_16;
1195 case 4:
1196 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1197 }
1198 break;
1199 case 32:
1200 switch (desc->nr_channels) {
1201 case 1:
1202 return V_008F14_IMG_DATA_FORMAT_32;
1203 case 2:
1204 return V_008F14_IMG_DATA_FORMAT_32_32;
1205 #if 0 /* Not supported for render targets */
1206 case 3:
1207 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1208 #endif
1209 case 4:
1210 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1211 }
1212 }
1213
1214 out_unknown:
1215 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1216 return ~0;
1217 }
1218
1219 static unsigned si_tex_wrap(unsigned wrap)
1220 {
1221 switch (wrap) {
1222 default:
1223 case PIPE_TEX_WRAP_REPEAT:
1224 return V_008F30_SQ_TEX_WRAP;
1225 case PIPE_TEX_WRAP_CLAMP:
1226 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1227 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1228 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1229 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1230 return V_008F30_SQ_TEX_CLAMP_BORDER;
1231 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1232 return V_008F30_SQ_TEX_MIRROR;
1233 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1234 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1235 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1236 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1237 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1238 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1239 }
1240 }
1241
1242 static unsigned si_tex_filter(unsigned filter)
1243 {
1244 switch (filter) {
1245 default:
1246 case PIPE_TEX_FILTER_NEAREST:
1247 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1248 case PIPE_TEX_FILTER_LINEAR:
1249 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1250 }
1251 }
1252
1253 static unsigned si_tex_mipfilter(unsigned filter)
1254 {
1255 switch (filter) {
1256 case PIPE_TEX_MIPFILTER_NEAREST:
1257 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1258 case PIPE_TEX_MIPFILTER_LINEAR:
1259 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1260 default:
1261 case PIPE_TEX_MIPFILTER_NONE:
1262 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1263 }
1264 }
1265
1266 static unsigned si_tex_compare(unsigned compare)
1267 {
1268 switch (compare) {
1269 default:
1270 case PIPE_FUNC_NEVER:
1271 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1272 case PIPE_FUNC_LESS:
1273 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1274 case PIPE_FUNC_EQUAL:
1275 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1276 case PIPE_FUNC_LEQUAL:
1277 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1278 case PIPE_FUNC_GREATER:
1279 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1280 case PIPE_FUNC_NOTEQUAL:
1281 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1282 case PIPE_FUNC_GEQUAL:
1283 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1284 case PIPE_FUNC_ALWAYS:
1285 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1286 }
1287 }
1288
1289 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1290 {
1291 switch (dim) {
1292 default:
1293 case PIPE_TEXTURE_1D:
1294 return V_008F1C_SQ_RSRC_IMG_1D;
1295 case PIPE_TEXTURE_1D_ARRAY:
1296 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1297 case PIPE_TEXTURE_2D:
1298 case PIPE_TEXTURE_RECT:
1299 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1300 V_008F1C_SQ_RSRC_IMG_2D;
1301 case PIPE_TEXTURE_2D_ARRAY:
1302 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1303 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1304 case PIPE_TEXTURE_3D:
1305 return V_008F1C_SQ_RSRC_IMG_3D;
1306 case PIPE_TEXTURE_CUBE:
1307 return V_008F1C_SQ_RSRC_IMG_CUBE;
1308 }
1309 }
1310
1311 /*
1312 * Format support testing
1313 */
1314
1315 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1316 {
1317 return si_translate_texformat(screen, format, util_format_description(format),
1318 util_format_get_first_non_void_channel(format)) != ~0U;
1319 }
1320
1321 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1322 const struct util_format_description *desc,
1323 int first_non_void)
1324 {
1325 unsigned type = desc->channel[first_non_void].type;
1326 int i;
1327
1328 if (type == UTIL_FORMAT_TYPE_FIXED)
1329 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1330
1331 if (desc->nr_channels == 4 &&
1332 desc->channel[0].size == 10 &&
1333 desc->channel[1].size == 10 &&
1334 desc->channel[2].size == 10 &&
1335 desc->channel[3].size == 2)
1336 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1337
1338 /* See whether the components are of the same size. */
1339 for (i = 0; i < desc->nr_channels; i++) {
1340 if (desc->channel[first_non_void].size != desc->channel[i].size)
1341 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1342 }
1343
1344 switch (desc->channel[first_non_void].size) {
1345 case 8:
1346 switch (desc->nr_channels) {
1347 case 1:
1348 return V_008F0C_BUF_DATA_FORMAT_8;
1349 case 2:
1350 return V_008F0C_BUF_DATA_FORMAT_8_8;
1351 case 3:
1352 case 4:
1353 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1354 }
1355 break;
1356 case 16:
1357 switch (desc->nr_channels) {
1358 case 1:
1359 return V_008F0C_BUF_DATA_FORMAT_16;
1360 case 2:
1361 return V_008F0C_BUF_DATA_FORMAT_16_16;
1362 case 3:
1363 case 4:
1364 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1365 }
1366 break;
1367 case 32:
1368 /* From the Southern Islands ISA documentation about MTBUF:
1369 * 'Memory reads of data in memory that is 32 or 64 bits do not
1370 * undergo any format conversion.'
1371 */
1372 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1373 !desc->channel[first_non_void].pure_integer)
1374 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1375
1376 switch (desc->nr_channels) {
1377 case 1:
1378 return V_008F0C_BUF_DATA_FORMAT_32;
1379 case 2:
1380 return V_008F0C_BUF_DATA_FORMAT_32_32;
1381 case 3:
1382 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1383 case 4:
1384 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1385 }
1386 break;
1387 }
1388
1389 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1390 }
1391
1392 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1393 const struct util_format_description *desc,
1394 int first_non_void)
1395 {
1396 switch (desc->channel[first_non_void].type) {
1397 case UTIL_FORMAT_TYPE_SIGNED:
1398 if (desc->channel[first_non_void].normalized)
1399 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1400 else if (desc->channel[first_non_void].pure_integer)
1401 return V_008F0C_BUF_NUM_FORMAT_SINT;
1402 else
1403 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1404 break;
1405 case UTIL_FORMAT_TYPE_UNSIGNED:
1406 if (desc->channel[first_non_void].normalized)
1407 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1408 else if (desc->channel[first_non_void].pure_integer)
1409 return V_008F0C_BUF_NUM_FORMAT_UINT;
1410 else
1411 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1412 break;
1413 case UTIL_FORMAT_TYPE_FLOAT:
1414 default:
1415 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1416 }
1417 }
1418
1419 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1420 {
1421 const struct util_format_description *desc;
1422 int first_non_void;
1423 unsigned data_format;
1424
1425 desc = util_format_description(format);
1426 first_non_void = util_format_get_first_non_void_channel(format);
1427 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1428 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1429 }
1430
1431 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1432 {
1433 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1434 r600_translate_colorswap(format) != ~0U;
1435 }
1436
1437 static bool si_is_zs_format_supported(enum pipe_format format)
1438 {
1439 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1440 }
1441
1442 boolean si_is_format_supported(struct pipe_screen *screen,
1443 enum pipe_format format,
1444 enum pipe_texture_target target,
1445 unsigned sample_count,
1446 unsigned usage)
1447 {
1448 struct si_screen *sscreen = (struct si_screen *)screen;
1449 unsigned retval = 0;
1450
1451 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1452 R600_ERR("r600: unsupported texture type %d\n", target);
1453 return FALSE;
1454 }
1455
1456 if (!util_format_is_supported(format, usage))
1457 return FALSE;
1458
1459 if (sample_count > 1) {
1460 if (HAVE_LLVM < 0x0304)
1461 return FALSE;
1462
1463 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1464 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1465 return FALSE;
1466
1467 switch (sample_count) {
1468 case 2:
1469 case 4:
1470 case 8:
1471 break;
1472 default:
1473 return FALSE;
1474 }
1475 }
1476
1477 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1478 if (target == PIPE_BUFFER) {
1479 if (si_is_vertex_format_supported(screen, format))
1480 retval |= PIPE_BIND_SAMPLER_VIEW;
1481 } else {
1482 if (si_is_sampler_format_supported(screen, format))
1483 retval |= PIPE_BIND_SAMPLER_VIEW;
1484 }
1485 }
1486
1487 if ((usage & (PIPE_BIND_RENDER_TARGET |
1488 PIPE_BIND_DISPLAY_TARGET |
1489 PIPE_BIND_SCANOUT |
1490 PIPE_BIND_SHARED)) &&
1491 si_is_colorbuffer_format_supported(format)) {
1492 retval |= usage &
1493 (PIPE_BIND_RENDER_TARGET |
1494 PIPE_BIND_DISPLAY_TARGET |
1495 PIPE_BIND_SCANOUT |
1496 PIPE_BIND_SHARED);
1497 }
1498
1499 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1500 si_is_zs_format_supported(format)) {
1501 retval |= PIPE_BIND_DEPTH_STENCIL;
1502 }
1503
1504 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1505 si_is_vertex_format_supported(screen, format)) {
1506 retval |= PIPE_BIND_VERTEX_BUFFER;
1507 }
1508
1509 if (usage & PIPE_BIND_TRANSFER_READ)
1510 retval |= PIPE_BIND_TRANSFER_READ;
1511 if (usage & PIPE_BIND_TRANSFER_WRITE)
1512 retval |= PIPE_BIND_TRANSFER_WRITE;
1513
1514 return retval == usage;
1515 }
1516
1517 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1518 {
1519 unsigned tile_mode_index = 0;
1520
1521 if (stencil) {
1522 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1523 } else {
1524 tile_mode_index = rtex->surface.tiling_index[level];
1525 }
1526 return tile_mode_index;
1527 }
1528
1529 /*
1530 * framebuffer handling
1531 */
1532
1533 static void si_initialize_color_surface(struct si_context *sctx,
1534 struct r600_surface *surf)
1535 {
1536 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1537 unsigned level = surf->base.u.tex.level;
1538 uint64_t offset = rtex->surface.level[level].offset;
1539 unsigned pitch, slice;
1540 unsigned color_info, color_attrib, color_pitch, color_view;
1541 unsigned tile_mode_index;
1542 unsigned format, swap, ntype, endian;
1543 const struct util_format_description *desc;
1544 int i;
1545 unsigned blend_clamp = 0, blend_bypass = 0;
1546 unsigned max_comp_size;
1547
1548 /* Layered rendering doesn't work with LINEAR_GENERAL.
1549 * (LINEAR_ALIGNED and others work) */
1550 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1551 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1552 offset += rtex->surface.level[level].slice_size *
1553 surf->base.u.tex.first_layer;
1554 color_view = 0;
1555 } else {
1556 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1557 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1558 }
1559
1560 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1561 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1562 if (slice) {
1563 slice = slice - 1;
1564 }
1565
1566 tile_mode_index = si_tile_mode_index(rtex, level, false);
1567
1568 desc = util_format_description(surf->base.format);
1569 for (i = 0; i < 4; i++) {
1570 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1571 break;
1572 }
1573 }
1574 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1575 ntype = V_028C70_NUMBER_FLOAT;
1576 } else {
1577 ntype = V_028C70_NUMBER_UNORM;
1578 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1579 ntype = V_028C70_NUMBER_SRGB;
1580 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1581 if (desc->channel[i].pure_integer) {
1582 ntype = V_028C70_NUMBER_SINT;
1583 } else {
1584 assert(desc->channel[i].normalized);
1585 ntype = V_028C70_NUMBER_SNORM;
1586 }
1587 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1588 if (desc->channel[i].pure_integer) {
1589 ntype = V_028C70_NUMBER_UINT;
1590 } else {
1591 assert(desc->channel[i].normalized);
1592 ntype = V_028C70_NUMBER_UNORM;
1593 }
1594 }
1595 }
1596
1597 format = si_translate_colorformat(surf->base.format);
1598 if (format == V_028C70_COLOR_INVALID) {
1599 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1600 }
1601 assert(format != V_028C70_COLOR_INVALID);
1602 swap = r600_translate_colorswap(surf->base.format);
1603 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1604 endian = V_028C70_ENDIAN_NONE;
1605 } else {
1606 endian = si_colorformat_endian_swap(format);
1607 }
1608
1609 /* blend clamp should be set for all NORM/SRGB types */
1610 if (ntype == V_028C70_NUMBER_UNORM ||
1611 ntype == V_028C70_NUMBER_SNORM ||
1612 ntype == V_028C70_NUMBER_SRGB)
1613 blend_clamp = 1;
1614
1615 /* set blend bypass according to docs if SINT/UINT or
1616 8/24 COLOR variants */
1617 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1618 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1619 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1620 blend_clamp = 0;
1621 blend_bypass = 1;
1622 }
1623
1624 color_info = S_028C70_FORMAT(format) |
1625 S_028C70_COMP_SWAP(swap) |
1626 S_028C70_BLEND_CLAMP(blend_clamp) |
1627 S_028C70_BLEND_BYPASS(blend_bypass) |
1628 S_028C70_NUMBER_TYPE(ntype) |
1629 S_028C70_ENDIAN(endian);
1630
1631 color_pitch = S_028C64_TILE_MAX(pitch);
1632
1633 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1634 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1635
1636 if (rtex->resource.b.b.nr_samples > 1) {
1637 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1638
1639 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1640 S_028C74_NUM_FRAGMENTS(log_samples);
1641
1642 if (rtex->fmask.size) {
1643 color_info |= S_028C70_COMPRESSION(1);
1644 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1645
1646 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1647
1648 if (sctx->b.chip_class == SI) {
1649 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1650 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1651 }
1652 if (sctx->b.chip_class >= CIK) {
1653 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1654 }
1655 }
1656 }
1657
1658 offset += r600_resource_va(sctx->b.b.screen, surf->base.texture);
1659
1660 surf->cb_color_base = offset >> 8;
1661 surf->cb_color_pitch = color_pitch;
1662 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1663 surf->cb_color_view = color_view;
1664 surf->cb_color_info = color_info;
1665 surf->cb_color_attrib = color_attrib;
1666
1667 if (rtex->fmask.size) {
1668 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1669 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1670 }
1671
1672 /* Determine pixel shader export format */
1673 max_comp_size = si_colorformat_max_comp_size(format);
1674 if (ntype == V_028C70_NUMBER_SRGB ||
1675 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1676 max_comp_size <= 10) ||
1677 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1678 surf->export_16bpc = true;
1679 }
1680
1681 surf->color_initialized = true;
1682 }
1683
1684 static void si_init_depth_surface(struct si_context *sctx,
1685 struct r600_surface *surf)
1686 {
1687 struct si_screen *sscreen = sctx->screen;
1688 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1689 unsigned level = surf->base.u.tex.level;
1690 unsigned pitch, slice, format, tile_mode_index, array_mode;
1691 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1692 uint32_t z_info, s_info, db_depth_info;
1693 uint64_t z_offs, s_offs;
1694 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl;
1695
1696 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1697 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1698 case PIPE_FORMAT_X8Z24_UNORM:
1699 case PIPE_FORMAT_Z24X8_UNORM:
1700 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1701 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1702 break;
1703 case PIPE_FORMAT_Z32_FLOAT:
1704 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1705 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1706 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1707 break;
1708 case PIPE_FORMAT_Z16_UNORM:
1709 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1710 break;
1711 default:
1712 assert(0);
1713 }
1714
1715 format = si_translate_dbformat(rtex->resource.b.b.format);
1716
1717 if (format == V_028040_Z_INVALID) {
1718 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1719 }
1720 assert(format != V_028040_Z_INVALID);
1721
1722 s_offs = z_offs = r600_resource_va(sctx->b.b.screen, surf->base.texture);
1723 z_offs += rtex->surface.level[level].offset;
1724 s_offs += rtex->surface.stencil_level[level].offset;
1725
1726 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1727 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1728 if (slice) {
1729 slice = slice - 1;
1730 }
1731
1732 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1733
1734 z_info = S_028040_FORMAT(format);
1735 if (rtex->resource.b.b.nr_samples > 1) {
1736 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1737 }
1738
1739 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1740 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1741 else
1742 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1743
1744 if (sctx->b.chip_class >= CIK) {
1745 switch (rtex->surface.level[level].mode) {
1746 case RADEON_SURF_MODE_2D:
1747 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1748 break;
1749 case RADEON_SURF_MODE_1D:
1750 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1751 case RADEON_SURF_MODE_LINEAR:
1752 default:
1753 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1754 break;
1755 }
1756 tile_split = rtex->surface.tile_split;
1757 stile_split = rtex->surface.stencil_tile_split;
1758 macro_aspect = rtex->surface.mtilea;
1759 bankw = rtex->surface.bankw;
1760 bankh = rtex->surface.bankh;
1761 tile_split = cik_tile_split(tile_split);
1762 stile_split = cik_tile_split(stile_split);
1763 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1764 bankw = cik_bank_wh(bankw);
1765 bankh = cik_bank_wh(bankh);
1766 nbanks = cik_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split);
1767 tile_mode_index = si_tile_mode_index(rtex, level, false);
1768 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1769
1770 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1771 S_02803C_PIPE_CONFIG(pipe_config) |
1772 S_02803C_BANK_WIDTH(bankw) |
1773 S_02803C_BANK_HEIGHT(bankh) |
1774 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1775 S_02803C_NUM_BANKS(nbanks);
1776 z_info |= S_028040_TILE_SPLIT(tile_split);
1777 s_info |= S_028044_TILE_SPLIT(stile_split);
1778 } else {
1779 tile_mode_index = si_tile_mode_index(rtex, level, false);
1780 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1781 tile_mode_index = si_tile_mode_index(rtex, level, true);
1782 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1783 }
1784
1785 /* HiZ aka depth buffer htile */
1786 /* use htile only for first level */
1787 if (rtex->htile_buffer && !level) {
1788 const struct util_format_description *fmt_desc;
1789
1790 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1791
1792 /* This is optimal for the clear value of 1.0 and using
1793 * the LESS and LEQUAL test functions. Set this to 0
1794 * for the opposite case. This can only be changed when
1795 * clearing. */
1796 z_info |= S_028040_ZRANGE_PRECISION(1);
1797
1798 fmt_desc = util_format_description(rtex->resource.b.b.format);
1799 if (!util_format_has_stencil(fmt_desc)) {
1800 /* Use all of the htile_buffer for depth */
1801 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1802 }
1803
1804 uint64_t va = r600_resource_va(&sctx->screen->b.b, &rtex->htile_buffer->b.b);
1805 db_htile_data_base = va >> 8;
1806 db_htile_surface = S_028ABC_FULL_CACHE(1);
1807 } else {
1808 db_htile_data_base = 0;
1809 db_htile_surface = 0;
1810 }
1811
1812 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1813 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1814 surf->db_htile_data_base = db_htile_data_base;
1815 surf->db_depth_info = db_depth_info;
1816 surf->db_z_info = z_info;
1817 surf->db_stencil_info = s_info;
1818 surf->db_depth_base = z_offs >> 8;
1819 surf->db_stencil_base = s_offs >> 8;
1820 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1821 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1822 surf->db_htile_surface = db_htile_surface;
1823 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1824
1825 surf->depth_initialized = true;
1826 }
1827
1828 static void si_set_framebuffer_state(struct pipe_context *ctx,
1829 const struct pipe_framebuffer_state *state)
1830 {
1831 struct si_context *sctx = (struct si_context *)ctx;
1832 struct r600_surface *surf = NULL;
1833 struct r600_texture *rtex;
1834 int i;
1835
1836 if (sctx->framebuffer.state.nr_cbufs) {
1837 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1838 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1839 }
1840 if (sctx->framebuffer.state.zsbuf) {
1841 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
1842 R600_CONTEXT_FLUSH_AND_INV_DB_META;
1843 }
1844
1845 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
1846
1847 sctx->framebuffer.export_16bpc = 0;
1848 sctx->framebuffer.compressed_cb_mask = 0;
1849 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1850 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
1851 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1852 util_format_is_pure_integer(state->cbufs[0]->format);
1853
1854 for (i = 0; i < state->nr_cbufs; i++) {
1855 if (!state->cbufs[i])
1856 continue;
1857
1858 surf = (struct r600_surface*)state->cbufs[i];
1859 rtex = (struct r600_texture*)surf->base.texture;
1860
1861 if (!surf->color_initialized) {
1862 si_initialize_color_surface(sctx, surf);
1863 }
1864
1865 if (surf->export_16bpc) {
1866 sctx->framebuffer.export_16bpc |= 1 << i;
1867 }
1868
1869 if (rtex->fmask.size || rtex->cmask.size) {
1870 sctx->framebuffer.compressed_cb_mask |= 1 << i;
1871 }
1872 }
1873 /* Set the 16BPC export for possible dual-src blending. */
1874 if (i == 1 && surf && surf->export_16bpc) {
1875 sctx->framebuffer.export_16bpc |= 1 << 1;
1876 }
1877
1878 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
1879
1880 if (state->zsbuf) {
1881 surf = (struct r600_surface*)state->zsbuf;
1882
1883 if (!surf->depth_initialized) {
1884 si_init_depth_surface(sctx, surf);
1885 }
1886 }
1887
1888 si_update_fb_rs_state(sctx);
1889 si_update_fb_blend_state(sctx);
1890
1891 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
1892 sctx->framebuffer.atom.num_dw += state->zsbuf ? 23 : 4;
1893 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
1894 sctx->framebuffer.atom.num_dw += 25; /* MSAA */
1895 sctx->framebuffer.atom.dirty = true;
1896 }
1897
1898 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
1899 {
1900 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
1901 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
1902 unsigned i, nr_cbufs = state->nr_cbufs;
1903 struct r600_texture *tex = NULL;
1904 struct r600_surface *cb = NULL;
1905
1906 /* Colorbuffers. */
1907 for (i = 0; i < nr_cbufs; i++) {
1908 cb = (struct r600_surface*)state->cbufs[i];
1909 if (!cb) {
1910 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1911 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1912 continue;
1913 }
1914
1915 tex = (struct r600_texture *)cb->base.texture;
1916 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1917 &tex->resource, RADEON_USAGE_READWRITE,
1918 tex->surface.nsamples > 1 ?
1919 RADEON_PRIO_COLOR_BUFFER_MSAA :
1920 RADEON_PRIO_COLOR_BUFFER);
1921
1922 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1923 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1924 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1925 RADEON_PRIO_COLOR_META);
1926 }
1927
1928 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1929 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1930 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1931 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1932 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1933 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1934 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1935 radeon_emit(cs, 0); /* R_028C78 unused */
1936 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1937 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1938 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1939 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1940 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1941 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1942 }
1943 /* set CB_COLOR1_INFO for possible dual-src blending */
1944 if (i == 1 && state->cbufs[0]) {
1945 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1946 cb->cb_color_info | tex->cb_color_info);
1947 i++;
1948 }
1949 for (; i < 8 ; i++) {
1950 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1951 }
1952
1953 /* ZS buffer. */
1954 if (state->zsbuf) {
1955 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1956 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
1957
1958 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1959 &rtex->resource, RADEON_USAGE_READWRITE,
1960 zb->base.texture->nr_samples > 1 ?
1961 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1962 RADEON_PRIO_DEPTH_BUFFER);
1963
1964 if (zb->db_htile_data_base) {
1965 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1966 rtex->htile_buffer, RADEON_USAGE_READWRITE,
1967 RADEON_PRIO_DEPTH_META);
1968 }
1969
1970 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1971 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
1972
1973 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
1974 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1975 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1976 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1977 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1978 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1979 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1980 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1981 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1982 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1983
1984 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
1985 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1986 zb->pa_su_poly_offset_db_fmt_cntl);
1987 } else {
1988 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1989 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1990 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1991 }
1992
1993 /* Framebuffer dimensions. */
1994 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
1995 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1996 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
1997
1998 cayman_emit_msaa_state(cs, sctx->framebuffer.nr_samples);
1999 }
2000
2001 /*
2002 * shaders
2003 */
2004
2005 /* Compute the key for the hw shader variant */
2006 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2007 struct si_pipe_shader_selector *sel,
2008 union si_shader_key *key)
2009 {
2010 struct si_context *sctx = (struct si_context *)ctx;
2011 memset(key, 0, sizeof(*key));
2012
2013 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
2014 sctx->queued.named.rasterizer) {
2015 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2016 key->vs.ucps_enabled |= 0x2;
2017 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2018 key->vs.ucps_enabled |= 0x1;
2019 }
2020
2021 if (sel->type == PIPE_SHADER_VERTEX) {
2022 unsigned i;
2023 if (!sctx->vertex_elements)
2024 return;
2025
2026 for (i = 0; i < sctx->vertex_elements->count; ++i)
2027 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2028
2029 key->vs.as_es = sctx->gs_shader != NULL;
2030 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2031 if (sel->fs_write_all)
2032 key->ps.nr_cbufs = sctx->framebuffer.state.nr_cbufs;
2033 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
2034
2035 if (sctx->queued.named.rasterizer) {
2036 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2037 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2038
2039 if (sctx->queued.named.blend) {
2040 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2041 sctx->queued.named.rasterizer->multisample_enable &&
2042 !sctx->framebuffer.cb0_is_integer;
2043 }
2044 }
2045 if (sctx->queued.named.dsa) {
2046 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2047
2048 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2049 if (sctx->framebuffer.cb0_is_integer)
2050 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2051 } else {
2052 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2053 }
2054 }
2055 }
2056
2057 /* Select the hw shader variant depending on the current state. */
2058 int si_shader_select(struct pipe_context *ctx,
2059 struct si_pipe_shader_selector *sel)
2060 {
2061 union si_shader_key key;
2062 struct si_pipe_shader * shader = NULL;
2063 int r;
2064
2065 si_shader_selector_key(ctx, sel, &key);
2066
2067 /* Check if we don't need to change anything.
2068 * This path is also used for most shaders that don't need multiple
2069 * variants, it will cost just a computation of the key and this
2070 * test. */
2071 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2072 return 0;
2073 }
2074
2075 /* lookup if we have other variants in the list */
2076 if (sel->num_shaders > 1) {
2077 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2078
2079 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2080 p = c;
2081 c = c->next_variant;
2082 }
2083
2084 if (c) {
2085 p->next_variant = c->next_variant;
2086 shader = c;
2087 }
2088 }
2089
2090 if (shader) {
2091 shader->next_variant = sel->current;
2092 sel->current = shader;
2093 } else {
2094 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2095 shader->selector = sel;
2096 shader->key = key;
2097
2098 shader->next_variant = sel->current;
2099 sel->current = shader;
2100 r = si_pipe_shader_create(ctx, shader);
2101 if (unlikely(r)) {
2102 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2103 sel->type, r);
2104 sel->current = NULL;
2105 FREE(shader);
2106 return r;
2107 }
2108 sel->num_shaders++;
2109 }
2110
2111 return 0;
2112 }
2113
2114 static void *si_create_shader_state(struct pipe_context *ctx,
2115 const struct pipe_shader_state *state,
2116 unsigned pipe_shader_type)
2117 {
2118 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2119 int r;
2120
2121 sel->type = pipe_shader_type;
2122 sel->tokens = tgsi_dup_tokens(state->tokens);
2123 sel->so = state->stream_output;
2124
2125 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2126 struct tgsi_shader_info info;
2127
2128 tgsi_scan_shader(state->tokens, &info);
2129 sel->fs_write_all = info.color0_writes_all_cbufs;
2130 }
2131
2132 r = si_shader_select(ctx, sel);
2133 if (r) {
2134 free(sel);
2135 return NULL;
2136 }
2137
2138 return sel;
2139 }
2140
2141 static void *si_create_fs_state(struct pipe_context *ctx,
2142 const struct pipe_shader_state *state)
2143 {
2144 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2145 }
2146
2147 #if HAVE_LLVM >= 0x0305
2148
2149 static void *si_create_gs_state(struct pipe_context *ctx,
2150 const struct pipe_shader_state *state)
2151 {
2152 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
2153 }
2154
2155 #endif
2156
2157 static void *si_create_vs_state(struct pipe_context *ctx,
2158 const struct pipe_shader_state *state)
2159 {
2160 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2161 }
2162
2163 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2164 {
2165 struct si_context *sctx = (struct si_context *)ctx;
2166 struct si_pipe_shader_selector *sel = state;
2167
2168 if (sctx->vs_shader == sel)
2169 return;
2170
2171 if (!sel || !sel->current)
2172 return;
2173
2174 sctx->vs_shader = sel;
2175 }
2176
2177 #if HAVE_LLVM >= 0x0305
2178
2179 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2180 {
2181 struct si_context *sctx = (struct si_context *)ctx;
2182 struct si_pipe_shader_selector *sel = state;
2183
2184 if (sctx->gs_shader == sel)
2185 return;
2186
2187 sctx->gs_shader = sel;
2188 }
2189
2190 #endif
2191
2192 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2193 {
2194 struct si_context *sctx = (struct si_context *)ctx;
2195 struct si_pipe_shader_selector *sel = state;
2196
2197 if (sctx->ps_shader == sel)
2198 return;
2199
2200 if (!sel || !sel->current)
2201 sel = sctx->dummy_pixel_shader;
2202
2203 sctx->ps_shader = sel;
2204 }
2205
2206 static void si_delete_shader_selector(struct pipe_context *ctx,
2207 struct si_pipe_shader_selector *sel)
2208 {
2209 struct si_context *sctx = (struct si_context *)ctx;
2210 struct si_pipe_shader *p = sel->current, *c;
2211
2212 while (p) {
2213 c = p->next_variant;
2214 if (sel->type == PIPE_SHADER_GEOMETRY)
2215 si_pm4_delete_state(sctx, gs, p->pm4);
2216 else if (sel->type == PIPE_SHADER_FRAGMENT)
2217 si_pm4_delete_state(sctx, ps, p->pm4);
2218 else if (p->key.vs.as_es)
2219 si_pm4_delete_state(sctx, es, p->pm4);
2220 else
2221 si_pm4_delete_state(sctx, vs, p->pm4);
2222 si_pipe_shader_destroy(ctx, p);
2223 free(p);
2224 p = c;
2225 }
2226
2227 free(sel->tokens);
2228 free(sel);
2229 }
2230
2231 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2232 {
2233 struct si_context *sctx = (struct si_context *)ctx;
2234 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2235
2236 if (sctx->vs_shader == sel) {
2237 sctx->vs_shader = NULL;
2238 }
2239
2240 si_delete_shader_selector(ctx, sel);
2241 }
2242
2243 #if HAVE_LLVM >= 0x0305
2244
2245 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
2246 {
2247 struct si_context *sctx = (struct si_context *)ctx;
2248 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2249
2250 if (sctx->gs_shader == sel) {
2251 sctx->gs_shader = NULL;
2252 }
2253
2254 si_delete_shader_selector(ctx, sel);
2255 }
2256
2257 #endif
2258
2259 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2260 {
2261 struct si_context *sctx = (struct si_context *)ctx;
2262 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2263
2264 if (sctx->ps_shader == sel) {
2265 sctx->ps_shader = NULL;
2266 }
2267
2268 si_delete_shader_selector(ctx, sel);
2269 }
2270
2271 /*
2272 * Samplers
2273 */
2274
2275 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2276 struct pipe_resource *texture,
2277 const struct pipe_sampler_view *state)
2278 {
2279 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2280 struct r600_texture *tmp = (struct r600_texture*)texture;
2281 const struct util_format_description *desc;
2282 unsigned format, num_format;
2283 uint32_t pitch = 0;
2284 unsigned char state_swizzle[4], swizzle[4];
2285 unsigned height, depth, width;
2286 enum pipe_format pipe_format = state->format;
2287 struct radeon_surface_level *surflevel;
2288 int first_non_void;
2289 uint64_t va;
2290
2291 if (view == NULL)
2292 return NULL;
2293
2294 /* initialize base object */
2295 view->base = *state;
2296 view->base.texture = NULL;
2297 pipe_resource_reference(&view->base.texture, texture);
2298 view->base.reference.count = 1;
2299 view->base.context = ctx;
2300 view->resource = &tmp->resource;
2301
2302 /* Buffer resource. */
2303 if (texture->target == PIPE_BUFFER) {
2304 unsigned stride;
2305
2306 desc = util_format_description(state->format);
2307 first_non_void = util_format_get_first_non_void_channel(state->format);
2308 stride = desc->block.bits / 8;
2309 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2310 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2311 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2312
2313 view->state[0] = va;
2314 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2315 S_008F04_STRIDE(stride);
2316 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2317 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2318 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2319 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2320 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2321 S_008F0C_NUM_FORMAT(num_format) |
2322 S_008F0C_DATA_FORMAT(format);
2323 return &view->base;
2324 }
2325
2326 state_swizzle[0] = state->swizzle_r;
2327 state_swizzle[1] = state->swizzle_g;
2328 state_swizzle[2] = state->swizzle_b;
2329 state_swizzle[3] = state->swizzle_a;
2330
2331 surflevel = tmp->surface.level;
2332
2333 /* Texturing with separate depth and stencil. */
2334 if (tmp->is_depth && !tmp->is_flushing_texture) {
2335 switch (pipe_format) {
2336 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2337 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2338 break;
2339 case PIPE_FORMAT_X8Z24_UNORM:
2340 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2341 /* Z24 is always stored like this. */
2342 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2343 break;
2344 case PIPE_FORMAT_X24S8_UINT:
2345 case PIPE_FORMAT_S8X24_UINT:
2346 case PIPE_FORMAT_X32_S8X24_UINT:
2347 pipe_format = PIPE_FORMAT_S8_UINT;
2348 surflevel = tmp->surface.stencil_level;
2349 break;
2350 default:;
2351 }
2352 }
2353
2354 desc = util_format_description(pipe_format);
2355
2356 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2357 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2358 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2359
2360 switch (pipe_format) {
2361 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2362 case PIPE_FORMAT_X24S8_UINT:
2363 case PIPE_FORMAT_X32_S8X24_UINT:
2364 case PIPE_FORMAT_X8Z24_UNORM:
2365 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2366 break;
2367 default:
2368 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2369 }
2370 } else {
2371 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2372 }
2373
2374 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2375
2376 switch (pipe_format) {
2377 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2378 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2379 break;
2380 default:
2381 if (first_non_void < 0) {
2382 if (util_format_is_compressed(pipe_format)) {
2383 switch (pipe_format) {
2384 case PIPE_FORMAT_DXT1_SRGB:
2385 case PIPE_FORMAT_DXT1_SRGBA:
2386 case PIPE_FORMAT_DXT3_SRGBA:
2387 case PIPE_FORMAT_DXT5_SRGBA:
2388 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2389 break;
2390 case PIPE_FORMAT_RGTC1_SNORM:
2391 case PIPE_FORMAT_LATC1_SNORM:
2392 case PIPE_FORMAT_RGTC2_SNORM:
2393 case PIPE_FORMAT_LATC2_SNORM:
2394 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2395 break;
2396 default:
2397 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2398 break;
2399 }
2400 } else {
2401 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2402 }
2403 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2404 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2405 } else {
2406 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2407
2408 switch (desc->channel[first_non_void].type) {
2409 case UTIL_FORMAT_TYPE_FLOAT:
2410 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2411 break;
2412 case UTIL_FORMAT_TYPE_SIGNED:
2413 if (desc->channel[first_non_void].normalized)
2414 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2415 else if (desc->channel[first_non_void].pure_integer)
2416 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2417 else
2418 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2419 break;
2420 case UTIL_FORMAT_TYPE_UNSIGNED:
2421 if (desc->channel[first_non_void].normalized)
2422 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2423 else if (desc->channel[first_non_void].pure_integer)
2424 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2425 else
2426 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2427 }
2428 }
2429 }
2430
2431 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2432 if (format == ~0) {
2433 format = 0;
2434 }
2435
2436 /* not supported any more */
2437 //endian = si_colorformat_endian_swap(format);
2438
2439 width = surflevel[0].npix_x;
2440 height = surflevel[0].npix_y;
2441 depth = surflevel[0].npix_z;
2442 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2443
2444 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2445 height = 1;
2446 depth = texture->array_size;
2447 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2448 depth = texture->array_size;
2449 }
2450
2451 va = r600_resource_va(ctx->screen, texture);
2452 va += surflevel[0].offset;
2453 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2454
2455 view->state[0] = va >> 8;
2456 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2457 S_008F14_DATA_FORMAT(format) |
2458 S_008F14_NUM_FORMAT(num_format));
2459 view->state[2] = (S_008F18_WIDTH(width - 1) |
2460 S_008F18_HEIGHT(height - 1));
2461 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2462 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2463 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2464 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2465 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2466 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2467 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2468 util_logbase2(texture->nr_samples) :
2469 state->u.tex.last_level - tmp->mipmap_shift) |
2470 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2471 S_008F1C_POW2_PAD(texture->last_level > 0) |
2472 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2473 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2474 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2475 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2476 view->state[6] = 0;
2477 view->state[7] = 0;
2478
2479 /* Initialize the sampler view for FMASK. */
2480 if (tmp->fmask.size) {
2481 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2482 uint32_t fmask_format;
2483
2484 switch (texture->nr_samples) {
2485 case 2:
2486 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2487 break;
2488 case 4:
2489 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2490 break;
2491 case 8:
2492 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2493 break;
2494 default:
2495 assert(0);
2496 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2497 }
2498
2499 view->fmask_state[0] = va >> 8;
2500 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2501 S_008F14_DATA_FORMAT(fmask_format) |
2502 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2503 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2504 S_008F18_HEIGHT(height - 1);
2505 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2506 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2507 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2508 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2509 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2510 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2511 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2512 S_008F20_PITCH(tmp->fmask.pitch - 1);
2513 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2514 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2515 view->fmask_state[6] = 0;
2516 view->fmask_state[7] = 0;
2517 }
2518
2519 return &view->base;
2520 }
2521
2522 static void si_sampler_view_destroy(struct pipe_context *ctx,
2523 struct pipe_sampler_view *state)
2524 {
2525 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2526
2527 pipe_resource_reference(&state->texture, NULL);
2528 FREE(resource);
2529 }
2530
2531 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2532 {
2533 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2534 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2535 (linear_filter &&
2536 (wrap == PIPE_TEX_WRAP_CLAMP ||
2537 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2538 }
2539
2540 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2541 {
2542 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2543 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2544
2545 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2546 state->border_color.ui[2] || state->border_color.ui[3]) &&
2547 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2548 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2549 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2550 }
2551
2552 static void *si_create_sampler_state(struct pipe_context *ctx,
2553 const struct pipe_sampler_state *state)
2554 {
2555 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2556 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2557 unsigned border_color_type;
2558
2559 if (rstate == NULL) {
2560 return NULL;
2561 }
2562
2563 if (sampler_state_needs_border_color(state))
2564 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2565 else
2566 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2567
2568 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2569 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2570 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2571 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2572 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2573 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2574 aniso_flag_offset << 16 | /* XXX */
2575 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2576 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2577 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2578 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2579 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2580 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2581 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2582 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2583
2584 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2585 memcpy(rstate->border_color, state->border_color.ui,
2586 sizeof(rstate->border_color));
2587 }
2588
2589 return rstate;
2590 }
2591
2592 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2593 * the si_set_sampler_view calls. LTO might help too. */
2594 static void si_set_sampler_views(struct pipe_context *ctx,
2595 unsigned shader, unsigned start,
2596 unsigned count,
2597 struct pipe_sampler_view **views)
2598 {
2599 struct si_context *sctx = (struct si_context *)ctx;
2600 struct si_textures_info *samplers = &sctx->samplers[shader];
2601 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2602 int i;
2603
2604 if (shader >= SI_NUM_SHADERS)
2605 return;
2606
2607 assert(start == 0);
2608
2609 for (i = 0; i < count; i++) {
2610 if (!views[i]) {
2611 samplers->depth_texture_mask &= ~(1 << i);
2612 samplers->compressed_colortex_mask &= ~(1 << i);
2613 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2614 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2615 NULL, NULL);
2616 continue;
2617 }
2618
2619 si_set_sampler_view(sctx, shader, i, views[i], rviews[i]->state);
2620
2621 if (views[i]->texture->target != PIPE_BUFFER) {
2622 struct r600_texture *rtex =
2623 (struct r600_texture*)views[i]->texture;
2624
2625 if (rtex->is_depth && !rtex->is_flushing_texture) {
2626 samplers->depth_texture_mask |= 1 << i;
2627 } else {
2628 samplers->depth_texture_mask &= ~(1 << i);
2629 }
2630 if (rtex->cmask.size || rtex->fmask.size) {
2631 samplers->compressed_colortex_mask |= 1 << i;
2632 } else {
2633 samplers->compressed_colortex_mask &= ~(1 << i);
2634 }
2635
2636 if (rtex->fmask.size) {
2637 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2638 views[i], rviews[i]->fmask_state);
2639 } else {
2640 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2641 NULL, NULL);
2642 }
2643 }
2644 }
2645 for (; i < samplers->n_views; i++) {
2646 samplers->depth_texture_mask &= ~(1 << i);
2647 samplers->compressed_colortex_mask &= ~(1 << i);
2648 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2649 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2650 NULL, NULL);
2651 }
2652
2653 samplers->n_views = count;
2654 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2655 }
2656
2657 static void si_set_sampler_states(struct si_context *sctx,
2658 struct si_pm4_state *pm4,
2659 unsigned count, void **states,
2660 struct si_textures_info *samplers,
2661 unsigned user_data_reg)
2662 {
2663 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2664 uint32_t *border_color_table = NULL;
2665 int i, j;
2666
2667 if (!count)
2668 goto out;
2669
2670 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2671
2672 si_pm4_sh_data_begin(pm4);
2673 for (i = 0; i < count; i++) {
2674 if (rstates[i] &&
2675 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2676 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2677 if (!sctx->border_color_table ||
2678 ((sctx->border_color_offset + count - i) &
2679 C_008F3C_BORDER_COLOR_PTR)) {
2680 r600_resource_reference(&sctx->border_color_table, NULL);
2681 sctx->border_color_offset = 0;
2682
2683 sctx->border_color_table =
2684 si_resource_create_custom(&sctx->screen->b.b,
2685 PIPE_USAGE_STAGING,
2686 4096 * 4 * 4);
2687 }
2688
2689 if (!border_color_table) {
2690 border_color_table =
2691 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2692 sctx->b.rings.gfx.cs,
2693 PIPE_TRANSFER_WRITE |
2694 PIPE_TRANSFER_UNSYNCHRONIZED);
2695 }
2696
2697 for (j = 0; j < 4; j++) {
2698 border_color_table[4 * sctx->border_color_offset + j] =
2699 util_le32_to_cpu(rstates[i]->border_color[j]);
2700 }
2701
2702 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2703 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2704 }
2705
2706 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2707 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2708 }
2709 }
2710 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2711
2712 if (border_color_table) {
2713 uint64_t va_offset =
2714 r600_resource_va(&sctx->screen->b.b,
2715 (void*)sctx->border_color_table);
2716
2717 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2718 if (sctx->b.chip_class >= CIK)
2719 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2720 sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf);
2721 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2722 RADEON_PRIO_SHADER_DATA);
2723 }
2724
2725 memcpy(samplers->samplers, states, sizeof(void*) * count);
2726
2727 out:
2728 samplers->n_samplers = count;
2729 }
2730
2731 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2732 {
2733 struct si_context *sctx = (struct si_context *)ctx;
2734 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2735
2736 si_set_sampler_states(sctx, pm4, count, states,
2737 &sctx->samplers[PIPE_SHADER_VERTEX],
2738 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2739 #if HAVE_LLVM >= 0x0305
2740 si_set_sampler_states(sctx, pm4, count, states,
2741 &sctx->samplers[PIPE_SHADER_VERTEX],
2742 R_00B330_SPI_SHADER_USER_DATA_ES_0);
2743 #endif
2744 si_pm4_set_state(sctx, vs_sampler, pm4);
2745 }
2746
2747 static void si_bind_gs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2748 {
2749 struct si_context *sctx = (struct si_context *)ctx;
2750 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2751
2752 si_set_sampler_states(sctx, pm4, count, states,
2753 &sctx->samplers[PIPE_SHADER_GEOMETRY],
2754 R_00B230_SPI_SHADER_USER_DATA_GS_0);
2755 si_pm4_set_state(sctx, gs_sampler, pm4);
2756 }
2757
2758 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2759 {
2760 struct si_context *sctx = (struct si_context *)ctx;
2761 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2762
2763 si_set_sampler_states(sctx, pm4, count, states,
2764 &sctx->samplers[PIPE_SHADER_FRAGMENT],
2765 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2766 si_pm4_set_state(sctx, ps_sampler, pm4);
2767 }
2768
2769
2770 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2771 unsigned start, unsigned count,
2772 void **states)
2773 {
2774 assert(start == 0);
2775
2776 switch (shader) {
2777 case PIPE_SHADER_VERTEX:
2778 si_bind_vs_sampler_states(ctx, count, states);
2779 break;
2780 case PIPE_SHADER_GEOMETRY:
2781 si_bind_gs_sampler_states(ctx, count, states);
2782 break;
2783 case PIPE_SHADER_FRAGMENT:
2784 si_bind_ps_sampler_states(ctx, count, states);
2785 break;
2786 default:
2787 ;
2788 }
2789 }
2790
2791
2792
2793 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2794 {
2795 struct si_context *sctx = (struct si_context *)ctx;
2796 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2797 uint16_t mask = sample_mask;
2798
2799 if (pm4 == NULL)
2800 return;
2801
2802 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2803 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2804
2805 si_pm4_set_state(sctx, sample_mask, pm4);
2806 }
2807
2808 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2809 {
2810 free(state);
2811 }
2812
2813 /*
2814 * Vertex elements & buffers
2815 */
2816
2817 static void *si_create_vertex_elements(struct pipe_context *ctx,
2818 unsigned count,
2819 const struct pipe_vertex_element *elements)
2820 {
2821 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2822 int i;
2823
2824 assert(count < PIPE_MAX_ATTRIBS);
2825 if (!v)
2826 return NULL;
2827
2828 v->count = count;
2829 for (i = 0; i < count; ++i) {
2830 const struct util_format_description *desc;
2831 unsigned data_format, num_format;
2832 int first_non_void;
2833
2834 desc = util_format_description(elements[i].src_format);
2835 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2836 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2837 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2838
2839 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2840 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2841 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2842 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2843 S_008F0C_NUM_FORMAT(num_format) |
2844 S_008F0C_DATA_FORMAT(data_format);
2845 }
2846 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2847
2848 return v;
2849 }
2850
2851 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2852 {
2853 struct si_context *sctx = (struct si_context *)ctx;
2854 struct si_vertex_element *v = (struct si_vertex_element*)state;
2855
2856 sctx->vertex_elements = v;
2857 }
2858
2859 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2860 {
2861 struct si_context *sctx = (struct si_context *)ctx;
2862
2863 if (sctx->vertex_elements == state)
2864 sctx->vertex_elements = NULL;
2865 FREE(state);
2866 }
2867
2868 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2869 const struct pipe_vertex_buffer *buffers)
2870 {
2871 struct si_context *sctx = (struct si_context *)ctx;
2872
2873 util_set_vertex_buffers_count(sctx->vertex_buffer, &sctx->nr_vertex_buffers, buffers, start_slot, count);
2874 }
2875
2876 static void si_set_index_buffer(struct pipe_context *ctx,
2877 const struct pipe_index_buffer *ib)
2878 {
2879 struct si_context *sctx = (struct si_context *)ctx;
2880
2881 if (ib) {
2882 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2883 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2884 } else {
2885 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2886 }
2887 }
2888
2889 /*
2890 * Misc
2891 */
2892 static void si_set_polygon_stipple(struct pipe_context *ctx,
2893 const struct pipe_poly_stipple *state)
2894 {
2895 }
2896
2897 static void si_texture_barrier(struct pipe_context *ctx)
2898 {
2899 struct si_context *sctx = (struct si_context *)ctx;
2900
2901 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2902 R600_CONTEXT_FLUSH_AND_INV_CB;
2903 }
2904
2905 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2906 {
2907 struct pipe_blend_state blend;
2908
2909 memset(&blend, 0, sizeof(blend));
2910 blend.independent_blend_enable = true;
2911 blend.rt[0].colormask = 0xf;
2912 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2913 }
2914
2915 static boolean si_dma_copy(struct pipe_context *ctx,
2916 struct pipe_resource *dst,
2917 unsigned dst_level,
2918 unsigned dst_x, unsigned dst_y, unsigned dst_z,
2919 struct pipe_resource *src,
2920 unsigned src_level,
2921 const struct pipe_box *src_box)
2922 {
2923 /* XXX implement this or share evergreen_dma_blit with r600g */
2924 return FALSE;
2925 }
2926
2927 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2928 {
2929 /* XXX Turn this into a proper state. Right now the queries are
2930 * enabled in draw_vbo, which snoops r600_common_context to see
2931 * if any occlusion queries are active. */
2932 }
2933
2934 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2935 bool include_draw_vbo)
2936 {
2937 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2938 }
2939
2940 void si_init_state_functions(struct si_context *sctx)
2941 {
2942 int i;
2943
2944 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.framebuffer, si_emit_framebuffer_state, 0);
2945
2946 sctx->b.b.create_blend_state = si_create_blend_state;
2947 sctx->b.b.bind_blend_state = si_bind_blend_state;
2948 sctx->b.b.delete_blend_state = si_delete_blend_state;
2949 sctx->b.b.set_blend_color = si_set_blend_color;
2950
2951 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2952 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2953 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2954
2955 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2956 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2957 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2958
2959 for (i = 0; i < 8; i++) {
2960 sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i);
2961 sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i);
2962 sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i);
2963 }
2964 sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0);
2965 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2966 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2967
2968 sctx->b.b.set_clip_state = si_set_clip_state;
2969 sctx->b.b.set_scissor_states = si_set_scissor_states;
2970 sctx->b.b.set_viewport_states = si_set_viewport_states;
2971 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2972
2973 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2974 sctx->b.b.get_sample_position = cayman_get_sample_position;
2975
2976 sctx->b.b.create_vs_state = si_create_vs_state;
2977 sctx->b.b.create_fs_state = si_create_fs_state;
2978 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2979 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2980 sctx->b.b.delete_vs_state = si_delete_vs_shader;
2981 sctx->b.b.delete_fs_state = si_delete_ps_shader;
2982 #if HAVE_LLVM >= 0x0305
2983 sctx->b.b.create_gs_state = si_create_gs_state;
2984 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2985 sctx->b.b.delete_gs_state = si_delete_gs_shader;
2986 #endif
2987
2988 sctx->b.b.create_sampler_state = si_create_sampler_state;
2989 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2990 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2991
2992 sctx->b.b.create_sampler_view = si_create_sampler_view;
2993 sctx->b.b.set_sampler_views = si_set_sampler_views;
2994 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2995
2996 sctx->b.b.set_sample_mask = si_set_sample_mask;
2997
2998 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2999 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3000 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3001 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3002 sctx->b.b.set_index_buffer = si_set_index_buffer;
3003
3004 sctx->b.b.texture_barrier = si_texture_barrier;
3005 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3006 sctx->b.dma_copy = si_dma_copy;
3007 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3008 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3009
3010 sctx->b.b.draw_vbo = si_draw_vbo;
3011 }
3012
3013 void si_init_config(struct si_context *sctx)
3014 {
3015 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
3016
3017 if (pm4 == NULL)
3018 return;
3019
3020 si_cmd_context_control(pm4);
3021
3022 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3023
3024 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3025 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3026 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3027 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3028 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3029 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3030 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3031 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3032 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3033 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3034 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3035 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3036
3037 /* FIXME calculate these values somehow ??? */
3038 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3039 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3040 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3041
3042 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3043 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3044 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3045 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3046
3047 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3048 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3049 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3050 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3051
3052 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3053 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3054 if (sctx->b.chip_class == SI) {
3055 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3056 S_028AA8_SWITCH_ON_EOP(1) |
3057 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3058 S_028AA8_PRIMGROUP_SIZE(63));
3059 }
3060 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3061 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3062 if (sctx->b.chip_class < CIK)
3063 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3064 S_008A14_CLIP_VTX_REORDER_ENA(1));
3065
3066 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3067 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3068
3069 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3070
3071 if (sctx->b.chip_class >= CIK) {
3072 switch (sctx->screen->b.family) {
3073 case CHIP_BONAIRE:
3074 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3075 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3076 break;
3077 case CHIP_HAWAII:
3078 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3079 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3080 break;
3081 case CHIP_KAVERI:
3082 /* XXX todo */
3083 case CHIP_KABINI:
3084 /* XXX todo */
3085 default:
3086 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3087 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3088 break;
3089 }
3090 } else {
3091 switch (sctx->screen->b.family) {
3092 case CHIP_TAHITI:
3093 case CHIP_PITCAIRN:
3094 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3095 break;
3096 case CHIP_VERDE:
3097 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3098 break;
3099 case CHIP_OLAND:
3100 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3101 break;
3102 case CHIP_HAINAN:
3103 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3104 break;
3105 default:
3106 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3107 break;
3108 }
3109 }
3110
3111 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3112 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3113 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3114 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3115 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3116 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3117 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3118
3119 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3120 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3121 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3122 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3123 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3124 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3125 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3126 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3127 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3128 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3129 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3130 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3131 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3132 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3133 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3134 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3135 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3136 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3137 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3138 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3139 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3140 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3141
3142 if (sctx->b.chip_class >= CIK) {
3143 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3144 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3145 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3146 }
3147
3148 si_pm4_set_state(sctx, init, pm4);
3149 }