radeonsi: rename init_config states to cs_preamble states
[mesa.git] / src / gallium / drivers / radeonsi / si_state.h
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef SI_STATE_H
26 #define SI_STATE_H
27
28 #include "pipebuffer/pb_slab.h"
29 #include "si_pm4.h"
30 #include "util/u_blitter.h"
31
32 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL + 1)
33 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE + 1)
34
35 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
36 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
37 #define SI_NUM_CONST_BUFFERS 16
38 #define SI_NUM_IMAGES 16
39 #define SI_NUM_IMAGE_SLOTS (SI_NUM_IMAGES * 2) /* the second half are FMASK slots */
40 #define SI_NUM_SHADER_BUFFERS 16
41
42 struct si_screen;
43 struct si_shader;
44 struct si_shader_ctx_state;
45 struct si_shader_selector;
46 struct si_texture;
47 struct si_qbo_state;
48
49 struct si_state_blend {
50 struct si_pm4_state pm4;
51 uint32_t cb_target_mask;
52 /* Set 0xf or 0x0 (4 bits) per render target if the following is
53 * true. ANDed with spi_shader_col_format.
54 */
55 unsigned cb_target_enabled_4bit;
56 unsigned blend_enable_4bit;
57 unsigned need_src_alpha_4bit;
58 unsigned commutative_4bit;
59 unsigned dcc_msaa_corruption_4bit;
60 bool alpha_to_coverage : 1;
61 bool alpha_to_one : 1;
62 bool dual_src_blend : 1;
63 bool logicop_enable : 1;
64 };
65
66 struct si_state_rasterizer {
67 struct si_pm4_state pm4;
68 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
69 struct si_pm4_state *pm4_poly_offset;
70 unsigned pa_sc_line_stipple;
71 unsigned pa_cl_clip_cntl;
72 float line_width;
73 float max_point_size;
74 unsigned sprite_coord_enable : 8;
75 unsigned clip_plane_enable : 8;
76 unsigned half_pixel_center : 1;
77 unsigned flatshade : 1;
78 unsigned flatshade_first : 1;
79 unsigned two_side : 1;
80 unsigned multisample_enable : 1;
81 unsigned force_persample_interp : 1;
82 unsigned line_stipple_enable : 1;
83 unsigned poly_stipple_enable : 1;
84 unsigned line_smooth : 1;
85 unsigned poly_smooth : 1;
86 unsigned uses_poly_offset : 1;
87 unsigned clamp_fragment_color : 1;
88 unsigned clamp_vertex_color : 1;
89 unsigned rasterizer_discard : 1;
90 unsigned scissor_enable : 1;
91 unsigned clip_halfz : 1;
92 unsigned cull_front : 1;
93 unsigned cull_back : 1;
94 unsigned depth_clamp_any : 1;
95 unsigned provoking_vertex_first : 1;
96 unsigned polygon_mode_enabled : 1;
97 unsigned polygon_mode_is_lines : 1;
98 };
99
100 struct si_dsa_stencil_ref_part {
101 uint8_t valuemask[2];
102 uint8_t writemask[2];
103 };
104
105 struct si_dsa_order_invariance {
106 /** Whether the final result in Z/S buffers is guaranteed to be
107 * invariant under changes to the order in which fragments arrive. */
108 bool zs : 1;
109
110 /** Whether the set of fragments that pass the combined Z/S test is
111 * guaranteed to be invariant under changes to the order in which
112 * fragments arrive. */
113 bool pass_set : 1;
114
115 /** Whether the last fragment that passes the combined Z/S test at each
116 * sample is guaranteed to be invariant under changes to the order in
117 * which fragments arrive. */
118 bool pass_last : 1;
119 };
120
121 struct si_state_dsa {
122 struct si_pm4_state pm4;
123 struct si_dsa_stencil_ref_part stencil_ref;
124
125 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
126 struct si_dsa_order_invariance order_invariance[2];
127
128 ubyte alpha_func : 3;
129 bool depth_enabled : 1;
130 bool depth_write_enabled : 1;
131 bool stencil_enabled : 1;
132 bool stencil_write_enabled : 1;
133 bool db_can_write : 1;
134 };
135
136 struct si_stencil_ref {
137 struct pipe_stencil_ref state;
138 struct si_dsa_stencil_ref_part dsa_part;
139 };
140
141 struct si_vertex_elements {
142 struct si_resource *instance_divisor_factor_buffer;
143 uint32_t rsrc_word3[SI_MAX_ATTRIBS];
144 uint16_t src_offset[SI_MAX_ATTRIBS];
145 uint8_t fix_fetch[SI_MAX_ATTRIBS];
146 uint8_t format_size[SI_MAX_ATTRIBS];
147 uint8_t vertex_buffer_index[SI_MAX_ATTRIBS];
148
149 /* Bitmask of elements that always need a fixup to be applied. */
150 uint16_t fix_fetch_always;
151
152 /* Bitmask of elements whose fetch should always be opencoded. */
153 uint16_t fix_fetch_opencode;
154
155 /* Bitmask of elements which need to be opencoded if the vertex buffer
156 * is unaligned. */
157 uint16_t fix_fetch_unaligned;
158
159 /* For elements in fix_fetch_unaligned: whether the effective
160 * element load size as seen by the hardware is a dword (as opposed
161 * to a short).
162 */
163 uint16_t hw_load_is_dword;
164
165 /* Bitmask of vertex buffers requiring alignment check */
166 uint16_t vb_alignment_check_mask;
167
168 uint8_t count;
169 bool uses_instance_divisors;
170
171 uint16_t first_vb_use_mask;
172 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
173 uint16_t vb_desc_list_alloc_size;
174 uint16_t instance_divisor_is_one; /* bitmask of inputs */
175 uint16_t instance_divisor_is_fetched; /* bitmask of inputs */
176 };
177
178 union si_state {
179 struct {
180 struct si_state_blend *blend;
181 struct si_state_rasterizer *rasterizer;
182 struct si_state_dsa *dsa;
183 struct si_pm4_state *poly_offset;
184 struct si_pm4_state *ls;
185 struct si_pm4_state *hs;
186 struct si_pm4_state *es;
187 struct si_pm4_state *gs;
188 struct si_pm4_state *vgt_shader_config;
189 struct si_pm4_state *vs;
190 struct si_pm4_state *ps;
191 } named;
192 struct si_pm4_state *array[0];
193 };
194
195 #define SI_STATE_IDX(name) (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
196 #define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name))
197 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
198
199 static inline unsigned si_states_that_always_roll_context(void)
200 {
201 return (SI_STATE_BIT(blend) | SI_STATE_BIT(rasterizer) | SI_STATE_BIT(dsa) |
202 SI_STATE_BIT(poly_offset) | SI_STATE_BIT(vgt_shader_config));
203 }
204
205 union si_state_atoms {
206 struct {
207 /* The order matters. */
208 struct si_atom render_cond;
209 struct si_atom streamout_begin;
210 struct si_atom streamout_enable; /* must be after streamout_begin */
211 struct si_atom framebuffer;
212 struct si_atom msaa_sample_locs;
213 struct si_atom db_render_state;
214 struct si_atom dpbb_state;
215 struct si_atom msaa_config;
216 struct si_atom sample_mask;
217 struct si_atom cb_render_state;
218 struct si_atom blend_color;
219 struct si_atom clip_regs;
220 struct si_atom clip_state;
221 struct si_atom shader_pointers;
222 struct si_atom guardband;
223 struct si_atom scissors;
224 struct si_atom viewports;
225 struct si_atom stencil_ref;
226 struct si_atom spi_map;
227 struct si_atom scratch_state;
228 struct si_atom window_rectangles;
229 struct si_atom shader_query;
230 } s;
231 struct si_atom array[0];
232 };
233
234 #define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / sizeof(struct si_atom)))
235 #define SI_NUM_ATOMS (sizeof(union si_state_atoms) / sizeof(struct si_atom *))
236
237 static inline unsigned si_atoms_that_always_roll_context(void)
238 {
239 return (SI_ATOM_BIT(streamout_begin) | SI_ATOM_BIT(streamout_enable) | SI_ATOM_BIT(framebuffer) |
240 SI_ATOM_BIT(msaa_sample_locs) | SI_ATOM_BIT(sample_mask) | SI_ATOM_BIT(blend_color) |
241 SI_ATOM_BIT(clip_state) | SI_ATOM_BIT(scissors) | SI_ATOM_BIT(viewports) |
242 SI_ATOM_BIT(stencil_ref) | SI_ATOM_BIT(scratch_state) | SI_ATOM_BIT(window_rectangles));
243 }
244
245 struct si_shader_data {
246 uint32_t sh_base[SI_NUM_SHADERS];
247 };
248
249 #define SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK \
250 (S_02881C_USE_VTX_POINT_SIZE(1) | S_02881C_USE_VTX_EDGE_FLAG(1) | \
251 S_02881C_USE_VTX_RENDER_TARGET_INDX(1) | S_02881C_USE_VTX_VIEWPORT_INDX(1) | \
252 S_02881C_VS_OUT_MISC_VEC_ENA(1) | S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1))
253
254 /* The list of registers whose emitted values are remembered by si_context. */
255 enum si_tracked_reg
256 {
257 SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */
258 SI_TRACKED_DB_COUNT_CONTROL,
259
260 SI_TRACKED_DB_RENDER_OVERRIDE2,
261 SI_TRACKED_DB_SHADER_CONTROL,
262
263 SI_TRACKED_CB_TARGET_MASK,
264 SI_TRACKED_CB_DCC_CONTROL,
265
266 SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */
267 SI_TRACKED_SX_BLEND_OPT_EPSILON,
268 SI_TRACKED_SX_BLEND_OPT_CONTROL,
269
270 SI_TRACKED_PA_SC_LINE_CNTL, /* 2 consecutive registers */
271 SI_TRACKED_PA_SC_AA_CONFIG,
272
273 SI_TRACKED_DB_EQAA,
274 SI_TRACKED_PA_SC_MODE_CNTL_1,
275
276 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
277 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
278
279 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, /* set with SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK*/
280 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL, /* set with ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK */
281 SI_TRACKED_PA_CL_CLIP_CNTL,
282
283 SI_TRACKED_PA_SC_BINNER_CNTL_0,
284 SI_TRACKED_DB_DFSM_CONTROL,
285
286 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */
287 SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
288 SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ,
289 SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ,
290
291 SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
292 SI_TRACKED_PA_SU_VTX_CNTL,
293
294 SI_TRACKED_PA_SC_CLIPRECT_RULE,
295
296 SI_TRACKED_PA_SC_LINE_STIPPLE,
297
298 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
299
300 SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */
301 SI_TRACKED_VGT_GSVS_RING_OFFSET_2,
302 SI_TRACKED_VGT_GSVS_RING_OFFSET_3,
303
304 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
305 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
306
307 SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* 4 consecutive registers */
308 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1,
309 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2,
310 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3,
311
312 SI_TRACKED_VGT_GS_INSTANCE_CNT,
313 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
314 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
315 SI_TRACKED_VGT_GS_MODE,
316 SI_TRACKED_VGT_PRIMITIVEID_EN,
317 SI_TRACKED_VGT_REUSE_OFF,
318 SI_TRACKED_SPI_VS_OUT_CONFIG,
319 SI_TRACKED_PA_CL_VTE_CNTL,
320 SI_TRACKED_PA_CL_NGG_CNTL,
321 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
322 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
323
324 SI_TRACKED_SPI_SHADER_IDX_FORMAT, /* 2 consecutive registers */
325 SI_TRACKED_SPI_SHADER_POS_FORMAT,
326
327 SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */
328 SI_TRACKED_SPI_PS_INPUT_ADDR,
329
330 SI_TRACKED_SPI_BARYC_CNTL,
331 SI_TRACKED_SPI_PS_IN_CONTROL,
332
333 SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */
334 SI_TRACKED_SPI_SHADER_COL_FORMAT,
335
336 SI_TRACKED_CB_SHADER_MASK,
337 SI_TRACKED_VGT_TF_PARAM,
338 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
339
340 SI_TRACKED_GE_PC_ALLOC,
341
342 SI_NUM_TRACKED_REGS,
343 };
344
345 struct si_tracked_regs {
346 uint64_t reg_saved;
347 uint32_t reg_value[SI_NUM_TRACKED_REGS];
348 uint32_t spi_ps_input_cntl[32];
349 };
350
351 /* Private read-write buffer slots. */
352 enum
353 {
354 SI_ES_RING_ESGS,
355 SI_GS_RING_ESGS,
356
357 SI_RING_GSVS,
358
359 SI_VS_STREAMOUT_BUF0,
360 SI_VS_STREAMOUT_BUF1,
361 SI_VS_STREAMOUT_BUF2,
362 SI_VS_STREAMOUT_BUF3,
363
364 SI_HS_CONST_DEFAULT_TESS_LEVELS,
365 SI_VS_CONST_INSTANCE_DIVISORS,
366 SI_VS_CONST_CLIP_PLANES,
367 SI_PS_CONST_POLY_STIPPLE,
368 SI_PS_CONST_SAMPLE_POSITIONS,
369
370 /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
371 SI_PS_IMAGE_COLORBUF0,
372 SI_PS_IMAGE_COLORBUF0_HI,
373 SI_PS_IMAGE_COLORBUF0_FMASK,
374 SI_PS_IMAGE_COLORBUF0_FMASK_HI,
375
376 GFX10_GS_QUERY_BUF,
377
378 SI_NUM_RW_BUFFERS,
379 };
380
381 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
382 * are contiguous:
383 *
384 * 0 - rw buffers
385 * 1 - vertex const and shader buffers
386 * 2 - vertex samplers and images
387 * 3 - fragment const and shader buffer
388 * ...
389 * 11 - compute const and shader buffers
390 * 12 - compute samplers and images
391 */
392 enum
393 {
394 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
395 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
396 SI_NUM_SHADER_DESCS,
397 };
398
399 #define SI_DESCS_RW_BUFFERS 0
400 #define SI_DESCS_FIRST_SHADER 1
401 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
402 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
403
404 #define SI_DESCS_SHADER_MASK(name) \
405 u_bit_consecutive(SI_DESCS_FIRST_SHADER + PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
406 SI_NUM_SHADER_DESCS)
407
408 static inline unsigned si_const_and_shader_buffer_descriptors_idx(unsigned shader)
409 {
410 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
411 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS;
412 }
413
414 static inline unsigned si_sampler_and_image_descriptors_idx(unsigned shader)
415 {
416 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
417 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES;
418 }
419
420 /* This represents descriptors in memory, such as buffer resources,
421 * image resources, and sampler states.
422 */
423 struct si_descriptors {
424 /* The list of descriptors in malloc'd memory. */
425 uint32_t *list;
426 /* The list in mapped GPU memory. */
427 uint32_t *gpu_list;
428
429 /* The buffer where the descriptors have been uploaded. */
430 struct si_resource *buffer;
431 uint64_t gpu_address;
432
433 /* The maximum number of descriptors. */
434 uint32_t num_elements;
435
436 /* Slots that are used by currently-bound shaders.
437 * It determines which slots are uploaded.
438 */
439 uint32_t first_active_slot;
440 uint32_t num_active_slots;
441
442 /* The SH register offset relative to USER_DATA*_0 where the pointer
443 * to the descriptor array will be stored. */
444 short shader_userdata_offset;
445 /* The size of one descriptor. */
446 ubyte element_dw_size;
447 /* If there is only one slot enabled, bind it directly instead of
448 * uploading descriptors. -1 if disabled. */
449 signed char slot_index_to_bind_directly;
450 };
451
452 struct si_buffer_resources {
453 struct pipe_resource **buffers; /* this has num_buffers elements */
454 unsigned *offsets; /* this has num_buffers elements */
455
456 enum radeon_bo_priority priority : 6;
457 enum radeon_bo_priority priority_constbuf : 6;
458
459 /* The i-th bit is set if that element is enabled (non-NULL resource). */
460 unsigned enabled_mask;
461 unsigned writable_mask;
462 };
463
464 #define si_pm4_state_changed(sctx, member) \
465 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
466
467 #define si_pm4_state_enabled_and_changed(sctx, member) \
468 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
469
470 #define si_pm4_bind_state(sctx, member, value) \
471 do { \
472 (sctx)->queued.named.member = (value); \
473 (sctx)->dirty_states |= SI_STATE_BIT(member); \
474 } while (0)
475
476 #define si_pm4_delete_state(sctx, member, value) \
477 do { \
478 if ((sctx)->queued.named.member == (value)) { \
479 (sctx)->queued.named.member = NULL; \
480 } \
481 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), SI_STATE_IDX(member)); \
482 } while (0)
483
484 /* si_descriptors.c */
485 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
486 const struct legacy_surf_level *base_level_info,
487 unsigned base_level, unsigned first_level, unsigned block_width,
488 bool is_stencil, bool force_dcc_off, uint32_t *state);
489 void si_update_ps_colorbuf0_slot(struct si_context *sctx);
490 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot,
491 struct pipe_constant_buffer *cbuf);
492 void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader, uint start_slot,
493 uint count, struct pipe_shader_buffer *sbuf);
494 void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource *buffer,
495 unsigned stride, unsigned num_records, bool add_tid, bool swizzle,
496 unsigned element_size, unsigned index_stride, uint64_t offset);
497 void si_init_all_descriptors(struct si_context *sctx);
498 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
499 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
500 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
501 void si_release_all_descriptors(struct si_context *sctx);
502 void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx);
503 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx);
504 bool si_gfx_resources_check_encrypted(struct si_context *sctx);
505 bool si_compute_resources_check_encrypted(struct si_context *sctx);
506 void si_shader_pointers_mark_dirty(struct si_context *sctx);
507 void si_add_all_descriptors_to_bo_list(struct si_context *sctx);
508 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf, const uint8_t *ptr,
509 unsigned size, uint32_t *const_offset);
510 void si_update_all_texture_descriptors(struct si_context *sctx);
511 void si_shader_change_notify(struct si_context *sctx);
512 void si_update_needs_color_decompress_masks(struct si_context *sctx);
513 void si_emit_graphics_shader_pointers(struct si_context *sctx);
514 void si_emit_compute_shader_pointers(struct si_context *sctx);
515 void si_set_rw_buffer(struct si_context *sctx, uint slot, const struct pipe_constant_buffer *input);
516 void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
517 const struct pipe_shader_buffer *sbuffer);
518 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
519 uint64_t new_active_mask);
520 void si_set_active_descriptors_for_shader(struct si_context *sctx, struct si_shader_selector *sel);
521 bool si_bindless_descriptor_can_reclaim_slab(void *priv, struct pb_slab_entry *entry);
522 struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap, unsigned entry_size,
523 unsigned group_index);
524 void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
525 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf);
526 /* si_state.c */
527 void si_init_state_compute_functions(struct si_context *sctx);
528 void si_init_state_functions(struct si_context *sctx);
529 void si_init_screen_state_functions(struct si_screen *sscreen);
530 void si_init_cs_preamble_state(struct si_context *sctx);
531 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
532 enum pipe_format format, unsigned offset, unsigned size,
533 uint32_t *state);
534 struct pipe_sampler_view *si_create_sampler_view_custom(struct pipe_context *ctx,
535 struct pipe_resource *texture,
536 const struct pipe_sampler_view *state,
537 unsigned width0, unsigned height0,
538 unsigned force_level);
539 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
540 void si_update_ps_iter_samples(struct si_context *sctx);
541 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
542 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
543 void si_set_occlusion_query_state(struct si_context *sctx, bool old_perfect_enable);
544
545 struct si_fast_udiv_info32 {
546 unsigned multiplier; /* the "magic number" multiplier */
547 unsigned pre_shift; /* shift for the dividend before multiplying */
548 unsigned post_shift; /* shift for the dividend after multiplying */
549 int increment; /* 0 or 1; if set then increment the numerator, using one of
550 the two strategies */
551 };
552
553 struct si_fast_udiv_info32 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits);
554
555 /* si_state_binning.c */
556 void si_emit_dpbb_state(struct si_context *sctx);
557
558 /* si_state_shaders.c */
559 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
560 unsigned char ir_sha1_cache_key[20]);
561 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
562 struct si_shader *shader);
563 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
564 struct si_shader *shader, bool insert_into_disk_cache);
565 bool si_update_shaders(struct si_context *sctx);
566 void si_init_screen_live_shader_cache(struct si_screen *sscreen);
567 void si_init_shader_functions(struct si_context *sctx);
568 bool si_init_shader_cache(struct si_screen *sscreen);
569 void si_destroy_shader_cache(struct si_screen *sscreen);
570 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
571 struct util_queue_fence *ready_fence,
572 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
573 util_queue_execute_func execute);
574 void si_get_active_slot_masks(const struct si_shader_info *info, uint32_t *const_and_shader_buffers,
575 uint64_t *samplers_and_images);
576 int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
577 struct si_compiler_ctx_state *compiler_state,
578 struct si_shader_key *key, int thread_index, bool optimized_or_none);
579 void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
580 struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key);
581 unsigned si_get_input_prim(const struct si_shader_selector *gs);
582 bool si_update_ngg(struct si_context *sctx);
583
584 /* si_state_draw.c */
585 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
586 unsigned cp_coher_cntl);
587 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx);
588 void gfx10_emit_cache_flush(struct si_context *sctx);
589 void si_emit_cache_flush(struct si_context *sctx);
590 void si_trace_emit(struct si_context *sctx);
591 void si_init_draw_functions(struct si_context *sctx);
592
593 /* si_state_msaa.c */
594 void si_init_msaa_functions(struct si_context *sctx);
595 void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
596
597 /* si_state_streamout.c */
598 void si_streamout_buffers_dirty(struct si_context *sctx);
599 void si_emit_streamout_end(struct si_context *sctx);
600 void si_update_prims_generated_query_state(struct si_context *sctx, unsigned type, int diff);
601 void si_init_streamout_functions(struct si_context *sctx);
602
603 static inline unsigned si_get_constbuf_slot(unsigned slot)
604 {
605 /* Constant buffers are in slots [16..31], ascending */
606 return SI_NUM_SHADER_BUFFERS + slot;
607 }
608
609 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
610 {
611 /* shader buffers are in slots [15..0], descending */
612 return SI_NUM_SHADER_BUFFERS - 1 - slot;
613 }
614
615 static inline unsigned si_get_sampler_slot(unsigned slot)
616 {
617 /* 32 samplers are in sampler slots [16..47], 16 dw per slot, ascending */
618 /* those are equivalent to image slots [32..95], 8 dw per slot, ascending */
619 return SI_NUM_IMAGE_SLOTS / 2 + slot;
620 }
621
622 static inline unsigned si_get_image_slot(unsigned slot)
623 {
624 /* image slots are in [31..0] (sampler slots [15..0]), descending */
625 /* images are in slots [31..16], while FMASKs are in slots [15..0] */
626 return SI_NUM_IMAGE_SLOTS - 1 - slot;
627 }
628
629 #endif