2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon/r600_pipe_common.h"
30 #include "pipebuffer/pb_slab.h"
32 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
33 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
35 #define SI_MAX_ATTRIBS 16
36 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
37 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
38 #define SI_NUM_CONST_BUFFERS 16
39 #define SI_NUM_IMAGES 16
40 #define SI_NUM_SHADER_BUFFERS 16
44 struct si_shader_selector
;
46 struct si_state_blend
{
47 struct si_pm4_state pm4
;
48 uint32_t cb_target_mask
;
49 /* Set 0xf or 0x0 (4 bits) per render target if the following is
50 * true. ANDed with spi_shader_col_format.
52 unsigned cb_target_enabled_4bit
;
53 unsigned blend_enable_4bit
;
54 unsigned need_src_alpha_4bit
;
55 unsigned commutative_4bit
;
56 bool alpha_to_coverage
:1;
58 bool dual_src_blend
:1;
59 bool logicop_enable
:1;
62 struct si_state_rasterizer
{
63 struct si_pm4_state pm4
;
64 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
65 struct si_pm4_state
*pm4_poly_offset
;
66 unsigned pa_sc_line_stipple
;
67 unsigned pa_cl_clip_cntl
;
70 unsigned sprite_coord_enable
:8;
71 unsigned clip_plane_enable
:8;
74 unsigned multisample_enable
:1;
75 unsigned force_persample_interp
:1;
76 unsigned line_stipple_enable
:1;
77 unsigned poly_stipple_enable
:1;
78 unsigned line_smooth
:1;
79 unsigned poly_smooth
:1;
80 unsigned uses_poly_offset
:1;
81 unsigned clamp_fragment_color
:1;
82 unsigned clamp_vertex_color
:1;
83 unsigned rasterizer_discard
:1;
84 unsigned scissor_enable
:1;
85 unsigned clip_halfz
:1;
88 struct si_dsa_stencil_ref_part
{
93 struct si_dsa_order_invariance
{
94 /** Whether the final result in Z/S buffers is guaranteed to be
95 * invariant under changes to the order in which fragments arrive. */
98 /** Whether the set of fragments that pass the combined Z/S test is
99 * guaranteed to be invariant under changes to the order in which
100 * fragments arrive. */
103 /** Whether the last fragment that passes the combined Z/S test at each
104 * sample is guaranteed to be invariant under changes to the order in
105 * which fragments arrive. */
109 struct si_state_dsa
{
110 struct si_pm4_state pm4
;
111 struct si_dsa_stencil_ref_part stencil_ref
;
113 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
114 struct si_dsa_order_invariance order_invariance
[2];
117 bool depth_enabled
:1;
118 bool depth_write_enabled
:1;
119 bool stencil_enabled
:1;
120 bool stencil_write_enabled
:1;
125 struct si_stencil_ref
{
126 struct r600_atom atom
;
127 struct pipe_stencil_ref state
;
128 struct si_dsa_stencil_ref_part dsa_part
;
131 struct si_vertex_elements
133 uint32_t instance_divisors
[SI_MAX_ATTRIBS
];
134 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
135 uint16_t src_offset
[SI_MAX_ATTRIBS
];
136 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
137 uint8_t format_size
[SI_MAX_ATTRIBS
];
138 uint8_t vertex_buffer_index
[SI_MAX_ATTRIBS
];
141 bool uses_instance_divisors
;
143 uint16_t first_vb_use_mask
;
144 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
145 uint16_t desc_list_byte_size
;
146 uint16_t instance_divisor_is_one
; /* bitmask of inputs */
147 uint16_t instance_divisor_is_fetched
; /* bitmask of inputs */
152 struct si_state_blend
*blend
;
153 struct si_state_rasterizer
*rasterizer
;
154 struct si_state_dsa
*dsa
;
155 struct si_pm4_state
*poly_offset
;
156 struct si_pm4_state
*ls
;
157 struct si_pm4_state
*hs
;
158 struct si_pm4_state
*es
;
159 struct si_pm4_state
*gs
;
160 struct si_pm4_state
*vgt_shader_config
;
161 struct si_pm4_state
*vs
;
162 struct si_pm4_state
*ps
;
164 struct si_pm4_state
*array
[0];
167 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
169 union si_state_atoms
{
171 /* The order matters. */
172 struct r600_atom
*render_cond
;
173 struct r600_atom
*streamout_begin
;
174 struct r600_atom
*streamout_enable
; /* must be after streamout_begin */
175 struct r600_atom
*framebuffer
;
176 struct r600_atom
*msaa_sample_locs
;
177 struct r600_atom
*db_render_state
;
178 struct r600_atom
*dpbb_state
;
179 struct r600_atom
*msaa_config
;
180 struct r600_atom
*sample_mask
;
181 struct r600_atom
*cb_render_state
;
182 struct r600_atom
*blend_color
;
183 struct r600_atom
*clip_regs
;
184 struct r600_atom
*clip_state
;
185 struct r600_atom
*shader_pointers
;
186 struct r600_atom
*scissors
;
187 struct r600_atom
*viewports
;
188 struct r600_atom
*stencil_ref
;
189 struct r600_atom
*spi_map
;
190 struct r600_atom
*scratch_state
;
192 struct r600_atom
*array
[0];
195 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
197 struct si_shader_data
{
198 struct r600_atom atom
;
199 uint32_t sh_base
[SI_NUM_SHADERS
];
202 /* Private read-write buffer slots. */
209 SI_VS_STREAMOUT_BUF0
,
210 SI_VS_STREAMOUT_BUF1
,
211 SI_VS_STREAMOUT_BUF2
,
212 SI_VS_STREAMOUT_BUF3
,
214 SI_HS_CONST_DEFAULT_TESS_LEVELS
,
215 SI_VS_CONST_INSTANCE_DIVISORS
,
216 SI_VS_CONST_CLIP_PLANES
,
217 SI_PS_CONST_POLY_STIPPLE
,
218 SI_PS_CONST_SAMPLE_POSITIONS
,
220 /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
221 SI_PS_IMAGE_COLORBUF0
,
222 SI_PS_IMAGE_COLORBUF0_HI
,
223 SI_PS_IMAGE_COLORBUF0_FMASK
,
224 SI_PS_IMAGE_COLORBUF0_FMASK_HI
,
229 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
233 * 1 - vertex const and shader buffers
234 * 2 - vertex samplers and images
235 * 3 - fragment const and shader buffer
237 * 11 - compute const and shader buffers
238 * 12 - compute samplers and images
241 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
242 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
246 #define SI_DESCS_RW_BUFFERS 0
247 #define SI_DESCS_FIRST_SHADER 1
248 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
249 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
250 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
251 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
253 #define SI_DESCS_SHADER_MASK(name) \
254 u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
255 PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
258 /* This represents descriptors in memory, such as buffer resources,
259 * image resources, and sampler states.
261 struct si_descriptors
{
262 /* The list of descriptors in malloc'd memory. */
264 /* The list in mapped GPU memory. */
267 /* The buffer where the descriptors have been uploaded. */
268 struct r600_resource
*buffer
;
269 uint64_t gpu_address
;
271 /* The maximum number of descriptors. */
272 uint32_t num_elements
;
274 /* Slots that are used by currently-bound shaders.
275 * It determines which slots are uploaded.
277 uint32_t first_active_slot
;
278 uint32_t num_active_slots
;
280 /* The SH register offset relative to USER_DATA*_0 where the pointer
281 * to the descriptor array will be stored. */
282 short shader_userdata_offset
;
283 /* The size of one descriptor. */
284 ubyte element_dw_size
;
285 /* If there is only one slot enabled, bind it directly instead of
286 * uploading descriptors. -1 if disabled. */
287 signed char slot_index_to_bind_directly
;
290 struct si_buffer_resources
{
291 struct pipe_resource
**buffers
; /* this has num_buffers elements */
293 enum radeon_bo_usage shader_usage
:4; /* READ, WRITE, or READWRITE */
294 enum radeon_bo_usage shader_usage_constbuf
:4;
295 enum radeon_bo_priority priority
:6;
296 enum radeon_bo_priority priority_constbuf
:6;
298 /* The i-th bit is set if that element is enabled (non-NULL resource). */
299 unsigned enabled_mask
;
302 #define si_pm4_block_idx(member) \
303 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
305 #define si_pm4_state_changed(sctx, member) \
306 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
308 #define si_pm4_state_enabled_and_changed(sctx, member) \
309 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
311 #define si_pm4_bind_state(sctx, member, value) \
313 (sctx)->queued.named.member = (value); \
314 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
317 #define si_pm4_delete_state(sctx, member, value) \
319 if ((sctx)->queued.named.member == (value)) { \
320 (sctx)->queued.named.member = NULL; \
322 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
323 si_pm4_block_idx(member)); \
326 /* si_descriptors.c */
327 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
328 struct r600_texture
*tex
,
329 const struct legacy_surf_level
*base_level_info
,
330 unsigned base_level
, unsigned first_level
,
331 unsigned block_width
, bool is_stencil
,
333 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
);
334 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
335 uint slot
, struct pipe_constant_buffer
*cbuf
);
336 void si_get_shader_buffers(struct si_context
*sctx
,
337 enum pipe_shader_type shader
,
338 uint start_slot
, uint count
,
339 struct pipe_shader_buffer
*sbuf
);
340 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
341 struct pipe_resource
*buffer
,
342 unsigned stride
, unsigned num_records
,
343 bool add_tid
, bool swizzle
,
344 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
345 void si_init_all_descriptors(struct si_context
*sctx
);
346 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
);
347 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
);
348 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
);
349 void si_release_all_descriptors(struct si_context
*sctx
);
350 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
351 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
);
352 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
353 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
354 void si_update_all_texture_descriptors(struct si_context
*sctx
);
355 void si_shader_change_notify(struct si_context
*sctx
);
356 void si_update_needs_color_decompress_masks(struct si_context
*sctx
);
357 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
358 struct r600_atom
*atom
);
359 void si_emit_compute_shader_pointers(struct si_context
*sctx
);
360 void si_set_rw_buffer(struct si_context
*sctx
,
361 uint slot
, const struct pipe_constant_buffer
*input
);
362 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
363 uint64_t new_active_mask
);
364 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
365 struct si_shader_selector
*sel
);
366 bool si_bindless_descriptor_can_reclaim_slab(void *priv
,
367 struct pb_slab_entry
*entry
);
368 struct pb_slab
*si_bindless_descriptor_slab_alloc(void *priv
, unsigned heap
,
370 unsigned group_index
);
371 void si_bindless_descriptor_slab_free(void *priv
, struct pb_slab
*pslab
);
372 void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
375 struct si_shader_selector
;
377 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
378 struct r600_atom
**list_elem
,
379 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
));
380 void si_init_state_functions(struct si_context
*sctx
);
381 void si_init_screen_state_functions(struct si_screen
*sscreen
);
383 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
384 enum pipe_format format
,
385 unsigned offset
, unsigned size
,
388 si_make_texture_descriptor(struct si_screen
*screen
,
389 struct r600_texture
*tex
,
391 enum pipe_texture_target target
,
392 enum pipe_format pipe_format
,
393 const unsigned char state_swizzle
[4],
394 unsigned first_level
, unsigned last_level
,
395 unsigned first_layer
, unsigned last_layer
,
396 unsigned width
, unsigned height
, unsigned depth
,
398 uint32_t *fmask_state
);
399 struct pipe_sampler_view
*
400 si_create_sampler_view_custom(struct pipe_context
*ctx
,
401 struct pipe_resource
*texture
,
402 const struct pipe_sampler_view
*state
,
403 unsigned width0
, unsigned height0
,
404 unsigned force_level
);
405 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
);
406 void si_update_ps_iter_samples(struct si_context
*sctx
);
407 void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
408 void si_set_occlusion_query_state(struct pipe_context
*ctx
,
409 bool old_perfect_enable
);
411 /* si_state_binning.c */
412 void si_emit_dpbb_state(struct si_context
*sctx
, struct r600_atom
*state
);
414 /* si_state_shaders.c */
415 bool si_update_shaders(struct si_context
*sctx
);
416 void si_init_shader_functions(struct si_context
*sctx
);
417 bool si_init_shader_cache(struct si_screen
*sscreen
);
418 void si_destroy_shader_cache(struct si_screen
*sscreen
);
419 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
420 uint32_t *const_and_shader_buffers
,
421 uint64_t *samplers_and_images
);
422 void *si_get_blit_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
423 unsigned num_layers
);
425 /* si_state_draw.c */
426 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
);
427 void si_emit_cache_flush(struct si_context
*sctx
);
428 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
);
429 void si_draw_rectangle(struct blitter_context
*blitter
,
430 void *vertex_elements_cso
,
431 blitter_get_vs_func get_vs
,
432 int x1
, int y1
, int x2
, int y2
,
433 float depth
, unsigned num_instances
,
434 enum blitter_attrib_type type
,
435 const union blitter_attrib
*attrib
);
436 void si_trace_emit(struct si_context
*sctx
);
438 /* si_state_msaa.c */
439 void si_init_msaa_functions(struct si_context
*sctx
);
440 void si_emit_sample_locations(struct radeon_winsys_cs
*cs
, int nr_samples
);
442 /* si_state_streamout.c */
443 void si_streamout_buffers_dirty(struct si_context
*sctx
);
444 void si_emit_streamout_end(struct si_context
*sctx
);
445 void si_update_prims_generated_query_state(struct si_context
*sctx
,
446 unsigned type
, int diff
);
447 void si_init_streamout_functions(struct si_context
*sctx
);
450 static inline unsigned
451 si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
454 return rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
456 return rtex
->surface
.u
.legacy
.tiling_index
[level
];
459 static inline unsigned si_get_constbuf_slot(unsigned slot
)
461 /* Constant buffers are in slots [16..31], ascending */
462 return SI_NUM_SHADER_BUFFERS
+ slot
;
465 static inline unsigned si_get_shaderbuf_slot(unsigned slot
)
467 /* shader buffers are in slots [15..0], descending */
468 return SI_NUM_SHADER_BUFFERS
- 1 - slot
;
471 static inline unsigned si_get_sampler_slot(unsigned slot
)
473 /* samplers are in slots [8..39], ascending */
474 return SI_NUM_IMAGES
/ 2 + slot
;
477 static inline unsigned si_get_image_slot(unsigned slot
)
479 /* images are in slots [15..0] (sampler slots [7..0]), descending */
480 return SI_NUM_IMAGES
- 1 - slot
;