src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef SI_STATE_H
  26 #define SI_STATE_H
  27
  28 #include "si_pm4.h"
  29 #include "radeon/r600_pipe_common.h"
  30
  31 #include "pipebuffer/pb_slab.h"
  32
  33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  35
  36 #define SI_MAX_ATTRIBS                  16
  37 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  38 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  39 #define SI_NUM_CONST_BUFFERS            16
  40 #define SI_NUM_IMAGES                   16
  41 #define SI_NUM_SHADER_BUFFERS           16
  42
  43 struct si_screen;
  44 struct si_shader;
  45 struct si_shader_selector;
  46
  47 struct si_state_blend {
  48         struct si_pm4_state     pm4;
  49         uint32_t                cb_target_mask;
  50         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  51          * true. ANDed with spi_shader_col_format.
  52          */
  53         unsigned                cb_target_enabled_4bit;
  54         unsigned                blend_enable_4bit;
  55         unsigned                need_src_alpha_4bit;
  56         unsigned                commutative_4bit;
  57         bool                    alpha_to_coverage:1;
  58         bool                    alpha_to_one:1;
  59         bool                    dual_src_blend:1;
  60         bool                    logicop_enable:1;
  61 };
  62
  63 struct si_state_rasterizer {
  64         struct si_pm4_state     pm4;
  65         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  66         struct si_pm4_state     *pm4_poly_offset;
  67         unsigned                pa_sc_line_stipple;
  68         unsigned                pa_cl_clip_cntl;
  69         float                   line_width;
  70         float                   max_point_size;
  71         unsigned                sprite_coord_enable:8;
  72         unsigned                clip_plane_enable:8;
  73         unsigned                flatshade:1;
  74         unsigned                two_side:1;
  75         unsigned                multisample_enable:1;
  76         unsigned                force_persample_interp:1;
  77         unsigned                line_stipple_enable:1;
  78         unsigned                poly_stipple_enable:1;
  79         unsigned                line_smooth:1;
  80         unsigned                poly_smooth:1;
  81         unsigned                uses_poly_offset:1;
  82         unsigned                clamp_fragment_color:1;
  83         unsigned                clamp_vertex_color:1;
  84         unsigned                rasterizer_discard:1;
  85         unsigned                scissor_enable:1;
  86         unsigned                clip_halfz:1;
  87 };
  88
  89 struct si_dsa_stencil_ref_part {
  90         uint8_t                 valuemask[2];
  91         uint8_t                 writemask[2];
  92 };
  93
  94 struct si_dsa_order_invariance {
  95         /** Whether the final result in Z/S buffers is guaranteed to be
  96          * invariant under changes to the order in which fragments arrive. */
  97         bool zs:1;
  98
  99         /** Whether the set of fragments that pass the combined Z/S test is
 100          * guaranteed to be invariant under changes to the order in which
 101          * fragments arrive. */
 102         bool pass_set:1;
 103
 104         /** Whether the last fragment that passes the combined Z/S test at each
 105          * sample is guaranteed to be invariant under changes to the order in
 106          * which fragments arrive. */
 107         bool pass_last:1;
 108 };
 109
 110 struct si_state_dsa {
 111         struct si_pm4_state             pm4;
 112         struct si_dsa_stencil_ref_part  stencil_ref;
 113
 114         /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
 115         struct si_dsa_order_invariance  order_invariance[2];
 116
 117         ubyte                           alpha_func:3;
 118         bool                            depth_enabled:1;
 119         bool                            depth_write_enabled:1;
 120         bool                            stencil_enabled:1;
 121         bool                            stencil_write_enabled:1;
 122         bool                            db_can_write:1;
 123
 124 };
 125
 126 struct si_stencil_ref {
 127         struct r600_atom                atom;
 128         struct pipe_stencil_ref         state;
 129         struct si_dsa_stencil_ref_part  dsa_part;
 130 };
 131
 132 struct si_vertex_elements
 133 {
 134         uint32_t                        instance_divisors[SI_MAX_ATTRIBS];
 135         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 136         uint16_t                        src_offset[SI_MAX_ATTRIBS];
 137         uint8_t                         fix_fetch[SI_MAX_ATTRIBS];
 138         uint8_t                         format_size[SI_MAX_ATTRIBS];
 139         uint8_t                         vertex_buffer_index[SI_MAX_ATTRIBS];
 140
 141         uint8_t                         count;
 142         bool                            uses_instance_divisors;
 143
 144         uint16_t                        first_vb_use_mask;
 145         /* Vertex buffer descriptor list size aligned for optimal prefetch. */
 146         uint16_t                        desc_list_byte_size;
 147         uint16_t                        instance_divisor_is_one; /* bitmask of inputs */
 148         uint16_t                        instance_divisor_is_fetched;  /* bitmask of inputs */
 149 };
 150
 151 union si_state {
 152         struct {
 153                 struct si_state_blend           *blend;
 154                 struct si_state_rasterizer      *rasterizer;
 155                 struct si_state_dsa             *dsa;
 156                 struct si_pm4_state             *poly_offset;
 157                 struct si_pm4_state             *ls;
 158                 struct si_pm4_state             *hs;
 159                 struct si_pm4_state             *es;
 160                 struct si_pm4_state             *gs;
 161                 struct si_pm4_state             *vgt_shader_config;
 162                 struct si_pm4_state             *vs;
 163                 struct si_pm4_state             *ps;
 164         } named;
 165         struct si_pm4_state     *array[0];
 166 };
 167
 168 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
 169
 170 union si_state_atoms {
 171         struct {
 172                 /* The order matters. */
 173                 struct r600_atom *render_cond;
 174                 struct r600_atom *streamout_begin;
 175                 struct r600_atom *streamout_enable; /* must be after streamout_begin */
 176                 struct r600_atom *framebuffer;
 177                 struct r600_atom *msaa_sample_locs;
 178                 struct r600_atom *db_render_state;
 179                 struct r600_atom *dpbb_state;
 180                 struct r600_atom *msaa_config;
 181                 struct r600_atom *sample_mask;
 182                 struct r600_atom *cb_render_state;
 183                 struct r600_atom *blend_color;
 184                 struct r600_atom *clip_regs;
 185                 struct r600_atom *clip_state;
 186                 struct r600_atom *shader_pointers;
 187                 struct r600_atom *scissors;
 188                 struct r600_atom *viewports;
 189                 struct r600_atom *stencil_ref;
 190                 struct r600_atom *spi_map;
 191                 struct r600_atom *scratch_state;
 192         } s;
 193         struct r600_atom *array[0];
 194 };
 195
 196 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
 197
 198 struct si_shader_data {
 199         struct r600_atom        atom;
 200         uint32_t                sh_base[SI_NUM_SHADERS];
 201 };
 202
 203 /* Private read-write buffer slots. */
 204 enum {
 205         SI_ES_RING_ESGS,
 206         SI_GS_RING_ESGS,
 207
 208         SI_RING_GSVS,
 209
 210         SI_VS_STREAMOUT_BUF0,
 211         SI_VS_STREAMOUT_BUF1,
 212         SI_VS_STREAMOUT_BUF2,
 213         SI_VS_STREAMOUT_BUF3,
 214
 215         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 216         SI_VS_CONST_INSTANCE_DIVISORS,
 217         SI_VS_CONST_CLIP_PLANES,
 218         SI_PS_CONST_POLY_STIPPLE,
 219         SI_PS_CONST_SAMPLE_POSITIONS,
 220
 221         /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
 222         SI_PS_IMAGE_COLORBUF0,
 223         SI_PS_IMAGE_COLORBUF0_HI,
 224         SI_PS_IMAGE_COLORBUF0_FMASK,
 225         SI_PS_IMAGE_COLORBUF0_FMASK_HI,
 226
 227         SI_NUM_RW_BUFFERS,
 228 };
 229
 230 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 231  * are contiguous:
 232  *
 233  *  0 - rw buffers
 234  *  1 - vertex const and shader buffers
 235  *  2 - vertex samplers and images
 236  *  3 - fragment const and shader buffer
 237  *   ...
 238  *  11 - compute const and shader buffers
 239  *  12 - compute samplers and images
 240  */
 241 enum {
 242         SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 243         SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 244         SI_NUM_SHADER_DESCS,
 245 };
 246
 247 #define SI_DESCS_RW_BUFFERS            0
 248 #define SI_DESCS_FIRST_SHADER          1
 249 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 250                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 251 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 252                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 253
 254 #define SI_DESCS_SHADER_MASK(name) \
 255         u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
 256                           PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
 257                           SI_NUM_SHADER_DESCS)
 258
 259 /* This represents descriptors in memory, such as buffer resources,
 260  * image resources, and sampler states.
 261  */
 262 struct si_descriptors {
 263         /* The list of descriptors in malloc'd memory. */
 264         uint32_t *list;
 265         /* The list in mapped GPU memory. */
 266         uint32_t *gpu_list;
 267
 268         /* The buffer where the descriptors have been uploaded. */
 269         struct r600_resource *buffer;
 270         uint64_t gpu_address;
 271
 272         /* The maximum number of descriptors. */
 273         uint32_t num_elements;
 274
 275         /* Slots that are used by currently-bound shaders.
 276          * It determines which slots are uploaded.
 277          */
 278         uint32_t first_active_slot;
 279         uint32_t num_active_slots;
 280
 281         /* The SH register offset relative to USER_DATA*_0 where the pointer
 282          * to the descriptor array will be stored. */
 283         short shader_userdata_offset;
 284         /* The size of one descriptor. */
 285         ubyte element_dw_size;
 286         /* If there is only one slot enabled, bind it directly instead of
 287          * uploading descriptors. -1 if disabled. */
 288         signed char slot_index_to_bind_directly;
 289 };
 290
 291 struct si_buffer_resources {
 292         struct pipe_resource            **buffers; /* this has num_buffers elements */
 293
 294         enum radeon_bo_usage            shader_usage:4; /* READ, WRITE, or READWRITE */
 295         enum radeon_bo_usage            shader_usage_constbuf:4;
 296         enum radeon_bo_priority         priority:6;
 297         enum radeon_bo_priority         priority_constbuf:6;
 298
 299         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 300         unsigned                        enabled_mask;
 301 };
 302
 303 #define si_pm4_block_idx(member) \
 304         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 305
 306 #define si_pm4_state_changed(sctx, member) \
 307         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 308
 309 #define si_pm4_state_enabled_and_changed(sctx, member) \
 310         ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
 311
 312 #define si_pm4_bind_state(sctx, member, value) \
 313         do { \
 314                 (sctx)->queued.named.member = (value); \
 315                 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
 316         } while(0)
 317
 318 #define si_pm4_delete_state(sctx, member, value) \
 319         do { \
 320                 if ((sctx)->queued.named.member == (value)) { \
 321                         (sctx)->queued.named.member = NULL; \
 322                 } \
 323                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 324                                   si_pm4_block_idx(member)); \
 325         } while(0)
 326
 327 /* si_descriptors.c */
 328 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 329                                     struct r600_texture *tex,
 330                                     const struct legacy_surf_level *base_level_info,
 331                                     unsigned base_level, unsigned first_level,
 332                                     unsigned block_width, bool is_stencil,
 333                                     uint32_t *state);
 334 void si_update_ps_colorbuf0_slot(struct si_context *sctx);
 335 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
 336                                  uint slot, struct pipe_constant_buffer *cbuf);
 337 void si_get_shader_buffers(struct si_context *sctx,
 338                            enum pipe_shader_type shader,
 339                            uint start_slot, uint count,
 340                            struct pipe_shader_buffer *sbuf);
 341 void si_set_ring_buffer(struct si_context *sctx, uint slot,
 342                         struct pipe_resource *buffer,
 343                         unsigned stride, unsigned num_records,
 344                         bool add_tid, bool swizzle,
 345                         unsigned element_size, unsigned index_stride, uint64_t offset);
 346 void si_init_all_descriptors(struct si_context *sctx);
 347 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
 348 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 349 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 350 void si_release_all_descriptors(struct si_context *sctx);
 351 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 352 void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
 353 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 354                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 355 void si_update_all_texture_descriptors(struct si_context *sctx);
 356 void si_shader_change_notify(struct si_context *sctx);
 357 void si_update_needs_color_decompress_masks(struct si_context *sctx);
 358 void si_emit_graphics_shader_pointers(struct si_context *sctx,
 359                                       struct r600_atom *atom);
 360 void si_emit_compute_shader_pointers(struct si_context *sctx);
 361 void si_set_rw_buffer(struct si_context *sctx,
 362                       uint slot, const struct pipe_constant_buffer *input);
 363 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
 364                                uint64_t new_active_mask);
 365 void si_set_active_descriptors_for_shader(struct si_context *sctx,
 366                                           struct si_shader_selector *sel);
 367 bool si_bindless_descriptor_can_reclaim_slab(void *priv,
 368                                              struct pb_slab_entry *entry);
 369 struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
 370                                                   unsigned entry_size,
 371                                                   unsigned group_index);
 372 void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
 373 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
 374                       uint64_t old_va);
 375 /* si_state.c */
 376 struct si_shader_selector;
 377
 378 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
 379                   struct r600_atom **list_elem,
 380                   void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
 381 void si_init_state_functions(struct si_context *sctx);
 382 void si_init_screen_state_functions(struct si_screen *sscreen);
 383 void
 384 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 385                           enum pipe_format format,
 386                           unsigned offset, unsigned size,
 387                           uint32_t *state);
 388 void
 389 si_make_texture_descriptor(struct si_screen *screen,
 390                            struct r600_texture *tex,
 391                            bool sampler,
 392                            enum pipe_texture_target target,
 393                            enum pipe_format pipe_format,
 394                            const unsigned char state_swizzle[4],
 395                            unsigned first_level, unsigned last_level,
 396                            unsigned first_layer, unsigned last_layer,
 397                            unsigned width, unsigned height, unsigned depth,
 398                            uint32_t *state,
 399                            uint32_t *fmask_state);
 400 struct pipe_sampler_view *
 401 si_create_sampler_view_custom(struct pipe_context *ctx,
 402                               struct pipe_resource *texture,
 403                               const struct pipe_sampler_view *state,
 404                               unsigned width0, unsigned height0,
 405                               unsigned force_level);
 406 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
 407 void si_update_ps_iter_samples(struct si_context *sctx);
 408 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
 409 void si_set_occlusion_query_state(struct si_context *sctx,
 410                                   bool old_perfect_enable);
 411
 412 /* si_state_binning.c */
 413 void si_emit_dpbb_state(struct si_context *sctx, struct r600_atom *state);
 414
 415 /* si_state_shaders.c */
 416 bool si_update_shaders(struct si_context *sctx);
 417 void si_init_shader_functions(struct si_context *sctx);
 418 bool si_init_shader_cache(struct si_screen *sscreen);
 419 void si_destroy_shader_cache(struct si_screen *sscreen);
 420 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
 421                               uint32_t *const_and_shader_buffers,
 422                               uint64_t *samplers_and_images);
 423 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
 424                      unsigned num_layers);
 425
 426 /* si_state_draw.c */
 427 void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
 428 void si_emit_cache_flush(struct si_context *sctx);
 429 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 430 void si_draw_rectangle(struct blitter_context *blitter,
 431                        void *vertex_elements_cso,
 432                        blitter_get_vs_func get_vs,
 433                        int x1, int y1, int x2, int y2,
 434                        float depth, unsigned num_instances,
 435                        enum blitter_attrib_type type,
 436                        const union blitter_attrib *attrib);
 437 void si_trace_emit(struct si_context *sctx);
 438
 439 /* si_state_msaa.c */
 440 void si_init_msaa_functions(struct si_context *sctx);
 441 void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples);
 442
 443 /* si_state_streamout.c */
 444 void si_streamout_buffers_dirty(struct si_context *sctx);
 445 void si_emit_streamout_end(struct si_context *sctx);
 446 void si_update_prims_generated_query_state(struct si_context *sctx,
 447                                            unsigned type, int diff);
 448 void si_init_streamout_functions(struct si_context *sctx);
 449
 450
 451 static inline unsigned
 452 si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
 453 {
 454         if (stencil)
 455                 return rtex->surface.u.legacy.stencil_tiling_index[level];
 456         else
 457                 return rtex->surface.u.legacy.tiling_index[level];
 458 }
 459
 460 static inline unsigned si_get_constbuf_slot(unsigned slot)
 461 {
 462         /* Constant buffers are in slots [16..31], ascending */
 463         return SI_NUM_SHADER_BUFFERS + slot;
 464 }
 465
 466 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
 467 {
 468         /* shader buffers are in slots [15..0], descending */
 469         return SI_NUM_SHADER_BUFFERS - 1 - slot;
 470 }
 471
 472 static inline unsigned si_get_sampler_slot(unsigned slot)
 473 {
 474         /* samplers are in slots [8..39], ascending */
 475         return SI_NUM_IMAGES / 2 + slot;
 476 }
 477
 478 static inline unsigned si_get_image_slot(unsigned slot)
 479 {
 480         /* images are in slots [15..0] (sampler slots [7..0]), descending */
 481         return SI_NUM_IMAGES - 1 - slot;
 482 }
 483
 484 #endif