2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "pipebuffer/pb_slab.h"
31 #include "util/u_blitter.h"
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
36 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
37 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
38 #define SI_NUM_CONST_BUFFERS 16
39 #define SI_NUM_IMAGES 16
40 #define SI_NUM_SHADER_BUFFERS 16
44 struct si_shader_selector
;
48 /* This encapsulates a state or an operation which can emitted into the GPU
51 void (*emit
)(struct si_context
*ctx
, struct r600_atom
*state
);
55 struct si_state_blend
{
56 struct si_pm4_state pm4
;
57 uint32_t cb_target_mask
;
58 /* Set 0xf or 0x0 (4 bits) per render target if the following is
59 * true. ANDed with spi_shader_col_format.
61 unsigned cb_target_enabled_4bit
;
62 unsigned blend_enable_4bit
;
63 unsigned need_src_alpha_4bit
;
64 unsigned commutative_4bit
;
65 bool alpha_to_coverage
:1;
67 bool dual_src_blend
:1;
68 bool logicop_enable
:1;
71 struct si_state_rasterizer
{
72 struct si_pm4_state pm4
;
73 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
74 struct si_pm4_state
*pm4_poly_offset
;
75 unsigned pa_sc_line_stipple
;
76 unsigned pa_cl_clip_cntl
;
79 unsigned sprite_coord_enable
:8;
80 unsigned clip_plane_enable
:8;
83 unsigned multisample_enable
:1;
84 unsigned force_persample_interp
:1;
85 unsigned line_stipple_enable
:1;
86 unsigned poly_stipple_enable
:1;
87 unsigned line_smooth
:1;
88 unsigned poly_smooth
:1;
89 unsigned uses_poly_offset
:1;
90 unsigned clamp_fragment_color
:1;
91 unsigned clamp_vertex_color
:1;
92 unsigned rasterizer_discard
:1;
93 unsigned scissor_enable
:1;
94 unsigned clip_halfz
:1;
97 struct si_dsa_stencil_ref_part
{
102 struct si_dsa_order_invariance
{
103 /** Whether the final result in Z/S buffers is guaranteed to be
104 * invariant under changes to the order in which fragments arrive. */
107 /** Whether the set of fragments that pass the combined Z/S test is
108 * guaranteed to be invariant under changes to the order in which
109 * fragments arrive. */
112 /** Whether the last fragment that passes the combined Z/S test at each
113 * sample is guaranteed to be invariant under changes to the order in
114 * which fragments arrive. */
118 struct si_state_dsa
{
119 struct si_pm4_state pm4
;
120 struct si_dsa_stencil_ref_part stencil_ref
;
122 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
123 struct si_dsa_order_invariance order_invariance
[2];
126 bool depth_enabled
:1;
127 bool depth_write_enabled
:1;
128 bool stencil_enabled
:1;
129 bool stencil_write_enabled
:1;
134 struct si_stencil_ref
{
135 struct r600_atom atom
;
136 struct pipe_stencil_ref state
;
137 struct si_dsa_stencil_ref_part dsa_part
;
140 struct si_vertex_elements
142 uint32_t instance_divisors
[SI_MAX_ATTRIBS
];
143 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
144 uint16_t src_offset
[SI_MAX_ATTRIBS
];
145 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
146 uint8_t format_size
[SI_MAX_ATTRIBS
];
147 uint8_t vertex_buffer_index
[SI_MAX_ATTRIBS
];
150 bool uses_instance_divisors
;
152 uint16_t first_vb_use_mask
;
153 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
154 uint16_t desc_list_byte_size
;
155 uint16_t instance_divisor_is_one
; /* bitmask of inputs */
156 uint16_t instance_divisor_is_fetched
; /* bitmask of inputs */
161 struct si_state_blend
*blend
;
162 struct si_state_rasterizer
*rasterizer
;
163 struct si_state_dsa
*dsa
;
164 struct si_pm4_state
*poly_offset
;
165 struct si_pm4_state
*ls
;
166 struct si_pm4_state
*hs
;
167 struct si_pm4_state
*es
;
168 struct si_pm4_state
*gs
;
169 struct si_pm4_state
*vgt_shader_config
;
170 struct si_pm4_state
*vs
;
171 struct si_pm4_state
*ps
;
173 struct si_pm4_state
*array
[0];
176 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
178 union si_state_atoms
{
180 /* The order matters. */
181 struct r600_atom
*render_cond
;
182 struct r600_atom
*streamout_begin
;
183 struct r600_atom
*streamout_enable
; /* must be after streamout_begin */
184 struct r600_atom
*framebuffer
;
185 struct r600_atom
*msaa_sample_locs
;
186 struct r600_atom
*db_render_state
;
187 struct r600_atom
*dpbb_state
;
188 struct r600_atom
*msaa_config
;
189 struct r600_atom
*sample_mask
;
190 struct r600_atom
*cb_render_state
;
191 struct r600_atom
*blend_color
;
192 struct r600_atom
*clip_regs
;
193 struct r600_atom
*clip_state
;
194 struct r600_atom
*shader_pointers
;
195 struct r600_atom
*scissors
;
196 struct r600_atom
*viewports
;
197 struct r600_atom
*stencil_ref
;
198 struct r600_atom
*spi_map
;
199 struct r600_atom
*scratch_state
;
201 struct r600_atom
*array
[0];
204 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
206 struct si_shader_data
{
207 struct r600_atom atom
;
208 uint32_t sh_base
[SI_NUM_SHADERS
];
211 /* Private read-write buffer slots. */
218 SI_VS_STREAMOUT_BUF0
,
219 SI_VS_STREAMOUT_BUF1
,
220 SI_VS_STREAMOUT_BUF2
,
221 SI_VS_STREAMOUT_BUF3
,
223 SI_HS_CONST_DEFAULT_TESS_LEVELS
,
224 SI_VS_CONST_INSTANCE_DIVISORS
,
225 SI_VS_CONST_CLIP_PLANES
,
226 SI_PS_CONST_POLY_STIPPLE
,
227 SI_PS_CONST_SAMPLE_POSITIONS
,
229 /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
230 SI_PS_IMAGE_COLORBUF0
,
231 SI_PS_IMAGE_COLORBUF0_HI
,
232 SI_PS_IMAGE_COLORBUF0_FMASK
,
233 SI_PS_IMAGE_COLORBUF0_FMASK_HI
,
238 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
242 * 1 - vertex const and shader buffers
243 * 2 - vertex samplers and images
244 * 3 - fragment const and shader buffer
246 * 11 - compute const and shader buffers
247 * 12 - compute samplers and images
250 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
251 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
255 #define SI_DESCS_RW_BUFFERS 0
256 #define SI_DESCS_FIRST_SHADER 1
257 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
258 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
259 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
260 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
262 #define SI_DESCS_SHADER_MASK(name) \
263 u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
264 PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
267 /* This represents descriptors in memory, such as buffer resources,
268 * image resources, and sampler states.
270 struct si_descriptors
{
271 /* The list of descriptors in malloc'd memory. */
273 /* The list in mapped GPU memory. */
276 /* The buffer where the descriptors have been uploaded. */
277 struct r600_resource
*buffer
;
278 uint64_t gpu_address
;
280 /* The maximum number of descriptors. */
281 uint32_t num_elements
;
283 /* Slots that are used by currently-bound shaders.
284 * It determines which slots are uploaded.
286 uint32_t first_active_slot
;
287 uint32_t num_active_slots
;
289 /* The SH register offset relative to USER_DATA*_0 where the pointer
290 * to the descriptor array will be stored. */
291 short shader_userdata_offset
;
292 /* The size of one descriptor. */
293 ubyte element_dw_size
;
294 /* If there is only one slot enabled, bind it directly instead of
295 * uploading descriptors. -1 if disabled. */
296 signed char slot_index_to_bind_directly
;
299 struct si_buffer_resources
{
300 struct pipe_resource
**buffers
; /* this has num_buffers elements */
302 enum radeon_bo_usage shader_usage
:4; /* READ, WRITE, or READWRITE */
303 enum radeon_bo_usage shader_usage_constbuf
:4;
304 enum radeon_bo_priority priority
:6;
305 enum radeon_bo_priority priority_constbuf
:6;
307 /* The i-th bit is set if that element is enabled (non-NULL resource). */
308 unsigned enabled_mask
;
311 #define si_pm4_block_idx(member) \
312 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
314 #define si_pm4_state_changed(sctx, member) \
315 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
317 #define si_pm4_state_enabled_and_changed(sctx, member) \
318 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
320 #define si_pm4_bind_state(sctx, member, value) \
322 (sctx)->queued.named.member = (value); \
323 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
326 #define si_pm4_delete_state(sctx, member, value) \
328 if ((sctx)->queued.named.member == (value)) { \
329 (sctx)->queued.named.member = NULL; \
331 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
332 si_pm4_block_idx(member)); \
335 /* si_descriptors.c */
336 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
337 struct r600_texture
*tex
,
338 const struct legacy_surf_level
*base_level_info
,
339 unsigned base_level
, unsigned first_level
,
340 unsigned block_width
, bool is_stencil
,
342 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
);
343 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
344 uint slot
, struct pipe_constant_buffer
*cbuf
);
345 void si_get_shader_buffers(struct si_context
*sctx
,
346 enum pipe_shader_type shader
,
347 uint start_slot
, uint count
,
348 struct pipe_shader_buffer
*sbuf
);
349 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
350 struct pipe_resource
*buffer
,
351 unsigned stride
, unsigned num_records
,
352 bool add_tid
, bool swizzle
,
353 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
354 void si_init_all_descriptors(struct si_context
*sctx
);
355 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
);
356 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
);
357 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
);
358 void si_release_all_descriptors(struct si_context
*sctx
);
359 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
360 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
);
361 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
362 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
363 void si_update_all_texture_descriptors(struct si_context
*sctx
);
364 void si_shader_change_notify(struct si_context
*sctx
);
365 void si_update_needs_color_decompress_masks(struct si_context
*sctx
);
366 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
367 struct r600_atom
*atom
);
368 void si_emit_compute_shader_pointers(struct si_context
*sctx
);
369 void si_set_rw_buffer(struct si_context
*sctx
,
370 uint slot
, const struct pipe_constant_buffer
*input
);
371 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
372 uint64_t new_active_mask
);
373 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
374 struct si_shader_selector
*sel
);
375 bool si_bindless_descriptor_can_reclaim_slab(void *priv
,
376 struct pb_slab_entry
*entry
);
377 struct pb_slab
*si_bindless_descriptor_slab_alloc(void *priv
, unsigned heap
,
379 unsigned group_index
);
380 void si_bindless_descriptor_slab_free(void *priv
, struct pb_slab
*pslab
);
381 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
,
384 struct si_shader_selector
;
386 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
387 struct r600_atom
**list_elem
,
388 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
));
389 void si_init_state_functions(struct si_context
*sctx
);
390 void si_init_screen_state_functions(struct si_screen
*sscreen
);
392 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
393 enum pipe_format format
,
394 unsigned offset
, unsigned size
,
397 si_make_texture_descriptor(struct si_screen
*screen
,
398 struct r600_texture
*tex
,
400 enum pipe_texture_target target
,
401 enum pipe_format pipe_format
,
402 const unsigned char state_swizzle
[4],
403 unsigned first_level
, unsigned last_level
,
404 unsigned first_layer
, unsigned last_layer
,
405 unsigned width
, unsigned height
, unsigned depth
,
407 uint32_t *fmask_state
);
408 struct pipe_sampler_view
*
409 si_create_sampler_view_custom(struct pipe_context
*ctx
,
410 struct pipe_resource
*texture
,
411 const struct pipe_sampler_view
*state
,
412 unsigned width0
, unsigned height0
,
413 unsigned force_level
);
414 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
);
415 void si_update_ps_iter_samples(struct si_context
*sctx
);
416 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
);
417 void si_set_occlusion_query_state(struct si_context
*sctx
,
418 bool old_perfect_enable
);
420 /* si_state_binning.c */
421 void si_emit_dpbb_state(struct si_context
*sctx
, struct r600_atom
*state
);
423 /* si_state_shaders.c */
424 bool si_update_shaders(struct si_context
*sctx
);
425 void si_init_shader_functions(struct si_context
*sctx
);
426 bool si_init_shader_cache(struct si_screen
*sscreen
);
427 void si_destroy_shader_cache(struct si_screen
*sscreen
);
428 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
429 uint32_t *const_and_shader_buffers
,
430 uint64_t *samplers_and_images
);
431 void *si_get_blit_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
432 unsigned num_layers
);
434 /* si_state_draw.c */
435 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
);
436 void si_emit_cache_flush(struct si_context
*sctx
);
437 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
);
438 void si_draw_rectangle(struct blitter_context
*blitter
,
439 void *vertex_elements_cso
,
440 blitter_get_vs_func get_vs
,
441 int x1
, int y1
, int x2
, int y2
,
442 float depth
, unsigned num_instances
,
443 enum blitter_attrib_type type
,
444 const union blitter_attrib
*attrib
);
445 void si_trace_emit(struct si_context
*sctx
);
447 /* si_state_msaa.c */
448 void si_init_msaa_functions(struct si_context
*sctx
);
449 void si_emit_sample_locations(struct radeon_winsys_cs
*cs
, int nr_samples
);
451 /* si_state_streamout.c */
452 void si_streamout_buffers_dirty(struct si_context
*sctx
);
453 void si_emit_streamout_end(struct si_context
*sctx
);
454 void si_update_prims_generated_query_state(struct si_context
*sctx
,
455 unsigned type
, int diff
);
456 void si_init_streamout_functions(struct si_context
*sctx
);
459 static inline unsigned si_get_constbuf_slot(unsigned slot
)
461 /* Constant buffers are in slots [16..31], ascending */
462 return SI_NUM_SHADER_BUFFERS
+ slot
;
465 static inline unsigned si_get_shaderbuf_slot(unsigned slot
)
467 /* shader buffers are in slots [15..0], descending */
468 return SI_NUM_SHADER_BUFFERS
- 1 - slot
;
471 static inline unsigned si_get_sampler_slot(unsigned slot
)
473 /* samplers are in slots [8..39], ascending */
474 return SI_NUM_IMAGES
/ 2 + slot
;
477 static inline unsigned si_get_image_slot(unsigned slot
)
479 /* images are in slots [15..0] (sampler slots [7..0]), descending */
480 return SI_NUM_IMAGES
- 1 - slot
;