2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "pipebuffer/pb_slab.h"
31 #include "util/u_blitter.h"
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
36 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
37 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
38 #define SI_NUM_CONST_BUFFERS 16
39 #define SI_NUM_IMAGES 16
40 #define SI_NUM_SHADER_BUFFERS 16
44 struct si_shader_selector
;
48 /* State atoms are callbacks which write a sequence of packets into a GPU
49 * command buffer (AKA indirect buffer, AKA IB, AKA command stream, AKA CS).
52 void (*emit
)(struct si_context
*ctx
);
55 struct si_state_blend
{
56 struct si_pm4_state pm4
;
57 uint32_t cb_target_mask
;
58 /* Set 0xf or 0x0 (4 bits) per render target if the following is
59 * true. ANDed with spi_shader_col_format.
61 unsigned cb_target_enabled_4bit
;
62 unsigned blend_enable_4bit
;
63 unsigned need_src_alpha_4bit
;
64 unsigned commutative_4bit
;
65 bool alpha_to_coverage
:1;
67 bool dual_src_blend
:1;
68 bool logicop_enable
:1;
71 struct si_state_rasterizer
{
72 struct si_pm4_state pm4
;
73 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
74 struct si_pm4_state
*pm4_poly_offset
;
75 unsigned pa_sc_line_stipple
;
76 unsigned pa_cl_clip_cntl
;
79 unsigned sprite_coord_enable
:8;
80 unsigned clip_plane_enable
:8;
83 unsigned multisample_enable
:1;
84 unsigned force_persample_interp
:1;
85 unsigned line_stipple_enable
:1;
86 unsigned poly_stipple_enable
:1;
87 unsigned line_smooth
:1;
88 unsigned poly_smooth
:1;
89 unsigned uses_poly_offset
:1;
90 unsigned clamp_fragment_color
:1;
91 unsigned clamp_vertex_color
:1;
92 unsigned rasterizer_discard
:1;
93 unsigned scissor_enable
:1;
94 unsigned clip_halfz
:1;
97 struct si_dsa_stencil_ref_part
{
102 struct si_dsa_order_invariance
{
103 /** Whether the final result in Z/S buffers is guaranteed to be
104 * invariant under changes to the order in which fragments arrive. */
107 /** Whether the set of fragments that pass the combined Z/S test is
108 * guaranteed to be invariant under changes to the order in which
109 * fragments arrive. */
112 /** Whether the last fragment that passes the combined Z/S test at each
113 * sample is guaranteed to be invariant under changes to the order in
114 * which fragments arrive. */
118 struct si_state_dsa
{
119 struct si_pm4_state pm4
;
120 struct si_dsa_stencil_ref_part stencil_ref
;
122 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
123 struct si_dsa_order_invariance order_invariance
[2];
126 bool depth_enabled
:1;
127 bool depth_write_enabled
:1;
128 bool stencil_enabled
:1;
129 bool stencil_write_enabled
:1;
134 struct si_stencil_ref
{
135 struct pipe_stencil_ref state
;
136 struct si_dsa_stencil_ref_part dsa_part
;
139 struct si_vertex_elements
141 uint32_t instance_divisors
[SI_MAX_ATTRIBS
];
142 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
143 uint16_t src_offset
[SI_MAX_ATTRIBS
];
144 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
145 uint8_t format_size
[SI_MAX_ATTRIBS
];
146 uint8_t vertex_buffer_index
[SI_MAX_ATTRIBS
];
149 bool uses_instance_divisors
;
151 uint16_t first_vb_use_mask
;
152 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
153 uint16_t desc_list_byte_size
;
154 uint16_t instance_divisor_is_one
; /* bitmask of inputs */
155 uint16_t instance_divisor_is_fetched
; /* bitmask of inputs */
160 struct si_state_blend
*blend
;
161 struct si_state_rasterizer
*rasterizer
;
162 struct si_state_dsa
*dsa
;
163 struct si_pm4_state
*poly_offset
;
164 struct si_pm4_state
*ls
;
165 struct si_pm4_state
*hs
;
166 struct si_pm4_state
*es
;
167 struct si_pm4_state
*gs
;
168 struct si_pm4_state
*vgt_shader_config
;
169 struct si_pm4_state
*vs
;
170 struct si_pm4_state
*ps
;
172 struct si_pm4_state
*array
[0];
175 #define SI_STATE_IDX(name) \
176 (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
177 #define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name))
178 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
180 static inline unsigned si_states_that_roll_context(void)
182 return (SI_STATE_BIT(blend
) |
183 SI_STATE_BIT(rasterizer
) |
185 SI_STATE_BIT(poly_offset
) |
188 SI_STATE_BIT(vgt_shader_config
) |
193 union si_state_atoms
{
195 /* The order matters. */
196 struct si_atom render_cond
;
197 struct si_atom streamout_begin
;
198 struct si_atom streamout_enable
; /* must be after streamout_begin */
199 struct si_atom framebuffer
;
200 struct si_atom msaa_sample_locs
;
201 struct si_atom db_render_state
;
202 struct si_atom dpbb_state
;
203 struct si_atom msaa_config
;
204 struct si_atom sample_mask
;
205 struct si_atom cb_render_state
;
206 struct si_atom blend_color
;
207 struct si_atom clip_regs
;
208 struct si_atom clip_state
;
209 struct si_atom shader_pointers
;
210 struct si_atom guardband
;
211 struct si_atom scissors
;
212 struct si_atom viewports
;
213 struct si_atom stencil_ref
;
214 struct si_atom spi_map
;
215 struct si_atom scratch_state
;
216 struct si_atom window_rectangles
;
218 struct si_atom array
[0];
221 #define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / \
222 sizeof(struct si_atom)))
223 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct si_atom*))
225 static inline unsigned si_atoms_that_roll_context(void)
227 return (SI_ATOM_BIT(streamout_begin
) |
228 SI_ATOM_BIT(streamout_enable
) |
229 SI_ATOM_BIT(framebuffer
) |
230 SI_ATOM_BIT(msaa_sample_locs
) |
231 SI_ATOM_BIT(db_render_state
) |
232 SI_ATOM_BIT(dpbb_state
) |
233 SI_ATOM_BIT(msaa_config
) |
234 SI_ATOM_BIT(sample_mask
) |
235 SI_ATOM_BIT(cb_render_state
) |
236 SI_ATOM_BIT(blend_color
) |
237 SI_ATOM_BIT(clip_regs
) |
238 SI_ATOM_BIT(clip_state
) |
239 SI_ATOM_BIT(guardband
) |
240 SI_ATOM_BIT(scissors
) |
241 SI_ATOM_BIT(viewports
) |
242 SI_ATOM_BIT(stencil_ref
) |
243 SI_ATOM_BIT(spi_map
) |
244 SI_ATOM_BIT(scratch_state
));
247 struct si_shader_data
{
248 uint32_t sh_base
[SI_NUM_SHADERS
];
251 /* The list of registers whose emitted values are remembered by si_context. */
252 enum si_tracked_reg
{
253 SI_TRACKED_DB_RENDER_CONTROL
, /* 2 consecutive registers */
254 SI_TRACKED_DB_COUNT_CONTROL
,
256 SI_TRACKED_DB_RENDER_OVERRIDE2
,
257 SI_TRACKED_DB_SHADER_CONTROL
,
259 SI_TRACKED_CB_TARGET_MASK
,
260 SI_TRACKED_CB_DCC_CONTROL
,
262 SI_TRACKED_SX_PS_DOWNCONVERT
, /* 3 consecutive registers */
263 SI_TRACKED_SX_BLEND_OPT_EPSILON
,
264 SI_TRACKED_SX_BLEND_OPT_CONTROL
,
266 SI_TRACKED_PA_SC_LINE_CNTL
, /* 2 consecutive registers */
267 SI_TRACKED_PA_SC_AA_CONFIG
,
270 SI_TRACKED_PA_SC_MODE_CNTL_1
,
272 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
274 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
275 SI_TRACKED_PA_CL_CLIP_CNTL
,
277 SI_TRACKED_PA_SC_BINNER_CNTL_0
,
278 SI_TRACKED_DB_DFSM_CONTROL
,
280 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ
, /* 4 consecutive registers */
281 SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ
,
282 SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ
,
283 SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ
,
285 SI_TRACKED_PA_SC_CLIPRECT_RULE
,
290 struct si_tracked_regs
{
292 uint32_t reg_value
[SI_NUM_TRACKED_REGS
];
293 uint32_t spi_ps_input_cntl
[32];
296 /* Private read-write buffer slots. */
303 SI_VS_STREAMOUT_BUF0
,
304 SI_VS_STREAMOUT_BUF1
,
305 SI_VS_STREAMOUT_BUF2
,
306 SI_VS_STREAMOUT_BUF3
,
308 SI_HS_CONST_DEFAULT_TESS_LEVELS
,
309 SI_VS_CONST_INSTANCE_DIVISORS
,
310 SI_VS_CONST_CLIP_PLANES
,
311 SI_PS_CONST_POLY_STIPPLE
,
312 SI_PS_CONST_SAMPLE_POSITIONS
,
314 /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
315 SI_PS_IMAGE_COLORBUF0
,
316 SI_PS_IMAGE_COLORBUF0_HI
,
317 SI_PS_IMAGE_COLORBUF0_FMASK
,
318 SI_PS_IMAGE_COLORBUF0_FMASK_HI
,
323 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
327 * 1 - vertex const and shader buffers
328 * 2 - vertex samplers and images
329 * 3 - fragment const and shader buffer
331 * 11 - compute const and shader buffers
332 * 12 - compute samplers and images
335 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
336 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
340 #define SI_DESCS_RW_BUFFERS 0
341 #define SI_DESCS_FIRST_SHADER 1
342 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
343 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
344 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
345 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
347 #define SI_DESCS_SHADER_MASK(name) \
348 u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
349 PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
352 /* This represents descriptors in memory, such as buffer resources,
353 * image resources, and sampler states.
355 struct si_descriptors
{
356 /* The list of descriptors in malloc'd memory. */
358 /* The list in mapped GPU memory. */
361 /* The buffer where the descriptors have been uploaded. */
362 struct r600_resource
*buffer
;
363 uint64_t gpu_address
;
365 /* The maximum number of descriptors. */
366 uint32_t num_elements
;
368 /* Slots that are used by currently-bound shaders.
369 * It determines which slots are uploaded.
371 uint32_t first_active_slot
;
372 uint32_t num_active_slots
;
374 /* The SH register offset relative to USER_DATA*_0 where the pointer
375 * to the descriptor array will be stored. */
376 short shader_userdata_offset
;
377 /* The size of one descriptor. */
378 ubyte element_dw_size
;
379 /* If there is only one slot enabled, bind it directly instead of
380 * uploading descriptors. -1 if disabled. */
381 signed char slot_index_to_bind_directly
;
384 struct si_buffer_resources
{
385 struct pipe_resource
**buffers
; /* this has num_buffers elements */
387 enum radeon_bo_usage shader_usage
:4; /* READ, WRITE, or READWRITE */
388 enum radeon_bo_usage shader_usage_constbuf
:4;
389 enum radeon_bo_priority priority
:6;
390 enum radeon_bo_priority priority_constbuf
:6;
392 /* The i-th bit is set if that element is enabled (non-NULL resource). */
393 unsigned enabled_mask
;
396 #define si_pm4_state_changed(sctx, member) \
397 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
399 #define si_pm4_state_enabled_and_changed(sctx, member) \
400 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
402 #define si_pm4_bind_state(sctx, member, value) \
404 (sctx)->queued.named.member = (value); \
405 (sctx)->dirty_states |= SI_STATE_BIT(member); \
408 #define si_pm4_delete_state(sctx, member, value) \
410 if ((sctx)->queued.named.member == (value)) { \
411 (sctx)->queued.named.member = NULL; \
413 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
414 SI_STATE_IDX(member)); \
417 /* si_descriptors.c */
418 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
419 struct si_texture
*tex
,
420 const struct legacy_surf_level
*base_level_info
,
421 unsigned base_level
, unsigned first_level
,
422 unsigned block_width
, bool is_stencil
,
424 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
);
425 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
426 uint slot
, struct pipe_constant_buffer
*cbuf
);
427 void si_get_shader_buffers(struct si_context
*sctx
,
428 enum pipe_shader_type shader
,
429 uint start_slot
, uint count
,
430 struct pipe_shader_buffer
*sbuf
);
431 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
432 struct pipe_resource
*buffer
,
433 unsigned stride
, unsigned num_records
,
434 bool add_tid
, bool swizzle
,
435 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
436 void si_init_all_descriptors(struct si_context
*sctx
);
437 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
);
438 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
);
439 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
);
440 void si_release_all_descriptors(struct si_context
*sctx
);
441 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
442 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
);
443 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
444 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
445 void si_update_all_texture_descriptors(struct si_context
*sctx
);
446 void si_shader_change_notify(struct si_context
*sctx
);
447 void si_update_needs_color_decompress_masks(struct si_context
*sctx
);
448 void si_emit_graphics_shader_pointers(struct si_context
*sctx
);
449 void si_emit_compute_shader_pointers(struct si_context
*sctx
);
450 void si_set_rw_buffer(struct si_context
*sctx
,
451 uint slot
, const struct pipe_constant_buffer
*input
);
452 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
453 uint64_t new_active_mask
);
454 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
455 struct si_shader_selector
*sel
);
456 bool si_bindless_descriptor_can_reclaim_slab(void *priv
,
457 struct pb_slab_entry
*entry
);
458 struct pb_slab
*si_bindless_descriptor_slab_alloc(void *priv
, unsigned heap
,
460 unsigned group_index
);
461 void si_bindless_descriptor_slab_free(void *priv
, struct pb_slab
*pslab
);
462 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
,
465 void si_init_state_functions(struct si_context
*sctx
);
466 void si_init_screen_state_functions(struct si_screen
*sscreen
);
468 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
469 enum pipe_format format
,
470 unsigned offset
, unsigned size
,
473 si_make_texture_descriptor(struct si_screen
*screen
,
474 struct si_texture
*tex
,
476 enum pipe_texture_target target
,
477 enum pipe_format pipe_format
,
478 const unsigned char state_swizzle
[4],
479 unsigned first_level
, unsigned last_level
,
480 unsigned first_layer
, unsigned last_layer
,
481 unsigned width
, unsigned height
, unsigned depth
,
483 uint32_t *fmask_state
);
484 struct pipe_sampler_view
*
485 si_create_sampler_view_custom(struct pipe_context
*ctx
,
486 struct pipe_resource
*texture
,
487 const struct pipe_sampler_view
*state
,
488 unsigned width0
, unsigned height0
,
489 unsigned force_level
);
490 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
);
491 void si_update_ps_iter_samples(struct si_context
*sctx
);
492 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
);
493 void si_set_occlusion_query_state(struct si_context
*sctx
,
494 bool old_perfect_enable
);
496 /* si_state_binning.c */
497 void si_emit_dpbb_state(struct si_context
*sctx
);
499 /* si_state_shaders.c */
500 void *si_get_ir_binary(struct si_shader_selector
*sel
);
501 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
502 struct si_shader
*shader
);
503 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
504 struct si_shader
*shader
,
505 bool insert_into_disk_cache
);
506 bool si_update_shaders(struct si_context
*sctx
);
507 void si_init_shader_functions(struct si_context
*sctx
);
508 bool si_init_shader_cache(struct si_screen
*sscreen
);
509 void si_destroy_shader_cache(struct si_screen
*sscreen
);
510 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
511 struct util_queue_fence
*ready_fence
,
512 struct si_compiler_ctx_state
*compiler_ctx_state
,
513 void *job
, util_queue_execute_func execute
);
514 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
515 uint32_t *const_and_shader_buffers
,
516 uint64_t *samplers_and_images
);
518 /* si_state_draw.c */
519 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
);
520 void si_emit_cache_flush(struct si_context
*sctx
);
521 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
);
522 void si_draw_rectangle(struct blitter_context
*blitter
,
523 void *vertex_elements_cso
,
524 blitter_get_vs_func get_vs
,
525 int x1
, int y1
, int x2
, int y2
,
526 float depth
, unsigned num_instances
,
527 enum blitter_attrib_type type
,
528 const union blitter_attrib
*attrib
);
529 void si_trace_emit(struct si_context
*sctx
);
531 /* si_state_msaa.c */
532 void si_init_msaa_functions(struct si_context
*sctx
);
533 void si_emit_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
535 /* si_state_streamout.c */
536 void si_streamout_buffers_dirty(struct si_context
*sctx
);
537 void si_emit_streamout_end(struct si_context
*sctx
);
538 void si_update_prims_generated_query_state(struct si_context
*sctx
,
539 unsigned type
, int diff
);
540 void si_init_streamout_functions(struct si_context
*sctx
);
543 static inline unsigned si_get_constbuf_slot(unsigned slot
)
545 /* Constant buffers are in slots [16..31], ascending */
546 return SI_NUM_SHADER_BUFFERS
+ slot
;
549 static inline unsigned si_get_shaderbuf_slot(unsigned slot
)
551 /* shader buffers are in slots [15..0], descending */
552 return SI_NUM_SHADER_BUFFERS
- 1 - slot
;
555 static inline unsigned si_get_sampler_slot(unsigned slot
)
557 /* samplers are in slots [8..39], ascending */
558 return SI_NUM_IMAGES
/ 2 + slot
;
561 static inline unsigned si_get_image_slot(unsigned slot
)
563 /* images are in slots [15..0] (sampler slots [7..0]), descending */
564 return SI_NUM_IMAGES
- 1 - slot
;