src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef SI_STATE_H
  26 #define SI_STATE_H
  27
  28 #include "si_pm4.h"
  29
  30 #include "pipebuffer/pb_slab.h"
  31 #include "util/u_blitter.h"
  32
  33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  35
  36 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  37 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  38 #define SI_NUM_CONST_BUFFERS            16
  39 #define SI_NUM_IMAGES                   16
  40 #define SI_NUM_SHADER_BUFFERS           16
  41
  42 struct si_screen;
  43 struct si_shader;
  44 struct si_shader_selector;
  45 struct si_texture;
  46 struct si_qbo_state;
  47
  48 struct si_state_blend {
  49         struct si_pm4_state     pm4;
  50         uint32_t                cb_target_mask;
  51         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  52          * true. ANDed with spi_shader_col_format.
  53          */
  54         unsigned                cb_target_enabled_4bit;
  55         unsigned                blend_enable_4bit;
  56         unsigned                need_src_alpha_4bit;
  57         unsigned                commutative_4bit;
  58         bool                    alpha_to_coverage:1;
  59         bool                    alpha_to_one:1;
  60         bool                    dual_src_blend:1;
  61         bool                    logicop_enable:1;
  62 };
  63
  64 struct si_state_rasterizer {
  65         struct si_pm4_state     pm4;
  66         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  67         struct si_pm4_state     *pm4_poly_offset;
  68         unsigned                pa_sc_line_stipple;
  69         unsigned                pa_cl_clip_cntl;
  70         float                   line_width;
  71         float                   max_point_size;
  72         unsigned                sprite_coord_enable:8;
  73         unsigned                clip_plane_enable:8;
  74         unsigned                half_pixel_center:1;
  75         unsigned                flatshade:1;
  76         unsigned                two_side:1;
  77         unsigned                multisample_enable:1;
  78         unsigned                force_persample_interp:1;
  79         unsigned                line_stipple_enable:1;
  80         unsigned                poly_stipple_enable:1;
  81         unsigned                line_smooth:1;
  82         unsigned                poly_smooth:1;
  83         unsigned                uses_poly_offset:1;
  84         unsigned                clamp_fragment_color:1;
  85         unsigned                clamp_vertex_color:1;
  86         unsigned                rasterizer_discard:1;
  87         unsigned                scissor_enable:1;
  88         unsigned                clip_halfz:1;
  89 };
  90
  91 struct si_dsa_stencil_ref_part {
  92         uint8_t                 valuemask[2];
  93         uint8_t                 writemask[2];
  94 };
  95
  96 struct si_dsa_order_invariance {
  97         /** Whether the final result in Z/S buffers is guaranteed to be
  98          * invariant under changes to the order in which fragments arrive. */
  99         bool zs:1;
 100
 101         /** Whether the set of fragments that pass the combined Z/S test is
 102          * guaranteed to be invariant under changes to the order in which
 103          * fragments arrive. */
 104         bool pass_set:1;
 105
 106         /** Whether the last fragment that passes the combined Z/S test at each
 107          * sample is guaranteed to be invariant under changes to the order in
 108          * which fragments arrive. */
 109         bool pass_last:1;
 110 };
 111
 112 struct si_state_dsa {
 113         struct si_pm4_state             pm4;
 114         struct si_dsa_stencil_ref_part  stencil_ref;
 115
 116         /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
 117         struct si_dsa_order_invariance  order_invariance[2];
 118
 119         ubyte                           alpha_func:3;
 120         bool                            depth_enabled:1;
 121         bool                            depth_write_enabled:1;
 122         bool                            stencil_enabled:1;
 123         bool                            stencil_write_enabled:1;
 124         bool                            db_can_write:1;
 125
 126 };
 127
 128 struct si_stencil_ref {
 129         struct pipe_stencil_ref         state;
 130         struct si_dsa_stencil_ref_part  dsa_part;
 131 };
 132
 133 struct si_vertex_elements
 134 {
 135         struct r600_resource            *instance_divisor_factor_buffer;
 136         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 137         uint16_t                        src_offset[SI_MAX_ATTRIBS];
 138         uint8_t                         fix_fetch[SI_MAX_ATTRIBS];
 139         uint8_t                         format_size[SI_MAX_ATTRIBS];
 140         uint8_t                         vertex_buffer_index[SI_MAX_ATTRIBS];
 141
 142         uint8_t                         count;
 143         bool                            uses_instance_divisors;
 144
 145         uint16_t                        first_vb_use_mask;
 146         /* Vertex buffer descriptor list size aligned for optimal prefetch. */
 147         uint16_t                        desc_list_byte_size;
 148         uint16_t                        instance_divisor_is_one; /* bitmask of inputs */
 149         uint16_t                        instance_divisor_is_fetched;  /* bitmask of inputs */
 150 };
 151
 152 union si_state {
 153         struct {
 154                 struct si_state_blend           *blend;
 155                 struct si_state_rasterizer      *rasterizer;
 156                 struct si_state_dsa             *dsa;
 157                 struct si_pm4_state             *poly_offset;
 158                 struct si_pm4_state             *ls;
 159                 struct si_pm4_state             *hs;
 160                 struct si_pm4_state             *es;
 161                 struct si_pm4_state             *gs;
 162                 struct si_pm4_state             *vgt_shader_config;
 163                 struct si_pm4_state             *vs;
 164                 struct si_pm4_state             *ps;
 165         } named;
 166         struct si_pm4_state     *array[0];
 167 };
 168
 169 #define SI_STATE_IDX(name) \
 170         (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
 171 #define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name))
 172 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
 173
 174 static inline unsigned si_states_that_always_roll_context(void)
 175 {
 176         return (SI_STATE_BIT(blend) |
 177                 SI_STATE_BIT(rasterizer) |
 178                 SI_STATE_BIT(dsa) |
 179                 SI_STATE_BIT(poly_offset) |
 180                 SI_STATE_BIT(vgt_shader_config));
 181 }
 182
 183 union si_state_atoms {
 184         struct {
 185                 /* The order matters. */
 186                 struct si_atom render_cond;
 187                 struct si_atom streamout_begin;
 188                 struct si_atom streamout_enable; /* must be after streamout_begin */
 189                 struct si_atom framebuffer;
 190                 struct si_atom msaa_sample_locs;
 191                 struct si_atom db_render_state;
 192                 struct si_atom dpbb_state;
 193                 struct si_atom msaa_config;
 194                 struct si_atom sample_mask;
 195                 struct si_atom cb_render_state;
 196                 struct si_atom blend_color;
 197                 struct si_atom clip_regs;
 198                 struct si_atom clip_state;
 199                 struct si_atom shader_pointers;
 200                 struct si_atom guardband;
 201                 struct si_atom scissors;
 202                 struct si_atom viewports;
 203                 struct si_atom stencil_ref;
 204                 struct si_atom spi_map;
 205                 struct si_atom scratch_state;
 206                 struct si_atom window_rectangles;
 207         } s;
 208         struct si_atom array[0];
 209 };
 210
 211 #define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / \
 212                                  sizeof(struct si_atom)))
 213 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct si_atom*))
 214
 215 static inline unsigned si_atoms_that_always_roll_context(void)
 216 {
 217         return (SI_ATOM_BIT(streamout_begin) |
 218                 SI_ATOM_BIT(streamout_enable) |
 219                 SI_ATOM_BIT(framebuffer) |
 220                 SI_ATOM_BIT(msaa_sample_locs) |
 221                 SI_ATOM_BIT(sample_mask) |
 222                 SI_ATOM_BIT(blend_color) |
 223                 SI_ATOM_BIT(clip_state) |
 224                 SI_ATOM_BIT(scissors) |
 225                 SI_ATOM_BIT(viewports) |
 226                 SI_ATOM_BIT(stencil_ref) |
 227                 SI_ATOM_BIT(scratch_state));
 228 }
 229
 230 struct si_shader_data {
 231         uint32_t                sh_base[SI_NUM_SHADERS];
 232 };
 233
 234 /* The list of registers whose emitted values are remembered by si_context. */
 235 enum si_tracked_reg {
 236         SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */
 237         SI_TRACKED_DB_COUNT_CONTROL,
 238
 239         SI_TRACKED_DB_RENDER_OVERRIDE2,
 240         SI_TRACKED_DB_SHADER_CONTROL,
 241
 242         SI_TRACKED_CB_TARGET_MASK,
 243         SI_TRACKED_CB_DCC_CONTROL,
 244
 245         SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */
 246         SI_TRACKED_SX_BLEND_OPT_EPSILON,
 247         SI_TRACKED_SX_BLEND_OPT_CONTROL,
 248
 249         SI_TRACKED_PA_SC_LINE_CNTL, /* 2 consecutive registers */
 250         SI_TRACKED_PA_SC_AA_CONFIG,
 251
 252         SI_TRACKED_DB_EQAA,
 253         SI_TRACKED_PA_SC_MODE_CNTL_1,
 254
 255         SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
 256         SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
 257
 258         SI_TRACKED_PA_CL_VS_OUT_CNTL,
 259         SI_TRACKED_PA_CL_CLIP_CNTL,
 260
 261         SI_TRACKED_PA_SC_BINNER_CNTL_0,
 262         SI_TRACKED_DB_DFSM_CONTROL,
 263
 264         SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */
 265         SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
 266         SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ,
 267         SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ,
 268
 269         SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
 270         SI_TRACKED_PA_SU_VTX_CNTL,
 271
 272         SI_TRACKED_PA_SC_CLIPRECT_RULE,
 273
 274         SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
 275
 276         SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 4 consecutive registers */
 277         SI_TRACKED_VGT_GSVS_RING_OFFSET_2,
 278         SI_TRACKED_VGT_GSVS_RING_OFFSET_3,
 279         SI_TRACKED_VGT_GS_OUT_PRIM_TYPE,
 280
 281         SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
 282         SI_TRACKED_VGT_GS_MAX_VERT_OUT,
 283
 284         SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* 4 consecutive registers */
 285         SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1,
 286         SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2,
 287         SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3,
 288
 289         SI_TRACKED_VGT_GS_INSTANCE_CNT,
 290         SI_TRACKED_VGT_GS_ONCHIP_CNTL,
 291         SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
 292         SI_TRACKED_VGT_GS_MODE,
 293         SI_TRACKED_VGT_PRIMITIVEID_EN,
 294         SI_TRACKED_VGT_REUSE_OFF,
 295         SI_TRACKED_SPI_VS_OUT_CONFIG,
 296         SI_TRACKED_SPI_SHADER_POS_FORMAT,
 297         SI_TRACKED_PA_CL_VTE_CNTL,
 298
 299         SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */
 300         SI_TRACKED_SPI_PS_INPUT_ADDR,
 301
 302         SI_TRACKED_SPI_BARYC_CNTL,
 303         SI_TRACKED_SPI_PS_IN_CONTROL,
 304
 305         SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */
 306         SI_TRACKED_SPI_SHADER_COL_FORMAT,
 307
 308         SI_TRACKED_CB_SHADER_MASK,
 309         SI_TRACKED_VGT_TF_PARAM,
 310         SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
 311
 312         SI_NUM_TRACKED_REGS,
 313 };
 314
 315 struct si_tracked_regs {
 316         uint64_t                reg_saved;
 317         uint32_t                reg_value[SI_NUM_TRACKED_REGS];
 318         uint32_t                spi_ps_input_cntl[32];
 319 };
 320
 321 /* Private read-write buffer slots. */
 322 enum {
 323         SI_ES_RING_ESGS,
 324         SI_GS_RING_ESGS,
 325
 326         SI_RING_GSVS,
 327
 328         SI_VS_STREAMOUT_BUF0,
 329         SI_VS_STREAMOUT_BUF1,
 330         SI_VS_STREAMOUT_BUF2,
 331         SI_VS_STREAMOUT_BUF3,
 332
 333         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 334         SI_VS_CONST_INSTANCE_DIVISORS,
 335         SI_VS_CONST_CLIP_PLANES,
 336         SI_PS_CONST_POLY_STIPPLE,
 337         SI_PS_CONST_SAMPLE_POSITIONS,
 338
 339         /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
 340         SI_PS_IMAGE_COLORBUF0,
 341         SI_PS_IMAGE_COLORBUF0_HI,
 342         SI_PS_IMAGE_COLORBUF0_FMASK,
 343         SI_PS_IMAGE_COLORBUF0_FMASK_HI,
 344
 345         SI_NUM_RW_BUFFERS,
 346 };
 347
 348 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 349  * are contiguous:
 350  *
 351  *  0 - rw buffers
 352  *  1 - vertex const and shader buffers
 353  *  2 - vertex samplers and images
 354  *  3 - fragment const and shader buffer
 355  *   ...
 356  *  11 - compute const and shader buffers
 357  *  12 - compute samplers and images
 358  */
 359 enum {
 360         SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 361         SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 362         SI_NUM_SHADER_DESCS,
 363 };
 364
 365 #define SI_DESCS_RW_BUFFERS            0
 366 #define SI_DESCS_FIRST_SHADER          1
 367 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 368                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 369 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 370                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 371
 372 #define SI_DESCS_SHADER_MASK(name) \
 373         u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
 374                           PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
 375                           SI_NUM_SHADER_DESCS)
 376
 377 /* This represents descriptors in memory, such as buffer resources,
 378  * image resources, and sampler states.
 379  */
 380 struct si_descriptors {
 381         /* The list of descriptors in malloc'd memory. */
 382         uint32_t *list;
 383         /* The list in mapped GPU memory. */
 384         uint32_t *gpu_list;
 385
 386         /* The buffer where the descriptors have been uploaded. */
 387         struct r600_resource *buffer;
 388         uint64_t gpu_address;
 389
 390         /* The maximum number of descriptors. */
 391         uint32_t num_elements;
 392
 393         /* Slots that are used by currently-bound shaders.
 394          * It determines which slots are uploaded.
 395          */
 396         uint32_t first_active_slot;
 397         uint32_t num_active_slots;
 398
 399         /* The SH register offset relative to USER_DATA*_0 where the pointer
 400          * to the descriptor array will be stored. */
 401         short shader_userdata_offset;
 402         /* The size of one descriptor. */
 403         ubyte element_dw_size;
 404         /* If there is only one slot enabled, bind it directly instead of
 405          * uploading descriptors. -1 if disabled. */
 406         signed char slot_index_to_bind_directly;
 407 };
 408
 409 struct si_buffer_resources {
 410         struct pipe_resource            **buffers; /* this has num_buffers elements */
 411
 412         enum radeon_bo_usage            shader_usage:4; /* READ, WRITE, or READWRITE */
 413         enum radeon_bo_usage            shader_usage_constbuf:4;
 414         enum radeon_bo_priority         priority:6;
 415         enum radeon_bo_priority         priority_constbuf:6;
 416
 417         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 418         unsigned                        enabled_mask;
 419 };
 420
 421 #define si_pm4_state_changed(sctx, member) \
 422         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 423
 424 #define si_pm4_state_enabled_and_changed(sctx, member) \
 425         ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
 426
 427 #define si_pm4_bind_state(sctx, member, value) \
 428         do { \
 429                 (sctx)->queued.named.member = (value); \
 430                 (sctx)->dirty_states |= SI_STATE_BIT(member); \
 431         } while(0)
 432
 433 #define si_pm4_delete_state(sctx, member, value) \
 434         do { \
 435                 if ((sctx)->queued.named.member == (value)) { \
 436                         (sctx)->queued.named.member = NULL; \
 437                 } \
 438                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 439                                   SI_STATE_IDX(member)); \
 440         } while(0)
 441
 442 /* si_descriptors.c */
 443 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 444                                     struct si_texture *tex,
 445                                     const struct legacy_surf_level *base_level_info,
 446                                     unsigned base_level, unsigned first_level,
 447                                     unsigned block_width, bool is_stencil,
 448                                     uint32_t *state);
 449 void si_update_ps_colorbuf0_slot(struct si_context *sctx);
 450 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
 451                                  uint slot, struct pipe_constant_buffer *cbuf);
 452 void si_get_shader_buffers(struct si_context *sctx,
 453                            enum pipe_shader_type shader,
 454                            uint start_slot, uint count,
 455                            struct pipe_shader_buffer *sbuf);
 456 void si_set_ring_buffer(struct si_context *sctx, uint slot,
 457                         struct pipe_resource *buffer,
 458                         unsigned stride, unsigned num_records,
 459                         bool add_tid, bool swizzle,
 460                         unsigned element_size, unsigned index_stride, uint64_t offset);
 461 void si_init_all_descriptors(struct si_context *sctx);
 462 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
 463 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 464 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 465 void si_release_all_descriptors(struct si_context *sctx);
 466 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 467 void si_all_resident_buffers_begin_new_cs(struct si_context *sctx);
 468 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 469                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 470 void si_update_all_texture_descriptors(struct si_context *sctx);
 471 void si_shader_change_notify(struct si_context *sctx);
 472 void si_update_needs_color_decompress_masks(struct si_context *sctx);
 473 void si_emit_graphics_shader_pointers(struct si_context *sctx);
 474 void si_emit_compute_shader_pointers(struct si_context *sctx);
 475 void si_set_rw_buffer(struct si_context *sctx,
 476                       uint slot, const struct pipe_constant_buffer *input);
 477 void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
 478                              const struct pipe_shader_buffer *sbuffer);
 479 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
 480                                uint64_t new_active_mask);
 481 void si_set_active_descriptors_for_shader(struct si_context *sctx,
 482                                           struct si_shader_selector *sel);
 483 bool si_bindless_descriptor_can_reclaim_slab(void *priv,
 484                                              struct pb_slab_entry *entry);
 485 struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
 486                                                   unsigned entry_size,
 487                                                   unsigned group_index);
 488 void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
 489 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
 490                       uint64_t old_va);
 491 /* si_state.c */
 492 void si_init_state_functions(struct si_context *sctx);
 493 void si_init_screen_state_functions(struct si_screen *sscreen);
 494 void
 495 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
 496                           enum pipe_format format,
 497                           unsigned offset, unsigned size,
 498                           uint32_t *state);
 499 void
 500 si_make_texture_descriptor(struct si_screen *screen,
 501                            struct si_texture *tex,
 502                            bool sampler,
 503                            enum pipe_texture_target target,
 504                            enum pipe_format pipe_format,
 505                            const unsigned char state_swizzle[4],
 506                            unsigned first_level, unsigned last_level,
 507                            unsigned first_layer, unsigned last_layer,
 508                            unsigned width, unsigned height, unsigned depth,
 509                            uint32_t *state,
 510                            uint32_t *fmask_state);
 511 struct pipe_sampler_view *
 512 si_create_sampler_view_custom(struct pipe_context *ctx,
 513                               struct pipe_resource *texture,
 514                               const struct pipe_sampler_view *state,
 515                               unsigned width0, unsigned height0,
 516                               unsigned force_level);
 517 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
 518 void si_update_ps_iter_samples(struct si_context *sctx);
 519 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
 520 void si_set_occlusion_query_state(struct si_context *sctx,
 521                                   bool old_perfect_enable);
 522
 523 /* si_state_binning.c */
 524 void si_emit_dpbb_state(struct si_context *sctx);
 525
 526 /* si_state_shaders.c */
 527 void *si_get_ir_binary(struct si_shader_selector *sel);
 528 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
 529                                  struct si_shader *shader);
 530 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
 531                                    struct si_shader *shader,
 532                                    bool insert_into_disk_cache);
 533 bool si_update_shaders(struct si_context *sctx);
 534 void si_init_shader_functions(struct si_context *sctx);
 535 bool si_init_shader_cache(struct si_screen *sscreen);
 536 void si_destroy_shader_cache(struct si_screen *sscreen);
 537 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
 538                                  struct util_queue_fence *ready_fence,
 539                                  struct si_compiler_ctx_state *compiler_ctx_state,
 540                                  void *job, util_queue_execute_func execute);
 541 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
 542                               uint32_t *const_and_shader_buffers,
 543                               uint64_t *samplers_and_images);
 544
 545 /* si_state_draw.c */
 546 void si_emit_cache_flush(struct si_context *sctx);
 547 void si_trace_emit(struct si_context *sctx);
 548 void si_init_draw_functions(struct si_context *sctx);
 549
 550 /* si_state_msaa.c */
 551 void si_init_msaa_functions(struct si_context *sctx);
 552 void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
 553
 554 /* si_state_streamout.c */
 555 void si_streamout_buffers_dirty(struct si_context *sctx);
 556 void si_emit_streamout_end(struct si_context *sctx);
 557 void si_update_prims_generated_query_state(struct si_context *sctx,
 558                                            unsigned type, int diff);
 559 void si_init_streamout_functions(struct si_context *sctx);
 560
 561
 562 static inline unsigned si_get_constbuf_slot(unsigned slot)
 563 {
 564         /* Constant buffers are in slots [16..31], ascending */
 565         return SI_NUM_SHADER_BUFFERS + slot;
 566 }
 567
 568 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
 569 {
 570         /* shader buffers are in slots [15..0], descending */
 571         return SI_NUM_SHADER_BUFFERS - 1 - slot;
 572 }
 573
 574 static inline unsigned si_get_sampler_slot(unsigned slot)
 575 {
 576         /* samplers are in slots [8..39], ascending */
 577         return SI_NUM_IMAGES / 2 + slot;
 578 }
 579
 580 static inline unsigned si_get_image_slot(unsigned slot)
 581 {
 582         /* images are in slots [15..0] (sampler slots [7..0]), descending */
 583         return SI_NUM_IMAGES - 1 - slot;
 584 }
 585
 586 #endif