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radeonsi/gfx10: export correct PrimitiveID from NGG vertex shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
187 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
188
189 if (sctx->chip_class == GFX6) {
190 /* GFX6 bug workaround, related to power management. Limit LS-HS
191 * threadgroups to only one wave.
192 */
193 unsigned one_wave = 64 / max_verts_per_patch;
194 *num_patches = MIN2(*num_patches, one_wave);
195 }
196
197 /* The VGT HS block increments the patch ID unconditionally
198 * within a single threadgroup. This results in incorrect
199 * patch IDs when instanced draws are used.
200 *
201 * The intended solution is to restrict threadgroups to
202 * a single instance by setting SWITCH_ON_EOI, which
203 * should cause IA to split instances up. However, this
204 * doesn't work correctly on GFX6 when there is no other
205 * SE to switch to.
206 */
207 if (has_primid_instancing_bug && tess_uses_primid)
208 *num_patches = 1;
209
210 sctx->last_num_patches = *num_patches;
211
212 output_patch0_offset = input_patch_size * *num_patches;
213 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
214
215 /* Compute userdata SGPRs. */
216 assert(((input_vertex_size / 4) & ~0xff) == 0);
217 assert(((output_vertex_size / 4) & ~0xff) == 0);
218 assert(((input_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch_size / 4) & ~0x1fff) == 0);
220 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
221 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
222 assert(num_tcs_input_cp <= 32);
223 assert(num_tcs_output_cp <= 32);
224
225 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
226 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
227
228 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
229 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
230 tcs_out_layout = (output_patch_size / 4) |
231 (num_tcs_input_cp << 13) |
232 ring_va;
233 tcs_out_offsets = (output_patch0_offset / 16) |
234 ((perpatch_output_offset / 16) << 16);
235 offchip_layout = *num_patches |
236 (num_tcs_output_cp << 6) |
237 (pervertex_output_patch_size * *num_patches << 12);
238
239 /* Compute the LDS size. */
240 lds_size = output_patch0_offset + output_patch_size * *num_patches;
241
242 if (sctx->chip_class >= GFX7) {
243 assert(lds_size <= 65536);
244 lds_size = align(lds_size, 512) / 512;
245 } else {
246 assert(lds_size <= 32768);
247 lds_size = align(lds_size, 256) / 256;
248 }
249
250 /* Set SI_SGPR_VS_STATE_BITS. */
251 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
252 C_VS_STATE_LS_OUT_VERTEX_SIZE;
253 sctx->current_vs_state |= tcs_in_layout;
254
255 /* We should be able to support in-shader LDS use with LLVM >= 9
256 * by just adding the lds_sizes together, but it has never
257 * been tested. */
258 assert(ls_current->config.lds_size == 0);
259
260 if (sctx->chip_class >= GFX9) {
261 unsigned hs_rsrc2 = ls_current->config.rsrc2;
262
263 if (sctx->chip_class >= GFX10)
264 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
265 else
266 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
267
268 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
269
270 /* Set userdata SGPRs for merged LS-HS. */
271 radeon_set_sh_reg_seq(cs,
272 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
273 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
274 radeon_emit(cs, offchip_layout);
275 radeon_emit(cs, tcs_out_offsets);
276 radeon_emit(cs, tcs_out_layout);
277 } else {
278 unsigned ls_rsrc2 = ls_current->config.rsrc2;
279
280 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
281 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
282
283 /* Due to a hw bug, RSRC2_LS must be written twice with another
284 * LS register written in between. */
285 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
286 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
287 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
288 radeon_emit(cs, ls_current->config.rsrc1);
289 radeon_emit(cs, ls_rsrc2);
290
291 /* Set userdata SGPRs for TCS. */
292 radeon_set_sh_reg_seq(cs,
293 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
294 radeon_emit(cs, offchip_layout);
295 radeon_emit(cs, tcs_out_offsets);
296 radeon_emit(cs, tcs_out_layout);
297 radeon_emit(cs, tcs_in_layout);
298 }
299
300 /* Set userdata SGPRs for TES. */
301 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
302 radeon_emit(cs, offchip_layout);
303 radeon_emit(cs, ring_va);
304
305 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
306 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
307 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
308
309 if (sctx->last_ls_hs_config != ls_hs_config) {
310 if (sctx->chip_class >= GFX7) {
311 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
312 ls_hs_config);
313 } else {
314 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
315 ls_hs_config);
316 }
317 sctx->last_ls_hs_config = ls_hs_config;
318 sctx->context_roll = true;
319 }
320 }
321
322 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
323 enum pipe_prim_type prim)
324 {
325 switch (prim) {
326 case PIPE_PRIM_PATCHES:
327 return info->count / info->vertices_per_patch;
328 case PIPE_PRIM_POLYGON:
329 return info->count >= 3;
330 case SI_PRIM_RECTANGLE_LIST:
331 return info->count / 3;
332 default:
333 return u_decomposed_prims_for_vertices(prim, info->count);
334 }
335 }
336
337 static unsigned
338 si_get_init_multi_vgt_param(struct si_screen *sscreen,
339 union si_vgt_param_key *key)
340 {
341 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
342 unsigned max_primgroup_in_wave = 2;
343
344 /* SWITCH_ON_EOP(0) is always preferable. */
345 bool wd_switch_on_eop = false;
346 bool ia_switch_on_eop = false;
347 bool ia_switch_on_eoi = false;
348 bool partial_vs_wave = false;
349 bool partial_es_wave = false;
350
351 if (key->u.uses_tess) {
352 /* SWITCH_ON_EOI must be set if PrimID is used. */
353 if (key->u.tess_uses_prim_id)
354 ia_switch_on_eoi = true;
355
356 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
357 if ((sscreen->info.family == CHIP_TAHITI ||
358 sscreen->info.family == CHIP_PITCAIRN ||
359 sscreen->info.family == CHIP_BONAIRE) &&
360 key->u.uses_gs)
361 partial_vs_wave = true;
362
363 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
364 if (sscreen->has_distributed_tess) {
365 if (key->u.uses_gs) {
366 if (sscreen->info.chip_class == GFX8)
367 partial_es_wave = true;
368 } else {
369 partial_vs_wave = true;
370 }
371 }
372 }
373
374 /* This is a hardware requirement. */
375 if (key->u.line_stipple_enabled ||
376 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
377 ia_switch_on_eop = true;
378 wd_switch_on_eop = true;
379 }
380
381 if (sscreen->info.chip_class >= GFX7) {
382 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
383 * 4 shader engines. Set 1 to pass the assertion below.
384 * The other cases are hardware requirements.
385 *
386 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
387 * for points, line strips, and tri strips.
388 */
389 if (sscreen->info.max_se <= 2 ||
390 key->u.prim == PIPE_PRIM_POLYGON ||
391 key->u.prim == PIPE_PRIM_LINE_LOOP ||
392 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
393 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
394 (key->u.primitive_restart &&
395 (sscreen->info.family < CHIP_POLARIS10 ||
396 (key->u.prim != PIPE_PRIM_POINTS &&
397 key->u.prim != PIPE_PRIM_LINE_STRIP &&
398 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
399 key->u.count_from_stream_output)
400 wd_switch_on_eop = true;
401
402 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
403 * We don't know that for indirect drawing, so treat it as
404 * always problematic. */
405 if (sscreen->info.family == CHIP_HAWAII &&
406 key->u.uses_instancing)
407 wd_switch_on_eop = true;
408
409 /* Performance recommendation for 4 SE Gfx7-8 parts if
410 * instances are smaller than a primgroup.
411 * Assume indirect draws always use small instances.
412 * This is needed for good VS wave utilization.
413 */
414 if (sscreen->info.chip_class <= GFX8 &&
415 sscreen->info.max_se == 4 &&
416 key->u.multi_instances_smaller_than_primgroup)
417 wd_switch_on_eop = true;
418
419 /* Required on GFX7 and later. */
420 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
421 ia_switch_on_eoi = true;
422
423 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
424 * to work around a GS hang.
425 */
426 if (key->u.uses_gs &&
427 (sscreen->info.family == CHIP_TONGA ||
428 sscreen->info.family == CHIP_FIJI ||
429 sscreen->info.family == CHIP_POLARIS10 ||
430 sscreen->info.family == CHIP_POLARIS11 ||
431 sscreen->info.family == CHIP_POLARIS12 ||
432 sscreen->info.family == CHIP_VEGAM))
433 partial_vs_wave = true;
434
435 /* Required by Hawaii and, for some special cases, by GFX8. */
436 if (ia_switch_on_eoi &&
437 (sscreen->info.family == CHIP_HAWAII ||
438 (sscreen->info.chip_class == GFX8 &&
439 (key->u.uses_gs || max_primgroup_in_wave != 2))))
440 partial_vs_wave = true;
441
442 /* Instancing bug on Bonaire. */
443 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
444 key->u.uses_instancing)
445 partial_vs_wave = true;
446
447 /* This only applies to Polaris10 and later 4 SE chips.
448 * wd_switch_on_eop is already true on all other chips.
449 */
450 if (!wd_switch_on_eop && key->u.primitive_restart)
451 partial_vs_wave = true;
452
453 /* If the WD switch is false, the IA switch must be false too. */
454 assert(wd_switch_on_eop || !ia_switch_on_eop);
455 }
456
457 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
458 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
459 partial_es_wave = true;
460
461 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
462 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
463 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
464 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
465 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
466 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
467 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
468 max_primgroup_in_wave : 0) |
469 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
470 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
471 }
472
473 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
474 {
475 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
476 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
477 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
478 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
479 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
480 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
481 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
482 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
483 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
484 union si_vgt_param_key key;
485
486 key.index = 0;
487 key.u.prim = prim;
488 key.u.uses_instancing = uses_instancing;
489 key.u.multi_instances_smaller_than_primgroup = multi_instances;
490 key.u.primitive_restart = primitive_restart;
491 key.u.count_from_stream_output = count_from_so;
492 key.u.line_stipple_enabled = line_stipple;
493 key.u.uses_tess = uses_tess;
494 key.u.tess_uses_prim_id = tess_uses_primid;
495 key.u.uses_gs = uses_gs;
496
497 sctx->ia_multi_vgt_param[key.index] =
498 si_get_init_multi_vgt_param(sctx->screen, &key);
499 }
500 }
501
502 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
503 const struct pipe_draw_info *info,
504 enum pipe_prim_type prim,
505 unsigned num_patches,
506 unsigned instance_count,
507 bool primitive_restart)
508 {
509 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
510 unsigned primgroup_size;
511 unsigned ia_multi_vgt_param;
512
513 if (sctx->tes_shader.cso) {
514 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
515 } else if (sctx->gs_shader.cso) {
516 primgroup_size = 64; /* recommended with a GS */
517 } else {
518 primgroup_size = 128; /* recommended without a GS and tess */
519 }
520
521 key.u.prim = prim;
522 key.u.uses_instancing = info->indirect || instance_count > 1;
523 key.u.multi_instances_smaller_than_primgroup =
524 info->indirect ||
525 (instance_count > 1 &&
526 (info->count_from_stream_output ||
527 si_num_prims_for_vertices(info, prim) < primgroup_size));
528 key.u.primitive_restart = primitive_restart;
529 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
530
531 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
532 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
533
534 if (sctx->gs_shader.cso) {
535 /* GS requirement. */
536 if (sctx->chip_class <= GFX8 &&
537 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
538 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
539
540 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
541 * The hw doc says all multi-SE chips are affected, but Vulkan
542 * only applies it to Hawaii. Do what Vulkan does.
543 */
544 if (sctx->family == CHIP_HAWAII &&
545 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
546 (info->indirect ||
547 (instance_count > 1 &&
548 (info->count_from_stream_output ||
549 si_num_prims_for_vertices(info, prim) <= 1))))
550 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
551 }
552
553 return ia_multi_vgt_param;
554 }
555
556 static unsigned si_conv_prim_to_gs_out(unsigned mode)
557 {
558 static const int prim_conv[] = {
559 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
560 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
561 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
562 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
563 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
564 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
565 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
566 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
567 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
568 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
569 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
570 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
571 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
572 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
573 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
574 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
575 };
576 assert(mode < ARRAY_SIZE(prim_conv));
577
578 return prim_conv[mode];
579 }
580
581 /* rast_prim is the primitive type after GS. */
582 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
583 {
584 struct radeon_cmdbuf *cs = sctx->gfx_cs;
585 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
586 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
587
588 if (likely(rast_prim == sctx->last_rast_prim &&
589 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple &&
590 (sctx->chip_class <= GFX9 ||
591 rs->flatshade_first == sctx->last_flatshade_first)))
592 return;
593
594 if (util_prim_is_lines(rast_prim)) {
595 /* For lines, reset the stipple pattern at each primitive. Otherwise,
596 * reset the stipple pattern at each packet (line strips, line loops).
597 */
598 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
599 rs->pa_sc_line_stipple |
600 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
601 sctx->context_roll = true;
602 }
603
604 unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
605
606 if (rast_prim != sctx->last_rast_prim &&
607 (sctx->ngg || sctx->gs_shader.cso)) {
608 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
609 sctx->context_roll = true;
610
611 if (sctx->chip_class >= GFX10) {
612 sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
613 sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
614 }
615 }
616
617 if (sctx->chip_class >= GFX10) {
618 unsigned vtx_index = rs->flatshade_first ? 0 : gs_out;
619 sctx->current_vs_state &= C_VS_STATE_PROVOKING_VTX_INDEX;
620 sctx->current_vs_state |= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
621 }
622
623 sctx->last_rast_prim = rast_prim;
624 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
625 sctx->last_flatshade_first = rs->flatshade_first;
626 }
627
628 static void si_emit_vs_state(struct si_context *sctx,
629 const struct pipe_draw_info *info)
630 {
631 sctx->current_vs_state &= C_VS_STATE_INDEXED;
632 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
633
634 if (sctx->num_vs_blit_sgprs) {
635 /* Re-emit the state after we leave u_blitter. */
636 sctx->last_vs_state = ~0;
637 return;
638 }
639
640 if (sctx->current_vs_state != sctx->last_vs_state) {
641 struct radeon_cmdbuf *cs = sctx->gfx_cs;
642
643 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
644 radeon_set_sh_reg(cs,
645 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
646 SI_SGPR_VS_STATE_BITS * 4,
647 sctx->current_vs_state);
648
649 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
650 * before the rasterizer.
651 *
652 * For TES or the GS copy shader without NGG:
653 */
654 if (sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
655 R_00B130_SPI_SHADER_USER_DATA_VS_0) {
656 radeon_set_sh_reg(cs,
657 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
658 SI_SGPR_VS_STATE_BITS * 4,
659 sctx->current_vs_state);
660 }
661
662 /* For NGG: */
663 if (sctx->chip_class >= GFX10 &&
664 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
665 R_00B230_SPI_SHADER_USER_DATA_GS_0) {
666 radeon_set_sh_reg(cs,
667 R_00B230_SPI_SHADER_USER_DATA_GS_0 +
668 SI_SGPR_VS_STATE_BITS * 4,
669 sctx->current_vs_state);
670 }
671
672 sctx->last_vs_state = sctx->current_vs_state;
673 }
674 }
675
676 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
677 bool primitive_restart,
678 unsigned restart_index)
679 {
680 return primitive_restart &&
681 (restart_index != sctx->last_restart_index ||
682 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
683 }
684
685 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
686 const struct pipe_draw_info *info,
687 enum pipe_prim_type prim,
688 unsigned num_patches,
689 unsigned instance_count,
690 bool primitive_restart)
691 {
692 struct radeon_cmdbuf *cs = sctx->gfx_cs;
693 unsigned ia_multi_vgt_param;
694
695 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
696 instance_count, primitive_restart);
697
698 /* Draw state. */
699 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
700 if (sctx->chip_class >= GFX9)
701 radeon_set_uconfig_reg_idx(cs, sctx->screen,
702 R_030960_IA_MULTI_VGT_PARAM, 4,
703 ia_multi_vgt_param);
704 else if (sctx->chip_class >= GFX7)
705 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
706 else
707 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
708
709 sctx->last_multi_vgt_param = ia_multi_vgt_param;
710 }
711 }
712
713 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
714 * We overload last_multi_vgt_param.
715 */
716 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
717 {
718 if (sctx->ngg)
719 return; /* set during PM4 emit */
720
721 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
722 unsigned primgroup_size;
723 unsigned vertgroup_size;
724
725 if (sctx->tes_shader.cso) {
726 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
727 vertgroup_size = 0;
728 } else if (sctx->gs_shader.cso) {
729 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
730 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
731 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
732 } else {
733 primgroup_size = 128; /* recommended without a GS and tess */
734 vertgroup_size = 0;
735 }
736
737 unsigned ge_cntl =
738 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
739 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
740 S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled) |
741 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
742
743 if (ge_cntl != sctx->last_multi_vgt_param) {
744 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
745 sctx->last_multi_vgt_param = ge_cntl;
746 }
747 }
748
749 static void si_emit_draw_registers(struct si_context *sctx,
750 const struct pipe_draw_info *info,
751 enum pipe_prim_type prim,
752 unsigned num_patches,
753 unsigned instance_count,
754 bool primitive_restart)
755 {
756 struct radeon_cmdbuf *cs = sctx->gfx_cs;
757 unsigned vgt_prim = si_conv_pipe_prim(info->mode);
758
759 if (sctx->chip_class >= GFX10)
760 gfx10_emit_ge_cntl(sctx, num_patches);
761 else
762 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
763 instance_count, primitive_restart);
764
765 if (vgt_prim != sctx->last_prim) {
766 if (sctx->chip_class >= GFX7)
767 radeon_set_uconfig_reg_idx(cs, sctx->screen,
768 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
769 else
770 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
771
772 sctx->last_prim = vgt_prim;
773 }
774
775 /* Primitive restart. */
776 if (primitive_restart != sctx->last_primitive_restart_en) {
777 if (sctx->chip_class >= GFX9)
778 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
779 primitive_restart);
780 else
781 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
782 primitive_restart);
783
784 sctx->last_primitive_restart_en = primitive_restart;
785
786 }
787 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
788 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
789 info->restart_index);
790 sctx->last_restart_index = info->restart_index;
791 sctx->context_roll = true;
792 }
793 }
794
795 static void si_emit_draw_packets(struct si_context *sctx,
796 const struct pipe_draw_info *info,
797 struct pipe_resource *indexbuf,
798 unsigned index_size,
799 unsigned index_offset,
800 unsigned instance_count,
801 bool dispatch_prim_discard_cs,
802 unsigned original_index_size)
803 {
804 struct pipe_draw_indirect_info *indirect = info->indirect;
805 struct radeon_cmdbuf *cs = sctx->gfx_cs;
806 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
807 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
808 uint32_t index_max_size = 0;
809 uint64_t index_va = 0;
810
811 if (info->count_from_stream_output) {
812 struct si_streamout_target *t =
813 (struct si_streamout_target*)info->count_from_stream_output;
814
815 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
816 t->stride_in_dw);
817 si_cp_copy_data(sctx, sctx->gfx_cs,
818 COPY_DATA_REG, NULL,
819 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
820 COPY_DATA_SRC_MEM, t->buf_filled_size,
821 t->buf_filled_size_offset);
822 }
823
824 /* draw packet */
825 if (index_size) {
826 if (index_size != sctx->last_index_size) {
827 unsigned index_type;
828
829 /* index type */
830 switch (index_size) {
831 case 1:
832 index_type = V_028A7C_VGT_INDEX_8;
833 break;
834 case 2:
835 index_type = V_028A7C_VGT_INDEX_16 |
836 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
837 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
838 break;
839 case 4:
840 index_type = V_028A7C_VGT_INDEX_32 |
841 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
842 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
843 break;
844 default:
845 assert(!"unreachable");
846 return;
847 }
848
849 if (sctx->chip_class >= GFX9) {
850 radeon_set_uconfig_reg_idx(cs, sctx->screen,
851 R_03090C_VGT_INDEX_TYPE, 2,
852 index_type);
853 } else {
854 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
855 radeon_emit(cs, index_type);
856 }
857
858 sctx->last_index_size = index_size;
859 }
860
861 if (original_index_size) {
862 index_max_size = (indexbuf->width0 - index_offset) /
863 original_index_size;
864 index_va = si_resource(indexbuf)->gpu_address + index_offset;
865
866 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
867 si_resource(indexbuf),
868 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
869 }
870 } else {
871 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
872 * so the state must be re-emitted before the next indexed draw.
873 */
874 if (sctx->chip_class >= GFX7)
875 sctx->last_index_size = -1;
876 }
877
878 if (indirect) {
879 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
880
881 assert(indirect_va % 8 == 0);
882
883 si_invalidate_draw_sh_constants(sctx);
884
885 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
886 radeon_emit(cs, 1);
887 radeon_emit(cs, indirect_va);
888 radeon_emit(cs, indirect_va >> 32);
889
890 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
891 si_resource(indirect->buffer),
892 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
893
894 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
895 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
896
897 assert(indirect->offset % 4 == 0);
898
899 if (index_size) {
900 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
901 radeon_emit(cs, index_va);
902 radeon_emit(cs, index_va >> 32);
903
904 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
905 radeon_emit(cs, index_max_size);
906 }
907
908 if (!sctx->screen->has_draw_indirect_multi) {
909 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
910 : PKT3_DRAW_INDIRECT,
911 3, render_cond_bit));
912 radeon_emit(cs, indirect->offset);
913 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
914 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
915 radeon_emit(cs, di_src_sel);
916 } else {
917 uint64_t count_va = 0;
918
919 if (indirect->indirect_draw_count) {
920 struct si_resource *params_buf =
921 si_resource(indirect->indirect_draw_count);
922
923 radeon_add_to_buffer_list(
924 sctx, sctx->gfx_cs, params_buf,
925 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
926
927 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
928 }
929
930 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
931 PKT3_DRAW_INDIRECT_MULTI,
932 8, render_cond_bit));
933 radeon_emit(cs, indirect->offset);
934 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
935 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
936 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
937 S_2C3_DRAW_INDEX_ENABLE(1) |
938 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
939 radeon_emit(cs, indirect->draw_count);
940 radeon_emit(cs, count_va);
941 radeon_emit(cs, count_va >> 32);
942 radeon_emit(cs, indirect->stride);
943 radeon_emit(cs, di_src_sel);
944 }
945 } else {
946 int base_vertex;
947
948 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
949 sctx->last_instance_count != instance_count) {
950 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
951 radeon_emit(cs, instance_count);
952 sctx->last_instance_count = instance_count;
953 }
954
955 /* Base vertex and start instance. */
956 base_vertex = original_index_size ? info->index_bias : info->start;
957
958 if (sctx->num_vs_blit_sgprs) {
959 /* Re-emit draw constants after we leave u_blitter. */
960 si_invalidate_draw_sh_constants(sctx);
961
962 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
963 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
964 sctx->num_vs_blit_sgprs);
965 radeon_emit_array(cs, sctx->vs_blit_sh_data,
966 sctx->num_vs_blit_sgprs);
967 } else if (base_vertex != sctx->last_base_vertex ||
968 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
969 info->start_instance != sctx->last_start_instance ||
970 info->drawid != sctx->last_drawid ||
971 sh_base_reg != sctx->last_sh_base_reg) {
972 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
973 radeon_emit(cs, base_vertex);
974 radeon_emit(cs, info->start_instance);
975 radeon_emit(cs, info->drawid);
976
977 sctx->last_base_vertex = base_vertex;
978 sctx->last_start_instance = info->start_instance;
979 sctx->last_drawid = info->drawid;
980 sctx->last_sh_base_reg = sh_base_reg;
981 }
982
983 if (index_size) {
984 if (dispatch_prim_discard_cs) {
985 index_va += info->start * original_index_size;
986 index_max_size = MIN2(index_max_size, info->count);
987
988 si_dispatch_prim_discard_cs_and_draw(sctx, info,
989 original_index_size,
990 base_vertex,
991 index_va, index_max_size);
992 return;
993 }
994
995 index_va += info->start * index_size;
996
997 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
998 radeon_emit(cs, index_max_size);
999 radeon_emit(cs, index_va);
1000 radeon_emit(cs, index_va >> 32);
1001 radeon_emit(cs, info->count);
1002 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
1003 } else {
1004 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1005 radeon_emit(cs, info->count);
1006 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1007 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
1008 }
1009 }
1010 }
1011
1012 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1013 unsigned cp_coher_cntl)
1014 {
1015 bool compute_ib = !sctx->has_graphics ||
1016 cs == sctx->prim_discard_compute_cs;
1017
1018 if (sctx->chip_class >= GFX9 || compute_ib) {
1019 /* Flush caches and wait for the caches to assert idle. */
1020 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
1021 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1022 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1023 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1024 radeon_emit(cs, 0); /* CP_COHER_BASE */
1025 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1026 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1027 } else {
1028 /* ACQUIRE_MEM is only required on a compute ring. */
1029 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1030 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1031 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1032 radeon_emit(cs, 0); /* CP_COHER_BASE */
1033 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1034 }
1035
1036 /* ACQUIRE_MEM has an implicit context roll if the current context
1037 * is busy. */
1038 if (!compute_ib)
1039 sctx->context_roll = true;
1040 }
1041
1042 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1043 {
1044 if (!si_compute_prim_discard_enabled(sctx))
1045 return;
1046
1047 if (!sctx->barrier_buf) {
1048 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
1049 &sctx->barrier_buf_offset,
1050 (struct pipe_resource**)&sctx->barrier_buf);
1051 }
1052
1053 /* Emit a placeholder to signal the next compute IB to start.
1054 * See si_compute_prim_discard.c for explanation.
1055 */
1056 uint32_t signal = 1;
1057 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
1058 4, V_370_MEM, V_370_ME, &signal);
1059
1060 sctx->last_pkt3_write_data =
1061 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1062
1063 /* Only the last occurence of WRITE_DATA will be executed.
1064 * The packet will be enabled in si_flush_gfx_cs.
1065 */
1066 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1067 }
1068
1069 void gfx10_emit_cache_flush(struct si_context *ctx)
1070 {
1071 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1072 uint32_t gcr_cntl = 0;
1073 unsigned cb_db_event = 0;
1074 unsigned flags = ctx->flags;
1075
1076 if (!ctx->has_graphics) {
1077 /* Only process compute flags. */
1078 flags &= SI_CONTEXT_INV_ICACHE |
1079 SI_CONTEXT_INV_SCACHE |
1080 SI_CONTEXT_INV_VCACHE |
1081 SI_CONTEXT_INV_L2 |
1082 SI_CONTEXT_WB_L2 |
1083 SI_CONTEXT_INV_L2_METADATA |
1084 SI_CONTEXT_CS_PARTIAL_FLUSH;
1085 }
1086
1087 /* We don't need these. */
1088 assert(!(flags & (SI_CONTEXT_VGT_FLUSH |
1089 SI_CONTEXT_VGT_STREAMOUT_SYNC |
1090 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1091
1092 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1093 ctx->num_cb_cache_flushes++;
1094 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1095 ctx->num_db_cache_flushes++;
1096
1097 if (flags & SI_CONTEXT_INV_ICACHE)
1098 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1099 if (flags & SI_CONTEXT_INV_SCACHE) {
1100 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1101 * to FORWARD when both L1 and L2 are written out (WB or INV).
1102 */
1103 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1104 }
1105 if (flags & SI_CONTEXT_INV_VCACHE)
1106 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1107 if (flags & SI_CONTEXT_INV_L2) {
1108 /* Writeback and invalidate everything in L2. */
1109 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
1110 ctx->num_L2_invalidates++;
1111 } else if (flags & SI_CONTEXT_WB_L2) {
1112 /* Writeback but do not invalidate. */
1113 gcr_cntl |= S_586_GL2_WB(1);
1114 }
1115 if (flags & SI_CONTEXT_INV_L2_METADATA)
1116 gcr_cntl |= S_586_GLM_INV(1);
1117
1118 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1119 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1120 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1121 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1122 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1123 EVENT_INDEX(0));
1124 }
1125 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1126 /* Flush HTILE. Will wait for idle later. */
1127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1129 EVENT_INDEX(0));
1130 }
1131
1132 /* First flush CB/DB, then L1/L2. */
1133 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1134
1135 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1136 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1137 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1138 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1139 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1140 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1141 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1142 } else {
1143 assert(0);
1144 }
1145 } else {
1146 /* Wait for graphics shaders to go idle if requested. */
1147 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1148 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1149 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1150 /* Only count explicit shader flushes, not implicit ones. */
1151 ctx->num_vs_flushes++;
1152 ctx->num_ps_flushes++;
1153 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1154 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1155 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1156 ctx->num_vs_flushes++;
1157 }
1158 }
1159
1160 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1161 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1162 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1163 ctx->num_cs_flushes++;
1164 ctx->compute_is_busy = false;
1165 }
1166
1167 if (cb_db_event) {
1168 /* CB/DB flush and invalidate (or possibly just a wait for a
1169 * meta flush) via RELEASE_MEM.
1170 *
1171 * Combine this with other cache flushes when possible; this
1172 * requires affected shaders to be idle, so do it after the
1173 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1174 * implied).
1175 */
1176 uint64_t va;
1177
1178 /* Do the flush (enqueue the event and wait for it). */
1179 va = ctx->wait_mem_scratch->gpu_address;
1180 ctx->wait_mem_number++;
1181
1182 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1183 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1184 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1185 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1186 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1187 assert(G_586_GL2_US(gcr_cntl) == 0);
1188 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1189 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1190 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1191 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1192 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1193
1194 gcr_cntl &= C_586_GLM_WB &
1195 C_586_GLM_INV &
1196 C_586_GLV_INV &
1197 C_586_GL1_INV &
1198 C_586_GL2_INV &
1199 C_586_GL2_WB; /* keep SEQ */
1200
1201 si_cp_release_mem(ctx, cs, cb_db_event,
1202 S_490_GLM_WB(glm_wb) |
1203 S_490_GLM_INV(glm_inv) |
1204 S_490_GLV_INV(glv_inv) |
1205 S_490_GL1_INV(gl1_inv) |
1206 S_490_GL2_INV(gl2_inv) |
1207 S_490_GL2_WB(gl2_wb) |
1208 S_490_SEQ(gcr_seq),
1209 EOP_DST_SEL_MEM,
1210 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1211 EOP_DATA_SEL_VALUE_32BIT,
1212 ctx->wait_mem_scratch, va,
1213 ctx->wait_mem_number, SI_NOT_QUERY);
1214 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1215 WAIT_REG_MEM_EQUAL);
1216 }
1217
1218 /* Ignore fields that only modify the behavior of other fields. */
1219 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1220 /* Flush caches and wait for the caches to assert idle.
1221 * The cache flush is executed in the ME, but the PFP waits
1222 * for completion.
1223 */
1224 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1225 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1226 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1227 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1228 radeon_emit(cs, 0); /* CP_COHER_BASE */
1229 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1230 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1231 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1232 } else if (cb_db_event ||
1233 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1234 SI_CONTEXT_PS_PARTIAL_FLUSH |
1235 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1236 /* We need to ensure that PFP waits as well. */
1237 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1238 radeon_emit(cs, 0);
1239 }
1240
1241 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1242 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1243 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1244 EVENT_INDEX(0));
1245 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1246 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1247 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1248 EVENT_INDEX(0));
1249 }
1250
1251 ctx->flags = 0;
1252 }
1253
1254 void si_emit_cache_flush(struct si_context *sctx)
1255 {
1256 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1257 uint32_t flags = sctx->flags;
1258
1259 if (!sctx->has_graphics) {
1260 /* Only process compute flags. */
1261 flags &= SI_CONTEXT_INV_ICACHE |
1262 SI_CONTEXT_INV_SCACHE |
1263 SI_CONTEXT_INV_VCACHE |
1264 SI_CONTEXT_INV_L2 |
1265 SI_CONTEXT_WB_L2 |
1266 SI_CONTEXT_INV_L2_METADATA |
1267 SI_CONTEXT_CS_PARTIAL_FLUSH;
1268 }
1269
1270 uint32_t cp_coher_cntl = 0;
1271 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1272 SI_CONTEXT_FLUSH_AND_INV_DB);
1273 const bool is_barrier = flush_cb_db ||
1274 /* INV_ICACHE == beginning of gfx IB. Checking
1275 * INV_ICACHE fixes corruption for DeusExMD with
1276 * compute-based culling, but I don't know why.
1277 */
1278 flags & (SI_CONTEXT_INV_ICACHE |
1279 SI_CONTEXT_PS_PARTIAL_FLUSH |
1280 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1281 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1282 sctx->compute_is_busy);
1283
1284 assert(sctx->chip_class <= GFX9);
1285
1286 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1287 sctx->num_cb_cache_flushes++;
1288 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1289 sctx->num_db_cache_flushes++;
1290
1291 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1292 * bit is set. An alternative way is to write SQC_CACHES, but that
1293 * doesn't seem to work reliably. Since the bug doesn't affect
1294 * correctness (it only does more work than necessary) and
1295 * the performance impact is likely negligible, there is no plan
1296 * to add a workaround for it.
1297 */
1298
1299 if (flags & SI_CONTEXT_INV_ICACHE)
1300 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1301 if (flags & SI_CONTEXT_INV_SCACHE)
1302 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1303
1304 if (sctx->chip_class <= GFX8) {
1305 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1306 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1307 S_0085F0_CB0_DEST_BASE_ENA(1) |
1308 S_0085F0_CB1_DEST_BASE_ENA(1) |
1309 S_0085F0_CB2_DEST_BASE_ENA(1) |
1310 S_0085F0_CB3_DEST_BASE_ENA(1) |
1311 S_0085F0_CB4_DEST_BASE_ENA(1) |
1312 S_0085F0_CB5_DEST_BASE_ENA(1) |
1313 S_0085F0_CB6_DEST_BASE_ENA(1) |
1314 S_0085F0_CB7_DEST_BASE_ENA(1);
1315
1316 /* Necessary for DCC */
1317 if (sctx->chip_class == GFX8)
1318 si_cp_release_mem(sctx, cs,
1319 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1320 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1321 EOP_DATA_SEL_DISCARD, NULL,
1322 0, 0, SI_NOT_QUERY);
1323 }
1324 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1325 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1326 S_0085F0_DB_DEST_BASE_ENA(1);
1327 }
1328
1329 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1330 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1331 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1332 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1333 }
1334 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1335 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1336 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1337 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1338 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1339 }
1340
1341 /* Wait for shader engines to go idle.
1342 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1343 * for everything including CB/DB cache flushes.
1344 */
1345 if (!flush_cb_db) {
1346 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1347 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1348 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1349 /* Only count explicit shader flushes, not implicit ones
1350 * done by SURFACE_SYNC.
1351 */
1352 sctx->num_vs_flushes++;
1353 sctx->num_ps_flushes++;
1354 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1355 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1356 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1357 sctx->num_vs_flushes++;
1358 }
1359 }
1360
1361 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1362 sctx->compute_is_busy) {
1363 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1364 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1365 sctx->num_cs_flushes++;
1366 sctx->compute_is_busy = false;
1367 }
1368
1369 /* VGT state synchronization. */
1370 if (flags & SI_CONTEXT_VGT_FLUSH) {
1371 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1372 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1373 }
1374 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1375 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1376 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1377 }
1378
1379 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1380 * wait for idle on GFX9. We have to use a TS event.
1381 */
1382 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1383 uint64_t va;
1384 unsigned tc_flags, cb_db_event;
1385
1386 /* Set the CB/DB flush event. */
1387 switch (flush_cb_db) {
1388 case SI_CONTEXT_FLUSH_AND_INV_CB:
1389 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1390 break;
1391 case SI_CONTEXT_FLUSH_AND_INV_DB:
1392 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1393 break;
1394 default:
1395 /* both CB & DB */
1396 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1397 }
1398
1399 /* These are the only allowed combinations. If you need to
1400 * do multiple operations at once, do them separately.
1401 * All operations that invalidate L2 also seem to invalidate
1402 * metadata. Volatile (VOL) and WC flushes are not listed here.
1403 *
1404 * TC | TC_WB = writeback & invalidate L2 & L1
1405 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1406 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1407 * TC | TC_NC = invalidate L2 for MTYPE == NC
1408 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1409 * TCL1 = invalidate L1
1410 */
1411 tc_flags = 0;
1412
1413 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1414 tc_flags = EVENT_TC_ACTION_ENA |
1415 EVENT_TC_MD_ACTION_ENA;
1416 }
1417
1418 /* Ideally flush TC together with CB/DB. */
1419 if (flags & SI_CONTEXT_INV_L2) {
1420 /* Writeback and invalidate everything in L2 & L1. */
1421 tc_flags = EVENT_TC_ACTION_ENA |
1422 EVENT_TC_WB_ACTION_ENA;
1423
1424 /* Clear the flags. */
1425 flags &= ~(SI_CONTEXT_INV_L2 |
1426 SI_CONTEXT_WB_L2 |
1427 SI_CONTEXT_INV_VCACHE);
1428 sctx->num_L2_invalidates++;
1429 }
1430
1431 /* Do the flush (enqueue the event and wait for it). */
1432 va = sctx->wait_mem_scratch->gpu_address;
1433 sctx->wait_mem_number++;
1434
1435 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1436 EOP_DST_SEL_MEM,
1437 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1438 EOP_DATA_SEL_VALUE_32BIT,
1439 sctx->wait_mem_scratch, va,
1440 sctx->wait_mem_number, SI_NOT_QUERY);
1441 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1442 WAIT_REG_MEM_EQUAL);
1443 }
1444
1445 /* Make sure ME is idle (it executes most packets) before continuing.
1446 * This prevents read-after-write hazards between PFP and ME.
1447 */
1448 if (sctx->has_graphics &&
1449 (cp_coher_cntl ||
1450 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1451 SI_CONTEXT_INV_VCACHE |
1452 SI_CONTEXT_INV_L2 |
1453 SI_CONTEXT_WB_L2)))) {
1454 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1455 radeon_emit(cs, 0);
1456 }
1457
1458 /* GFX6-GFX8 only:
1459 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1460 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1461 *
1462 * cp_coher_cntl should contain all necessary flags except TC flags
1463 * at this point.
1464 *
1465 * GFX6-GFX7 don't support L2 write-back.
1466 */
1467 if (flags & SI_CONTEXT_INV_L2 ||
1468 (sctx->chip_class <= GFX7 &&
1469 (flags & SI_CONTEXT_WB_L2))) {
1470 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1471 * WB must be set on GFX8+ when TC_ACTION is set.
1472 */
1473 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1474 S_0085F0_TC_ACTION_ENA(1) |
1475 S_0085F0_TCL1_ACTION_ENA(1) |
1476 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1477 cp_coher_cntl = 0;
1478 sctx->num_L2_invalidates++;
1479 } else {
1480 /* L1 invalidation and L2 writeback must be done separately,
1481 * because both operations can't be done together.
1482 */
1483 if (flags & SI_CONTEXT_WB_L2) {
1484 /* WB = write-back
1485 * NC = apply to non-coherent MTYPEs
1486 * (i.e. MTYPE <= 1, which is what we use everywhere)
1487 *
1488 * WB doesn't work without NC.
1489 */
1490 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1491 S_0301F0_TC_WB_ACTION_ENA(1) |
1492 S_0301F0_TC_NC_ACTION_ENA(1));
1493 cp_coher_cntl = 0;
1494 sctx->num_L2_writebacks++;
1495 }
1496 if (flags & SI_CONTEXT_INV_VCACHE) {
1497 /* Invalidate per-CU VMEM L1. */
1498 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1499 S_0085F0_TCL1_ACTION_ENA(1));
1500 cp_coher_cntl = 0;
1501 }
1502 }
1503
1504 /* If TC flushes haven't cleared this... */
1505 if (cp_coher_cntl)
1506 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1507
1508 if (is_barrier)
1509 si_prim_discard_signal_next_compute_ib_start(sctx);
1510
1511 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1512 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1513 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1514 EVENT_INDEX(0));
1515 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1516 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1517 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1518 EVENT_INDEX(0));
1519 }
1520
1521 sctx->flags = 0;
1522 }
1523
1524 static void si_get_draw_start_count(struct si_context *sctx,
1525 const struct pipe_draw_info *info,
1526 unsigned *start, unsigned *count)
1527 {
1528 struct pipe_draw_indirect_info *indirect = info->indirect;
1529
1530 if (indirect) {
1531 unsigned indirect_count;
1532 struct pipe_transfer *transfer;
1533 unsigned begin, end;
1534 unsigned map_size;
1535 unsigned *data;
1536
1537 if (indirect->indirect_draw_count) {
1538 data = pipe_buffer_map_range(&sctx->b,
1539 indirect->indirect_draw_count,
1540 indirect->indirect_draw_count_offset,
1541 sizeof(unsigned),
1542 PIPE_TRANSFER_READ, &transfer);
1543
1544 indirect_count = *data;
1545
1546 pipe_buffer_unmap(&sctx->b, transfer);
1547 } else {
1548 indirect_count = indirect->draw_count;
1549 }
1550
1551 if (!indirect_count) {
1552 *start = *count = 0;
1553 return;
1554 }
1555
1556 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1557 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1558 indirect->offset, map_size,
1559 PIPE_TRANSFER_READ, &transfer);
1560
1561 begin = UINT_MAX;
1562 end = 0;
1563
1564 for (unsigned i = 0; i < indirect_count; ++i) {
1565 unsigned count = data[0];
1566 unsigned start = data[2];
1567
1568 if (count > 0) {
1569 begin = MIN2(begin, start);
1570 end = MAX2(end, start + count);
1571 }
1572
1573 data += indirect->stride / sizeof(unsigned);
1574 }
1575
1576 pipe_buffer_unmap(&sctx->b, transfer);
1577
1578 if (begin < end) {
1579 *start = begin;
1580 *count = end - begin;
1581 } else {
1582 *start = *count = 0;
1583 }
1584 } else {
1585 *start = info->start;
1586 *count = info->count;
1587 }
1588 }
1589
1590 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1591 enum pipe_prim_type prim, unsigned instance_count,
1592 bool primitive_restart, unsigned skip_atom_mask)
1593 {
1594 unsigned num_patches = 0;
1595
1596 si_emit_rasterizer_prim_state(sctx);
1597 if (sctx->tes_shader.cso)
1598 si_emit_derived_tess_state(sctx, info, &num_patches);
1599
1600 /* Emit state atoms. */
1601 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1602 while (mask)
1603 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1604
1605 sctx->dirty_atoms &= skip_atom_mask;
1606
1607 /* Emit states. */
1608 mask = sctx->dirty_states;
1609 while (mask) {
1610 unsigned i = u_bit_scan(&mask);
1611 struct si_pm4_state *state = sctx->queued.array[i];
1612
1613 if (!state || sctx->emitted.array[i] == state)
1614 continue;
1615
1616 si_pm4_emit(sctx, state);
1617 sctx->emitted.array[i] = state;
1618 }
1619 sctx->dirty_states = 0;
1620
1621 /* Emit draw states. */
1622 si_emit_vs_state(sctx, info);
1623 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1624 primitive_restart);
1625 }
1626
1627 static bool
1628 si_all_vs_resources_read_only(struct si_context *sctx,
1629 struct pipe_resource *indexbuf)
1630 {
1631 struct radeon_winsys *ws = sctx->ws;
1632 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1633
1634 /* Index buffer. */
1635 if (indexbuf &&
1636 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1637 RADEON_USAGE_WRITE))
1638 goto has_write_reference;
1639
1640 /* Vertex buffers. */
1641 struct si_vertex_elements *velems = sctx->vertex_elements;
1642 unsigned num_velems = velems->count;
1643
1644 for (unsigned i = 0; i < num_velems; i++) {
1645 if (!((1 << i) & velems->first_vb_use_mask))
1646 continue;
1647
1648 unsigned vb_index = velems->vertex_buffer_index[i];
1649 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1650 if (!res)
1651 continue;
1652
1653 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1654 RADEON_USAGE_WRITE))
1655 goto has_write_reference;
1656 }
1657
1658 /* Constant and shader buffers. */
1659 struct si_descriptors *buffers =
1660 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1661 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1662 unsigned index = buffers->first_active_slot + i;
1663 struct pipe_resource *res =
1664 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1665 if (!res)
1666 continue;
1667
1668 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1669 RADEON_USAGE_WRITE))
1670 goto has_write_reference;
1671 }
1672
1673 /* Samplers. */
1674 struct si_shader_selector *vs = sctx->vs_shader.cso;
1675 if (vs->info.samplers_declared) {
1676 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1677
1678 for (unsigned i = 0; i < num_samplers; i++) {
1679 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1680 if (!view)
1681 continue;
1682
1683 if (ws->cs_is_buffer_referenced(cs,
1684 si_resource(view->texture)->buf,
1685 RADEON_USAGE_WRITE))
1686 goto has_write_reference;
1687 }
1688 }
1689
1690 /* Images. */
1691 if (vs->info.images_declared) {
1692 unsigned num_images = util_last_bit(vs->info.images_declared);
1693
1694 for (unsigned i = 0; i < num_images; i++) {
1695 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1696 if (!res)
1697 continue;
1698
1699 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1700 RADEON_USAGE_WRITE))
1701 goto has_write_reference;
1702 }
1703 }
1704
1705 return true;
1706
1707 has_write_reference:
1708 /* If the current gfx IB has enough packets, flush it to remove write
1709 * references to buffers.
1710 */
1711 if (cs->prev_dw + cs->current.cdw > 2048) {
1712 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1713 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1714 return true;
1715 }
1716 return false;
1717 }
1718
1719 static ALWAYS_INLINE bool pd_msg(const char *s)
1720 {
1721 if (SI_PRIM_DISCARD_DEBUG)
1722 printf("PD failed: %s\n", s);
1723 return false;
1724 }
1725
1726 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1727 {
1728 struct si_context *sctx = (struct si_context *)ctx;
1729 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1730 struct pipe_resource *indexbuf = info->index.resource;
1731 unsigned dirty_tex_counter, dirty_buf_counter;
1732 enum pipe_prim_type rast_prim, prim = info->mode;
1733 unsigned index_size = info->index_size;
1734 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1735 unsigned instance_count = info->instance_count;
1736 bool primitive_restart = info->primitive_restart &&
1737 (!sctx->screen->options.prim_restart_tri_strips_only ||
1738 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1739 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1740
1741 if (likely(!info->indirect)) {
1742 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1743 * no workaround for indirect draws, but we can at least skip
1744 * direct draws.
1745 */
1746 if (unlikely(!instance_count))
1747 return;
1748
1749 /* Handle count == 0. */
1750 if (unlikely(!info->count &&
1751 (index_size || !info->count_from_stream_output)))
1752 return;
1753 }
1754
1755 if (unlikely(!sctx->vs_shader.cso ||
1756 !rs ||
1757 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1758 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1759 assert(0);
1760 return;
1761 }
1762
1763 /* Recompute and re-emit the texture resource states if needed. */
1764 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1765 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1766 sctx->last_dirty_tex_counter = dirty_tex_counter;
1767 sctx->framebuffer.dirty_cbufs |=
1768 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1769 sctx->framebuffer.dirty_zsbuf = true;
1770 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1771 si_update_all_texture_descriptors(sctx);
1772 }
1773
1774 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1775 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1776 sctx->last_dirty_buf_counter = dirty_buf_counter;
1777 /* Rebind all buffers unconditionally. */
1778 si_rebind_buffer(sctx, NULL);
1779 }
1780
1781 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1782
1783 /* Set the rasterization primitive type.
1784 *
1785 * This must be done after si_decompress_textures, which can call
1786 * draw_vbo recursively, and before si_update_shaders, which uses
1787 * current_rast_prim for this draw_vbo call. */
1788 if (sctx->gs_shader.cso)
1789 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1790 else if (sctx->tes_shader.cso) {
1791 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1792 rast_prim = PIPE_PRIM_POINTS;
1793 else
1794 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1795 } else
1796 rast_prim = prim;
1797
1798 if (rast_prim != sctx->current_rast_prim) {
1799 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1800 util_prim_is_points_or_lines(rast_prim))
1801 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1802
1803 sctx->current_rast_prim = rast_prim;
1804 sctx->do_update_shaders = true;
1805 }
1806
1807 if (sctx->tes_shader.cso &&
1808 sctx->screen->has_ls_vgpr_init_bug) {
1809 /* Determine whether the LS VGPR fix should be applied.
1810 *
1811 * It is only required when num input CPs > num output CPs,
1812 * which cannot happen with the fixed function TCS. We should
1813 * also update this bit when switching from TCS to fixed
1814 * function TCS.
1815 */
1816 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1817 bool ls_vgpr_fix =
1818 tcs &&
1819 info->vertices_per_patch >
1820 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1821
1822 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1823 sctx->ls_vgpr_fix = ls_vgpr_fix;
1824 sctx->do_update_shaders = true;
1825 }
1826 }
1827
1828 if (sctx->chip_class <= GFX9 && sctx->gs_shader.cso) {
1829 /* Determine whether the GS triangle strip adjacency fix should
1830 * be applied. Rotate every other triangle if
1831 * - triangle strips with adjacency are fed to the GS and
1832 * - primitive restart is disabled (the rotation doesn't help
1833 * when the restart occurs after an odd number of triangles).
1834 */
1835 bool gs_tri_strip_adj_fix =
1836 !sctx->tes_shader.cso &&
1837 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1838 !primitive_restart;
1839
1840 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1841 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1842 sctx->do_update_shaders = true;
1843 }
1844 }
1845
1846 if (index_size) {
1847 /* Translate or upload, if needed. */
1848 /* 8-bit indices are supported on GFX8. */
1849 if (sctx->chip_class <= GFX7 && index_size == 1) {
1850 unsigned start, count, start_offset, size, offset;
1851 void *ptr;
1852
1853 si_get_draw_start_count(sctx, info, &start, &count);
1854 start_offset = start * 2;
1855 size = count * 2;
1856
1857 indexbuf = NULL;
1858 u_upload_alloc(ctx->stream_uploader, start_offset,
1859 size,
1860 si_optimal_tcc_alignment(sctx, size),
1861 &offset, &indexbuf, &ptr);
1862 if (!indexbuf)
1863 return;
1864
1865 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1866 index_offset + start,
1867 count, ptr);
1868
1869 /* info->start will be added by the drawing code */
1870 index_offset = offset - start_offset;
1871 index_size = 2;
1872 } else if (info->has_user_indices) {
1873 unsigned start_offset;
1874
1875 assert(!info->indirect);
1876 start_offset = info->start * index_size;
1877
1878 indexbuf = NULL;
1879 u_upload_data(ctx->stream_uploader, start_offset,
1880 info->count * index_size,
1881 sctx->screen->info.tcc_cache_line_size,
1882 (char*)info->index.user + start_offset,
1883 &index_offset, &indexbuf);
1884 if (!indexbuf)
1885 return;
1886
1887 /* info->start will be added by the drawing code */
1888 index_offset -= start_offset;
1889 } else if (sctx->chip_class <= GFX7 &&
1890 si_resource(indexbuf)->TC_L2_dirty) {
1891 /* GFX8 reads index buffers through TC L2, so it doesn't
1892 * need this. */
1893 sctx->flags |= SI_CONTEXT_WB_L2;
1894 si_resource(indexbuf)->TC_L2_dirty = false;
1895 }
1896 }
1897
1898 bool dispatch_prim_discard_cs = false;
1899 bool prim_discard_cs_instancing = false;
1900 unsigned original_index_size = index_size;
1901 unsigned direct_count = 0;
1902
1903 if (info->indirect) {
1904 struct pipe_draw_indirect_info *indirect = info->indirect;
1905
1906 /* Add the buffer size for memory checking in need_cs_space. */
1907 si_context_add_resource_size(sctx, indirect->buffer);
1908
1909 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1910 if (sctx->chip_class <= GFX8) {
1911 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1912 sctx->flags |= SI_CONTEXT_WB_L2;
1913 si_resource(indirect->buffer)->TC_L2_dirty = false;
1914 }
1915
1916 if (indirect->indirect_draw_count &&
1917 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1918 sctx->flags |= SI_CONTEXT_WB_L2;
1919 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1920 }
1921 }
1922 } else {
1923 /* Multiply by 3 for strips and fans to get an approximate vertex
1924 * count as triangles. */
1925 direct_count = info->count * instance_count *
1926 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1927 }
1928
1929 /* Determine if we can use the primitive discard compute shader. */
1930 if (si_compute_prim_discard_enabled(sctx) &&
1931 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1932 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1933 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1934 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1935 (primitive_restart ?
1936 /* Supported prim types with primitive restart: */
1937 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1938 /* Disallow instancing with primitive restart: */
1939 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1940 /* Supported prim types without primitive restart + allow instancing: */
1941 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1942 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1943 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1944 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1945 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1946 (instance_count == 1 ||
1947 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1948 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1949 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1950 (!sctx->render_cond || pd_msg("render condition")) &&
1951 /* Forced enablement ignores pipeline statistics queries. */
1952 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1953 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1954 pd_msg("pipestat or primgen query")) &&
1955 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1956 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1957 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1958 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1959 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1960 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1961 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1962 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1963 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1964 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
1965 !sctx->vs_shader.cso->so.num_outputs &&
1966 #else
1967 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
1968 #endif
1969 /* Check that all buffers are used for read only, because compute
1970 * dispatches can run ahead. */
1971 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
1972 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
1973 case SI_PRIM_DISCARD_ENABLED:
1974 original_index_size = index_size;
1975 prim_discard_cs_instancing = instance_count > 1;
1976 dispatch_prim_discard_cs = true;
1977
1978 /* The compute shader changes/lowers the following: */
1979 prim = PIPE_PRIM_TRIANGLES;
1980 index_size = 4;
1981 instance_count = 1;
1982 primitive_restart = false;
1983 sctx->compute_num_verts_rejected -= direct_count;
1984 sctx->compute_num_verts_accepted += direct_count;
1985 break;
1986 case SI_PRIM_DISCARD_DISABLED:
1987 break;
1988 case SI_PRIM_DISCARD_DRAW_SPLIT:
1989 sctx->compute_num_verts_rejected -= direct_count;
1990 goto return_cleanup;
1991 }
1992 }
1993
1994 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
1995 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
1996 sctx->do_update_shaders = true;
1997 }
1998
1999 if (sctx->do_update_shaders && !si_update_shaders(sctx))
2000 goto return_cleanup;
2001
2002 si_need_gfx_cs_space(sctx);
2003
2004 if (sctx->bo_list_add_all_gfx_resources)
2005 si_gfx_resources_add_all_to_bo_list(sctx);
2006
2007 /* Since we've called si_context_add_resource_size for vertex buffers,
2008 * this must be called after si_need_cs_space, because we must let
2009 * need_cs_space flush before we add buffers to the buffer list.
2010 */
2011 if (!si_upload_vertex_buffer_descriptors(sctx))
2012 goto return_cleanup;
2013
2014 /* Vega10/Raven scissor bug workaround. When any context register is
2015 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2016 * registers must be written too.
2017 */
2018 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
2019 unsigned masked_atoms = 0;
2020
2021 if (has_gfx9_scissor_bug) {
2022 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2023
2024 if (info->count_from_stream_output ||
2025 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
2026 sctx->dirty_states & si_states_that_always_roll_context())
2027 sctx->context_roll = true;
2028 }
2029
2030 /* Use optimal packet order based on whether we need to sync the pipeline. */
2031 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
2032 SI_CONTEXT_FLUSH_AND_INV_DB |
2033 SI_CONTEXT_PS_PARTIAL_FLUSH |
2034 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2035 /* If we have to wait for idle, set all states first, so that all
2036 * SET packets are processed in parallel with previous draw calls.
2037 * Then draw and prefetch at the end. This ensures that the time
2038 * the CUs are idle is very short.
2039 */
2040 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2041 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2042
2043 if (!si_upload_graphics_shader_descriptors(sctx))
2044 goto return_cleanup;
2045
2046 /* Emit all states except possibly render condition. */
2047 si_emit_all_states(sctx, info, prim, instance_count,
2048 primitive_restart, masked_atoms);
2049 sctx->emit_cache_flush(sctx);
2050 /* <-- CUs are idle here. */
2051
2052 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
2053 sctx->atoms.s.render_cond.emit(sctx);
2054
2055 if (has_gfx9_scissor_bug &&
2056 (sctx->context_roll ||
2057 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2058 sctx->atoms.s.scissors.emit(sctx);
2059
2060 sctx->dirty_atoms = 0;
2061
2062 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2063 instance_count, dispatch_prim_discard_cs,
2064 original_index_size);
2065 /* <-- CUs are busy here. */
2066
2067 /* Start prefetches after the draw has been started. Both will run
2068 * in parallel, but starting the draw first is more important.
2069 */
2070 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2071 cik_emit_prefetch_L2(sctx, false);
2072 } else {
2073 /* If we don't wait for idle, start prefetches first, then set
2074 * states, and draw at the end.
2075 */
2076 if (sctx->flags)
2077 sctx->emit_cache_flush(sctx);
2078
2079 /* Only prefetch the API VS and VBO descriptors. */
2080 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2081 cik_emit_prefetch_L2(sctx, true);
2082
2083 if (!si_upload_graphics_shader_descriptors(sctx))
2084 goto return_cleanup;
2085
2086 si_emit_all_states(sctx, info, prim, instance_count,
2087 primitive_restart, masked_atoms);
2088
2089 if (has_gfx9_scissor_bug &&
2090 (sctx->context_roll ||
2091 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2092 sctx->atoms.s.scissors.emit(sctx);
2093
2094 sctx->dirty_atoms = 0;
2095
2096 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2097 instance_count, dispatch_prim_discard_cs,
2098 original_index_size);
2099
2100 /* Prefetch the remaining shaders after the draw has been
2101 * started. */
2102 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2103 cik_emit_prefetch_L2(sctx, false);
2104 }
2105
2106 /* Clear the context roll flag after the draw call. */
2107 sctx->context_roll = false;
2108
2109 if (unlikely(sctx->current_saved_cs)) {
2110 si_trace_emit(sctx);
2111 si_log_draw_state(sctx, sctx->log);
2112 }
2113
2114 /* Workaround for a VGT hang when streamout is enabled.
2115 * It must be done after drawing. */
2116 if ((sctx->family == CHIP_HAWAII ||
2117 sctx->family == CHIP_TONGA ||
2118 sctx->family == CHIP_FIJI) &&
2119 si_get_strmout_en(sctx)) {
2120 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2121 }
2122
2123 if (unlikely(sctx->decompression_enabled)) {
2124 sctx->num_decompress_calls++;
2125 } else {
2126 sctx->num_draw_calls++;
2127 if (sctx->framebuffer.state.nr_cbufs > 1)
2128 sctx->num_mrt_draw_calls++;
2129 if (primitive_restart)
2130 sctx->num_prim_restart_calls++;
2131 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2132 sctx->num_spill_draw_calls++;
2133 }
2134
2135 return_cleanup:
2136 if (index_size && indexbuf != info->index.resource)
2137 pipe_resource_reference(&indexbuf, NULL);
2138 }
2139
2140 static void
2141 si_draw_rectangle(struct blitter_context *blitter,
2142 void *vertex_elements_cso,
2143 blitter_get_vs_func get_vs,
2144 int x1, int y1, int x2, int y2,
2145 float depth, unsigned num_instances,
2146 enum blitter_attrib_type type,
2147 const union blitter_attrib *attrib)
2148 {
2149 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2150 struct si_context *sctx = (struct si_context*)pipe;
2151
2152 /* Pack position coordinates as signed int16. */
2153 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2154 ((uint32_t)(y1 & 0xffff) << 16);
2155 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2156 ((uint32_t)(y2 & 0xffff) << 16);
2157 sctx->vs_blit_sh_data[2] = fui(depth);
2158
2159 switch (type) {
2160 case UTIL_BLITTER_ATTRIB_COLOR:
2161 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2162 sizeof(float)*4);
2163 break;
2164 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2165 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2166 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2167 sizeof(attrib->texcoord));
2168 break;
2169 case UTIL_BLITTER_ATTRIB_NONE:;
2170 }
2171
2172 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2173
2174 struct pipe_draw_info info = {};
2175 info.mode = SI_PRIM_RECTANGLE_LIST;
2176 info.count = 3;
2177 info.instance_count = num_instances;
2178
2179 /* Don't set per-stage shader pointers for VS. */
2180 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2181 sctx->vertex_buffer_pointer_dirty = false;
2182
2183 si_draw_vbo(pipe, &info);
2184 }
2185
2186 void si_trace_emit(struct si_context *sctx)
2187 {
2188 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2189 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2190
2191 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2192 0, 4, V_370_MEM, V_370_ME, &trace_id);
2193
2194 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2195 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2196
2197 if (sctx->log)
2198 u_log_flush(sctx->log);
2199 }
2200
2201 void si_init_draw_functions(struct si_context *sctx)
2202 {
2203 sctx->b.draw_vbo = si_draw_vbo;
2204
2205 sctx->blitter->draw_rectangle = si_draw_rectangle;
2206
2207 si_init_ia_multi_vgt_param_table(sctx);
2208 }